www.renesas.com
All information contained in these materials, including products and product specifications,
represents informat ion on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
REJ09B0324-0200
R8C/2A Group, R8C/2B Group
Hardware Manual
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
16
Rev.2.00
Revision Date: Nov 26, 2007
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Notes regarding these materials
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/2A Group, R8C/2B Group. Make sure to refer to the latest versions of
these documents. Th e newest versions of the docum ents listed may be obtai ned from the Renesas Tech nology Web
site.
Document Type Description Document Title Document No.
Datasheet Hardware overview and electrical characteristics R8C/2A Group,
R8C/2B Group
Group Datasheet
REJ03B0182
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
R8C/2A Group,
R8C/2B Group
Hardware Manual
This hardware
manual
Software manual Description of CPU instruction set R8C/Tiny Series
Software Manual
REJ09B0001
Application note Information on using peripheral functions and
application examples
Sample programs
Information on writing programs in assembly
language and C
Available from Renesas
Technology Web site.
Renesas
technical update
Product specifications, updates on documents,
etc.
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b ” is append ed to numer ic values gi ven in binary fo rmat. Ho wever, nothing is appende d to the
values of single bits. The indication “h” is appended to numeric values given in hexadecim al format. Nothi ng
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 123 4
3. Register Notation
The symbols and terms used in register diagrams are described below.
*1 Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2 RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3• Reserved bit
Reserved bit. Set to specified value.
*4• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used fo r future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual mode s.
XXX Register
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
XXX bits 1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
b1 b0
XXX1
XXX0
XXX4
Reserved bits
XXX5
XXX7
XXX6
Function
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
XXX bit
Function varies according to the operating
mode.
Set to 0.
0
(b3)
(b2)
RW
RW
RW
RW
WO
RW
RO
XXX bits
0: XXX
1: XXX
*1
*2
*3
*4
4. List of Abbreviations and Acronyms
Abbreviation Full Form
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment bus
I/O Input/Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connection
PLL Phase Locked Loop
PWM Pulse Width Modulation
SFR Special Function Registers
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
A - 1
SFR Page Reference ........................................................................................................................... B - 1
1. Overview ......................................................................................................................................... 1
1.1 Features ..................................................................................................................................................... 1
1.1.1 Applications .......................................................................................................................................... 1
1.1.2 Specifications ........................................................................................................................................ 2
1.2 Product List ............................................................................................................................................... 6
1.3 Block Diagram .................... ................................................................................................................... 10
1.4 Pin Assignment ........................................................................................................................................ 11
1.5 Pin Functions ........................................................................................................................................... 15
2. Central Processing Unit (CPU) ..................................................................................................... 17
2.1 Data Registers (R0, R1, R2, and R3) ...................................................................................................... 18
2.2 Address Registers (A0 and A1) ............................................................................................................... 18
2.3 Frame Base Register (FB) ....................................................................................................................... 18
2.4 Interrupt Table Register (INTB) .............................................................................................................. 18
2.5 Program Counter (PC) .......................................................... ................................................................... 18
2.6 User Stack Pointer (USP ) and Interrupt Stack Pointer (ISP) .................................................................. 18
2.7 Static Base Register (SB) ....................................... ................................................................................. 18
2.8 Flag Register (FLG) ................................................................................................................................ 18
2.8.1 Carry Flag (C) ..................................................................................................................................... 18
2.8.2 Debug Flag (D) ................................................................................................................................... 18
2.8.3 Zero Flag (Z) ....................................................................................................................................... 18
2.8.4 Sign Flag (S) ....................................................................................................................................... 18
2.8.5 Register Bank Select Flag (B) ............................................................................................................ 18
2.8.6 Overflow Flag (O) .............................................................................................................................. 18
2.8.7 Interrupt Enable Flag (I) ..................................................................................................................... 19
2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 19
2.8.9 Processor Interrupt Priority Le vel (IPL) ............................................................................................. 19
2.8.10 Reserved Bit ..................... ..................................................................................... .. ............................ 19
3. Memory ......................................................................................................................................... 20
3.1 R8C/2A Group ........................................................................................................................................ 20
3.2 R8C/2B Group ......................................................................................................................................... 21
4. Special Function Registers (SFRs) ............................................................................................... 22
5. Resets ........................................................................................................................................... 34
5.1 Hardware Reset ....................................................................................................................................... 37
5.1.1 When Power Supply is Stable ............................................................................................................. 37
5.1.2 Power On ............................................................................................................................................ 37
5.2 Power-On Reset Function ....................................................................................................................... 39
5.3 Voltage Monitor 0 Reset ......................................................................................................................... 40
5.4 Voltage Monitor 1 Reset ......................................................................................................................... 40
5.5 Voltage Monitor 2 Reset ......................................................................................................................... 40
5.6 Watchdog Timer Reset ............................................................................................................................ 41
5.7 Software Reset ......................................................................................................................................... 41
Table of Contents
A - 2
6. Voltage Detection Circuit .............................................................................................................. 42
6.1 VCC Input Voltage .................................................................................................................................. 49
6.1.1 Monitoring Vdet0 ............................................................................................................................... 49
6.1.2 Monitoring Vdet1 ............................................................................................................................... 49
6.1.3 Monitoring Vdet2 ............................................................................................................................... 49
6.2 Voltage Monitor 0 Reset ......................................................................................................................... 50
6.3 Voltage Monitor 1 Interru pt and Voltage Monitor 1 Reset ..................................................................... 51
6.4 Voltage Monitor 2 Interru pt and Voltage Monitor 2 Reset ..................................................................... 53
7. Programmable I/O Ports ............................................................................................................... 55
7.1 Functions of Programmable I/O Ports ..................................................................................................... 55
7.2 Effect on Peripheral Functions ................................................................................................................ 56
7.3 Pins Other than Programmable I/O Ports ................................................................................................ 56
7.4 Port settings .................. ........................................................................................................................... 72
7.5 Unassigned Pin Handling ........................................................................................................................ 89
8. Processor Mode ............................................................................................................................ 90
8.1 Processor Modes ............................... ....................................................................................................... 90
9. Bus ................................................................................................................................................ 91
10. Clock Generation Circuit ............................................................................................................... 93
10.1 X IN Clock ............................................................................................................................ ................. 103
10.2 On-Chip Oscillator Clocks .................................................................................................................... 104
10.2.1 Low-Speed On-Chip Oscillator Clock .............................................................................................. 104
10.2.2 High-Speed On-Chip Oscillator Clock ............................................................................................. 104
10.3 XCIN Clock .................................................................................................................. ......................... 105
10.4 CPU Clock and Peripheral Function Clock ........................................................................................... 106
10.4.1 System Clock .............................................................................................................. ...................... 106
10.4.2 CPU Clock . ................. .................................................................................................. .................... 106
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ........................................................................... 106
10.4.4 fOCO ..................................................................................................................... ............................ 106
10.4.5 fOCO40M ..................................................................................................................... .................... 106
10.4.6 fOCO-F ............................................................................................................................................. 106
10.4.7 fOCO-S ............................................................................................................................................. 106
10.4.8 fOCO128 ........................................................................................................................................... 106
10.4.9 fC4 and fC32 ...... .......................................................................... ..................................................... 107
10.5 Power Control .................................................................................................................. ...................... 108
10.5.1 Standard Operating Mode ................................................................................................................. 108
10.5.2 Wait Mode ....................................................................................................................... ................. 110
10.5.3 Stop Mode ......................................................................................................................................... 114
10.6 Oscillation Stop Detection Function ..................................................................................................... 117
10.6.1 How to Use Oscillation Stop Detection Function ........................................... ................. ................. 117
10.7 Notes on Clock Generation Circuit ....................................................................................................... 120
10.7.1 Stop Mode ......................................................................................................................................... 120
10.7.2 Wait Mode ....................................................................................................................... ................. 120
10.7.3 Oscillation Stop Detection Function .............................................................................................. ... 120
10.7.4 Oscillation Circuit Constants .............................................................................................. .............. 120
A - 3
11. Protection .................................................................................................................................... 121
12. Interrupts ..................................................................................................................................... 122
12.1 I nterrupt Overview ........................ .................................................................................... .................... 122
12.1.1 Types of Interrupts ............................................................................................................................ 122
12.1.2 Software Interrupts .......................................................................................................... ................. 123
12.1.3 Special Interrupts .............................................................................................................................. 124
12.1.4 Peripheral Funct ion Interrup t .............................................................................................. .............. 124
12.1.5 Interrupts and Interrupt Vectors .......................................................................................... .............. 125
12.1.6 Interrupt Control .............................................................. ......................................... ........................ 127
12.2 INT Interrupt ......................................................................................................................................... 136
12.2.1 INTi Interrupt (i = 0 to 3) .................................................................................................................. 136
12.2.2 INTi Input Filter (i = 0 to 3) ............................ ............................................................ ............ .......... 139
12.3 Key Input Interrupt ................................................................................................................................ 140
12.4 A ddress Match Interrupt ............................................ ............................... ......................... .................... 142
12.5 Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and
I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) ................................ 144
12.6 Notes on Interrupts ............................................................................................................... ................. 146
12.6.1 Reading Add ress 00000 h ............................................................................................................... ... 146
12.6.2 SP Setting ............................................................................................................................ .............. 146
12.6.3 External Interrupt and Key Input Interrupt ....................................................................................... 146
12.6.4 Changing Interrupt Sources ........................................................................................................ ...... 147
12.6.5 Changing Interrupt Control Register Contents ................................................................................. 148
13. Watchdog Timer .......................................................................................................................... 149
13.1 Count Source Protection Mode Disabled ........................................................................................ ...... 153
13.2 Count Source Protection Mode Enabled ............................................................................................... 154
14. Timers ......................................................................................................................................... 155
14.1 Timer RA ................................................................................................................... ............................ 158
14.1.1 Timer Mode ...................................................................................................................................... 161
14.1.2 Pulse Output Mode ........................................................................ ........................................ ........... 163
14.1.3 Event Counter Mode ......................................................................................................................... 165
14.1.4 Pulse Width Measurement Mode ...................................................................................................... 167
14.1.5 Pulse Period Measurement Mode .................................... ............................... ............................ ...... 170
14.1.6 Notes on Timer RA ................................................................................................................... ........ 173
14.2 Timer RB ......................................................................................................................... ...................... 174
14.2.1 Timer Mode ...................................................................................................................................... 178
14.2.2 Programmable Waveform Generation Mode ........ ............................................. ............................... 181
14.2.3 Programmable One-shot Generation Mode ...................................................................................... 183
14.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 187
14.2.5 Notes on Timer RB ........................................................................................................................... 191
14.3 Timer RC ......................................................................................................................... ...................... 195
14.3.1 Overview ........................................................................................................................................... 195
14.3.2 Registers Associated with Timer RC ................................................................................................ 197
14.3.3 Common Items for Multiple Modes ................................................................................................. 207
14.3.4 Timer Mode (Input Capture Function) ............................................................................................. 213
14.3.5 Timer Mode (Output Compare Function) ......................................................................................... 218
14.3.6 PWM Mode ................. ......................................................................... ............................ ................. 224
A - 4
14.3.7 PWM2 Mode ....................................................................................................................... .............. 229
14.3.8 Timer RC Interrupt ........................................................................................................................... 235
14.3.9 Notes on Timer RC ........................................................................................................................... 236
14.4 Timer RD ................................................................................................................... ............................ 237
14.4.1 Count Sources ................................................................................................................................... 242
14.4.2 Buffer Operation .................................................................................................................... ........... 243
14.4.3 Synchronous Operation ............. ................. ........................................................... ............................ 245
14.4.4 Pulse Output Forced Cutoff .............................................................................................................. 246
14.4.5 Input Capture Function ..................................................................................................................... 248
14.4.6 Output Compare Function ........................................................... ..................................................... 263
14.4.7 PWM Mode ................. ......................................................................... ............................ ................. 281
14.4.8 Reset Synchronou s PWM Mode ....................................................................................................... 295
14.4.9 Complementary PWM Mode ......................................................................................................... ... 306
14.4.10 PWM3 Mode ..................................................................................................................................... 321
14.4.11 Timer RD Interrupt ........................................................................................................................... 335
14.4.12 Notes on Timer RD ........................................................................................................................ ... 337
14.5 Timer RE ................................................................................................................... ............................ 343
14.5.1 Real-Time Clock Mode .................................................................................................................... 344
14.5.2 Output Compare Mode ................ ............................... ...................................................................... 352
14.5.3 Notes on Timer RE ........................................................................................................................... 358
14.6 Timer RF ...................................................................................................................... ......................... 361
14.6.1 Input Capture Mode .......................................................................................................................... 366
14.6.2 Output Compare Mode ................ ............................... ...................................................................... 369
14.6.3 Notes on Timer RF .......................................................................................................... ................. 373
15. Serial Interface ............................................................................................................................ 374
15.1 Clock Synchronous Serial I/O Mode ............................................................................................. ........ 381
15.1.1 Polarity Select Function ......................................................................................................... ........... 385
15.1.2 LSB First/MSB First Select Function ............................................................................................... 385
15.1.3 Continuous Receive Mode ........................................................................................................ ........ 386
15.2 Clock Asynchronous Serial I/O (UART) Mode .................................................. .................................. 387
15.2.1 Bit Rate .............. .................................................................................................. ............................. 392
15.3 Notes on Serial Interface ......................................................................................................... .............. 393
16. Clock Synchronous Serial Interface ............................................................................................ 394
16.1 Mode Selection ............................................................................................................. ......................... 394
16.2 Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................ 395
16.2.1 Transfer Clock .................................................................................................................................. 404
16.2.2 SS Shift Register (SSTRSR) ............................................................................................... .............. 406
16.2.3 Interrupt Requests ............................. ........................................................... .............. ....................... 407
16.2.4 Communication Modes and Pin Functions ....................................................................................... 408
16.2.5 Clock Synchronous Communicati o n Mode ...................................................................................... 409
16.2.6 Operation in 4-Wire Bus Co mmunication Mode .............................................................................. 416
16.2.7 SCS Pin Control and Arbitration ...................................................................................................... 422
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 423
16.3 I2C bus Interface .................................................................................................................................... 424
16.3.1 Transfer Clock .................................................................................................................................. 434
16.3.2 Interrupt Requests ............................. ........................................................... .............. ....................... 435
16.3.3 I2C bus Interface Mode ..................................................................................................................... 436
A - 5
16.3.4 Clock Synchronous Serial Mode ................................................................................................... ... 447
16.3.5 Examples of Register Setting ...................................................................................................... ...... 450
16.3.6 Noise Canceller ................................................................................................................... .............. 454
16.3.7 Bit Synchronization Circuit .............................................................................................................. 455
16.3.8 Notes on I2C bus Interface ................................................................................................................ 456
17. Hardware LIN .............................................................................................................................. 457
17.1 Features ........................................................................................................................... ...................... 457
17.2 Input/Output Pins .................... ................. ........................................................... .................................. 458
17.3 Register Configuration ......................................................................................................... ................. 459
17.4 Functional Description ............................................................................................................... ........... 461
17.4.1 Master Mode ..................................................................................................................................... 461
17.4.2 Slave Mode ................................................................................................................... .................... 464
17.4.3 Bus Collision Detection Function .................................................................................................. ... 468
17.4.4 Hardware LIN End Processing .............................................................................................. ........... 469
17.5 Interrupt Requests .................... ............................................. ................................................................. 470
17.6 Notes on Hardware LIN ....................................................................................................... ................. 471
18. A/D Converter ............................................................................................................................. 472
18.1 One-Shot Mode ..................................................................................................................................... 477
18.2 Repeat Mode 0 ....................................................................................................................................... 480
18.3 Sample and Hold ................................... .................................................................................. .............. 483
18.4 A /D Conversion Cycles .................................................................... ..................................................... 483
18.5 Internal Equivalent Circuit of Analog Input .................................................................................. ........ 484
18.6 Output Impedance of Sensor under A/D Conversion ............................................................................ 485
18.7 Notes on A/D Converter ........................................................................................................................ 486
19. D/A Converter ............................................................................................................................. 487
20. Flash Memory ............................................................................................................................. 489
20.1 Overview ............................................................................................................................................... 489
20.2 Memory Map ............. .......................................... .................................................................... .............. 490
20.3 Functions to Prevent Rewriting of Flash Memory ................................................................................ 492
20.3.1 ID Code Check Function .................................................................................................................. 492
20.3.2 ROM Code Protect Function ............................................................................................................ 493
20.4 CPU Rewrite Mode ...................................................... ............................................. ............................ 494
20.4.1 EW0 Mode .................................................................................................................. ...................... 495
20.4.2 EW1 Mode .................................................................................................................. ...................... 495
20.4.3 Software Commands ................................................................................................................... ...... 504
20.4.4 Status Registers ................................................................................................................ ................. 509
20.4.5 Full Status Check .......................................................................................................... .............. ...... 510
20.5 Standard Serial I/O Mode ...................................................................................................................... 512
20.5.1 ID Code Check Function .................................................................................................................. 512
20.6 Parallel I/O Mode ....................... ............................................. .......................................... .................... 516
20.6.1 ROM Code Protect Function ............................................................................................................ 516
20.7 Notes on Flash Memory ........................................................................................................................ 517
20.7.1 CPU Rewrite Mode .......... ............................... ............................................. ............................. ........ 517
A - 6
21. Electrical Characteristics ............................................................................................................ 520
22. Usage Notes ............................................................................................................................... 545
22.1 Notes on Clock Generation Circuit ....................................................................................................... 545
22.1.1 Stop Mode ......................................................................................................................................... 545
22.1.2 Wait Mode ....................................................................................................................... ................. 545
22.1.3 Oscillation Stop Detection Function .............................................................................................. ... 545
22.1.4 Oscillation Circuit Constants .............................................................................................. .............. 545
22.2 Notes on Interrupts ............................................................................................................... ................. 546
22.2.1 Reading Add ress 00000 h ............................................................................................................... ... 546
22.2.2 SP Setting ............................................................................................................................ .............. 546
22.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 546
22.2.4 Changing Interrupt Sources ........................................................................................................ ...... 547
22.2.5 Changing Interrupt Control Register Contents ................................................................................. 548
22.3 Notes on Timers ................................................................................................................ .................... 549
22.3.1 Notes on Timer RA ................................................................................................................... ........ 549
22.3.2 Notes on Timer RB ........................................................................................................................... 550
22.3.3 Notes on Timer RC ........................................................................................................................... 554
22.3.4 Notes on Timer RD ................................................................................................................... ........ 555
22.3.5 Notes on Timer RE ........................................................................................................................... 561
22.3.6 Notes on Timer RF .......................................................................................................... ................. 564
22.4 Notes on Serial Interface ......................................................................................................... .............. 565
22.5 Notes on Clock Synchronous Serial Interface ....................................................................................... 566
22.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 566
22.5.2 Notes on I2C bus Interface ................................................................................................................ 566
22.6 Notes on Hardware LIN ....................................................................................................... ................. 567
22.7 Notes on A/D Converter ........................................................................................................................ 568
22.8 Notes on Flash Memory ........................................................................................................................ 569
22.8.1 CPU Rewrite Mode .......... ............................... ............................................. ............................. ........ 569
22.9 Notes on Noise ...................................................................................................................................... 572
22.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ........................................................................................................................... ................. 572
22.9.2 Countermeasures against Noise Error of Port Control Registers ............................... ...................... 572
23. Notes on On-Chip Debugger ...................................................................................................... 573
24. Notes on Emulator Debugger ..................................................................................................... 574
Appendix 1. Package Dimensions ........................................................................................................ 575
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 577
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 578
Index ..................................................................................................................................................... 579
B - 1
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 90
0005h Processor Mode Register 1 PM1 90
0006h System Clock Control Register 0 CM0 96
0007h System Clock Control Register 1 CM1 97
0008h Module Standby Control Register MSTCR 198, 250,
265, 283,
297, 308,
323, 396,
426
0009h
000Ah Protect Register PRCR 121
000Bh
000Ch Oscillation Stop Detection Register OCD 98
000Dh Watchdog Timer Reset Register WDTR 151
000Eh Watchdog Timer Start Register WDTS 151
000Fh Watchdog Timer Control Register WDC 151
0010h Address Match Interrupt Register 0 RMAD0 143
0011h
0012h
0013h Address Match Interrupt Enable Register AIER 143
0014h Address Match Interrupt Register 1 RMAD1 143
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 152
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 99
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 99
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 100
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 101
0029h
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 100
002Ch High-Speed On-Chip Oscillator Control Register 7 FRA7 100
002Dh
002Eh
002Fh
0030h
0031h Voltage Detection Register 1 VCA1 45
0032h Voltage Detection Register 2 VCA2 45, 101
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register VW1C 47
0037h Voltage Monitor 2 Circuit Control Register VW2C 48
0038h Voltage Monitor 0 Circuit Control Register VW0C 46
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Address Register Symbol Page
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register TRCIC 128
0048h Timer RD0 Interrupt Control Register TRD0IC 128
0049h Timer RD1 Interrupt Control Register TRD1IC 128
004Ah Timer RE Interrupt Control Register TREIC 127
004Bh UART2 Transmit Interrupt Control Register S2TIC 127
004Ch UART2 Receive Interrupt Control Register S2RIC 127
004Dh Key Input Interrupt Control Register KUPIC 127
004Eh
004Fh SSU/IIC Interrupt Control Register SSUIC/IICIC 128
0050h Compare 1 Interrupt Control Register CMP1IC 127
0051h UART0 Transmit Interrupt Control Register S0TIC 127
0052h UART0 Receive Interrupt Control Register S0RIC 127
0053h UART1 Transmit Interrupt Control Register S1TIC 127
0054h UART1 Receive Interrupt Control Register S1RIC 127
0055h INT2 Interrupt Control Register INT2IC 129
0056h Timer RA Interrupt Control Register TRAIC 127
0057h
0058h Timer RB Interrupt Control Register TRBIC 127
0059h INT1 Interrupt Control Register INT1IC 129
005Ah INT3 Interrupt Control Register INT3IC 129
005Bh Timer RF Interrupt Control Register TRFIC 127
005Ch Compare 0 Interrupt Control Register CMP0IC 127
005Dh INT0 Interrupt Control Register INT0IC 129
005Eh A/D Conversion Interrupt Control Register ADIC 127
005Fh Capture Interrupt Control Register CAPIC 127
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SFR Page Reference
B - 2
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 377
00A1h UART0 Bit Rate Register U0BRG 377
00A2h UART0 Transmit Buffer Register U0TB 378
00A3h
00A4h UART0 Transmit / Receive Control Register 0 U0C0 378
00A5h UART0 Transmit / Receive Control Register 1 U0C1 379
00A6h UART0 Receive Buffer Register U0RB 379
00A7h
00A8h UART1 Transmit/Receive Mode Register U1MR 377
00A9h UART1 Bit Rate Register U1BRG 377
00AAh UART1 Transmit Buffer Register U1TB 378
00ABh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 378
00ADh UART1 Transmit/Receive Control Register 1 U1C1 379
00AEh UART1 Receive Buffer Register U1RB 379
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
SS Control Register H / IIC bus Control Register 1
SSCRH/ICCR1 397, 427
00B9h
SS Control Register L / IIC bus Control Register 2
SSCRL/ICCR2 398, 428
00BAh SS Mode Register / IIC bus Mode Register SSMR/ICMR 399, 429
00BBh SS Enable Register / IIC bus Interrupt Enable
Register
SSER/ICIER 400, 430
00BCh SS Status Register / IIC bus Status Register SSSR/ICSR 401, 431
00BDh SS Mode Register 2 / Slave Address Register SSMR2/SAR 402, 432
00BEh SS Transmit Data Register/IIC Bus Transmit
Data Register
SSTDR/ICDRT 403, 432
00BFh SS Receive Data Register/IIC Bus Receive
Data Register
SSRDR/ICDRR 403, 433
Address Register Symbol Page
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h D/A Register 0 DA0 488
00D9h
00DAh D/A Register 1 DA1 488
00DBh
00DCh D/A Control Register DACON 488
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 69
00E1h Port P1 Register P1 69
00E2h Port P0 Direction Register PD0 68
00E3h Port P1 Direction Register PD1 68
00E4h Port P2 Register P2 69
00E5h Port P3 Register P3 69
00E6h Port P2 Direction Register PD2 68
00E7h Port P3 Direction Register PD3 68
00E8h Port P4 Register P4 69
00E9h Port P5 Register P5 69
00EAh Port P4 Direction Register PD4 68
00EBh Port P5 Direction Register PD5 68
00ECh Port P6 Register P6 69
00EDh
00EEh Port P6 Direction Register PD6 68
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h Port P2 Drive Capacity Control Register P2DRR 70
00F5h UART1 Function Select Register U1SR 380
00F6h
00F7h
00F8h Port Mode Register PMR 70, 136, 380,
403, 433
00F9h External Input Enable Register INTEN 137
00FAh INT Input Filter Select Register INTF 138
00FBh Key Input Enable Register KIEN 141
00FCh Pull-Up Control Register 0 PUR0 71
00FDh Pull-Up Control Register 1 PUR1 71
00FEh
00FFh
B - 3
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0100h Timer RA Control Register TRACR 159
0101h Timer RA I/O Control Register TRAIOC 159, 161, 164,
166, 168, 171
0102h Timer RA Mode Register TRAMR 160
0103h Timer RA Prescaler Register TRAPRE 160
0104h Timer RA Register TRA 160
0105h LIN Control Register 2 LINCR2 459
0106h LIN Control Register LINCR 459
0107h LIN Status Register LINST 460
0108h Timer RB Control Register TRBCR 175
0109h Timer RB One-Shot Control Register TRBOCR 175
010Ah Timer RB I/O Control Register TRBIOC 176, 178, 182,
184, 189
010Bh Timer RB Mode Register TRBMR 176
010Ch Timer RB Prescaler Register TRBPRE 177
010Dh Timer RB Secondary Register TRBSC 177
010Eh Timer RB Primary Register TRBPR 177
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter
Data Register
TRESEC 346, 354
0119h Timer RE Minute Data Register / Compare
Data Register
TREMIN 346, 354
011Ah Timer RE Hour Data Register TREHR 347
011Bh Timer RE Day of Week Data Register TREWK 347
011Ch Timer RE Control Register 1 TRECR1 348, 355
011Dh Timer RE Control Register 2 TRECR2 349, 355
011Eh Timer RE Clock Source Select Register TRECSR 350, 356
011Fh
0120h Timer RC Mode Register TRCMR 198
0121h Timer RC Control Register 1 TRCCR1 199, 222, 226,
231
0122h Timer RC Interrupt Enable Register TRCIER 200
0123h Timer RC Status Register TRCSR 201
0124h Timer RC I/O Control Register 0 TRCIOR0 206, 215, 220
0125h Timer RC I/O Control Register 1 TRCIOR1 206, 216, 221
0126h Timer RC Counter TRC 202
0127h
0128h Timer RC General Register A TRCGRA 202
0129h
012Ah Timer RC General Register B TRCGRB 202
012Bh
012Ch Timer RC General Register C TRCGRC 202
012Dh
012Eh Timer RC General Register D TRCGRD 202
012Fh
Address Register Symbol Page
0130h Timer RC Control Register 2 TRCCR2 203
0131h Timer RC Digital Filter Function Select
Register
TRCDF 204
0132h Timer RC Output Master Enable Register TRCOER 205
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR 251, 266, 284,
298, 309, 324
0138h Timer RD Mode Register TRDMR 251, 266, 284,
298, 310, 325
0139h Timer RD PWM Mode Register TRDPMR 252, 267, 285
013Ah Timer RD Function Control Register TRDFCR 253, 268, 286,
299, 311, 326
013Bh Timer RD Output Master Enable Register 1 TRDOER1 269, 287, 300,
312, 327
013Ch Timer RD Output Master Enable Register 2 TRDOER2 269, 287, 300,
312, 327
013Dh Timer RD Output Control Register TRDOCR 270, 288, 328
013Eh Timer RD Digital Filter Function Select
Register 0
TRDDF0 254
013Fh Timer RD Digital Filter Function Select
Register 1
TRDDF1 254
0140h Timer RD Control Register 0 TRDCR0 255, 271, 288,
301, 313, 329
0141h Timer RD I/O Control Register A0 TRDIORA0 256, 272
0142h Timer RD I/O Control Register C0 TRDIORC0 257, 273
0143h Timer RD Status Register 0 TRDSR0 258, 274, 289,
302, 314, 330
0144h Timer RD Interrupt Enable Register 0 TRDIER0 259, 275, 290,
303, 315, 331
0145h Timer RD PWM Mode Output Level Control
Register 0
TRDPOCR0 291
0146h Timer RD Counter 0 TRD0 259, 276, 291,
303, 316, 331
0147h
0148h Timer RD General Register A0 TRDGRA0 260, 276, 292,
304, 316, 332
0149h
014Ah Timer RD General Register B0 TRDGRB0 260, 276, 292,
304, 316, 332
014Bh
014Ch Timer RD General Register C0 TRDGRC0 260, 276, 292,
304, 332
014Dh
014Eh Timer RD General Register D0 TRDGRD0 260, 276, 292,
304, 316, 332
014Fh
0150h Timer RD Control Register 1 TRDCR1 255, 271, 288,
313
0151h Timer RD I/O Control Register A1 TRDIORA1 256, 272
0152h Timer RD I/O Control Register C1 TRDIORC1 257, 273
0153h Timer RD Status Register 1 TRDSR1 258, 274, 289,
302, 314, 330
0154h Timer RD Interrupt Enable Register 1 TRDIER1 259, 275, 290,
303, 315, 331
0155h Timer RD PWM Mode Output Level Control
Register 1
TRDPOCR1 291
0156h Timer RD Counter 1 TRD1 259, 276, 291,
316
0157h
0158h Timer RD General Register A1 TRDGRA1 260, 276, 292,
304, 316, 332
0159h
015Ah Timer RD General Register B1 TRDGRB1 260, 276, 292,
304, 316, 332
015Bh
015Ch Timer RD General Register C1 TRDGRC1 260, 276, 292,
304, 316, 332
015Dh
015Eh Timer RD General Register D1 TRDGRD1 260, 276, 292,
304, 316, 332
015Fh
B - 4
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0160h UART2 Transmit/Receive Mode Register U2MR 377
0161h UART2 Bit Rate Register U2BRG 377
0162h UART2 Transmit Buffer Register U2TB 378
0163h
0164h UART2 Transmit/Receive Control Register 0 U2C0 378
0165h UART2 Transmit/Receive Control Register 1 U2C1 379
0166h UART2 Receive Buffer Register U2RB 379
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
Address Register Symbol Page
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 500
01B4h
01B5h Flash Memory Control Register 1 FMR1 499
01B6h
01B7h Flash Memory Control Register 0 FMR0 498
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
B - 5
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
Address Register Symbol Page
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
B - 6
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h Timer RF Register TRF 363
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah Timer RF Control Register 0 TRFCR0 364
029Bh Timer RF Control Register 1 TRFCR1 365
029Ch Capture / Compare 0 Register TRFM0 363
029Dh
029Eh Compare 1 Register TRFM1 363
029Fh
Address Register Symbol Page
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h A/D Register 0 AD0 474
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h A/D Control Register 2 ADCON2 474
02D5h
02D6h A/D Control Register 0 ADCON0 475
02D7h A/D Control Register 1 ADCON1 476
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
B - 7
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
Address Register Symbol Page
02E0h
02E1h
02E2h
02E3h
02E4h Port P8 Direction Register PD8 68
02E5h
02E6h Port P8 Register P8 69
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh Pull-Up Control Register 2 PUR2 71
02FDh
02FEh
02FFh Timer RF Output Control Register TRFOUT 365
FFFFh Option Function Select Register OFS 36, 152, 493
Rev.2.00 Nov 26, 2007 Page 1 of 580
REJ09B0324-0200
R8C/2A Group, R8C/2B Group
RENESAS MCU
1. Overview
1.1 Features
The R8C/2A Group and R8C/2B Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2B Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2A Group and R8C/2B Group is only the presen ce or absence of data flash. Their
peripheral functions are the same.
1.1.1 Applications
Electronic household appli a nces, office equipment, audio equipment, consumer equipment, etc.
REJ09B0324-0200
Rev.2.00
Nov 26, 2007
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 2 of 580
REJ09B0324-0200
1.1.2 Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2A Group and Tables 1.3 and 1.4 outlines the
Specification s for R8C/2B Group.
Table 1.1 Specific ations for R8C/2A Group (1)
Item Function Specification
CPU Central processing
unit
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.5 Product List for R8C/2A Group.
Power Supply
Voltage
Detection
Voltage detection
circuit
• Power-on reset
• Voltage detection 2
I/O Ports Programmable I/O
ports
• Input-only: 2 pins
• CMOS I/O ports: 55, selectable pull-up resistor
• High current drive ports: 8
Clock Clock generation
circuits
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts • External: 5 sources, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC 16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
Timer RD 16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE 8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Timer RF 16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 3 of 580
REJ09B0324-0200
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Table 1.2 Specific ations for R8C/2A Group (2)
Item Function Specification
Serial
Interface
UART0, UART1,
UART2
Clock synchronous serial I/O/UART × 3
Clock Synchronous Serial I/O with
Chip Select (SSU)
1 (shared with I2C-bus)
I2C bus(1) 1 (shared with SSU)
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 12 channels, includes sample and hold function
D/A Converter 8-bit resolution × 2 circuits
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
Operating Frequency/Supply
Voltage
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
Current consumption 12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package 64-pin LQFP
• Package code: PLQP0064KB-A (previous code: 64P6Q-A)
• Package code: PLQP0064GA-A (previous code: 64P6U-A)
64-pin FLGA
• Package code: PTLG0064JA-A (previous code: 64F0G)
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 4 of 580
REJ09B0324-0200
Table 1.3 Specific ations for R8C/2B Group (1)
Item Function Specification
CPU Central processing
unit
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.6 Product List for R8C/2B Group.
Power Supply
Voltage
Detection
Voltage detection
circuit
• Power-on reset
• Voltage detection 2
I/O Ports Programmable I/O
ports
• Input-only: 2 pins
• CMOS I/O ports: 55, selectable pull-up resistor
• High current drive ports: 8
Clock Clock generation
circuits
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts • External: 5 sources, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC 16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
Timer RD 16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE 8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Timer RF 16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 5 of 580
REJ09B0324-0200
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Table 1.4 Specific ations for R8C/2B Group (2)
Item Function Specification
Serial
Interface
UART0, UART1,
UART2
Clock synchronous serial I/O/UART × 3
Clock Synchronous Serial I/O with
Chip Select (SSU)
1 (shared with I2C-bus)
I2C bus(1) 1 (shared with SSU)
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 12 channels, includes sample and hold function
D/A Converter 8-bit resolution × 2 circuits
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
Operating Frequency/Supply
Voltage
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
Current consumption 12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package 64-pin LQFP
• Package code: PLQP0064KB-A (previous code: 64P6Q-A)
• Package code: PLQP0064GA-A (previous code: 64P6U-A)
64-pin FLGA
• Package code: PTLG0064JA-A (previous code: 64F0G)
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 6 of 580
REJ09B0324-0200
1.2 Product List
Table 1.5 lists Product List for R8C/2A Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2A Group, Table 1.6 lists Product List for R8C/2B Group, and Figure 1.2 shows a Part Number, Memory
Size, and Package of R8C/2B Group.
NOTE:
1. The user ROM is programmed before shipment.
Table 1.5 Product List for R8C/2A Group Current of Nov. 2007
Part No. ROM Capacity RAM Capacity Package Type Remarks
R5F212A7SNFP 48 Kbytes 2.5 Kbytes PLQP0064KB-A N version
R5F212A7SNFA 48 Kbytes 2.5 Kbytes PLQP0064GA-A
R5F212A7SNLG 48 Kbytes 2.5 Kbytes PTLG0064JA-A
R5F212A8SNFP 64 Kbytes 3 Kbytes PLQP0064KB-A
R5F212A8SNFA 64 Kbytes 3 Kbytes PLQP0064GA-A
R5F212A8SNLG 64 Kbytes 3 Kbytes PLTG0064JA-A
R5F212AASNFP 96 Kbytes 7 Kbytes PLQP0064KB-A
R5F212AASNFA 96 Kbytes 7 Kbytes PLQP0064GA-A
R5F212AASNLG 96 Kbytes 7 Kbytes PLTG0064JA-A
R5F212ACSNFP 128 Kbytes 7.5 Kbytes PLQP0064KB-A
R5F212ACSNFA 128 Kbytes 7.5 Kbytes PLQP0064GA-A
R5F212ACSNLG 128 Kbytes 7.5 Kbytes PLTG0064JA-A
R5F212A7SDFP 48 Kbytes 2.5 Kbytes PLQP0064KB-A D version
R5F212A7SDFA 48 Kbytes 2.5 Kbytes PLQP0064GA-A
R5F212A8SDFP 64 Kbytes 3 Kbytes PLQP0064KB-A
R5F212A8SDFA 64 Kbytes 3 Kbytes PLQP0064GA-A
R5F212AASDFP 96 Kbytes 7 Kbytes PLQP0064KB-A
R5F212AASDFA 96 Kbytes 7 Kbytes PLQP0064GA-A
R5F212ACSDFP 128 Kbytes 7.5 Kbytes PLQP0064KB-A
R5F212ACSDFA 128 Kbytes 7.5 Kbytes PLQP0064GA-A
R5F212A7SNXXXFP 48 Kbytes 2.5 Kbytes PLQP0064KB-A N version Factory
programming
product(1)
R5F212A7SNXXXFA 48 Kbytes 2.5 Kbytes PLQP0064GA-A
R5F212A7SNXXXLG 48 Kbytes 2.5 Kbytes PTLG0064JA-A
R5F212A8SNXXXFP 64 Kbytes 3 Kbytes PLQP0064KB-A
R5F212A8SNXXXFA 64 Kbytes 3 Kbytes PLQP0064GA-A
R5F212A8SNXXXLG 64 Kbytes 3 Kbytes PLTG0064JA-A
R5F212AASNXXXFP 96 Kbytes 7 Kbytes PLQP0064KB-A
R5F212AASNXXXFA 96 Kbytes 7 Kbytes PLQP0064GA-A
R5F212AASNXXXLG 96 Kbytes 7 Kbytes PLTG0064JA-A
R5F212ACSNXXXFP 128 Kbytes 7.5 Kbytes PLQP0064KB-A
R5F212ACSNXXXFA 128 Kbytes 7.5 Kbytes PLQP0064GA-A
R5F212ACSNXXXLG 128 Kbytes 7.5 Kbytes PLTG0064JA-A
R5F212A7SDXXXFP 48 Kbytes 2.5 Kbytes PLQP0064KB-A D version
R5F212A7SDXXXFA 48 Kbytes 2.5 Kbytes PLQP0064GA-A
R5F212A8SDXXXFP 64 Kbytes 3 Kbytes PLQP0064KB-A
R5F212A8SDXXXFA 64 Kbytes 3 Kbytes PLQP0064GA-A
R5F212AASDXXXFP 96 Kbytes 7 Kbytes PLQP0064KB-A
R5F212AASDXXXFA 96 Kbytes 7 Kbytes PLQP0064GA-A
R5F212ACSDXXXFP 128 Kbytes 7.5 Kbytes PLQP0064KB-A
R5F212ACSDXXXFA 128 Kbytes 7.5 Kbytes PLQP0064GA-A
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 7 of 580
REJ09B0324-0200
Figure 1.1 Part Number, Memory Size, and Package of R8C/2A Group
Part No. R 5 F 21 2A 7 S N XXX FP
Package type:
FP: PLQP0064KB-A (0.5 mm pin-pitch, 10 mm square body)
FA: PLQP0064GA-A (0.8 mm pin-pitch, 14 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2A Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1: Please contact Renesas Technology sales offices for the Y version.
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 8 of 580
REJ09B0324-0200
NOTE:
1. The user ROM is programmed before shipment.
Table 1.6 Product List for R8C/2B Group Current of Nov. 2007
Part No. ROM Capacity RAM
Capacity Package Type Remarks
Program ROM Data flash
R5F212B7SNFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064KB-A N version
R5F212B7SNFA 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064GA-A
R5F212B7SNLG 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PTLG0064JA-A
R5F212B8SNFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064KB-A
R5F212B8SNFA 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064GA-A
R5F212B8SNLG 64 Kbytes 1 Kbyte × 2 3 Kbytes PTLG0064JA-A
R5F212BASNFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064KB-A
R5F212BASNFA 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064GA-A
R5F212BASNLG 96 Kbytes 1 Kbyte × 2 7 Kbytes PTLG0064JA-A
R5F212BCSNFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064KB-A
R5F212BCSNFA 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064GA-A
R5F212BCSNLG 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PTLG0064JA-A
R5F212B7SDFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064KB-A D version
R5F212B7SDFA 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064GA-A
R5F212B8SDFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064KB-A
R5F212B8SDFA 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064GA-A
R5F212BASDFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064KB-A
R5F212BASDFA 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064GA-A
R5F212BCSDFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064KB-A
R5F212BCSDFA 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064GA-A
R5F212B7SNXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064KB-A N version Factory
programming
product(1)
R5F212B7SNXXXFA 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064GA-A
R5F212B7SNXXXLG 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PTLG0064JA-A
R5F212B8SNXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064KB-A
R5F212B8SNXXXFA 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064GA-A
R5F212B8SNXXXLG 64 Kbytes 1 Kbyte × 2 3 Kbytes PTLG0064JA-A
R5F212BASNXXXFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064KB-A
R5F212BASNXXXFA 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064GA-A
R5F212BASNXXXLG 96 Kbytes 1 Kbyte × 2 7 Kbytes PTLG0064JA-A
R5F212BCSNXXXFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064KB-A
R5F212BCSNXXXFA 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064GA-A
R5F212BCSNXXXLG 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PTLG0064JA-A
R5F212B7SDXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064KB-A D version
R5F212B7SDXXXFA 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0064GA-A
R5F212B8SDXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064KB-A
R5F212B8SDXXXFA 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0064GA-A
R5F212BASDXXXFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064KB-A
R5F212BASDXXXFA 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0064GA-A
R5F212BCSDXXXFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064KB-A
R5F212BCSDXXXFA 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0064GA-A
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 9 of 580
REJ09B0324-0200
Figure 1.2 Part Number, Memory Size, and Package of R8C/2B Group
Part No. R 5 F 21 2B 7 S N XXX FP
Package type:
FP: PLQP0064KB-A (0.5 mm pin-pitch, 10 mm square body)
FA: PLQP0064GA-A (0.8 mm pin-pitch, 14 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2B Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1: Please contact Renesas Technology sales offices for the Y version.
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 10 of 580
REJ09B0324-0200
1.3 Block Diagram
Figure 1.3 shows a Block Diagram.
Figure 1.3 Blo ck Diag ra m
D/A converter
(8 bits × 2) R8C/Tiny Series CPU core Memory
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
8
Port P1
8
Port P3
3 2
Port P4
8
Port P0
8
Port P2
5
Port P5
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RF (16 bits × 1)
UART or
clock synchronous serial I/O
(8 bits × 3)
I2C bus or SSU
(8 bits × 1)
Peripheral functions
Watchdog timer
(15 bits)
A/D converter
(10 bits × 12 channels)
LIN module
8
Port P6
7
Port P8
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 11 of 580
REJ09B0324-0200
1.4 Pin Assignment
Figure 1.4 shows 64-pin LQFP Package Pin Assignment (Top View). Figure 1.5 shows 64-pin FLGA Package Pin
Assignment (Top Perspectiv e View). Tables 1.7 and 1.8 outlines the Pin Name Information by Pin Number.
Figure 1.4 64-pin LQFP Package Pin Assignment (Top View)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
R8C/2A Group
R8C/2B Group
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1 3 4 5 6 7 8 9 10 11 12 13 14 15 162
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P1_0/Kl0/AN8
P3_5/SCL/SSCK
P3_7/SSO
VCC/AVCC
VREF
P0_7/AN0/DA1
VSS/AVSS
P0_6/AN1/DA0
P0_5/AN2/CLK1
P6_1
P6_2
P0_3/AN4
P0_2/AN5
P0_0/AN7
P0_1/AN6
P0_4/AN3
P8_2/TRFO02
P2_6/TRDIOC1
P2_5/TRDIOB1
P2_4/TRDIOA1
P2_3/TRDIOD0
P2_2/TRDIOC0
P2_1/TRDIOB0
P2_0/TRDIOA0/TRDCLK
P1_7/TRAIO/INT1
P1_6/CLK0
P1_5/RXD0/(TRAIO)/(INT1)(2)
P8_6
P8_5/TRFO12
P8_3/TRFO10/TRFI
P8_4/TRFO11
P1_4/TXD0
P1_1/Kl1/AN9
P8_1/TRFO01
P8_0/TRFO00
P6_0/TREO
P4_5/INT0
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P6_5/(CLK1)/CLK2(2)
P6_4/RXD2
P6_3/TXD2
P3_1/TRBO
P3_6/(INT1)(2)
P3_2/(INT2)(2)
P1_2/Kl2/AN10
P1_3/Kl3/AN11
P3_0/TRAO
P3_3/SSI
P2_7/TRDIOD1
P5_0/TRCCLK
P5_1/TRCIOA/TRCTRG
P5_2/TRCIOB
P5_3/TRCIOC
P5_4/TRCIOD
VCC/AVCC
P4_6/XIN
VSS/AVSS
P4_7/XOUT(1)
P4_4/XCOUT
P4_3/XCIN
P3_4/SDA/SCS
MODE
RESET
NOTES:
1. P4_7/XOUT are an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
PLQP0064KB-A(64P6Q-A)
PLQP0064GA-A(64P6U-A)
(top view)
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 12 of 580
REJ09B0324-0200
Figure 1.5 64-pin FLGA Package Pin Assignment (Top Perspective View)
P2_7/
TRDIOD1
P2_6/
TRDIOC1
P2_3/
TRDIOD0
P1_7/TRAIO/
INT
P1_6/CLK0 P8_5/
TRFO12
P4_5/INT0 P6_7/INT3/
RXD1
P4_6/XIN P2_2/
TRDIOC0
P2_0/TRDIOA0/
TRDCLK
P1_4/TXD0 P6_6/INT2/
TXD1
VSS/AVSS P2_4/
TRDIOA1
P2_1/
TRDIOB0
P1_5/RXD0/
(TRAIO)/(INT1)(2)
P8_1/
TRFO01
P4_4/XCOUT P4_3/XCIN P3_5/SCL/
SSCK
P6_2 P6_3/TXD2 P1_3/KI3/
AN11
MODE P3_7/SSO P0_4/AN3 P6_1 P0_5/AN2/
CLK1
P3_1/TRBO
P3_4/SDA/
SCS
P0_0/AN7 P5_2/
TRCIOB
VREF P3_0/TRAO P6_5/CLK2/
(CLK1)(2)
P0_1/AN6 P5_0/
TRCCLK
P0_6/AN1/
DA0
P6_0/TREO P0_2/AN5
P5_4/
TRCIOD
VCC/AVCC P4_7/
XOUT(1)
RESET P8_3/
TRFO10/TRFI
P6_4/RXD2
ABCDEFGH
ABCDEFGH
R5F212A7
SNLG
JAPAN
Pin assignments (top view)
Package: PTLG0064JA-A (64F0G)
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a
program.
P3_3/SSI
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
P0_3/AN4 P1_0/KI0/
AN8
P0_7/AN0/
DA1
P1_1/KI1/
AN9
P5_3/
TRCIOC
P3_6/
(INT1)(2)
P2_5/
TRDIOB1
P3_2/
(INT2)(2)
VCC/AVCC P1_2/KI2/
AN10
VSS/AVSS P8_2/
TRFO02
P8_4/
TRFO11
P5_1/TRCIOA/
TRCTRG
P8_6 P8_0/
TRFO00
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 13 of 580
REJ09B0324-0200
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Table 1.7 Pin Name Information by Pin Number (1)
Pin
Number Control Pin Port
I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial
Interface SSU I2C bus
A/D Converter,
D/A Converter
1 P3_3 SSI
2 P3_4 SCS SDA
3MODE
4 XCIN P4_3
5 XCOUT P4_4
6RESET
7 XOUT P4_7
8 VSS/AVSS
9 XIN P4_6
10 VCC/AVCC
11 P5_4 TRCIOD
12 P5_3 TRCIOC
13 P5_2 TRCIOB
14 P5_1 TRCIOA/TRCTRG
15 P5_0 TRCCLK
16 P2_7 TRDIOD1
17 P2_6 TRDIOC1
18 P2_5 TRDIOB1
19 P2_4 TRDIOA1
20 P2_3 TRDIOD0
21 P2_2 TRDIOC0
22 P2_1 TRDIOB0
23 P2_0 TRDIOA0/TRDCLK
24 P1_7 INT1 TRAIO
25 P1_6 CLK0
26 P1_5 (INT1)(1) (TRAIO)(1) RXD0
27 P1_4 TXD0
28 P8_6
29 P8_5 TRFO12
30 P8_4 TRFO11
31 P8_3 TRFO10/TRFI
32 P8_2 TRFO02
33 P8_1 TRFO01
34 P8_0 TRFO00
35 P6_0 TREO
36 P4_5 INT0 INT0
37 P6_6 INT2 TXD1
38 P6_7 INT3 RXD1
39 P6_5 (CLK1)(1)/
CLK2
40 P6_4 RXD2
41 P6_3 TXD2
42 P3_1 TRBO
43 P3_0 TRAO
44 P3_6 (INT1)(1)
45 P3_2 (INT2)(1)
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 14 of 580
REJ09B0324-0200
Table 1.8 Pin Name Information by Pin Number (2)
Pin
Number Control Pin Port
I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial
Interface SSU I2C bus
A/D Converter,
D/A Converter
46 P1_3 Kl3 AN11
47 P1_2 KI2 AN10
48 P1_1 KI1 AN9
49 P1_0 KI0 AN8
50 P0_0 AN7
51 P0_1 AN6
52 P0_2 AN5
53 P0_3 AN4
54 P0_4 AN3
55 P6_2
56 P6_1
57 P0_5 CLK1 AN2
58 P0_6 AN1/DA0
59 VSS/AVSS
60 P0_7 AN0/DA1
61 VREF
62 VCC/AVCC
63 P3_7 SSO
64 P3_5 SSCK SCL
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 15 of 580
REJ09B0324-0200
1.5 Pin Functions
Tables 1.9 and 1.10 list Pin Functions.
I: Input O: Output I/O: Input and output
NOTE:
1. Refer to the oscillator manufacturer for oscillation characteristics.
Table 1.9 Pin Functions (1)
Item Pin Name
I/O Type
Description
Power supply input VCC, VSS −Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS −Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins(1). To use an external clock, input it
to the XIN pin and leave the XOUT pin open.
XIN clock output XOUT O
XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins(1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
XCIN clock output XCOUT O
INT interrupt input INT0 to INT3 IINT interrupt input pins.
INT0 is timer RD input pin. INT1 is timer RA input pin.
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAIO I/O Timer RA I/O pin
TRAO O Timer RA output pin
Timer RB TRBO O Timer RB output pin
Timer RC TRCCLK I External clock input pin
TRCTRG I External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O Timer RC I/O pins
Timer RD TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O Timer RD I/O pins
TRDCLK I External clock input pin
Timer RE TREO O Divided clock output pin
Timer RF TRFI I Timer RF input pin
TRFO00 to TRFO02,
TRFO10 to TRFO12
O Timer RF output pins
Serial interface CLK0, CLK1, CLK2 I/O Transfer clock I/O pins
RXD0, RXD1, RXD2 I Serial data input pins
TXD0, TXD1, TXD2 O Serial data output pins
I2C bus SCL I/O Clock I/O pin
SDA I/O Data I/O pin
SSU SSI I/O Data I/O pin
SCS I/O Chip-select signal I/O pin
SSCK I/O Clock I/O pin
SSO I/O Data I/O pin
Reference voltage
input
VREF I Reference voltage input pin to A/D converter and D/A
converter
R8C/2A Group, R8C/2B Group 1. Overview
Rev.2.00 Nov 26, 2007 Page 16 of 580
REJ09B0324-0200
I: Input O: Output I/O: Input and output
Table 1.10 Pin Functions (2)
Item Pin Name
I/O Type
Description
A/D converter AN0 to AN11 I Analog input pins to A/D converter
D/A converter DA0 to DA1 O D/A converter output pins
I/O port P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_5,
P5_0 to P5_4,
P6_0 to P6_7,
P8_0 to P8_6
I/O CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.
Input port P4_6, P4_7 I Input-only ports
R8C/2A Group, R8C/2B Group 2. Central Processing Unit (CPU)
Rev.2.00 Nov 26, 2007 Page 17 of 580
REJ09B0324-0200
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1 CPU Registers
R2
b31 b15 b8b7 b0
Data registers(1)
Address registers(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15b19 b0
INTBL
FB Frame base register(1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
R8C/2A Group, R8C/2B Group 2. Central Processing Unit (CPU)
Rev.2.00 Nov 26, 2007 Page 18 of 580
REJ09B0324-0200
2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer , arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/2A Group, R8C/2B Group 2. Central Processing Unit (CPU)
Rev.2.00 Nov 26, 2007 Page 19 of 580
REJ09B0324-0200
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/2A Group, R8C/2B Group 3. Memory
Rev.2.00 Nov 26, 2007 Page 20 of 580
REJ09B0324-0200
3. Memory
3.1 R8C/2A Grou p
Figure 3.1 is a Memory Map of R8C/2A Group. The R8C/2A group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0 FFFFh. For exam ple, a 48 -Kbyte i nternal
ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.1 Memory Map of R8C/2A Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
(Reserved)
(Reserved)
Reset
Internal ROM Internal RAM
Size Address 0YYYYh
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
−
13FFFh
1BFFFh
23FFFh
00DFFh
00FFFh
011FFh
011FFh
00400h
002FFh
00000h
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
Address 0XXXXh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address ZZZZZh Size
2.5 Kbytes
3 Kbytes
7 Kbytes
7.5 Kbytes
04000h
04000h
04000h
04000h
FFFFFh
0FFFFh
0YYYYh
Internal ROM
(program ROM)
Expanded area
Internal ROM
(program ROM)
ZZZZZh
0XXXXh
03000h
Internal RAM
0WWWWh
−
−
03DFFh
03FFFh
Address 0WWWWh
R8C/2A Group, R8C/2B Group 3. Memory
Rev.2.00 Nov 26, 2007 Page 21 of 580
REJ09B0324-0200
3.2 R8C/2B Grou p
Figure 3.2 is a Memory Map of R8C/2B Group. The R8C/2B group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.2 Memory Map of R8C/2B Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
(Reserved)
(Reserved)
Reset
Internal ROM Internal RAM
Size Address 0YYYYh
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
00DFFh
00FFFh
011FFh
011FFh
FFFFFh
0FFFFh
0YYYYh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Expanded area
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
Address 0XXXXh
Address ZZZZZh Size
2.5 Kbytes
3 Kbytes
7 Kbytes
7.5 Kbytes
Internal ROM
(data flash)(1)
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
0XXXXh
02400h
02BFFh
Internal ROM
(program ROM)
ZZZZZh
−
13FFFh
1BFFFh
23FFFh
04000h
04000h
04000h
04000h
Address 0WWWWh
−
−
03DFFh
03FFFh
03000h
Internal RAM
0WWWWh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 22 of 580
REJ09B0324-0200
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1 SFR Information (1)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
6. The CSPROINI bit in the OFS register is set to 0.
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h Module Operation Enable Register MSTCR 00h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation Stop Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
10000000b(6)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0029h
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When Shipping
002Ch High-Speed On-Chip Oscillator Control Register 7 FRA7 When Shipping
0030h
0031h Voltage Detection Register 1(2) VCA1 00001000b
0032h Voltage Detection Register 2(2) VCA2 00h(3)
00100000b(4)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register(5) VW1C 00001000b
0037h Voltage Monitor 2 Circuit Control Register(5) VW2C 00h
0038h Voltage Monitor 0 Circuit Control Register(2) VW0C 0000X000b(3)
0100X001b(4)
0039h
003Ah
003Eh
003Fh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 23 of 580
REJ09B0324-0200
Table 4.2 SFR Information (2)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Address Register Symbol After reset
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register TRCIC XXXXX000b
0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b
0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b
004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh
004Fh SSU/IIC Interrupt Control Register(2) SSUIC / IICIC XXXXX000b
0050h Compare 1 Interrupt Control Register CMP1IC XXXXX000b
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h INT2 Interrupt Control Register INT2IC XX00X000b
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh Timer RF Interrupt Control Register TRFIC XXXXX000b
005Ch Compare 0 Interrupt Control Register CMP0IC XXXXX000b
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
005Fh Capture Interrupt Control Register CAPIC XXXXX000b
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 24 of 580
REJ09B0324-0200
Table 4.3 SFR Information (3)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Address Register Symbol After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Rate Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Rate Register U1BRG XXh
00AAh UART1 Transmit Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(2) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(2) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Register(2) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(2) SSER / ICIER 00h
00BCh SS Status Register / IIC bus Status Register(2) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register(2) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(2) SSRDR / ICDRR FFh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 25 of 580
REJ09B0324-0200
Table 4.4 SFR Information (4)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h D/A Register 0 DA0 00h
00D9h
00DAh D/A Register 1 DA1 00h
00DBh
00DCh D/A Control Register DACON 00h
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 XXh
00E1h Port P1 Register P1 XXh
00E2h Port P0 Direction Register PD0 00h
00E3h Port P1 Direction Register PD1 00h
00E4h Port P2 Register P2 XXh
00E5h Port P3 Register P3 XXh
00E6h Port P2 Direction Register PD2 00h
00E7h Port P3 Direction Register PD3 00h
00E8h Port P4 Register P4 XXh
00E9h Port P5 Register P5 XXh
00EAh Port P4 Direction Register PD4 00h
00EBh Port P5 Direction Register PD5 00h
00ECh Port P6 Register P6 XXh
00EDh
00EEh Port P6 Direction Register PD6 00h
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h Port P2 Drive Capacity Control Register P2DRR 00h
00F5h UART1 Function Select Register U1SR 000000XXb
00F6h
00F7h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 XX000000b
00FEh
00FFh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 26 of 580
REJ09B0324-0200
Table 4.5 SFR Information (5)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions
Address Register Symbol After reset
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h LIN Control Register 2 LINCR2 00h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h
0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h
011Ah Timer RE Hour Data Register TREHR 00h
011Bh Timer RE Day of Week Data Register TREWK 00h
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Clock Source Select Register TRECSR 00001000b
011Fh
0120h Timer RC Mode Register TRCMR 01001000b
0121h Timer RC Control Register 1 TRCCR1 00h
0122h Timer RC Interrupt Enable Register TRCIER 01110000b
0123h Timer RC Status Register TRCSR 01110000b
0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b
0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b
0126h Timer RC Counter TRC 00h
0127h 00h
0128h Timer RC General Register A TRCGRA FFh
0129h FFh
012Ah Timer RC General Register B TRCGRB FFh
012Bh FFh
012Ch Timer RC General Register C TRCGRC FFh
012Dh FFh
012Eh Timer RC General Register D TRCGRD FFh
012Fh FFh
0130h Timer RC Control Register 2 TRCCR2 00011111b
0131h Timer RC Digital Filter Function Select Register TRCDF 00h
0132h Timer RC Output Master Enable Register TRCOER 01111111b
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR 11111100b
0138h Timer RD Mode Register TRDMR 00001110b
0139h Timer RD PWM Mode Register TRDPMR 10001000b
013Ah Timer RD Function Control Register TRDFCR 10000000b
013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh
013Ch Timer RD Output Master Enable Register 2 TRDOER2 01111111b
013Dh Timer RD Output Control Register TRDOCR 00h
013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h
013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 27 of 580
REJ09B0324-0200
Table 4.6 SFR Information (6)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0140h Timer RD Control Register 0 TRDCR0 00h
0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b
0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b
0143h Timer RD Status Register 0 TRDSR0 11000000b
0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b
0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b
0146h Timer RD Counter 0 TRD0 00h
0147h 00h
0148h Timer RD General Register A0 TRDGRA0 FFh
0149h FFh
014Ah Timer RD General Register B0 TRDGRB0 FFh
014Bh FFh
014Ch Timer RD General Register C0 TRDGRC0 FFh
014Dh FFh
014Eh Timer RD General Register D0 TRDGRD0 FFh
014Fh FFh
0150h Timer RD Control Register 1 TRDCR1 00h
0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b
0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b
0153h Timer RD Status Register 1 TRDSR1 11000000b
0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b
0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b
0156h Timer RD Counter 1 TRD1 00h
0157h 00h
0158h Timer RD General Register A1 TRDGRA1 FFh
0159h FFh
015Ah Timer RD General Register B1 TRDGRB1 FFh
015Bh FFh
015Ch Timer RD General Register C1 TRDGRC1 FFh
015Dh FFh
015Eh Timer RD General Register D1 TRDGRD1 FFh
015Fh FFh
0160h UART2 Transmit/Receive Mode Register U2MR 00h
0161h UART2 Bit Rate Register U2BRG XXh
0162h UART2 Transmit Buffer Register U2TB XXh
0163h XXh
0164h UART2 Transmit/Receive Control Register 0 U2C0 00001000b
0165h UART2 Transmit/Receive Control Register 1 U2C1 00000010b
0166h UART2 Receive Buffer Register U2RB XXh
0167h XXh
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 28 of 580
REJ09B0324-0200
Table 4.7 SFR Information (7)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 29 of 580
REJ09B0324-0200
Table 4.8 SFR Information (8)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 30 of 580
REJ09B0324-0200
Table 4.9 SFR Information (9)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 31 of 580
REJ09B0324-0200
Table 4.10 SFR Information (10 )(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 32 of 580
REJ09B0324-0200
Table 4.11 SFR Information (11)(1)
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. After input capture mode.
3. After output compare mode.
Address Register Symbol After reset
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h Timer RF Register TRF 00h
0291h 00h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah Timer RF Control Register 0 TRFCR0 00h
029Bh Timer RF Control Register 1 TRFCR1 00h
029Ch Capture / Compare 0 Register TRFM0 0000h(2)
029Dh FFFFh(3)
029Eh Compare 1 Register TRFM1 FFh
029Fh FFh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs)
Rev.2.00 Nov 26, 2007 Page 33 of 580
REJ09B0324-0200
Table 4.12 SFR Information (12 )(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Address Register Symbol After reset
02C0h A/D Register 0 AD0 XXh
02C1h XXh
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h A/D Control Register 2 ADCON2 00001000b
02D5h
02D6h A/D Control Register 0 ADCON0 00000011b
02D7h A/D Control Register 1 ADCON1 00h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h Port P8 Direction Register PD8 00h
02E5h
02E6h Port P8 Register P8 XXh
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh Pull-Up Control Register 2 PUR2 XXX00000b
02FDh
02FEh
02FFh Timer RF Output Control Register TRFOUT 00h
FFFFh Option Function Select Register OFS (Note 2)
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 34 of 580
REJ09B0324-0200
5. Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset,
voltage monitor 2 reset, watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources.
Figure 5.1 Block Diagra m of Rese t Circ ui t
Table 5.1 Reset Names and Sour ce s
Reset Name Source
Hardware reset Input voltage of RESET pin is held “L”
Power-on reset VCC rises
Voltage monitor 0 reset VCC falls (monitor voltage: Vdet0)
Voltage monitor 1 reset VCC falls (monitor voltage: Vdet1)
Voltage monitor 2 reset VCC falls (monitor voltage: Vdet2)
Watchdog timer reset Underflow of watchdog timer
Software reset Write 1 to PM03 bit in PM0 register
RESET
Power-on reset
circuit
Voltage
detection
circuit
Watchdog
timer
CPU
Voltage monitor 0 reset
SFRs
Bits VCA25,
VW0C0, and
VW0C6
SFRs
Bits VCA13, VCA26, VCA27,
VW1C2, VW1C3,
VW2C2, VW2C3,
VW0C1, VW0F0,
VW0F1, and VW0C7
Pin, CPU, and
SFR bits other than
those listed above
VCC
Hardware reset
Power-on reset
Voltage monitor 1 reset
Watchdog timer
reset
Software reset
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
Voltage monitor 2
reset
SFRs
Bits VCA25,
VW0C0, and
VW0C6
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 35 of 580
REJ09B0324-0200
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.
Figure 5.2 CPU Register Status after Reset
Table 5.2 Pin Functions while RESET Pin Level is “L”
Pin Name Pin Functions
P0 to P3 Input port
P4_3 to P4_7 Input port
P5_0 to P5_4 Input port
P6 Input port
P8_0 to P8_6 Input port
b19 b0
Interrupt table register(INTB)
Program counter(PC)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Content of addresses 0FFFEh to 0FFFCh
Flag register(FLG)
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
b15 b0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
00000h
0000h
0000h
0000h
0000h
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 36 of 580
REJ09B0324-0200
Figure 5.3 Reset Sequence
Figure 5.4 OFS Register
Start time of flash memory
(CPU clock × 14 cycles)
0FFFCh 0FFFEh
0FFFDh Content of reset vector
CPU clock
Address
(internal address
signal)
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
CPU clock × 28 cycles
fOCO-S clock × 32 cycles(2)
fOCO-S
Internal reset
signal
RESET pin
10 cycles or more are needed(1)
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 37 of 580
REJ09B0324-0200
5.1 Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the suppl y voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.5 shows a n Example of Hardware Reset Circuit and O peration and Figure 5.6 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1 When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs or more.
(3) Apply “H” to the RESET pin.
5.1.2 Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 21. Electrical
Characteristics).
(4) Wait for 10 µs or more.
(5) Apply “H” to the RESET pin.
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 38 of 580
REJ09B0324-0200
Figure 5.5 Example of Hardware Reset Circuit and Operation
Figure 5.6 Exam p le o f Hardwa re Re se t Circ ui t (Us a ge Exa mple of External Suppl y Voltage
Detection Circuit) and Operation
RESET
VCC
VCC
RESET
2.2 V
0 V
0.2 VCC or below
td(P-R) + 10 µs or more
0 V
NOTE:
1. Refer to 21. Electrical Characteristics.
RESET VCC
VCC
RESET
2.2 V
0 V
0 V
5 V
5 V
Example when
VCC = 5 V
Supply voltage
detection circuit
NOTE:
1. Refer to 21. Electrical Characteristics.
td(P-R) + 10 µs or more
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 39 of 580
REJ09B0324-0200
5.2 Power-On Reset Function
When the RESET pin is connected to the V CC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
Figure 5.7 Example of Power-On Reset Circuit and Operation
RESET
VCC
4.7 kΩ
(reference)
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 21. Electrical Character is tics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
Vdet0(3)
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
2.2V
External
Power VCC
trth
trth
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 40 of 580
REJ09B0324-0200
5.3 Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware
reset. Setting the LVD0ON bit is only valid after a hardware reset.
To use the power-on reset function, enable volt age monitor 0 reset by setti ng the LVD0ON bit in the OFS register
to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register
to 1.
The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset
enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
5.4 Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are
reset and a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.5 Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin
reaches
the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
R8C/2A Group, R8C/2B Group 5. Resets
Rev.2.00 Nov 26, 2007 Page 41 of 580
REJ09B0324-0200
5.6 Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchd og timer underflows. Then t he program beginning with t he address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog tim er un derflows, the contents of internal RAM are undefined.
Refer to 13. Watchdog Timer for details of the watchdog timer.
5.7 Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is auto matically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) fo r detai ls.
The internal RAM is not reset.
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 42 of 580
REJ09B0324-0200
6. Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor th e VCC
input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset,
voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures
6.5 to 6.8 show the Associated Registers.
Table 6.1 Specifications of Voltage Detection Circuit
Item Voltage Detection 0 Voltage Detection 1 Voltage Detection 2
VCC Monitor Voltage to monitor Vdet0 Vdet1 Vdet2
Detection target Whether passing
through Vdet0 by rising
or falling
Passing through Vdet1 by
rising or falling
Passing through Vdet2 by
rising or falling
Monitor None VW1C3 bit in VW1C
register
VCA13 bit in VCA1
register
Whether VCC is higher or
lower than Vdet1
Whether VCC is higher or
lower than Vdet2
Process
When Voltage
is Detected
Reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset
Reset at Vdet0 > VCC;
restart CPU operation at
VCC > Vdet0
Reset at Vdet1 > VCC;
restart CPU operation
after a specified time
Reset at Vdet2 > VCC;
restart CPU operation
after a specified time
Interrupt None Voltage monitor 1 interrupt Voltage monitor 2 interrupt
Interrupt request at Vdet1
> VCC and VCC > Vdet1
when digital filter is
enabled;
interrupt request at Vdet1
> VCC or VCC > Vdet1
when digital filter is
disabled
Interrupt request at Vdet2
> VCC and VCC > Vdet2
when digital filter is
enabled;
interrupt request at Vdet2
> VCC or VCC > Vdet2
when digital filter is
disabled
Digital Filter Switch
enabled/disabled
Available Available Available
Sampling time (Divide-by-n of fOCO-S)
× 4
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S)
× 4
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S)
× 4
n: 1, 2, 4, and 8
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 43 of 580
REJ09B0324-0200
Figure 6.1 Block Diag ra m of Voltage Detection Circuit
Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit
≥ Vdet2
VCA27
+
-
VCC
b3
VCA13 bit
VCA1 register
Voltage detection 2
signal
Voltage detection 1
signal
Internal
reference
voltage
VCA26
+
-≥ Vdet1
VCA25
+
-≥ Vdet0
Voltage detection 0
signal
b3
VW1C3 bit
VW1C register
Noise
filter
Noise
filter
+
-
1/2 1/2 1/2
Voltage detection 0 circuit
VCA25
VCC
Internal
reference
voltage
Voltage detection 0
signal is held “H” when
VCA25 bit is set to 0
(disabled)
Voltage
detection 0
signal
fOCO-S
VW0F1 to VW0F0
= 00b
= 01b
= 10b
= 11b
VW0C7
Voltage monitor 0
reset signal
Voltage monitor 0 reset generation circuit
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register
VCA25: Bit in VCA2 register
VW0C0
VW0C6
VW0C1
VW0C1
Digital
filter
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 44 of 580
REJ09B0324-0200
Figure 6.3 Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
+
-
1/2 1/2 1/2
Voltage detection 1 circuit
VCA26
VCC
Internal
reference
voltage
VW1C3
Noise filter
(Filter width: 200 ns)
Voltage detection 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
Voltage
detection
1 signal
Digital
filter
fOCO-S
VW1F1 to VW1F0
= 00b
= 01b
= 10b
= 11b
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
Voltage monitor 1 interrupt/reset generation circuit
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA26: Bit in VCA2 register
VW1C1
VW1C1
VW1C2
VW1C7
VW1C0
VW1C6
Non-maskable
interrupt signal
Voltage monitor 1
interrupt signal
Watchdog
timer interrupt
signal
Oscillation stop
detection
interrupt signal
Voltage monitor 1
reset signal
+
-
1/2 1/2 1/2
Voltage detection 2 circuit
VCA27
VCC
Internal
reference
voltage
VCA13
Noise filter
(Filter width: 200 ns)
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Voltage
detection
2 signal
Digital
filter
fOCO-S
VW2F1 to VW2F0
= 00b
= 01b
= 10b
= 11b
VW2C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
VW2C3
Watchdog timer block
Watchdog timer
underflow signal This bit is set to 0 (not detected) by writing 0
by a program.
Voltage monitor 2 interrupt/reset generation circuit
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
VW2C1
VW2C1
VW2C2
VW2C7
VW2C0
VW2C6
Non-maskable
interrupt signal
Voltage monitor 2
interrupt signal
Watchdog
timer interrupt
signal
Oscillation stop
detection
interrupt signal
Voltage monitor 2
reset signal
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 45 of 580
REJ09B0324-0200
Figure 6.5 Regis te rs VCA1 an d VCA2
Voltage Detection Register 1
Symbol Address After Reset(2)
VCA1 0031h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
VCA13
Voltage detection 2 signal monitor
flag(1)
00
—
(b2-b0) RW
0 : VCC < Vdet2
1 : VCC ≥ Vdet2 or voltage detection 2
circuit disabled
RO
Reserved bits
b0
0000
Set to 0.
0
b7 b6 b5 b4 b3 b2 b1
The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled).
—
(b7-b4)
Reserved bits Set to 0. RW
Voltage Detection Register 2(1)
Symbol Address After Reset(5)
VCA2 0032h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset : 00100000b
VCA25 Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled RW
—
(b4-b1)
Reserved bits Set to 0. RW
b7 b6 b5 b4 b3 b2 b1 b0
0000
VCA26 Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled RW
VCA27 Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled RW
Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
1 0.1 0 Procedure for Ena bling Reduced Internal Power Consumption Usi ng VCA20 bi t.
VCA20 Internal pow er low
consumption enable bit(6)
0 : Disables low consumption
1 : Enables low consumption RW
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 46 of 580
REJ09B0324-0200
Figure 6.6 VW0C Register
Voltage Monitor 0 Circuit Control Register (1)
Symbol Address
VW0C 0038h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 0000X000b
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is set
to 0, and hardw are reset : 0100X001b
After Reset(2)
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW0C register.
The value remains unchanged af ter a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
VW0C6
Voltage monitor 0 circuit
mode select bit
When the VW0C0 bit is set to 1 (voltage monitor 0
reset enabled), set to 1. RW
—
(b3)
Reserved bit
The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
VW0C7
Voltage monitor 0 reset
generation condition select
bit(4)
When the VW0C1 bit is set to 1 (digital filter
disabled mode), set to 1. RW
VW0F1 RW
Sampling clock select bits b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
VW0F0 RW
When read, the content is undefined. RO
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW0C2 Reserved bit
VW0C1
Voltage monitor 0 digital filter
disable mode select bit
VW0C0 RW
Voltage monitor 0 reset
enable bit(3)
0 : Disable
1 : Enable
0
b7 b6 b5 b4
The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
b3 b2
Set to 0. RW
b1 b0
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 47 of 580
REJ09B0324-0200
Figure 6.7 VW1C Register
Voltage Monitor 1 Circuit Control Register (1)
Symbol Address After Reset(8)
VW1C 0036h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset).
The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
VW1C7
Voltage monitor 1 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet1 or above
1 : When VCC reaches Vdet1 or below RW
VW1C6 Voltage monitor 1 circuit mode
select bit(5)
0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode RW
VW1C3
Voltage detection 1 signal monitor
flag(3, 8)
VW1F1 RW
Sampling clock select bits b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
VW1F0 RW
0 : V CC < V det1
1 : V CC ≥ Vdet1 or voltage detection 1
circuit disabled
RO
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW1C2 Voltage change detection
flag(3, 4, 8)
VW1C1
Voltage monitor 1 digital filter
disable mode select bit(2)
VW1C0 RW
Voltage monitor 1 interrupt/reset
enable bit(6)
0 : Disable
1 : Enable
b7 b6 b5 b4 b2
0 : Not detected
1 : Vdet1 crossing detected RW
b1 b0b3
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 48 of 580
REJ09B0324-0200
Figure 6.8 VW2C Register
Volta
g
e Monitor 2 Circuit Control Re
g
ister (1)
Symbol Address After Reset(8)
VW2C 0037h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2
or below ). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register.
To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1
bit before w riting 1.
The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset).
The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).
Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
VW2C7
Voltage monitor 2 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet2 or above
1 : When VCC reaches Vdet2 or below RW
VW2C6 Voltage monitor 2 circuit mode
select bit(5)
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode RW
VW2C3 WDT detection flag(4, 8)
VW2F1 RW
Sampling clock select bits b5 b4
0 0 : f OCO-S divided by 1
0 1 : f OCO-S divided by 2
1 0 : f OCO-S divided by 4
1 1 : f OCO-S divided by 8
VW2F0 RW
0 : Not detected
1 : Detected RW
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW2C2 Voltage change detection
flag(3, 4, 8)
VW2C1
Voltage monitor 2 digital filter
disable mode select bit(2)
VW2C0 RW
Voltage monitor 2 interrupt/reset
enable bit(6)
0 : Disable
1 : Enable
b7 b6 b5 b4 b3 b2
0 : Not detected
1 : VCC has crossed Vdet2 RW
b1 b0
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 49 of 580
REJ09B0324-0200
6.1 VCC Input Voltage
6.1.1 Monitoring Vdet0
Vdet0 cannot be monitored.
6.1.2 Monitoring Vdet1
Set the VCA 26 bit in the VCA2 r egister to 1 (vol tage detection 1 circuit enabled ). After td(E-A ) has elapsed
(refer to 21. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW 1C register.
6.1.3 Monitoring Vdet2
Set the VCA 27 bit in the VCA2 r egister to 1 (vol tage detection 2 circuit enabled ). After td(E-A ) has elapsed
(refer to 21. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA 1 regi ster.
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 50 of 580
REJ09B0324-0200
6.2 Voltage Monitor 0 Reset
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.9 shows an
Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the
VW0C1 bit in the VW0C reg ister to 1 (digital filter disabled).
NOTE:
1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Figure 6.9 Example of Voltage Monit or 0 Reset Operation
Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor Reset
Step When Using Digital Filter When Not Using Digital Filter
1 Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)
2 Wait for td(E-A)
3
Select the sampling clock of the digital filter
by the VW0F0 to VW0F1 bits in the VW0C
register
Set the VW0C7 bit in the VW0C register to
1
4(1) Set the VW0C1 bit in the VW0C register to
0 (digital filter enabled)
Set the VW0C1 bit in the VW0C register to
1 (digital filter disabled)
5(1) Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)
6 Set the VW0C2 bit in the VW0C register to 0
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
−
8 Wait for 4 cycles of the sampling clock of
the digital filter
− (No wait time required)
9 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
Vdet0
Internal reset signal
VCC
The above applies under the following conditions.
• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
1
fOCO-S × 32
Sampling clock of
digital filter × 4 cycles
When the VW0C1 bit is set
to 0 (digital filter enabled)
Internal reset signal
When the VW0C1 bit is set
to 1 (digital filter disabled)
and the VW0C7 bit is set
to 1
1
fOCO-S × 32
VW0C1 and VW0C7: Bits in VW0C register
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 51 of 580
REJ09B0324-0200
6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.10
shows an Example of Vo ltage Monitor 1 Interrupt and Vo ltage Monitor 1 Reset Operation. To use the voltage
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
Step
When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
2 Wait for td(E-A)
3
Select the sampling clock of the digital filter
by the VW1F0 to VW1F1 bits in the VW1C
register
Select the timing of the interrupt and reset
request by the VW1C7 bit in the VW1C
register(1)
4(2) Set the VW1C1 bit in the VW1C register to 0
(digital filter enabled)
Set the VW1C1 bit in the VW1C register to 1
(digital filter disabled)
5(2) Set the VW1C6 bit in
the VW1C register to
0 (voltage monitor 1
interrupt mode)
Set the VW1C6 bit in
the VW1C register to
1 (voltage monitor 1
reset mode)
Set the VW1C6 bit in
the VW1C register to
0 (voltage monitor 1
interrupt mode)
Set the VW1C6 bit in
the VW1C register to
1 (voltage monitor 1
reset mode)
6 Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected)
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
-
8 Wait for 4 cycles of the sampling clock of the
digital filter
− (No wait time required)
9 Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 52 of 580
REJ09B0324-0200
Figure 6.10 Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
Vdet1
VW1C3 bit
Internal reset signal
(VW1C6 = 1)
VCC
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
2.2 V(1)
0
1
4 cycles of sampling clock of
digital filter
VW1C2 bit
0
1
When the VW1C1 bit is set
to 0 (digital filter enabled)
VW1C2 bit
0
1
When the VW1C1 bit is
set to 1 (digital filter
disabled) and the
VW1C7 bit is set to 0
(Vdet1 or above)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
VW1C2 bit
0
1
When the VW1C1 bit is
set to 1 (digital filter
disabled) and the
VW1C7 bit is set to 1
(Vdet1 or below)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
4 cycles of sampling clock of
digital filter
Set to 0 by a program
Set to 0 by interrupt
request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt
request acknowledgement
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 53 of 580
REJ09B0324-0200
6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.11
shows an Example of Vo ltage Monitor 2 Interrupt and Vo ltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
Step
When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
1 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
2 Wait for td(E-A)
3
Select the sampling clock of the digital filter
by the VW2F0 to VW2F1 bits in the VW2C
register
Select the timing of the interrupt and reset
request by the VW2C7 bit in the VW2C
register(1)
4Set the VW2C1 bit in the VW2C register to 0
(digital filter enabled)
Set the VW2C1 bit in the VW2C register to 1
(digital filter disabled)
5(2) Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
6 Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
-
8 Wait for 4 cycles of the sampling clock of the
digital filter
− (No wait time required)
9 Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit
Rev.2.00 Nov 26, 2007 Page 54 of 580
REJ09B0324-0200
Figure 6.11 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
Vdet2
VCA13 bit
Internal reset signal
(VW2C6 = 1)
VCC
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)
NOTE:
1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
2.2 V(1)
0
1
4 cycles of sampling clock of
digital filter
VW2C2 bit
0
1
When the VW2C1 bit is set
to 0 (digital filter enabled)
VW2C2 bit
0
1
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 0
(Vdet2 or above)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
VW2C2 bit
0
1
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 1
(Vdet2 or below)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
4 cycles of sampling clock of
digital filter
Set to 0 by a program
Set to 0 by interrupt
request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt
request acknowledgement
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 55 of 580
REJ09B0324-0200
7. Programmable I/O Ports
There are 55 programmable Input/Output ports (I/O p orts) P0 to P3, P4_3 to P4_5, P5_0 to P5_4, P6, and P8_ 0 to
P8_6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used.
Table 7.1 lists a n Ov erview of Programmab le I/O Ports.
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers
PUR0, PUR1, and PUR2.
2. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.
7.1 Functions of Programmable I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 6, 8) register controls I/O of the ports P0 to P3, P4_3 to P4_5, P5_0 to
P5_4, P6, and P8_0 to P8_6. The Pi register consists of a port latch to hold output data and a circuit to read pin
states.
Figures 7.1 to 7.10 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of
Programmable I/O Ports. Also, Figure 7.12 shows the PDi (i = 0 to 6 and 8) Registers. Figure 7.13 shows the Pi (i =
0 to 6 and 8) Registers, Figure 7.14 shows the P2DRR Register, Figure 7.15 shows the PMR Reg ister, and Figure
7.16 shows Registers PUR0, PUR1, and PUR2.
i = 0 to 6, 8, j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD4_0 to PD4_2, PD4_6, and PD4_7.
Table 7.1 O v erv iew of Programmable I/O Ports
Ports I/O Type of Output I/O Setting Internal Pull-Up Resister
P0 to P3, P5_0 to P5_3,
P6, P8_0 to P8_3 I/O CMOS3 State Set per bit Set every 4 bits(1)
P4_3, P5_4 I/O CMOS3 State Set per bit Set every bit(1)
P4_4, P4_5 I/O CMOS3 State Set per bit Set every 2 bits(1)
P4_6, P4_7(2) I (No output function) None None
P8_4 to P8_6 I/O CMOS3 State Set per bit Set every 3 bits(1)
Table 7.2 Functions of Programmable I/O Ports
Operation When
Accessing
Pi Register
Value of PDi_j Bit in PDi Register(1)
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Reading Read pin input level Read the port latch
Writing Write to the port latch Write to the port latch. The value written to
the port latch is output from the pin.
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 56 of 580
REJ09B0324-0200
7.2 Effect on Peripheral Functions
Programmable I/ O port s function as I/O ports for peripheral functions (Refer to Table 1.7 Pin Name Information
by Pin Number (1) and Table 1.8 Pin Name Information by Pin Number (2)).
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 6, 8, j = 0 to
7).
Refer to the description of each function for information on how to set peripheral functions.
7.3 Pins Other than Programmable I/O Ports
Figure 7.11 shows the Configuration of I/O Pins.
Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions
(i = 0 to 6, 8, j = 0 to 7)
I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions
Input Set this bit to 0 (input mode).
Output This bit can be set to either 0 or 1 (output regardless of the port setting)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 57 of 580
REJ09B0324-0200
Figure 7.1 Configuration of Programmable I/O Ports (1)
P0_0 to P0_4
Direction
register
Port latchData bus
Pull-up selection
Analog input
P0_6 and P0_7
Direction
register
Port latchData bus
Pull-up selection
Analog input
Analog output
D/A converter output enable
P0_5
Direction
register
1
Analog input
Data bus
Pull-up selection
Input to individual peripheral function
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Output from individual peripheral function
Port latch
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 58 of 580
REJ09B0324-0200
Figure 7.2 Configuration of Programmable I/O Ports (2)
P1_5 and P1_7
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual peripheral function
INT1 input Digital
filter
P1_4
Direction
register
1
Data bus
Pull-up selection
Output from individual peripheral function
Port latch
P1_0 to P1_3
Direction
register
1
Output from individual peripheral function
Analog input
Port latchData bus
Pull-up selection
Input to individual peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 59 of 580
REJ09B0324-0200
Figure 7.3 Configuration of Programmable I/O Ports (3)
P3_0 and P3_1
Direction
register
Data bus
Pull-up selection
1
Output from individual peripheral function
Port latch
Direction
register
1
Data bus
Pull-up selection
Input to individual peripheral function
Output from individual peripheral function
P2 Drive capacity selection
Drive capacity selection
P1_6
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
Port latch
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 60 of 580
REJ09B0324-0200
Figure 7.4 Configuration of Programmable I/O Ports (4)
P3_2 and P3_6
Direction
register
Input to INT1 and INT2
Port latchData bus
Pull-up selection
Digital
filter
P3_3, P3_4, P3_5, and P3_7
Direction
register
1
Data bus
Pull-up selection
Input to individual peripheral function
Output from individual peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 61 of 580
REJ09B0324-0200
Figure 7.5 Configuration of Programmable I/O Ports (5)
P4_3/XCIN
Data bus
Pull-up selection
P4_4/XCOUT
Data bus
Pull-up selection
Clocked inverter(2)
(Note 3)
Port latch
Direction
register
Port latch
Direction
register
P4_5
Direction
register
INT0 input
Port latchData bus
Pull-up selection
Digital
filter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
NOTES:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off.
3. When CM04 = 0 the feedback resistor is disconnected.
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 62 of 580
REJ09B0324-0200
Figure 7.6 Configuration of Programmable I/O Ports (6)
P4_6/XIN
Data bus
Clocked inverter(2)
P4_7/XOUT
Data bus
(Note 3)
(Note 4)
P5_0
Direction
register
Input to individual peripheral function
Port latchData bus
Pull-up selection
NOTES:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cut off.
3. When CM10 = 1 or CM13 = 0, the feedback resistor is disconnected.
4. When CM05 = CM13 = 1 or CM10 = CM13 = 1, this pin is pulled up.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 63 of 580
REJ09B0324-0200
Figure 7.7 Configuration of Programmable I/O Ports (7)
P5_1 to P5_4
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual peripheral function
P6_0
Direction
register
1
Data bus
Pull-up selection
Output from individual peripheral function
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
Port latch
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 64 of 580
REJ09B0324-0200
Figure 7.8 Configuration of Programmable I/O Ports (8)
P6_1 and P6_2
Direction
register
Port latchData bus
Pull-up selection
P6_3
Direction
register
1
Data bus
Pull-up selection
Output from individual peripheral function
Port latch
P6_4
Direction
register
Input to individual peripheral function
Port latchData bus
Pull-up selection
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 65 of 580
REJ09B0324-0200
Figure 7.9 Configuration of Programmable I/O Ports (9)
P6_6
Direction
register
Data bus
Pull-up selection
Digital
filter
1
Output from individual peripheral function
INT2 input
Data bus
P6_7
Direction
register
INT3 input
Port latchData bus
Pull-up selection
Digital
filter
Input to individual peripheral function
P6_5
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual peripheral function
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
Port latch
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 66 of 580
REJ09B0324-0200
Figure 7.10 Configurat ion of Programmable I/O Ports (10)
P8_3
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual peripheral function
P8_0 to P8_2, P8_4, and P8_5
Direction
register
1
Data bus
Pull-up selection
Output from individual peripheral function
Port latch
P8_6
Direction
register
Port latchData bus
Pull-up selection
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 67 of 580
REJ09B0324-0200
Figure 7.11 Configuration of I/O Pins
MODE
MODE signal input
RESET
RESET signal input
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 68 of 580
REJ09B0324-0200
Figure 7.12 PDi (i = 0 to 6 and 8) Registers
Port Pi Direction Register (i = 0 to 6, 8)
Symbol Address After Reset
PD0(1) 00E2h 00h
PD1 00E3h 00h
PD2 00E6h 00h
PD3 00E7h 00h
PD4(2) 00EAh 00h
PD5(3) 00EBh 00h
PD6 00EEh 00h
PD8(4) 02E4h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
Port Pi_0 direction bit
Port Pi_2 direction bit
PDi_4
The PD8_7 bit in the PD8 register is a reserved bit. If it is necessary to set the PD8_7 bit, set to 0.
Port Pi_5 direction bit
RW
Port Pi_1 direction bit
Bits PD5_5 to PD5_7 in the PD5 register are reserved bits. If it is necessary to set bits PD5_5 to PD5_7, set to 0.
PDi_6
RW
PDi_3 Port Pi_3 direction bit
RW
RW
RW0 : Input mode
(functions as an input port)
1 : Output mode
(functions as an output port)
RW
RW
Port Pi_6 direction bit
b7 b6 b5 b4 b3 b2
PDi_2
b1 b0
PDi_1
PDi_0
Port Pi_4 direction bit
PDi_5
Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_2, PD4_6 and PD4_7 in the PD4 register, set to 0 (input mode). When read,
the content is 0.
PDi_7 Port Pi_7 direction bit RW
Write to the PD0 register w ith the next instruction after that used to set the PRC2 bit in the PRCR register to 1 (w rite
enabled).
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 69 of 580
REJ09B0324-0200
Figure 7.13 Pi (i = 0 to 6 and 8) Registers
Port Pi Register (i = 0 to 6, 8)
Symbol Address After Reset
P0 00E0h Undefined
P1 00E1h Undefined
P2 00E4h Undefined
P3 00E5h Undefined
P4(1) 00E8h Undefined
P5(2) 00E9h Undefined
P6 00ECh Undefined
P8(3) 02E6h Undefined
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. The P8_7 bit in the P8 register is a reserved bit. If it is necessary to set the P8_7 bit, set to 0.
Bits P5_5 to P5_7 in the P5 register are reserved bits. If it is necessary to set bits P5_5 to P5_7, set to 0.
Bits P4_0 to P4_2 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 to P4_2, set to 0 (“L” level). When read, the content is 0.
Pi_7
Pi_6
RW
b3 b2 b1 b0
Pi_1
Pi_5
Pi_0
Pi_2
Pi_4
Pi_3
b7 b6 b5 b4
Port Pi_0 bit
Port Pi_1 bit
Port Pi_7 bit
Port Pi_5 bit
Port Pi_4 bit
Port Pi_3 bit
RW
Port Pi_6 bit RW
Port Pi_2 bit
RW
The pin level of any I/O port w hich is set to
input mode can be read by reading the
corresponding bit in this register. The pin level
of any I/O port w hich is set to output mode
can be controlled by w riting to the
corresponding bit in this register.
0 : “L” level
1 : “H” level
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 70 of 580
REJ09B0324-0200
Figure 7.14 P2DRR Register
Figure 7.15 PM R Re gi st er
Port P2 Drive Capacity Control Register
Symbol Address Af ter Reset
P2 DRR 00F4h 00h
Bit Symbol Bit Name Function RW
NOTE:
1. Both “H” and “L” output are set to high drive capacity.
P2DRR7
P2DRR5
RW
Set P2 output transistor drive capacity
0 : Low
1 : High(1)
P2DRR2
P2_7 drive capacity
P2_3 drive capacity
P2DRR6 P2_6 drive capacity
b3 b2 b1 b0
P2DRR0
b7 b6 b5 b4
RW
P2_1 drive capacity
P2_0 drive capacity
P2DRR3
P2_2 drive capacity
P2DRR1
RW
RW
RW
P2DRR4
RW
P2_4 drive capacity RW
P2_5 drive capacity RW
Port Mode Registe
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ pin select bit
INT2
_
____ pin select bit
IICSEL RW
0 : Selects SSU function
1 : Selects I
2C bus function
0 : Selects P6_6
1 : Selects P3_2
To use the UART1, set to 1.
Set to 0.
RW
SSU / I2C bus sw itch bit
RW
b0
RW
Res er v ed bits
U1 PINSEL UART1 enable bit
INT2SEL
—
(b6-b5)
INT1SEL 0 : Selects P1_5, P1_7
1 : Selects P3_6
b3 b2
0
b1
0
b7 b6 b5 b4
00
RW
—
(b3-b2)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 71 of 580
REJ09B0324-0200
Figure 7.16 Registers PUR0, PUR1, and PUR2
Pull-Up Control Register 1
Symbol Address After Reset
PUR1 00FDh XX000000b
Bit Symbol Bit Name Function RW
NOTE:
1.
PU12 P5_0 to P5_3 pull-up(1)
0 : Not pulled up
1 : Pulled up
RW
RW
PU15 P6_4 to P6_7 pull-up(1) RW
PU11 P4_4 and P4_5 pull-up(1)
PU13
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is undef ined. —
RW
P5_4 pull-up(1) RW
PU14 P6_0 to P6_3 pull-up(1)
RW
PU10 P4_ 3 pull- up(1)
b7 b6 b5 b4 b0
When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
b3 b2 b1
Pull-Up Control Register 0
Symbol Address After Reset
PUR0 00FCh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
P2_4 to P2_7 pull-up(1) RW
RW
RW
RW
P2_0 to P2_3 pull-up(1)
RW
P0_4 to P0_7 pull-up(1)
P0_0 to P0_3 pull-up(1)
PU03 P1_4 to P1_7 pull-up(1)
P1_0 to P1_3 pull-up(1)
PU01
PU00 0 : Not pulled up
1 : Pulled up
RW
b0b7 b6 b5 b4 b3 b2 b1
PU04
PU02
When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
PU07
PU05
RWP3_4 to P3_7 pll-up(1)
PU06 P3_0 to P3_3 pll-up(1) RW
Pull-Up Control Register 2
Symbol Address After Reset
PUR2 02FCh XXX00000b
Bit Symbol Bit Name Function RW
NOTE:
1.
—
(b1-b0)
b0
0
b7 b6
0
When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
b3 b2 b1
0
b5 b4
—
(b7-b5)
Nothing is assigned. If necessary, set to 0.
When read, the content is undef ined. —
—
(b4)
Reserved bit RW
Set to 0.
Reserved bits
RW
PU22 P8_0 to P8_3 pull-up(1) RW
RW
Set to 0.
PU23
0 : Not pulled up
1 : Pulled up
P8_4 to P8_6 pull-up(1)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 72 of 580
REJ09B0324-0200
7.4 Port settings
Tables 7.4 to 7.65 list the port settings.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.4 P o rt P0 _0 /AN7
Register PD0 ADCON0 ADCON2 Function
Bit PD0_0 CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX
Input port(1)
1 X X X X X Output port
011100A/D converter input (AN7)
Table 7.5 P o rt P0 _1 /AN6
Register PD0 ADCON0 ADCON2 Function
Bit PD0_1 CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX
Input port(1)
1 X X X X X Output port
011000A/D converter input (AN6)
Table 7.6 P o rt P0 _2 /AN5
Register PD0 ADCON0 ADCON2 Function
Bit PD0_2 CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX
Input port(1)
1 X X X X X Output port
010100A/D converter input (AN5)
Table 7.7 P o rt P0 _3 /AN4
Register PD0 ADCON0 ADCON2 Function
Bit PD0_3 CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX
Input port(1)
1 X X X X X Output port
010000A/D converter input (AN4)
Table 7.8 P o rt P0 _4 /AN3
Register PD0 ADCON0 ADCON2 Function
Bit PD0_4 CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX
Input port(1)
1 X X X X X Output port
001100A/D converter input (AN3)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 73 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.9 P o rt P0 _5 /AN2/CLK1
Register PD0 ADCON0 ADCON2 PMR U1MR U1SR Function
Bit PD0_5 CH2 CH1 CH0 ADGSEL1 ADGSEL0 U1PINSEL SMD2 SMD1 SMD0 CKDIR CLK11PSEL CLK10PSEL
Setting
Value
0 XXX X X
X Other than 001b X X X
Input port(1)
0 XXX X X X
X XXX 1 X X
1 XXX X X
X Other than 001b X X X
Output port0 XXX X X X
X XXX 0 X X
0010 0 0 X XXX X X X A/D converter
input (AN2)
0 XXX X X 1 X X X 1
01
CLK1 (external
clock) input
X XXX X X 1 0 0 1 0 CLK1 (internal
clock) output
Table 7.10 Port P0_6/AN1/DA0
Register PD0 ADCON0 ADCON2 DACON Function
Bit PD0_6 CH2 CH1 CH0 ADGSEL1 ADGSEL0 DA0E
Setting
Value
0XXXX X X
Input port(1)
1 X X X X X X Output port
0 0 0 1 0 0 X A/D converter input (AN1)
0 X X X X X 1 D/A converter output (DA0)
Table 7.11 Port P0_7/AN0/DA1
Register PD0 ADCON0 ADCON2 DACON Function
Bit PD0_7 CH2 CH1 CH0 ADGSEL1 ADGSEL0 DA1E
Setting
Value
0XXXXXX
Input port(1)
1 X X X X X X Output port
0 0 0 0 0 0 X A/D converter input (AN0)
0 X X X X X 1 D/A converter output (DA1)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 74 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1.
Table 7.12 Port P1_0/KI0/AN8
Register PD1 KIEN ADCON0 ADCON2 Function
Bit PD1_0 KI0EN CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX X
Input port(1)
1 X X X X X X Output port
0 1XXXX X
KI0 input
0 X 1 0 0 0 1 A/D converter input (AN8)
Table 7.13 Port P1_1/KI1/AN9
Register PD1 KIEN ADCON0 ADCON2 Function
Bit PD1_1 KI1EN CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX X
Input port(1)
1 X X X X X X Output port
01XXXX X
KI1 input
0 X 1 0 1 0 1 A/D converter input (AN9)
Table 7.14 Port P1_2/KI2/AN10
Register PD1 KIEN ADCON0 ADCON2 Function
Bit PD1_2 KI2EN CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX X
Input port(1)
1 X X X X X X Output port
01XXXX X
KI2 input
0 X 1 1 0 0 1 A/D converter input (AN10)
Table 7.15 Port P1_3/KI3/AN11
Register PD1 KIEN ADCON0 ADCON2 Function
Bit PD1_3 KI3EN CH2 CH1 CH0 ADGSEL1 ADGSEL0
Setting
Value
0XXXXX X
Input port(1)
1 X X X X X X Output port
01XXXX X
KI3 input
0 X 1 1 1 0 1 A/D converter input (AN11)
Table 7.16 Port P1_4/TXD0
Register PD1 U0MR Function
Bit PD1_4 SMD2 SMD1 SMD0
Setting
Value
0000
Input port(1)
1 0 0 0 Output port
X
001
TXD0 output(2)
100
101
110
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 75 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Table 7.17 Port P1_5/RXD0/ (TRAIO)/(INT1)
Register PD1 TRAIOC TRAMR INTEN PMR Function
Bit PD1_5 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN INT1SEL
Setting
Value
0
0XXXX
XX
Input port(1)
X1XXX
X X Other than 001b
1
0XXXX
X X Output portX1XXX
X X Other than 001b
0XXOther than 001b XX
RXD0 input(1)
0001
0 1 X Other than 001b X X TRAIO input
0 1 X Other than 001b 1 0 TRAIO/INT1 input
X 1 0 0 0 1 X X TRAIO pulse output
Table 7.18 Port P1_6/CLK0
Register PD1 U0MR Function
Bit PD1_6 SMD2 SMD1 SMD0 CKDIR
Setting
Value
0Other than 001b X Input port(1)
XXX1
1 Other than 001b X Output port
0 X X X 1 CLK0 (external clock) input
X 0 0 1 0 CLK0 (internal clock) output
Table 7.19 Port P1_7/TRAIO/ INT 1
Register PD1 TRAIOC TRAMR INTEN PMR Function
Bit PD1_7 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN INT1SEL
Setting
Value
0
1XXXX
XX
Input port(1)
X1XXX
X X Other than 001b
1
1XXXX
X X Output portX1XXX
X X Other than 001b
0 0 X Other than 001b X X TRAIO input
0 0 X Other than 001b 1 0 TRAIO/INT1 input
X 0 0 0 0 1 X X TRAIO pulse output
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 76 of 580
REJ09B0324-0200
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR0 bit in the P2DRR register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR1 bit in the P2DRR register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR2 bit in the P2DRR register to 1.
Table 7.20 Port P2_0/TRDIOA 0/T R DCL K
Register PD2 TRDOER1 TRDFCR TRDIORA0 Function
Bit PD2_0 EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA0
Setting
Value
0 1 XXXXXXX
Input port(1)
1 1 XXXXXXX
Output port(2)
0 X 0 0 0 1 1 X X Timer mode (input capture function)
0 X XX 1 1000External clock input (TRDCLK)
X00000XXX
PWM3 mode waveform output(2)
X00001
001
Timer mode waveform output
(output compare function)(2)
01X
Table 7.21 Port P2_1/TRDIOB 0
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA0 Function
Bit PD2_1 EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0
Setting
Value
01XXXXXXX
Input port(1)
11XXXXXXX
Output port(2)
0 X 0 0 1 0 1 X X Timer mode (input capture function)
X010X X X X X Complementary PWM mode waveform output
11
X001XXXXX
Reset synchronous PWM mode waveform output
X0000XXXX
PWM3 mode waveform output(2)
X00011XXX
PWM mode waveform output(2)
X00010
001
Timer mode waveform output (output compare
function)(2)
01X
Table 7.22 Port P2_2/TRDIOC 0
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0 Function
Bit PD2_2 EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0
Setting
Value
0 1 XXX X XXX
Input port(1)
1 1 XXX X XXX
Output port(2)
0 X 0 0 1 0 1 X X Timer mode (input capture function)
X010XXXXX
Complementary PWM mode waveform
output(2)
11
X001XXXXX
Reset synchronous PWM mode waveform
output(2)
X 0 001 1 XXX
PWM mode waveform output(2)
X 0 001 0 001
Timer mode waveform output (output
compare function)(2)
01X
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 77 of 580
REJ09B0324-0200
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR3 bit in the P2DRR register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR4 bit in the P2DRR register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR5 bit in the P2DRR register to 1.
Table 7.23 Port P2_3/TRDIOD 0
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0 Function
Bit PD2_3 ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0
Setting
Value
0 1 XXX X XXX
Input port(1)
1 1 XXX X XXX
Output port(2)
0 X 0 0 1 0 1 X X Timer mode (input capture function)
X010XXXXX
Complementary PWM mode waveform
output(2)
11
X001XXXXX
Reset synchronous PWM mode waveform
output(2)
X 0 001 1 XXX
PWM mode waveform output(2)
X 0 001 0 001
Timer mode waveform output (output
compare function)(2)
01X
Table 7.24 Port P2_4/TRDIOA 1
Register PD2 TRDOER1 TRDFCR TRDIORA1 Function
Bit PD2_4 EA1 CMD1 CMD0 PWM3 IOA2 IOA1 IOA0
Setting
Value
0 1 XXXXXX
Input port(1)
1 1 XXXXXX
Output port(2)
0 X 0 0 1 1 X X Timer mode (input capture function)
X010XXXX
Complementary PWM mode waveform output(2)
11
X001XXXX
Reset synchronous PWM mode waveform output(2)
X 0 001
001
Timer mode waveform output
(output compare function)(2)
01X
Table 7.25 Port P2_5/TRDIOB 1
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA1 Function
Bit PD2_5 EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0
Setting
Value
0 1 XXX X XXX
Input port(1)
1 1 XXX X XXX
Output port(2)
0 X 0 0 1 0 1 X X Timer mode (input capture function)
X010XXXXX
Complementary PWM mode waveform
output(2)
11
X001XXXXX
Reset synchronous PWM mode waveform
output(2)
X 0 001 1 XXX
PWM mode waveform output(2)
X 0 001 0 001
Timer mode waveform output (output
compare function)(2)
01X
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 78 of 580
REJ09B0324-0200
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR6 bit in the P2DRR register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR7 bit in the P2DRR register to 1.
Table 7.26 Port P2_6/TRDIOC 1
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC1 Function
Bit PD2_6 EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0
Setting
Value
0 1 XXX X XXX
Input port(1)
1 1 XXX X XXX
Output port(2)
0 X 0 0 1 0 1 X X Timer mode (input capture function)
X010XXXXX
Complementary PWM mode waveform
output(2)
11
X001XXXXX
Reset synchronous PWM mode waveform
output(2)
X 0 001 1 XXX
PWM mode waveform output(2)
X 0 001 0 001
Timer mode waveform output (output
compare function)(2)
01X
Table 7.27 Port P2_7/TRDIOD 1
Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC1 Function
Bit PD2_7 ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0
Setting
Value
0 1 XXX X XXX
Input port(1)
1 1 XXX X XXX
Output port(2)
0 X 0 0 1 0 1 X X Timer mode (input capture function)
X010XXXXX
Complementary PWM mode waveform
output(2)
11
X001XXXXX
Reset synchronous PWM mode waveform
output(2)
X 0 001 1 XXX
PWM mode waveform output(2)
X 0 001 0 001
Timer mode waveform output
(output compare function)(2)
01X
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 79 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.28 Port P3_0/TRAO
Register PD3 TRAIOC Function
Bit PD3_0 TOENA
Setting
Value
00
Input port(1)
1 0 Output port
X 1 TRAO output
Table 7.29 Port P3_1/TRBO
Register PD3 TRBMR TRBIOC Function
Bit PD3_1 TMOD1 TMOD0 TOCNT
Setting
Value
000X
Input port(1)
100X
Output port
X 01b 1
X Other than 00b 0 TRBO output
Table 7.30 Port P3_2/(INT2 )
Register PD3 INTEN PMR Function
Bit PD3_2 INT2EN INT2SEL
Setting
Value
0XX
Input port(1)
1 X X Output port
011
INT2 input
Table 7.31 Port P3_3/SSI
Register PD3
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
Communication Mod es and I/O Pins.)
PMR Function
Bit PD3_3 SSI output control SSI input control IICSEL
Setting
Value
0000
Input port(1)
XX
1
1000
Output port(2)
XX1
X 0 1 0 SSI input
X1 00
SSI output(2)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 80 of 580
REJ09B0324-0200
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1 when this pin functions as output.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Table 7.32 Port P3_4/SDA/SCS
Register PD3 SSMR2 PMR ICCR1 Function
Bit PD3_4 CSS1 CSS0 IICSEL ICE
Setting
Value
0000X
Input port(1)
000X0
1000X
Output port(2)
100X0
X010X
SCS input
X100X
SCS output(2)
11
X X X 1 1 SDA input/output
Table 7.33 Port P3_5/SCL/SSCK
Register PD3
Clock Synchronous Serial I/O with Chip Select
(Refer to Tab l e 16.4 Association between
Communication Modes and I/O Pins.)
PMR ICCR1 Function
Bit PD3_5 SSCK output control SSCK input control IICSEL ICE
Setting
Value
00 00X
Input port(1)
00 0X0
10 00X
Output port(2)
10 0X0
X 0 1 0 0 SSCK input
X1 000
SSCK output(2)
X 1 0 1 1 SCL input/output
Table 7.34 Port P3_6/(INT1 )
Register PD3 INTEN PMR Function
Bit PD3_6 INT1EN INT1SEL
Setting
Value
0XX
Input port(1)
1 X X Output port
011
INT1 input
Table 7.35 Port P3_7/SSO
Register PD3
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
SSMR2 PMR Function
Bit PD3_7 SSO output control SSO input control SOOS IICSEL
Setting
Value
000
X0Input port(1)
XX 1
100
00Output port
XX 1
X 0 1 0 0 SSO input
X 1 0 0 0 SSO output (CMOS output)
X1 0 10
SSO output (N-channel open-drain
output)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 81 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU10 bit in the PUR1 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
2. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as
the CMOS level signal directly.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
Table 7.36 VREF
Register ADCON1 Function
Bit VCUT
Setting
Value
0 Not the pin function
1 VREF input
Table 7.37 Port P4_3/XCIN
Register PD4 CM0 CM1 Circuit specifications
Function
Bit PD4_3 CM04 CM10 CM12 Oscillation
buffer
Feedback
resistor
Setting
Value
00XXOFFOFF
Input port(1)
1 0 X X OFF OFF Output port
X 1 0 0 ON ON XCIN-XCOUT oscillation (on-chip feedback resistor
enabled)
X 1 0 1 ON OFF XCIN-XCOUT oscillation (on-chip feedback resistor
disabled)
X110OFFON
XCIN-XCOUT oscillation stop
1OFFOFF
X100ONON
External XCIN input
1ONOFF
Table 7.38 Port P4_4/XCOUT
Register PD4 CM0 CM1 Circuit specifications
Function
Bit PD4_4 CM04 CM10 CM12 Oscillation
buffer
Feedback
resistor
Setting
Value
00XX OFFOFF
Input port(1)
1 0 X X OFF OFF Output port
X 1 0 0 ON ON XCIN-XCOUT oscillation (on-chip feedback resistor
enabled)
X 1 0 1 ON OFF XCIN-XCOUT oscillation (on-chip feedback resistor
disabled)
X110OFFON
XCIN-XCOUT oscillation stop
1OFFOFF
X100ONON
External XCOUT output (inverted output of XCIN)(2)
1ONOFF
Table 7.39 Port P4_5/INT0
Register PD4 INTEN Function
Bit PD4_5 INT0EN
Setting
Value
0X
Input port(1)
1 X Output port
01
INT0 input
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 82 of 580
REJ09B0324-0200
X: 0 or 1
X: 0 or 1
Table 7.40 Port P4_6/XIN
Register CM1 CM0 Circuit specifications
Function
Bit CM13 CM10 CM05 Oscillation
buffer
Feedback
resistor
Setting
Value
0 X X OFF OFF Input port
1 0 0 ON ON XIN-XOUT oscillation
1 0 1 OFF ON External XIN input
1 1 0 OFF OFF XIN-XOUT oscillation stop
1 1 1 OFF OFF XIN-XOUT oscillation stop
Table 7.41 Port P4_7/XOUT
Register CM1 CM0 Circuit specifications
Function
Bit CM13 CM10 CM05 Oscillation
buffer
Feedback
resistor
Setting
Value
0 X X OFF OFF Input port
1 0 0 ON ON XIN-XOUT oscillation
1 0 1 OFF ON XOUT is “H” pull-up
1 1 0 OFF OFF XIN-XOUT oscillation stop
1 1 1 OFF OFF XIN-XOUT oscillation stop
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 83 of 580
REJ09B0324-0200
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
X: 0 or 1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
X: 0 or 1
Table 7.42 Port P5_0/TRCC LK
Register PD5 TRCCR1 Function
Bit PD5_0 TCK2 TCK1 TCK0
Setting
Value
0 Other than 101b Input port(1)
1 Other than 101b Output port
0 1 0 1 TRCCLK input
Table 7.43 Port P5_1/TRCIOA /T RCTRG
Register PD5 Timer RC Setting Function
Bit PD5_1 −
Setting
Value
0Other than TRCIOA usage conditions Input port(1)
1 Output port
XRefer to Table 7.44 TRCIOA Pin Setting TRCIOA output
0 TRCIOA input
Table 7.44 TRCIO A Pin Set ti ng
Register TRCOER TRCMR TRCIOR0 TRCCR2 Function
Bit EA PWM2 IOA2 IOA1 IOA0 TCEG1 TCEG2
Setting
value
01001XX
Timer waveform output
(output compare function)
01XXX
011XXXX
Timer mode (input capture function)
1XX
00XXX01
PWM2 mode TRCTRG input
11X
Other than above Other than TRCIOA usage conditions
Table 7.45 Port P5_2/TRCIOB
Register PD5 Timer RC Setting Function
Bit PD5_2 −
Setting
Value
0Other than TRCIOB usage conditions Input port(1)
1 Output port
XRefer to Table 7.46 TRCIOB Pin Setting TRCIOB output
0 TRCIOB input
Table 7.46 TRCIO B Pin Set ti ng
Register TRCOER TRCMR TRCIOR0 Function
Bit EB PWM2 PWMB IOB2 IOB1 IOB0
Setting
value
00XXXXPWM2 mode waveform output
0 1 1 X X X PWM mode waveform output
010001
Timer waveform output (output compare
function)
01X
01 0 1 X X Timer mode (input capture function)
1
Other than above Other than TRCIOB usage conditions
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 84 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
X: 0 or 1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU13 bit in the PUR1 register to 1.
X: 0 or 1
Table 7.47 Port P5_3/TRCIOC
Register PD5 Timer RC Setting Function
Bit PD5_3 −
Setting
Value
0Other than TRCIOC usage conditions Input port(1)
1 Output port
XRefer to Table 7.48 TRCIOC Pin Setting TRCIOC output
0 TRCIOC input
Table 7.48 TRCIO C Pin Set ti ng
Register TRCOER TRCMR TRCIOR1 Function
Bit EC PWM2 PWMC IOC2 IOC1 IOC0
Setting
value
0 1 1 X X X PWM mode waveform output
010
001
Timer waveform output (output compare function)
01X
01 0 1 X X Timer mode (input capture function)
1
Other than above Other than TRCIOC usage conditions
Table 7.49 Port P5_4/TRCIOD
Register PD5 Timer RC Setting Function
Bit PD5_4 −
Setting
Value
0Other than TRCIOD usage conditions Input port(1)
1 Output port
XRefer to Table 7.50 TRCIOD Pin Setting TRCIOD output
0 TRCIOD input
Table 7.50 TRCIO D Pin Set ti ng
Register TRCOER TRCMR TRCIOR1 Function
Bit EC PWM2 PWMD IOD2 IOD1 IOD0
Setting
value
0 1 1 X X X PWM mode waveform output
010
001
Timer waveform output (output compare function)
01X
01 0 1 X X Timer mode (input capture function)
1
Other than above Other than TRCIOD usage conditions
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 85 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.51 Port P6_0/TREO
Register PD6 TRECR1 Function
Bit PD6_0 TOENA
Setting
Value
00
Input port(1)
1 0 Output port
X 1 TREO output
Table 7.52 Port P6_1
Register PD6 Function
Bit PD6_1
Setting
Value
0Input port(1)
1 Output port
Table 7.53 Port P6_2
Register PD6 Function
Bit PD6_2
Setting
Value
0Input port(1)
1 Output port
Table 7.54 Port P6_3/TXD2
Register PD6 U2MR U2C0 Function
Bit PD6_3 SMD2 SMD1 SMD0 NCH
Setting
Value
0000XInput port(1)
XXX
1000X Output port
XXX
X
001
0 TXD2 output (CMOS output)
100
101
110
X
001
1TXD2 output (N-channel open-drain
output)
100
101
110
Table 7.55 Port P6_4/RXD2
Register PD6 Function
Bit PD6_4
Setting
Value
0Input port(1)
1 Output port
0RXD2 input(1)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 86 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.56 Port P6_5/(CLK1) /C LK 2
Register PD6 PMR U1MR U1SR Function
Bit PD6_5 U1PINSEL SMD2 SMD1 SMD0 CKDIR CLK11PSEL CLK10PSEL
Setting
Value
0
X Other than 001b X X X
Input port(1)
0 XXXX X X
X XXX1 X X
1
X Other than 001b XXX
Output port0 XXX X X
X XXX0 X X
0 1 XXX1 10
CLK1 (external clock) input
X 1 0010 CLK1 (internal clock) output
0 X XXX1 0X
CLK2 (external clock) input
X X 0010 CLK2 (internal clock) output
Table 7.57 Port P6_6/INT2/TXD1
Register PD6 PMR U1MR U1C0 INTEN PMR Function
Bit PD6_6 U1PINSEL SMD2 SMD1 SMD0 NCH INT2EN INT2SEL
Setting
Value
0X 000 XX X
Input port(1)
0XXX
1X 000 X X X Output port
0XXX
0XXXXX1 0
INT2 input
X1
001
0 X X TXD1 output (CMOS output)
100
101
110
X1
001
1X X
TXD1 output (N-channel open-
drain)
100
101
110
Table 7.58 Port P6_7/INT3/RXD1
Register PD6 PMR INTEN Function
Bit PD6_7 U1PINSEL INT3EN
Setting
Value
0XX
Input port(1)
1 X X Output port
0X1
INT3 input
01X
RXD1 input(1)
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 87 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU23 bit in the PUR2 register to 1.
Table 7.59 Port P8_0/TRFO0 0
Register PD8 TRFOUT P8 Function
Bit PD8_0 TRFOUT0 P8_0
Setting
Value
00X
Input port(1)
10X
Output port
X10
X 1 1 TRFO00 output
Table 7.60 Port P8_1/TRFO0 1
Register PD8 TRFOUT P8 Function
Bit PD8_1 TRFOUT1 P8_1
Setting
Value
00X
Input port(1)
10X
Output port
X10
X 1 1 TRFO01 output
Table 7.61 Port P8_2/TRFO0 2
Register PD8 TRFOUT P8 Function
Bit PD8_2 TRFOUT2 P8_2
Setting
Value
00X
Input port(1)
10X
Output port
X10
X 1 1 TRFO02 output
Table 7.62 Port P8_3/TRFO1 0 /TRF I
Register PD8 TRFOUT P8 Function
Bit PD8_3 TRFOUT3 P8_3
Setting
Value
00X
Input port(1)
10X
Output port
X10
X 1 1 TRFO02 output
0 0 X TRFI input
Table 7.63 Port P8_4/TRFO11
Register PD8 TRFOUT P8 Function
Bit PD8_4 TRFOUT4 P8_4
Setting
Value
00X
Input port(1)
10X
Output port
X10
X 1 1 TRFO11output
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 88 of 580
REJ09B0324-0200
X: 0 or 1
NOTE:
1. Pulled up by setting the PU23 bit in the PUR2 register to 1.
NOTE:
1. Pulled up by setting the PU23 bit in the PUR2 register to 1.
Table 7.64 Port P8_5/TRFO1 2
Register PD8 TRFOUT P8 Function
Bit PD8_5 TRFOUT5 P8_5
Setting
Value
00X
Input port(1)
10X
Output port
X10
X 1 1 TRFO12output
Table 7.65 Port P8_6
Register PD8 Function
Bit PD8_6
Setting
Value
0Input port(1)
1 Output port
R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports
Rev.2.00 Nov 26, 2007 Page 89 of 580
REJ09B0324-0200
7.5 Unassigned Pin Handling
Table 7.66 lists Unassigned Pin Handling.
NOTES:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
Figure 7.17 Unassigned Pin Handling
Table 7.66 Unassigned Pin Handling
Pin Name Connection
Ports P0 to P3, P4_3 to P4_5,
P5_0 to P5_4, P6, P8_0 to P8_6
• After setting to input mode, connect each pin to VSS via a resistor
(pull-down) or connect each pin to VCC via a resistor (pull-up).(2)
• After setting to output mode, leave these pins open.(1,2)
Ports P4_6, P4_7 Connect to VCC via a pull-up resistor(2)
VREF Connect to VCC
RESET (3) Connect to VCC via a pull-up resistor(2)
NOTE:
1. When the power-on reset function is in use.
MCU
Port P0 to P3,
P4_3 to P4_5,
P5_0 to P5_4, P6,
P8_0 to P8_6
(Input mode )
:
:
(Input mode)
(Output mode)
Port P4_6, P4_7
RESET(1)
VREF
:
:
Open
R8C/2A Group, R8C/2B Group 8. Processor Mode
Rev.2.00 Nov 26, 2007 Page 90 of 580
REJ09B0324-0200
8. Processor Mode
8.1 Processor Modes
Single-chip mode can be selected as the processor mode.
Table 8.1 lists Features of Processor Mod e. Figure 8.1 shows the PM0 Register and Figure 8.2 sho ws the PM1
Register.
Figure 8.1 PM0 Register
Figure 8.2 PM1 Register
Table 8.1 Features of Processor Mode
Processor Mode Accessible Areas Pins Assignable as I/O Port Pins
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Processor Mode Register 0(1)
Symbol Address Af ter Reset
PM0 0004h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
RW
Reserved bits Set to 0.
Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
The MCU is reset w hen this bit is set to 1.
When read, the content is 0. RW
—
(b7-b4)
PM0 3 Softw are reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4 b3 b2
—
b1 b0
000
—
(b2-b0)
Processor Mode Register 1(1)
Symbol Address After Reset
PM1 0005h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
0
—
(b1-b0) RW
Reserved bits Set to 0.
b7 b6 b5 b4 b3 b2
—
b1 b0
00
0 : Watchdog timer interrupt
1 : Watchdog timer reset(2) RW
The PM12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automatically set to 1.
Reserved bit Set to 0.
Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
—
(b7) RW
—
(b6-b3)
PM1 2 WDT interrupt/reset sw itch bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
R8C/2A Group, R8C/2B Group 9. Bus
Rev.2.00 Nov 26, 2007 Page 91 of 580
REJ09B0324-0200
9. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/2A Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/2B Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations and Tab le 9.4 lists Access Units and Bu s Operations o f SFR (address
0200h to 02FFh).
Table 9.3 Access Units and Bus Operations
Table 9.1 Bus Cycles by Access S pace of the R8C/2A Group
Access Area Bus Cycle
SFR (address 0000h to 01FFh) 2 cycles of CPU clock
SFR (address 0200h to 02FFh) 3 cycles of CPU clock
ROM/RAM 1 cycle of CPU clock
Table 9.2 Bus Cycles by Access S pace of the R8C/2B Group
Access Area Bus Cycle
SFR (address 0000h to 01FFh)/Data flash 2 cycles of CPU clock
SFR (address 0200h to 02FFh) 3 cycles of CPU clock
Program ROM/RAM 1 cycle of CPU clock
Area SFR (address 0000h to 01FFh), data flash
Even address
Byte access
ROM (program ROM), RAM
Odd address
Byte access
Even address
Word access
Odd address
Word access
CPU clock
Data Data Data
Even Even
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
Data Data
Odd Odd
Data
Even Even + 1
Data
Data
Odd Odd + 1
Data
Data
Even Even + 1
Data
Data
Odd Odd + 1
Data
R8C/2A Group, R8C/2B Group 9. Bus
Rev.2.00 Nov 26, 2007 Page 92 of 580
REJ09B0324-0200
Table 9.4 Access Units and Bus Operations of SFR (address 0200h to 02FFh)
However, only following SFRs are connected with the 16-bit bus:
Timer RC: registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD
Timer RD: registers TRDi (i = 0,1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address
byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is accessed at a time.
SFR (address 0200h to 02FFh)
CPU clock
Data Data
Even
Address
CPU clock
Data
Address
CPU clock
Data
Address
CPU clock
Data
Address
Data
Odd
Odd
Data
Odd + 1
Data
Even
Data
Even + 1
Data
Area
Even address
Byte access
Odd address
Byte access
Even address
Word access
Odd address
Word access
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 93 of 580
REJ09B0324-0200
10. Clock Generation Circuit
The clock generation circuit has:
• XIN clock oscillation circuit
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figure 10.2
shows a Peripheral Function Clock. Figures 10.3 to 10.9 show clock associated registers. Figure 10.10 shows a
Procedure for Enabling Reduced Int e rnal Power Consumption Using VCA20 bit.
NOTES:
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the
XIN clock oscillation circuit is not used.
2. These pins can be used as P4_3 and P4_4 when using the XIN clock oscillation circuit and on-chip oscillator
clock for a CPU clock while the XCIN clock oscillation circuit is not used.
3. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XIN-
XOUT pin) when an external clock is input.
4. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip
oscillator as the CPU clock source.
Table 10.1 Specifications of Clock Generation Circuit
Item XIN Clock
Oscillation Circuit
XCIN Clock Oscillation
Circuit
On-Chip Oscillator
High-Speed On-Chip
Oscillator
Low-Speed On-Chip
Oscillator
Applications • CPU clock source
• Peripheral function
clock source
• CPU clock source
• Timer RA and timer RE
clock source
• CPU clock source
• Peripheral function
clock source
• CPU and peripheral
function clock
sources when XIN
clock stops oscillating
• CPU clock source
• Peripheral function
clock source
• CPU and peripheral
function clock
sources when XIN
clock stops oscillating
Clock frequency 0 to 20 MHz 32.768 kHz Approx. 40 MHz(4) Approx. 125 kHz
Connectable
oscillator
• Ceramic resonator
• Crystal oscillator
• Crystal oscillator −−
Oscillator
connect pins
XIN, XOUT(1) XCIN, XCOUT(2) −(1) −(1)
Oscillation stop,
restart function
Usable Usable Usable Usable
Oscillator status
after reset
Stop Stop Stop Oscillate
Others Externally
generated clock can
be input(3)
• Externally generated
clock can be input
• On-chip feedback
resistor Rf (connected/
not connected,
selectable)
−−
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 94 of 580
REJ09B0324-0200
Figure 10.1 Clock Generation Circuit
Oscillation
stop
detection
Divider
SQ
R
1/2 1/2 1/2 1/2 1/2
Pulse generation
circuit for clock
edge detection and
charge, discharge
control circuit
Charge,
discharge circuit
Oscillation stop detection
interrupt generation
circuit detection
SQ
R
FRA00 High-speed
on-chip oscillator
FRA01 = 1
FRA01 = 0
CM14
CPU clock
a
b
c
d
e
OCD2 = 0
OCD2 = 1
XIN clock
XOUT
CM13
CM05
XIN
CM02
WAIT instruction
RESET
CM10 = 1 (stop mode)
a
d
c
h
b
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
CM17 to
CM16 = 10b
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Oscillation Stop Detection Circuit
XIN clock
Forcible discharge when OCD0 = 0
Watchdog timer
interrupt
OCD1
OCD2 bit switch signal
CM14 bit switch signal
Oscillation stop detection,
Watchdog timer,
Voltage monitor 1 interrupt,
Voltage monitor 2 interrupt
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
FRA00, FRA01: Bits in FRA0 register
eg
FRA2 register
fOCO
fOCO-S
g
f1
f2
f4
f8
f32
h
Voltage monitor 2
interrupt
System clock
Low-speed
on-chip oscillator
FRA1 register
Frequency adjustable
CM13
Divider
fOCO40M
On-chip oscillator
clock
fOCO-F
XCOUT
CM04
XCIN
fC4
fC32
fC
fC
CM07 = 0
CM07 = 1
Power-on
reset circuit
Voltage
detection
circuit
Voltage monitor 1
interrupt
Divider
(1/128) fOCO128
Power-on reset
Software reset
Interrupt request
1/81/4
fOCO
fOCO-F
fOCO-S
Peripheral
function
clock
Clock prescaler
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 95 of 580
REJ09B0324-0200
Figure 10.2 Peripheral Function Clock
UART0
A/D converter
Timer RDTimer RBTimer RA
INT0
SSU /
I2C bus
Watchdog
timer
UART1Timer RE
CPU clock
f1
f2
f4
f8
f32
fOCO40M
fOCO-F
fC4
fC32
fOCO128
Timer RC UART2Timer RF
fOCO-S
fOCO
CPU
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 96 of 580
REJ09B0324-0200
Figure 10.3 CM0 Register
System Clock Control Register 0(1)
Symbol Address After Reset
CM0 0006h 01101000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
b7 b6 b5 b4 b3 b2 b1 b0
00
—
(b1-b0)
Reserved bits Set to 0. RW
CM02
WAIT peripheral function clock
stop bit
0 : Peripheral function clock does not stop
in w ait mode
1 : Peripheral function clock stops in w ait
mode
RW
CM03 XCIN-XCOUT drive capacity
select bit(9)
0 : Low
1 : High RW
CM04 Por t, XCIN- XCOUT s w itc h bit(6) 0 : I/O port P4_3, P4_4
1 : XCIN-XCOUT pin(7) RW
CM05 XIN clock (XIN-XOUT)
stop bit(2, 4)
0 : XIN clock oscillates
1 : XIN clock stops(3) RW
CM06 System clock division select bit
0(5)
0 : CM16, CM17 enabled
1 : Divide-by-8 mode RW
CM07 CPU clock select bit(8) 0 : System clock
1 : XCIN clock RW
When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is
selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the
follow ing order:
(a) Set bits OCD1 to OCD0 in the OCD register to 00b.
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
During external clock input, only the clock oscillation buf f er is turned off and clock input is acknow ledged.
When the CM05 bit is set to 1 (XIN clock stopped) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7), P4_6
and P4_7 can be used as input ports.
The MCU enters stop mode, the CM03 bit is set to 1 (high). Rew rite the CM03 bit w hile the XCIN clock oscillation
stabilizes.
The CM04 bit can be set to 1 by a program but cannot be set to 0.
To use the XCIN clock, set the CM04 bit to 1. Also, set ports P4_3 and P4_4 as input ports w ithout pull-up.
Set the CM07 bit to 1 f rom 0 (XCIN clock) after setting the CM04 bit to 1 (XCIN-XCOUT pin) and allow ing XCIN clock
oscillation to stabilize.
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 97 of 580
REJ09B0324-0200
Figure 10.4 CM1 Register
System Clock Control Register 1(1)
Symbol Address After Reset
CM1 0007h 00100000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
When entering stop mode, the CM15 bit is set to 1 (drive capacity high).
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit(4, 7, 8) 0 : Clock operates
1 : Stops all clocks (stop mode) RW
CM11 XIN-XOUT on-chip feedback resistor
select bit
0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled RW
CM12 XCIN-XCOUT on-chip feedback
resistor select bit
0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled RW
CM13 Port XIN-XOUT s w itc h bit(7, 9) 0 : Input ports P4_6, P4_7
1 : XIN-XOUT pin RW
CM14 Low -speed on-chip oscillation stop
bit(5, 6, 8)
0 : Low -speed on-chip oscillator on
1 : Low -speed on-chip oscillator of f RW
CM15 XIN-XOUT drive capacity select bit(2) 0 : Low
1 : High RW
CM17 RW
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
System clock division select bits 1(3)
CM16 RW
When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”.
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.
In count source protect mode (Refer to 13.2 Count Source Protection Mode Enabled), the value remains
unchanged even if bits CM10 and CM14 are set.
When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped).
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip
oscillator on). It remains unchanged even if 1 is w ritten to it.
When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14
bit to 0 (low -speed on-chip oscillator on).
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 98 of 580
REJ09B0324-0200
Figure 10.5 OCD Register
Oscillation Stop Detection Register(1)
Symbol Address After Reset
OCD 000Ch 00000100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
Ref er to Figure 10. 17 Procedure for Switchi ng C loc k Sourc e from Low-Speed On-Chip Oscil lator to X IN
Clock for the sw itching procedure w hen the XIN clock re-oscillates af ter detecting an oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.
The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains
unchanged even w hen set to 0 (XIN clock selected).
The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection f unction enabled).
Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip
oscillator mode (XIN clock stops).
—
(b7-b4)
Reserved bits Set to 0. RW
OCD3 Clock monitor bit(5, 6) 0 : XIN clock oscillates
1 : XIN clock stops RO
OCD2 System clock select bit(4) 0 : Selects XIN clock(7)
1 : Selects on-chip oscillator clock(3) RW
OCD1 RW
OCD0 RW
Oscillation stop detection enable
bit(7)
Oscillation stop detection
interrupt enable bit
0 : Oscillation stop detection f unction
disabled(2)
1 : Oscillation stop detection f unction
enabled
0 : Disabled(2)
1 : Enabled
0000
b3 b2 b1 b0b7 b6 b5 b4
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 99 of 580
REJ09B0324-0200
Figure 10.6 Registers FRA0 and FRA1
High-Speed On-Chip Oscillator Control Register 0(1)
Symbol Address After Reset
FRA 0 0023h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
b7 b6 b5 b4 b3 b2 b1 b0
000000
FRA 00 RW
FRA 01 RW
High-speed on-chip oscillator
enable bit
0 : High-speed on-chip oscillator of f
1 : High-speed on-chip oscillator on
High-speed on-chip oscillator
select bit(2)
0 : Selects low -speed on-chip oscillator(3)
1 : Selects high-speed on-chip oscillator
Change the FRA01 bit under the follow ing conditions.
• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register:
All divide ratio mode settings are supported w hen VCC = 3.0 V to 5.5 V 000b to 111b
Divide ratio of 4 or more w hen VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more)
Divide ratio of 8 or more w hen VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more)
When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA 00 bit to 0 (high-speed
on-chip oscillator off) at the same time.
Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
—
(b7-b2)
Reserved bits Set to 0. RW
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register.
High-Speed On-Chip Oscillator Control Register 1(1)
Symbol Address After Reset
FRA 1 0024h When Shipping
RW
NOTE:
1.
2.
b7 b6 b5 b4 b3 b2 b1 b0
When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed
on-chip oscillator clock w ill be 40 MHz or less.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA1 register.
RW
Function
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
High-speed on-chip oscillator f requency = 40 MHz (FRA1 register = value w hen shipping)
Setting the FRA1 register to a low er value results in a higher frequency.
Setting the FRA1 register to a higher value results in a low er frequency.(2)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 100 of 580
REJ09B0324-0200
Figure 10.7 Registers FRA2, FRA6 and FRA7
High-Speed On-Chip Oscillator Control Register 2(1)
Symbol Address After Reset
FRA 2 0025h 00h
Bit Symbol Bit Name Function RW
NOTE:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register.
b7 b6 b5 b4 b3 b2 b1 b0
00000
RW
Selects the dividing ratio for the high-
speed on-chip oscillator clock.
b2 b1 b0
0 0 0: Divide-by-2 mode
0 0 1: Divide-by-3 mode
0 1 0: Divide-by-4 mode
0 1 1: Divide-by-5 mode
1 0 0: Divide-by-6 mode
1 0 1: Divide-by-7 mode
1 1 0: Divide-by-8 mode
1 1 1: Divide-by-9 mode
FRA 20
FRA 22 RW
—
(b7-b3) RW
Reserved bits Set to 0.
High-speed on-chip oscillator
frequency sw itching bits RW
FRA 21
High-Speed On-Chip Oscillator Control Register 6
Symbol Address After Reset
FRA 6 002Bh When Shipping
RW
RO
Function
Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction
to match the voltage conditions can be achieved by transferring this value to the FRA1
register.
b3 b2 b1 b0b7 b6 b5 b4
High-Speed On-Chip Oscillator Control Register 7
Symbol Address After Reset
FRA 7 002Ch When Shipping
RW
RO
Function
36.864 MHz frequency correction data is stored.
The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz
by transferring this value to the FRA1 register.
b3 b2 b1 b0b7 b6 b5 b4
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 101 of 580
REJ09B0324-0200
Figure 10.8 CPSRF Register
Figure 10.9 VCA2 Register
Clock Prescaler Reset Flag
Symbol Address After Reset
CPSRF 0028h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b7 b6 b5 b4 b3 b2 b1 b0
0000000
—
(b6-b0)
Reserved bits Set to 0. RW
Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
CPSR Clock prescaler reset flag(1) Setting this bit to 1 initializes the clock
prescaler. (When read, the content is 0) RW
Voltage Detection Register 2(1)
Symbol Address After Reset(5)
VCA2 0032h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
1 0.1 0 Procedure for Enabl ing Reduced Internal Power Consumpti on Usi ng VCA20 bit.
VCA20 Internal pow er low
consumption enable bit(6)
0 : Disables low consumption
1 : Enables low consumption RW
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits f or td(E-A) to elapse before starting
operation.
To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits f or td(E-A) to elapse before starting
operation.
Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not af fect this
register.
To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits f or td(E-A) to elapse before starting
operation.
VCA27 Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled RW
VCA26 Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled RW
0000
b3 b2 b1 b0b7 b6 b5 b4
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset : 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset : 00100000b
VCA25 Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled RW
—
(b4-b1)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 102 of 580
REJ09B0324-0200
Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
Handling procedure of internal power
low consumption enabled by VCA20 bit
Enter low-speed clock mode or low-speed
on-chip oscillator mode
Stop XIN clock and high-speed on-chip
oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Enter wait mode(4)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start XIN clock or high-speed on-chip
oscillator clock
(Wait until XIN clock oscillation stabilizes)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
In interrupt routine
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start XIN clock or high-speed on-chip
oscillator clock
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Exit wait mode by interrupt
Stop XIN clock and high-speed on-chip
oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Interrupt handling completed
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
Step (5)
Step (6)
Step (7)
Step (8)
(Wait until XIN clock oscillation stabilizes)
Step (1)
Step (2)
Step (3)
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (7) in the interrupt
routine.
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
(Note 1)
Interrupt handling
VCA20: Bit in VCA2 register
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 103 of 580
REJ09B0324-0200
The clocks generated by the clock generation circuits are described below.
10.1 XIN Clock
This clock is supplied by the XIN clock oscillat ion circuit. This clock is used as the clock source for the CPU and
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the
XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN
pin.
Figure 10.11 shows Examples of XIN Clock Connection C ircu it.
In reset and after reset, the XIN clock stops.
The XIN clock starts oscillating when the CM05 bi t in the CM0 register is set to 0 (XIN clock oscillates) after
setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin).
To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after
the XIN clock is oscillating stably.
The power consu mption can be reduced by setting the CM0 5 bit in the CM0 reg ister to 1 (XIN clock stops) i f the
OCD2 bit is set to 1 (select on-chip oscillator clock ).
When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 b it is set to 1. If
necessary, use an external circuit to stop the clock.
In stop mode, all clocks including the XIN clock stop. Refer to 10.5 Power Control for details.
Figure 10.11 Examples of XIN Clock Connection Circuit
XIN XOUT
MCU
(on-chip feedback resistor)
Rd(1)
COUTCIN
XIN XOUT
MCU
(on-chip feedback resistor)
Externally derived clock
VCC
VSS
NOTE:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the
oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so
after oscillation stabilizes.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator
manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a
feedback resistor between XIN and XOUT following the instructions.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the
CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and
connect the feedback resistor to the chip externally.
Open
Ceramic resonator external circuit External clock input circuit
Rf(1)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 104 of 580
REJ09B0324-0200
10.2 On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1 Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
If the XIN clock stops oscil lating when bits OC D1 to OCD0 in the OCD register are set to 11b, the low-speed
on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.
The frequency of the low-speed on-chip oscillator var ies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
10.2.2 High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fO CO-F, and fOCO40M.
To use the high-sp eed on-chip oscillat or clock as the clock source for the CPU clock, peripheral clock, fOCO,
and fOCO-F, set bits FRA20 to FRA22 in the FRA2 regist er as follows:
•All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V 000b to 111b
•Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more)
•Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more)
After reset, the on-chip oscillator cloc k ge nerat e d by the high-speed on-chip oscillator stops. Oscillation is
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can
be adjusted by registers FRA1 and FRA2.
Furthermore, frequency correction data corresponding to the supply voltage ranges VCC = 2.2 V to 5.5 V is
stored in FRA6 register. To use separat e correction values to m atch this voltage ranges, transfer them from the
FRA6 register to the FRA1 register.
The frequency correction data of 36.864 MHz is stored in the FRA7 register. To set the frequency of the high-
speed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register
before use.
Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make
adjustments by changing t he settings of individual bits. Adjust the FRA1 register so that the frequency of the
high-speed on-chip oscillator clock will be 40 MHz or less.
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 105 of 580
REJ09B0324-0200
10.3 XCIN Clock
This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU
clock, timer RA, and timer RE. The XCIN clock oscillation circuit is configured by connecting a resonator between
the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is
disconnected from the oscillation circuit i n stop mode in order to reduce the amount of power consumed in the
chip. The XCIN clock oscillation c ircuit may also be confi gured by feeding an ex ternally generate d clock to the
XCIN pin.
Figure 10.12 shows Examples of XCIN Clock Connection Circuits.
During and after reset, the XCIN clock stops.
The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin).
To use the XCIN clock for the CPU clock source, set the CM07 bit in the CM0 register to 1 (XCIN clock) after the
XCIN clock is oscillating stably. To input an external clock to the XCIN pin, set the CM04 bit in the CM0 register
to 1 (XCIN-XCOUT pin) and leave the XCOUT pin open.
This MCU has an on-chip feedback resistor and on-chip resistor disab le/enable switchin g is possible b y the CM12
bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 10.5 Power Control for details.
Figure 10.12 Examples of XCIN Clock Connection Circuits
XCIN XCOUT
MCU
(on-chip feedback resistor)
Rd(1)
COUTCIN
XCIN XCOUT
MCU
(on-chip feedback resistor)
Externally derived clock
VCC
VSS
NOTE:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between
XCIN and XCOUT following the instructions.
Open
External crystal oscillator circuit External clock input circuit
Rf(1)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 106 of 580
REJ09B0324-0200
10.4 CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 10.1 Clock Generation Circuit.
10.4.1 System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the
on-chip oscillator clock can be selected.
10.4.2 CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
When the CM07 bit in the CM0 register is set to 0 (system clock), the system clock can be divided by 1 (no
division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 to
CM17 in the CM1 register to select the value of th e divi sion.
When the CM07 bit in the CM0 register is set to 1 (XCIN clock), the XCIN clock is used for the CPU clock.
Use the XCIN clock while the XCIN clock oscillation stabilizes.
After reset, the low-speed on-chip oscill ator clock div ided by 8 prov ides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 m ode).
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock fo r the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system cloc k divi ded by i. The clock fi is used for timers
RA, RB, RC, RD, and RE, the serial interface and the A/D converter. The f1, f8, and f32 clock are used for
timer RF.
When the WAIT instruction is executed after setting the CM02 bit i n th e CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
10.4.4 fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
10.4.5 fOCO40M
fOCO40M is used as the count source for timer RC and timer RD. fOCO40M is generated by the high-speed
on-chip oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO40M does not stop.
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.
10.4.6 fOCO-F
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does no t stop.
10.4.7 fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on-
chip oscillator. When the WAIT instruction i s executed or in count source protect mode of the watc hdog timer,
fOCO-S does not stop.
10.4.8 fOCO128
fOCO128 is generated by fOCO divided by 128.
The clock fOCO128 is used for capture signal of timer RD (channel 0).
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 108 of 580
REJ09B0324-0200
10.5 Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
10.5.1 Standard Operating Mode
Standard operating mode is further separated into four mo des.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program
until oscillation is stabilized before exiti ng.
−: can be 0 or 1, no change in outcome
Table 10.2 Settings and Modes of Clock Associated Bits
Modes
OCD
Register CM1 Register CM0 Register FRA0 Register
OCD2 CM17,
CM16 CM14 CM13 CM07 CM06 CM05 CM04 FRA01 FRA00
High-speed
clock mode
No division 0 00b −1000−−−
Divide-by-2 0 01b −1000−−−
Divide-by-4 0 10b −1000−−−
Divide-by-8 0 −−1010−−−
Divide-by-16 0 11b −1000−−−
Low-speed
clock mode
No division − −−−1−−1−−
High-speed
on-chip
oscillator
mode
No division 1 00b −−00−−11
Divide-by-2 1 01b −−00−−11
Divide-by-4 1 10b −−00−−11
Divide-by-8 1 −−−01−−11
Divide-by-16 1 11b −−00−−11
Low-speed
on-chip
oscillator
mode
No division 1 00b 0 −00−−0−
Divide-by-2 1 01b 0 −00−−0−
Divide-by-4 1 10b 0 −00−−0−
Divide-by-8 1 −0−01−−0−
Divide-by-16 1 11b 0 −00−−0−
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 109 of 580
REJ09B0324-0200
10.5.1.1 High-Speed Clock Mode
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed on-chip oscillator mod e, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-
speed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be
used as timer RC and timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO -S can
be used for the watchdog timer and voltage detection circuit.
10.5.1.2 Low-Speed Clock Mode
The XCIN clock divided by 1 (no division) provides the CPU clock.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consum pti on current read mode enabled) enables low consumption operation.
When the FRA00 bit is set to 1, fOCO40M can be used as timer RC and timer RD. When the CM14 bit is set to
0 (low-speed on-chip oscillator on), fOCO-S can be us ed for the watchdog timer and voltage detection circuit.
To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lowe r consum ption current in wait mode.
When enabling reduced internal power consumption using the VCA2 0 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
10.5.1.3 High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip osci llator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on-
chip oscillator divided by 1 (no division ), 2, 4, 8, or 16 provides the CPU clo ck. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as
timer RC and timer RD. When the CM14 bit is set to 0 (low-speed on -chip o scillator on), fOCO-S can be used
for the watchdog timer and voltage detection circuit.
10.5.1.4 Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set t o 0 (low-speed on-chip osci llator on) or the FRA 01bit in the FR A0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8
mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as
timer RC and timer RD. When the CM14 bit is set to 0 (low-speed on -chip o scillator on), fOCO-S can be used
as the watchdog timer and voltage detection circuit.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumptio n enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA2 0 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 110 of 580
REJ09B0324-0200
10.5.2 Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, and on-chip oscillator
clock do not stop and the peripheral function s using these clocks continue operating.
10.5.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1 , f2, f4, f 8, and f32 clocks st op
in wait mode. This reduces power consumption.
10.5.2.2 Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction.
If the MCU enters wa it mode while the OCD1 bit is set to 1 (osci llation stop detection interru pt enabled),
current consumption is not reduced because the CPU clock does not stop.
10.5.2.3 Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 111 of 580
REJ09B0324-0200
10.5.2.4 Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function inte rrupt .
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt CM02 = 0 CM02 = 1
Serial interface interrupt Usable when operating with internal
or external clock
Usable when operating with external
clock
Clock synchronous serial I/O
with chip select interrupt / I2C
bus interface interrupt
Usable in all modes (Do not use)
Key input interrupt Usable Usable
A/D conversion interrupt Usable in one-shot mode (Do not use)
Timer RA interrupt Usable in all modes Can be used if there is no filter in
event counter mode.
Usable by selecting fOCO or fC32
as count source.
Timer RB interrupt Usable in all modes (Do not use)
Timer RC interrupt Usable in all modes (Do not use)
Timer RD interrupt Usable in all modes Usable by selecting fOCO40M as
count source
Timer RE interrupt Usable in all modes Usable when operating in real time
clock mode
Timer RF interrupt Usable in all modes (Do not use)
INT interrupt Usable Usable (INT0 to INT3 can be used if
there is no filter.)
Voltage monitor 1 interrupt Usable Usable
Voltage monitor 2 interrupt Usable Usable
Oscillation stop detection
interrupt
Usable (Do not use)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 112 of 580
REJ09B0324-0200
Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 i n the interrup t control regist ers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mod e to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execut ion is determ in ed by the sett ings of the FMSTP bit in the FMR 0 regist er
and the CM07 bit in the CM0 register, as described in Figure 10.13.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
Figure 10.13 Time from Wait Mode to Interrupt Routine Execution
0
(system clock)
1
(XCIN clock)
0
(system clock)
1
(XCIN clock)
Period of CPU clock
× 20 cycles
Same as above
Same as above
Same as above
Following total
time is the time
from wait mode
until an interrupt
routine is
executed.
0
(flash memory
operates)
1
(flash memory
stops)
Wait mode Flash memory
activation sequence
T1
CPU clock restart sequence
T2
Interrupt sequence
T3
Interrupt request generated
CM07 Bit
Time for Interrupt
Sequence (T3) Remarks
FMSTP Bit
FMR0 Register CM0 Register
Period of system clock
× 12 cycles + 30 µs (max.)
Period of XCIN clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles
Period of XCIN clock
× 12 cycles
Time until Flash Memory
is Activated (T1)
Period of CPU clock
× 6 cycles
Same as above
Same as above
Same as above
Time until CPU Clock
is Supplied (T2)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 113 of 580
REJ09B0324-0200
10.5.2.5 Reducing Internal Power Consumption
Internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator
mode. Figure 10.14 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
When enabling reduced internal power consumption using the VCA2 0 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
Figure 10.14 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
Handling procedure of internal power
low consumption enabled by VCA20 bit
Enter low-speed clock mode or low-speed
on-chip oscillator mode
Stop XIN clock and high-speed on-chip
oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Enter wait mode(4)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start XIN clock or high-speed on-chip
oscillator clock
(Wait until XIN clock oscillation stabilizes)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
In interrupt routine
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start XIN clock or high-speed on-chip
oscillator clock
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Exit wait mode by interrupt
Stop XIN clock and high-speed on-chip
oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Interrupt handling completed
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
Step (5)
Step (6)
Step (7)
Step (8)
(Wait until XIN clock oscillation stabilizes)
Step (1)
Step (2)
Step (3)
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (7) in the interrupt
routine.
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
(Note 1)
Interrupt handling
VCA20: Bit in VCA2 register
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 114 of 580
REJ09B0324-0200
10.5.3 Stop Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals conti nue operating.
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
10.5.3.1 Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is
set to 1 (XIN clock oscillator circuit drive capacity high).
When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.
10.5.3.2 Pin Status in Stop Mode
The status before wait mode was entered is maintained.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status.
Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions
Interrupt Usage Conditions
Key input interrupt −
INT0 to INT3 interrupt Can be used if there is no filter
Timer RA interrupt Can be used if there is no filter when external pulse is counted in event
counter mode
Serial interface interrupt When external clock is selected
Voltage monitor 1 interrupt Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set
to 1)
Voltage monitor 2 interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set
to 1)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 115 of 580
REJ09B0324-0200
10.5.3.3 Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.15 shows the Time from Stop Mode to Interrupt Routin e Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setti ng the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode . Set bit s ILVL2 to ILVL0 of the peripheral function interrup ts that are not t o be used
for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt
request is generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the prev ious system clock divided by 8.
Figure 10.15 Time from Stop Mode to Interrupt Routine Execution
FMSTP Bit
Time until Flash Memory
is Activated (T2)
T2
0
(flash memory
operates)
1
(flash memory stops)
Period of CPU clock
× 6 cycles
Same as above
Period of CPU clock
× 20 cycles Following total
time of T0 to
T4 is the time
from stop
mode until an
interrupt
handling is
executed.
CM07 Bit
Period of system clock
× 12 cycles + 30 µs (max.)
Period of XCIN clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles
Period of XCIN clock
× 12 cycles
Same as above
Same as above
Same as above
Same as above
Same as above
Time until CPU Clock
is Supplied (T3)
Time for Interrupt
Sequence (T4) Remarks
Flash memory
activation sequence
CPU clock restart
sequence Interrupt sequence
Oscillation time of
CPU clock source
used immediately
before stop mode
Stop
mode
T3 T4
Internal
power
stability time
T1T0
150 µs
(max.)
Interrupt
request
generated
0 (system clock)
1 (XCIN clock)
0 (system clock)
1 (XCIN clock)
FMR0 Register CM0 Register
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 116 of 580
REJ09B0324-0200
Figure 10.16 shows the State Transitions in Power Control Mode.
Figure 10.16 State Transitions in Power Control Mode
CM10 = 1
CPU operation stops
Stop mode
State Transitions in Power Control Mode
Reset
Wait mode
Low-speed on-chip oscillator mode
CM07 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
High-speed on-chip oscillator mode
CM07 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
High-speed clock mode
CM05 = 0
CM07 = 0
CM13 = 1
OCD2 = 0
Standard operating mode
CM14 = 0
OCD2 = 1
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
FRA00 = 1
FRA01 = 1
CM14 = 0
FRA01 = 0
All oscillators stop
InterruptWAIT instructionInterrupt
CM04, CM05, CM07: Bits in CM0 register
CM13, CM14: Bits in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 register
Low-speed clock mode
CM04 = 1
CM07 = 1
CM07 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM04 = 1
CM07 = 1
CM07 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
CM04 = 1
CM07 = 1
CM04 = 1
CM07 = 1
CM05 = 0
CM07 = 0
CM13 = 1
OCD2 = 0
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 117 of 580
REJ09B0324-0200
10.6 Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop
detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the
following state if the XIN clock stops.
•OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
•OCD3 bit in OCD register = 1 (XIN clock stops)
•CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
•Oscillation stop detection interrupt request is generated.
10.6.1 How to Use Oscillation Stop Detection Function
•The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage
monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt
and watchdog timer interrupt, the interrupt source needs to be determined.
Table 10.6 lists De termining Interrupt Source for Oscill ation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Moni tor 2 Interrupts. Figure 10.18 shows an Example of Determining Interrupt
Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2
Interrupt.
•When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU
clock and peripheral functions by a program.
Figure 10.17 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to
XIN Clock.
•To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does no t stop in wait mode).
•Since the oscillation stop detection functi on is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 to OCD0 t o 00b when the XIN clock stops or is started by a program, (stop
mode is selected or the CM05 bit is changed).
•This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1
to OCD0 to 00b.
•To use the low-speed on-chip oscillator clock for the CPU clock an d clock sources of peripheral funct ions
after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip
oscillator selected) and bits OCD1 to OCD0 to 11b.
To use the high-speed on-chi p oscillator clock for the CPU clock and cl ock sources of peripheral functions
after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01
bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.
Table 10.5 Specifications of Oscillation Stop Detection Function
Item Specification
Oscillation stop detection clock and
frequency bandwidth
f(XIN) ≥ 2 MHz
Enabled condition for oscillation stop
detection function
Set bits OCD1 to OCD0 to 11b
Operation at oscillation stop detection Oscillation stop detection interrupt is generated
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 118 of 580
REJ09B0324-0200
Figure 10.17 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, and Voltage Monitor 2 Interrup ts
Generated Interrupt Source Bit Showing Interrupt Cause
Oscillation stop detection
((a) or (b))
(a) OCD3 bit in OCD register = 1
(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1
Watchdog timer VW2C3 bit in VW2C register = 1
Voltage monitor 1 VW1C2 bit in VW1C register = 1
Voltage monitor 2 VW2C2 bit in VW2C register = 1
OCD3 to OCD0: Bits in OCD register
Switch to XIN clock
Multiple confirmations
that OCD3 bit is set to 0 (XIN
clock oscillates) ?
Set OCD1 to OCD0 bits to 00b
Set OCD2 bit to 0
(select XIN clock)
End
YES
NO
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 119 of 580
REJ09B0324-0200
Figure 10.18 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
Interrupt sources judgement
OCD3 = 1 ?
(XIN clock stopped)
OCD1 = 1
(oscillation stop detection
interrupt enabled) and OCD2 = 1
(on-chip oscillator clock selected
as system clock) ?
VW2C3 = 1 ?
(Watchdog timer
underflow)
VW2C2 = 1 ?
(passing Vdet2)
To oscillation stop detection
interrupt routine
To voltage monitor 1
interrupt routine
To voltage monitor 2
interrupt routine
To watchdog timer
interrupt routine
NO
YES
NO
YES
NO
YES
NO
YES
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C2, VW2C3: Bits in VW2C register
Set OCD1 bit to 0 (oscillation stop
detection interrupt disabled).(1)
R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit
Rev.2.00 Nov 26, 2007 Page 120 of 580
REJ09B0324-0200
10.7 Notes on Clock Generation Circuit
10.7.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR 1,FMR0 ; CPU rewrite mode disabled
BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
10.7.2 Wait Mode
When entering wait m ode, set the FMR01 bit in the FMR0 regist er to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WA IT instruction
BCLR 1,FMR0 ; CPU rewrite mode disabled
FSET I ; Enable interrupt
WAIT ; Wait mode
NOP
NOP
NOP
NOP
10.7.3 Oscillation S top Detection Function
Since the oscillation stop detectio n function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
10.7.4 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
R8C/2A Group, R8C/2B Group 11. Protection
Rev.2.00 Nov 26, 2007 Page 121 of 580
REJ09B0324-0200
11. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, and VW2C
Figure 11.1 PRCR Register
Protect Registe
r
Symbol Address After Reset
PRCR 000Ah 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
RO
PRC3
Protect bit 3 Writing to registers VCA2, VW0C, VW1C, and
VW2C is enabled.
0 : Disables w riting
1 : Enables w riting
—
(b7-b6)
Reserved bits When read, the content is 0.
b7 b6 b5 b4 b3 b2 b1 b0
00
PRC0 RW
PRC1 RW
Protect bit 0 Writing to registers CM0, CM1, OCD, FRA0, FRA1,
and FRA2 is enabled.
0 : Disables w riting
1 : Enables w riting
Protect bit 1 Writing to registers PM0 and PM1 is enabled.
0 : Disables w riting
1 : Enables w riting
This bit is set to 0 after w riting 1 to the PRC2 bit and executing a w rite to any address. Since the other bits are not
set to 0, set them to 0 by a program.
PRC2
Protect bit 2 Writing to the PD0 register is enabled.
0 : Disables w riting
1 : Enables w riting(1)
RW
RW
—
(b5-b4)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 122 of 580
REJ09B0324-0200
12. Interrupts
12.1 Interrupt Overview
12.1.1 Types of Interrupts
Figure 12.1 sh ow s th e ty pes of Interrupts .
Figure 12.1 Interrupts
•Maskable Interrupts: The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
•Non-Maskable Interrupts: The interrupt enable flag (I flag) does not enable or disable these interrupt s.
The interrupt priority order cannot be changed based on interrupt priority
level.
Interrupts
(non-maskable interrupts)
Hardware
Software
(non-maskable interrupts)
(maskable interrupts)
Special
Peripheral functions(1)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Single step(2)
Address break(2)
Address match
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. Do not use this interrupt. This is for use with development tools only.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 123 of 580
REJ09B0324-0200
12.1.2 Software Interrupts
A software interrupt is generated when an instructio n is executed. Software interrupts are non-m askable.
12.1.2.1 Undefined Instruction Interrupt
The undefined instruction interrup t is generat e d when the UND instruction is executed.
12.1.2.2 Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
12.1.2.3 BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
12.1.2.4 INT Instruction Interrupt
An INT instruction int errupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the M CU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 124 of 580
REJ09B0324-0200
12.1.3 Special Interrupts
Special interru pts are non-maskable.
12.1.3.1 Watchdog Timer Interrupt
The watchdog timer in terrupt is gen erated by the watchdog timer. For details, refer to 13. Watchdog Timer.
12.1.3.2 Oscillation Stop Detection Interrupt
The oscillation stop detection interru pt is gen erated by the oscillat ion stop detect ion function . For de tails of the
oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3 Voltage Monitor 1 Interrupt
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.4 Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.5 Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by develo pm ent tools only.
12.1.3.6 Address Match Interrupt
The address match interrupt is generat ed immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER 1 bit in the AIER reg ister is set to
1 (address match interrupt enable). For details of the address match in terrupt, refer to 12.4 Address Match
Interrupt.
12.1.4 Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable
interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to th e descript ions of individual peripheral functions.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 125 of 580
REJ09B0324-0200
12.1.5 Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the sta rting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows an Interrupt Vector.
Figure 12.2 Interrupt Vector
12.1.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory.
NOTES:
1. Do not use these interrupts. They are for use by development tools only.
Table 12.1 Fixed Vector Tables
Interrupt Source Vector Addresses
Address (L) to (H) Remarks Reference
Undefined instruction 0FFDCh to 0FFDFh Interrupt on UND
instruction
R8C/Tiny Series Software
Manual
Overflow 0FFE0h to 0FFE3h Interrupt on INTO
instruction
BRK instruction 0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
Address match 0FFE8h to 0FFEBh 12.4 Address Match
Interrupt
Single step(1) 0FFECh to 0FFEFh
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1,
Voltage monitor 2
0FFF0h to 0FFF3h 13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
Address break(1) 0FFF4h to 0FFF7h
(Reserved) 0FFF8h to 0FFFBh
Reset 0FFFCh to 0FFFFh 5. Resets
Vector address (L)
Vector address (H)
MSB LSB
Low address
Mid address
High address0 0 0 0
0 0 0 0 0 0 0 0
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 126 of 580
REJ09B0324-0200
12.1.5.2 Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 12.2 lists the Relocatable Vector Tables.
NOTES:
1. These addresses are relative to those in the INTB register.
2. The IICSEL bit in the PMR register switches functions.
3. The I flag does not disable these interrupts.
Table 12.2 Reloca table Vector Tables
Interrupt Source Vector Addresses(1)
Address (L) to Address (H)
Software
Interrupt
Number
Interrupt Control
Register Reference
BRK instruction(3) +0 to +3 (0000h to 0003h) 0 −R8C/Tiny Series Software
Manual
(Reserved) 1 to 2 −
(Reserved) 3 to 6 −−
Timer RC +28 to +31 (001Ch to 001Fh) 7 TRCIC 14.3 Timer RC
Timer RD
(channel 0)
+32 to +35 (0020h to 0023h) 8 TRD0IC 14.4 Timer RD
Timer RD
(channel 1)
+36 to +39 (0024h to 0027h) 9 TRD1IC
Timer RE +40 to +43 (0028h to 002Bh) 10 TREIC 14.5 Timer RE
UART2 transmit +44 to +47 (002Ch to 002Fh) 11 S2TIC 15. Serial Interface
UART2 receive +48 to +51 (0030h to 0033h) 12 S2RIC
Key input +52 to +55 (0034h to 0037h) 13 KUPIC 12.3 Key Input Interrupt
(Reserved) 14 −−
Clock synchronous
serial I/O with chip
select / I2C bus
interface(2)
+60 to +63 (003Ch to 003Fh) 15 SSUIC/IICIC 16.2 Clock Synchronous
Serial I/O with Chip
Select (SSU),
16.3 I2C bus Interface
Compare 1 +64 to +67 (0040h to 0043h) 16 CMP1IC 14.6 Timer RF
UART0 transmit +68 to +71 (0044h to 0047h) 17 S0TIC 15. Serial Interface
UART0 receive +72 to +75 (0048h to 004Bh) 18 S0RIC
UART1 transmit +76 to +79 (004Ch to 004Fh) 19 S1TIC
UART1 receive +80 to +83 (0050h to 0053h) 20 S1RIC
INT2 +84 to +87 (0054h to 0057h) 21 INT2IC 12.2 INT Interrupt
Timer RA +88 to +91 (0058h to 005Bh) 22 TRAIC 14.1 Timer RA
(Reserved) 23 −−
Timer RB +96 to +99 (0060h to 0063h) 24 TRBIC 14.2 Timer RB
INT1 +100 to +103 (0064h to 0067h) 25 INT1IC 12.2 INT Interrupt
INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC
Timer RF +108 to +111 (006Ch to 006Fh) 27 TRFIC 14.6 Timer RF
Compare 0 +112 to +115 (0070h to 0073h) 28 CMP0IC
INT0 +116 to +119 (0074h to 0077h) 29 INT0IC 12.2 INT Interrupt
A/D +120 to +123 (0078h to 007Bh) 30 ADIC 18. A/D Converter
Capture +124 to +127 (007Ch to 007Fh) 31 CAPIC 14.6 Timer RF
Software interrupt(3) +128 to +131 (0080h to 0083h) to
+252 to +255 (00FCh to 00FFh)
32 to 63 −R8C/Tiny Series Software
Manual
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 127 of 580
REJ09B0324-0200
12.1.6 Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, TRD0IC, TRD1IC,
SSUIC, and IICIC and Figure 12.5 shows the INTiIC Register.
Figure 12.3 Interrupt Control Register
Interrupt Control Register(2)
Address After Reset
004Ah XXXXX000b
004Bh XXXXX000b
004Ch XXXXX000b
004Dh XXXXX000b
0050h XXXXX000b
0051h XXXXX000b
0052h XXXXX000b
0053h XXXXX000b
0054h XXXXX000b
0056h XXXXX000b
0058h XXXXX000b
TRFIC 005Bh XXXXX000b
CMP0IC 005Ch XXXXX000b
005Eh XXXXX000b
005Fh XXXXX000b
Bit Symbol Function RW
NOTES:
1.
2.
Only 0 can be w ritten to the IR bit. Do not w rite 1.
IR 0 : Requests no interrupt
1 : Requests interrupt RW(1)
—
(b7-b4) —
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILV L1 RW
ILV L2 RW
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Ref er to 1 2.6 .5 Changing Interrupt Control Register Contents.
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Bit Name
Interrupt priority level select bits
Interrupt request bit
ILV L0
CA PIC
S1TIC
S1RIC
ADIC
TREIC
TRBIC
S2TIC
S2RIC
TRA IC
KUPIC
CMP1IC
S0TIC
S0RIC
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 128 of 580
REJ09B0324-0200
Figure 12.4 Registers TRCIC, TRD0IC, TRD1IC, SSUIC, and IICIC
Interrupt Control Register(1)
Address After Reset
0047h XXXXX000b
0048h XXXXX000b
0049h XXXXX000b
004Fh XXXXX000b
Bit Symbol Function RW
NOTES:
1.
2.
IR 0 : Requests no interrupt
1 : Requests interrupt RO
—
(b7-b4) —
ILV L0 RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILV L1 RW
ILV L2 RW
The IICSEL bit in the PMR register sw itches functions.
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Ref er to 1 2.6 .5 Changing Interrupt Control Register Contents.
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Symbol
TRD1IC
TRD0IC
SSUIC/IICIC(2)
TRCIC
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 129 of 580
REJ09B0324-0200
Figure 12.5 INTiIC Register
INTi Interrupt Control Register (i=0 to 3)(2)
Symbol Address After Reset
INT2IC 0055h XX00X000b
INT1IC 0059h XX00X000b
INT3IC 005Ah XX00X000b
INT0IC 005Dh XX00X000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is undef ined.
Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
—
(b5)
Reserved bit Set to 0. RW
POL Polarity sw itch bit(4) 0 : Selects f alling edge
1 : Selects rising edge(3) RW
IR Interrupt request bit 0 : Requests no interrupt
1 : Requests interrupt RW(1)
ILV L0 RW
Interrupt priority level select bits b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILV L1 RW
ILV L2 RW
b0
0
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Ref er to 12.6.5 Changing Interrupt Control Register Contents.
If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12. 6.4 Changi ng Interrupt
Sources.
b7 b6 b5 b4 b3 b2 b1
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 130 of 580
REJ09B0324-0200
12.1.6.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not request ed).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrup t and the I2C bus I nterface Interrup t are different. Refer to 12.5 Timer RC Interrupt, Timer RD
Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interfac e Interrupt
(Interrupts with Multiple Interrupt Request Sources).
12.1.6.3 Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrup t is acknowledged:
•I flag = 1
•IR bit = 1
•Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 12.3 Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order
000b Level 0 (interrupt disabled) −
001b Level 1 Low
010b Level 2
011b Level 3
100b Level 4
101b Level 5
110b Level 6
111b Level 7 High
T able 12.4 Interrupt Priority Levels Enabled by
IPL
IPL Enabled Interrupt Priority Levels
000b Interrupt level 1 and above
001b Interrupt level 2 and above
010b Interrupt level 3 and above
011b Interrupt level 4 and above
100b Interrupt level 5 and above
101b Interrupt level 6 and above
110b Interrupt level 7 and above
111b All maskable interrupts are disabled
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 131 of 580
REJ09B0324-0200
12.1.6.4 Interrupt Sequence
An interrupt sequence is p erformed between an interrupt request acknowled gement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU det ermines it s interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instruction if an in terrupt request is generated wh ile the
instruction is being executed, the MCU su spends the instruction to start the inter rupt sequence. The interrup t
sequence is performed as indicated below.
Figure 12.6 show s th e Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interru pt is set to 0 (interrupt not requested).(2)
(2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 3 2 to 63
is executed.
(4) The CPU’s internal temporary register(1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vecto r is stored in the PC.
After the inte rrupt sequence is compl eted, instructions are executed from the starting address of the interrupt
routine.
Figure 12.6 Ti me Required for Executing Interrupt Sequence
NOTES:
1. This register cannot be accessed by the user.
2. Refer to 12.5 Timer RC Interrupt, T imer RD Interrupt, Clock Synchronous Serial I/O with Chip
Select Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request
Sources) for the IR bit operations of the timer RC Interrupt, timer RD Interrupt, Clock Synchronous
Serial I/O with Chip Select Interrupt, and the I 2C bus Interface Interrupt.
1234567891011 12 13 14 15 16 17 18 19 20
CPU Clock
Address Bus
Data Bus
RD
WR
Address
0000h Undefined
Undefined
Undefined
Interrupt
information
SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC
SP-2
contents SP-1
contents SP-4
contents SP-3
contents VEC
contents VEC+1
contents VEC+2
contents
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 132 of 580
REJ09B0324-0200
12.1.6.5 Interrupt Response Time
Figure 12.7 shows the Interrupt Respo nse Time. The interrupt response time is th e period between an interrupt
request generation and the execution of the first i nstructio n in the int errupt routine. The int errupt response ti me
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
Figure 12.7 Interrupt Re sponse Time
12.1.6.6 IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Tabl e 12.5 is set in
the IPL.
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Source Value Set in IPL
Watchdog timer, oscillation stop detection, voltage monitor 1,
voltage monitor 2, Address break
7
Software, address match, single-step Not changed
Interrupt request is generated. Interrupt request is acknowledged.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
(a) 20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a
register is set as the divisor).
(b) 21 cycles for address match and single-step interrupts.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 133 of 580
REJ09B0324-0200
12.1.6.7 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used(1) with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Figure 12.8 Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, wh ich is performed as part o f the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
Figure 12.9 Register Saving Operation
Stack
[SP]
SP value before
interrupt is generated
Previous stack contents
LSBMSB
Address
Previous stack contents
m−4
m−3
m−2
m−1
m
m+1
Stack state before interrupt request
is acknowledged
[SP]
New SP value
Previous stack contents
LSBMSB
Previous stack contents
m
m+1
Stack state after interrupt request
is acknowledged
PCL
PCM
FLGL
FLGH PCH
m−4
m−3
m−2
m−1
Stack
Address
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
NOTE:
1.When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Stack
Completed saving
registers in four
operations.
Address
[SP]−5
[SP]
PCL
PCM
FLGL
FLGH PCH
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
Sequence in which
order registers are
saved
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
[SP]−4
[SP]−3
[SP]−2
[SP]−1
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 134 of 580
REJ09B0324-0200
12.1.6.8 Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the i nterrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
12.1.6.9 Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, their in terrupt pri ority is resolv ed by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 12.10 shows the Priority Levels of Hardware Interrupts.
The interrupt priori ty does not affect software interrupts. The MCU jumps to the interrup t routine when the
instruction is executed.
Figure 12.10 Priority Levels of Hardware Interrupts
Address break
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Peripheral function
Single step
Address match
High
Low
Reset
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 135 of 580
REJ09B0324-0200
12.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority ju dgem e nt circuit selects the highest priority interrupt, as shown in Figure 12.11.
Figure 12.11 Interrupt Priority Level Judgement Circuit
UART1 receive
UART0 receive
UART2 receive
UART0 transmit
SSU / I2C bus(1)
Key input
IPL Lowest
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Interrupt request level
judgment output signal
Interrupt request
acknowledged
I flag
Address match
Watchdog timer
Oscillation stop detection
Voltage monitor 1
NOTE:
1. The IICSEL bit in the PMR register switches functions.
INT2
UART1 transmit
Timer RE
Timer RD0
Timer RD1
INT0
INT1
INT3
Timer RB
Timer RA
Priority level of interrupt
Level 0 (default value)
Voltage monitor 2
A/D conversion
Compare 0
Timer RF
Timer RC
Compare 1
UART2 transmit
Capture
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 136 of 580
REJ09B0324-0200
12.2 INT Interrupt
12.2.1 INTi Interrupt (i = 0 to 3)
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register. The INT1 input and the INT2 input can select the input pin.
Inputs can be passed through a digital filter wit h three di fferent sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff of timer RC and timer RD, and the external trigger
input of timer RB.
Figure 12.12 shows the PMR Register, Figure 12.13 shows the INTEN Register, Figure 12.14 shows the INTF
Register, and Figure 12.15 shows the TRAIOC Register
Figure 12.12 P M R Re gi ster
Port Mode Registe
r
Symbol Address Af ter Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ pin select bit
INT2
_
____ pin select bit
IICSEL RW
0 : Selects SSU function
1 : Selects I
2C bus function
0 : Selects P6_6
1 : Selects P3_2
To use the UART1, set to 1.
Set to 0.
RW
SSU / I2C bus sw itch bit
RW
b0
RW
Res er v ed bits
U1 PINSEL UART1 enable bit
INT2SEL
—
(b6-b5)
INT1SEL 0 : Selects P1_5, P1_7
1 : Selects P3_6
b3 b2
0
b1
0
b7 b6 b5 b4
00
RW
—
(b3-b2)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 137 of 580
REJ09B0324-0200
Figure 12.13 INTEN Register
External Input Enable Register
Symbol Address After Reset
INTEN 00F9h 00h
Bit Symbol Bit Name Function RW
INT0
_
____
input enable bit
INT0
_
____ input polarity select bit(1,2)
INT1
_
____ input enable bit
INT1
_
____ input polarity select bit(1,2)
INT2
_
____ input enable bit
INT2
_
____ input polarity select bit(1,2)
INT3
_
____ input enable bit
INT3
_
____ input polarity select bit(1,2)
NOTES:
1.
2.
0 : Disable
1 : Enable RW
INT2EN 0 : Disable
1 : Enable RW
INT2 PL 0 : One edge
1 : Both edges RW
When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4
Changing Interrupt Sources.
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
RW
INT0 PL RW
INT1EN 0 : Disable
1 : Enable
RW
INT0EN
RW
INT1 PL 0 : One edge
1 : Both edges RW
INT3EN
INT3 PL
b3 b2 b1 b0b7 b6 b5 b4
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 138 of 580
REJ09B0324-0200
Figure 12.1 4 INTF Regi st er
Figure 12.15 TRAIOC Register
INT
_
____
Input Filter Select Registe
r
Symbol Address After Reset
INTF 00FAh 00h
Bit Symbol Bit Name Function RW
INT0
_____
input f ilter select bits
INT1
_____ input f ilter select bits
INT2
_____
input f ilter select bits
INT3
_____ input f ilter select bits
INT0F0 RW
INT0F1 RW
b7 b6 b5 b4 b3 b2 b1 b0
RW
b1 b0
0 0 : No filter
0 1 : Filter w ith f 1 sampling
1 0 : Filter w ith f 8 sampling
1 1 : Filter w ith f 32 sampling
RW
b7 b6
0 0 : No filter
0 1 : Filter w ith f 1 sampling
1 0 : Filter w ith f 8 sampling
1 1 : Filter w ith f 32 sampling
INT3F1
INT3F0
INT1F0
b3 b2
0 0 : No filter
0 1 : Filter w ith f 1 sampling
1 0 : Filter w ith f 8 sampling
1 1 : Filter w ith f 32 sampling
RW
INT1F1 RW
INT2F0
b5 b4
0 0 : No filter
0 1 : Filter w ith f 1 sampling
1 0 : Filter w ith f 8 sampling
1 1 : Filter w ith f 32 sampling
RW
INT2F1 RW
Timer RA I/O Control Registe
r
Symbol Address Af ter Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
b3 b2
TIOSEL
b1 b0
TEDGSEL
b7 b6 b5 b4
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0 RW
TIPF1
RW
TRAIO polarity sw itch bit Function varies depending on operating mode.
TRAIO output control bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Function varies depending on operating mode.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 139 of 580
REJ09B0324-0200
12.2.2 INTi Input Filter (i = 0 to 3)
The INTi input contains a dig ital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF
register.
The INT i level is sampled every sampling clock cycle and if the sampled input level matches three times, the IR
bit in the INTiIC register is set to 1 (interrupt requested).
Figure 12.16 sh ows the Configuration of INTi Input Filter. Figure 12.17 shows an Operating Example of INTi
Input Filter.
Figure 12.16 Configuration of INTi Input Filter
Figure 12.17 Operating Example of INTi Input Filter
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0 to 3
= 01b
INTi
Port direction
register(1)
Sampling clock
Digital filter
(input level
matches 3x)
INTi interrupt
= 10b
= 11b
f32
f8
f1
INTiF1 to INTiF0
INTiEN
Other than
INTiF1 to INTiF0
= 00b
= 00b INTiPL = 0
INTiPL = 1
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin
Port P1_7 direction register when using the P1_7 pin
Port P3_6 direction register when using the P3_6 pin
INT2: Port P6_6 direction register when using the P6_6 pin
Port P3_2 direction register when using the P3_2 pin
INT3: Port P6_7 direction register
Both edges
detection
circuit
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 by a program
This is an operation example when bits INTiF1 to INTiF0 in the
INTiF register are set to 01b, 10b, or 11b (digital filter enabled).
i = 0 to 3
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 140 of 580
REJ09B0324-0200
12.3 Key Input In terrupt
A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can
be used as a key-on wake-up function to exit wait or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN regist er can select whether or not the pins are used as KIi input. The KIiPL
bit in the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 12.18 shows a Block Diag ram of Key Input Interrupt.
Figure 12.18 Block Diagram of Key Input Interrupt
KI3
Pull-up
transistor
KI2
Pull-up
transistor
KI3PL = 0
KI3PL = 1
PD1_3 bit
KI3EN bit
PU02 bit in PUR0 register
PD1_3 bit in PD1 register
KUPIC register
Interrupt control
circuit
Key input interrupt
request
KI2PL = 0
KI2PL = 1
PD1_2 bit
KI2EN bit
KI1
Pull-up
transistor KI1PL = 0
KI1PL = 1
PD1_1 bit
KI1EN bit
KI0
Pull-up
transistor KI0PL = 0
KI0PL = 1
PD1_0 bit
KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 141 of 580
REJ09B0324-0200
Figure 12.1 9 KIEN Regist er
Key Input Enable Register(1)
Symbol Address After Reset
KIEN 00FBh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
KI3 input polarity select bit 0 : Falling edge
1 : Rising edge
KI0EN RW
KI0PL RW
KI0 input enable bit 0 : Disable
1 : Enable
RW
0 : Disable
1 : Enable
The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.
Ref er to 12.6.4 Changing Interrupt Sources.
KI1EN RW
KI3EN KI3 input enable bit
KI3PL RW
KI2PL KI2 input polarity select bit 0 : Falling edge
1 : Rising edge
b1 b0b7 b6 b5 b4 b3 b2
RW
KI2EN RW
KI1PL KI1 input polarity select bit 0 : Falling edge
1 : Rising edge
KI2 input enable bit 0 : Disable
1 : Enable
RW
KI0 input polarity select bit 0 : Falling edge
1 : Rising edge
KI1 input enable bit 0 : Disable
1 : Enable
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 142 of 580
REJ09B0324-0200
12.4 Address Match Interrupt
An address ma tch interrupt reques t is generated imme diately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register . Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match inte rrupt.
The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match inter rupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
•Change the content of the stack and use the REIT instruction.
•Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowl edged.
Then use a jump instruction.
Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged.
Figure 12.20 shows Registers AIER and RMAD0 to RMAD1.
NOTES:
1. Refer to the 12.1.6.7 Savi n g a Re gi st er for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 12.6 Values of PC Saved to Stack wh en Address Match Interrupt is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved(1)
• Instruction with 2-byte operation code(2)
• Instruction with 1-byte operation code(2)
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest
STNZ #IMM8,dest STZX #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (however, dest = A0 or A1)
Address indicated by
RMADi register + 2
• Instructions other than the above Address indicated by
RMADi register + 1
Table 12.7
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 143 of 580
REJ09B0324-0200
Figure 12.2 0 Registers AI ER and RMAD0 to RMAD1
A
ddress Match Interrupt Enable Registe
r
Symbol Address After Reset
AIER 0013h 00h
Bit Symbol Bit Name Function RW
AIER1 Address match interrupt 1 enable bit
AIER0 0 : Disable
1 : Enable RW
b2 b1 b0
Address match interrupt 0 enable bit
—
(b7-b2) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4
0 : Disable
1 : Enable RW
b3
Address Match Interrupt Register i(i = 0 or 1)
b0
Symbol Address After Reset
RMA D0 0012h-0010h 000000h
RMA D1 0016h-0014h 000000h
Setting Range RWFunction
RW
(b19)
b3
(b15)
b7
(b8)
b0 b7
—
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Address setting register for address match interrupt 00000h to FFFFFh
(b16)
b0
(b23)
b7
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 144 of 580
REJ09B0324-0200
12.5 Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with
Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with
Multiple Interrupt Request Sources)
The timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1) interru pt, clock synchronous serial
I/O with chip select interrupt, and I2C bus interface interrupt each have multiple interrupt request sources. An
interrupt request is generated by the logical OR of several interrupt request factors and is reflected i n the IR bit in
the corresponding interrupt control register. Therefore, each of these peripheral functions has its own interrupt
request source status register (status register) and interrupt request source enable register (enable register) to
control the gene ration of interrupt requests (c hange the IR b it in the interrupt cont rol register). Table 12.8 lists the
Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt, and I2C bus Interface Interrupt and Figure 12.21 shows a Block Diagram of Timer RD Interrupt.
Figure 12.21 Block Diagram of Timer RD Interrupt
Table 12.8 Registers Associated with Timer RC Interrupt, T imer RD Interrupt, Clock
Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Inte rrup t
Peripheral Function
Name
Status Register of
Interrupt Request Source
Enable Register of
Interrupt Request
Source
Interrupt Control
Register
Timer RC
TRCSR
TRCIER TRCIC
Timer RD Channel 0 TRDSR0 TRDIER0 TRD0IC
Channel 1 TRDSR1 TRDIER1 TRD1IC
Clock synchronous serial
I/O with chip select
SSSR SSER SSUIC
I2C bus interface ICSR ICIER IICIC
Timer RD (channel i)
interrupt request
(IR bit in TRDiIC register)
IMFA bit
IMIEA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Channel i
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 145 of 580
REJ09B0324-0200
As with other maskable interrupts, the timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1)
interrupt, cloc k synchronou s serial I/O with chip select interrupt, an d I2C bus interface interrupt are controlled by
the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is
generated by a combi nation of multiple interru pt request sources, the following differences from other maskable
interrupts apply:
•When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
•When either bits in the status register or bits in the enable register corresponding to bits in the status register , or
both, are set to 0, the IR bit is set to 0 (interru pt not requested). B asically, even though the interrupt is not
acknowledged after the IR bit is set to 1, the interrupt request will not be main tained. Also, the I R bi t is not set
to 0 even if 0 is written to the IR bit.
•Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowl edged. Set each bit in the
status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the
status register to 0.
•When multiple bi ts in the enable regist er are set to 1 an d other requ est sources are generat ed after the IR bi t is
set to 1, the IR bit remains 1.
•When multiple bits in the enable register are set to 1, determine by the status register which request source
causes an interrupt.
Refer to chapters of the individual peripheral functions (14.3 Timer RC, 14.4 Timer RD, 16.2 Clock
Synchronous Serial I/O with Chip Select (SSU) and 16 .3 I2C bus Interface) for the status register and enable
register.
Refer to 12.1.6 Interrupt Control for the interrupt control register.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 146 of 580
REJ09B0324-0200
12.6 Notes on Interrupts
12.6.1 Reading Address 00000h
Do not read address 0000 0h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
12.6.2 SP Setting
Set any value in the SP before an interrupt is acknowl edged. The SP i s set to 000 0h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
12.6.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is ne cessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, re fer to Table 21.22 (V CC = 5V), Table 21.29 (VCC = 3V), Table 21.36 (VCC = 2.2V) External
Interrupt INTi (i = 0, 2, 3) Input and Table 21.19 (VCC = 5V), Table 21.26 (VCC = 3V), Table 21.33 (VCC
= 2.2V) TRAIO Input, INT1 Input.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 147 of 580
REJ09B0324-0200
12.6.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involve s interrupt so urces, edge polarities, an d timing, set t he IR bit to 0 (no i nterrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 12.22 shows an Examp le of Procedure for Changing Interrupt Sources.
Figure 12.22 Example of Procedure for Changing Interrupt Sources
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated,
disable the peripheral function before changing the
interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled. If all maskable interrupts cannot
be disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Interrupt source change
Disable interrupts(2, 3)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Change interrupt source (including mode
of peripheral function)
Enable interrupts(2, 3)
Change completed
IR bit: The interrupt control register bit of an
interrupt whose source is changed.
R8C/2A Group, R8C/2B Group 12. Interrupts
Rev.2.00 Nov 26, 2007 Page 148 of 580
REJ09B0324-0200
12.6.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are gen erated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt req uested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR , BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the samp le programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts
R8C/2A Group, R8C/2B Group 13. Watchdog Timer
Rev.2.00 Nov 26, 2007 Page 149 of 580
REJ09B0324-0200
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Watchdog Timer Specifications.
Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diag ram of Wa tchdog Timer. Figure 13.2 shows the Registers WDTR, WDTS, and
WDC. Figure 13.3 shows the Registers CSPR and OFS.
Table 13.1 Wa tchdog Timer Specifications
Item Count Source Protection
Mode Disabled
Count Source Protection
Mode Enabled
Count source CPU clock Low-speed on-chip oscillator
clock
Count operation Decrement
Count start condition Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition Stop mode, wait mode None
Reset condition of watchdog
timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time of underflow Watchdog timer interrupt or
watchdog timer reset
Watchdog timer reset
Select functions • Division ratio of prescaler
Selected by the WDC7 bit in the WDC register
• Count source protection mode
Whether count source protection mode is enabled or disabled after a
reset can be selected by the CSPROINI bit in the OFS register (flash
memory). If count source protection mode is disabled after a reset, it
can be enabled or disabled by the CSPRO bit in the CSPR register
(program).
• Starts or stops of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
R8C/2A Group, R8C/2B Group 13. Watchdog Timer
Rev.2.00 Nov 26, 2007 Page 150 of 580
REJ09B0324-0200
Figure 13.1 Block Diagram of Watchdog Timer
Internal reset signal
(“L” active)
Write to WDTR register
Set to
7FFFh(1)
PM12 = 1
Watchdog
timer reset
PM12 = 0
Watchdog timer
interrupt request
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
CM07: Bit in CM0 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
1/128
1/2
CM07 = 1
Prescaler
CSPRO = 0
fOCO-S
CSPRO = 1
1/16
CM07 = 0,
WDC7 = 0
CM07 = 0,
WDC7 = 1
CPU clock Watchdog timer
R8C/2A Group, R8C/2B Group 13. Watchdog Timer
Rev.2.00 Nov 26, 2007 Page 151 of 580
REJ09B0324-0200
Figure 13.2 Registers WDTR, WDTS, and WDC
Watchdog Timer Control Register
Symbol Address After Reset
WDC 000Fh 00X11111b
Bit Symbol Bit Name Function RW
b3 b2 b1 b0
RW
High-order bits of w atchdog timer—
(b4-b0)
RW
—
(b5) RW
00
b7 b6 b5 b4
Reserved bit Set to 0. When read, the content is undefined.
RO
WDC7
—
(b6)
Reserved bit Set to 0.
Prescaler select bit 0 : Divide-by-16
1 : Divide-by-128
Watchdog Timer Reset Register
Symbol Address After Reset
WDTR 000Dh Undefined
RW
NOTES:
1.
2.
Function
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)
b7 b0
Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is s et in the w atchdog timer.
WO
Watchdog Timer Start Register
Symbol Address After Reset
WDTS 000Eh Undefined
RW
WO
Function
The w atchdog timer starts counting after a w rite instruction to this register.
b0b7
R8C/2A Group, R8C/2B Group 13. Watchdog Timer
Rev.2.00 Nov 26, 2007 Page 152 of 580
REJ09B0324-0200
Figure 13.3 Registers CSPR and OFS
Count Source Protection Mode Register
Symbol Address After Reset(1)
CSPR 001Ch 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
(b6-b0) RW
00
Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
0
Reserved bits Set to 0.
RW
0
CSPRO Count source protection mode
select bit(2)
0 : Count source protection mode disabled
1 : Count source protection mode enabled
b3 b2 b1 b0b7 b6 b5 b4
000
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
R8C/2A Group, R8C/2B Group 13. Watchdog Timer
Rev.2.00 Nov 26, 2007 Page 153 of 580
REJ09B0324-0200
13.1 Count Source Protection Mode Disabled
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Item Specification
Count source CPU clock
Count operation Decrement
Period
Division ratio of prescaler (n) × count value of watchdog timer (32768)
(1)
CPU clock
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
divided by 16, the period is approximately 32.8 ms
Reset condition of watchdog
timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count start condition The WDTON bit(2) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting)
• The watchdog timer and prescaler start counting automatically after a
reset
Count stop condition Stop and wait modes (inherit the count from the held value after exiting
modes)
Operation at time of underflow • When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
R8C/2A Group, R8C/2B Group 13. Watchdog Timer
Rev.2.00 Nov 26, 2007 Page 154 of 580
REJ09B0324-0200
13.2 Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI
bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with
a flash programmer.
Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item Specification
Count source Low-speed on-chip oscillator clock
Count operation Decrement
Period Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed on-
chip oscillator clock frequency is 125 kHz
Reset condition of watchdog
timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count start condition The WDTON bit(1) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
a reset
Count stop condition None (The count does not stop in wait mode after the count starts.
The MCU does not enter stop mode.)
Operation at time of underflow Watchdog timer reset (Refer to 5.6 Watchdo g Timer Reset.)
Registers, bits • When setting the CSPPRO bit in the CSPR register to 1 (count
source protection mode is enabled)(2), the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 155 of 580
REJ09B0324-0200
14. Timers
The MCU has two 8-bit timers with 8-bit prescalers, three 16-bit timers, and a timer with a 4-bit counter and an 8-bi t
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to
store the default value of the counter. The three 16-bit timers is timer RC, timer RD, and timer RF, and have input
capture and output compare functions. The 4-bit and 8-bit counters are ti mer RE, and has an outp ut comp are function .
All the timers operate independ ently.
Tables 14.1 and 14.2 list Functional Comparison of Timers.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 156 of 580
REJ09B0324-0200
NOTE:
1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of
the pulses are the same.
Table 14.1 Functional Comparison of Timers (1)
Item Timer RA Timer RB Timer RC Timer RD Timer RE Timer RF
Configuration 8-bit timer
with 8-bit
prescaler
(with reload
register)
8-bit timer with
8-bit prescaler
(with reload
register)
16-bit timer (with
input capture and
output compare)
16-bit timer × 2
(with input capture
and output
compare)
4-bit counter
8-bit counter
16-bit timer
(with input
capture and
output
compare)
Count Decrement Decrement Increment Increment/
Decrement
Increment Increment
Count sources • f1
•f2
•f8
•fOCO
•fC32
•f1
•f2
•f8
•Timer RA
underflow
•f1
•f2
•f4
•f8
•f32
• fOCO40M
• TRCCLK
•f1
•f2
•f4
•f8
•f32
• fOCO40M
•TRDIOA0
•f4
•f8
•f32
•fC4
•f1
•f8
•f32
Function Count of the
internal count
source
Timer mode Timer mode Timer mode
(output compare
function)
Timer mode
(output compare
function)
— Output
compare
mode
Count of the
external count
source
Event counter
mode
— Timer mode
(output compare
function)
Timer mode
(output compare
function)
——
External pulse
width/period
measurement
Pulse width
measurement
mode, pulse
period
measurement
mode
— Timer mode (input
capture function; 4
pins)
Timer mode (input
compare function;
2 channels × 4
pins)
— Input capture
mode
PWM output Pulse output
mode(1),
Event counter
mode(1)
Programmable
waveform
generation
mode
Timer mode
(output compare
function; 4 pins)(1),
PWM mode (3 pins),
PWM2 mode (1 pin)
Timer mode
(output compare
function; 2
channels
× 4 pins)
(1),
PWM mode
(2 channels × 3 pins),
PWM3 mode
(2 channels × 2 pins)
Output
compare
mode(1)
Output
compare
mode
One-shot
waveform
output
— Programmable
one-shot
generation
mode,
Programmable
wait one-shot
generation
mode
PWM mode (3 pins)
PWM mode
(2 channels × 3 pins)
——
Three-phase
waveforms
output
—— — Reset
synchronous PWM
mode (2 channels
× 3 pins, Sawtooth
wave modulation),
Complementary
PWM mode
(2 channels × 3 pins,
triangular wave
modulation, dead
time)
——
Timer Timer mode
(only fC32
count)
— — — Real-time
clock mode
—
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 157 of 580
REJ09B0324-0200
NOTE:
1. The underflow interrupt can be set to channel 1.
Table 14.2 Functional Comparison of Timers (2)
Item Timer RA Timer RB Timer RC Timer RD Timer RE Timer RF
Input pin TRAIO INT0 INT0, TRCCLK,
TRCTRG,
TRCIOA,
TRCIOB,
TRCIOC,
TRCIOD
INT0, TRDCLK,
TRDIOA0,
TRDIOA1,
TRDIOB0,
TRDIOB1,
TRDIOC0,
TRDIOC1,
TRDIOD0,
TRDIOD1
—TRFI
Output pin TRAO
TRAIO
TRBO TRCIOA,
TRCIOB,
TRCIOC,
TRCIOD
TRDIOA0,
TRDIOA1,
TRDIOB0,
TRDIOB1,
TRDIOC0,
TRDIOC1,
TRDIOD0,
TRDIOD1
TREO TRFO00 to
TRFO02,
TRFO10 to
TRFO12
Related interrupt Timer RA
interrupt,
INT1 interrupt
Timer RB
interrupt,
INT0 interrupt
Compare match/
input capture A
to D interrupt,
Overflow
interrupt,
INT0 interrupt
Compare match/
input capture A0 to
D0 interrupt,
Compare match/
input capture A1 to
D1 interrupt,
Overflow interrupt,
Underflow
interrupt(1),
INT0 interrupt
Timer RE
interrupt
Timer RF
interrupt,
Compare 0
interrupt,
Compare 1
interrupt,
Timer stop Provided Provided Provided Provided Provided Provided
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 158 of 580
REJ09B0324-0200
14.1 Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.3 to 14.7
the Specifications of Each Mode).
The count source for t im er RA is the operating cl ock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.1 shows a Blo ck Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associat ed with Timer
RA.
Timer RA has the following five operating modes:
•Timer mode: The timer counts the internal count source.
•Pulse output mode: The timer count s the in tern al count source and outputs pul ses of which
polarity inverted by underflow of th e timer.
•Event counter mode: The timer counts external pulses.
•Pulse width measurement mode: The timer measures the pulse width of an external pulse.
•Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Figure 14.1 Block Diagram of Timer RA
= 000b
= 001b
= 011b
f2
f8
f1
= 010b
fOCO
TCK2 to TCK0 bit
TMOD2 to TMOD0
= other than 010b
Counter
Reload
register
TRAPRE register
(prescaler)
Data bus
Timer RA interrupt
Write to TRAMR register
Write 1 to TSTOP bit
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
Toggle flip-flop
Q
QCLR
CK
TOENA bit
TRAO pin
INT1/TRAIO (P1_5) pin
TCSTF bit
TCKCUT bit
TMOD2 to TMOD0
= 011b or 100b
TMOD2 to TMOD0
= 010b
Polarity
switching
Digital
filter
Counter
Reload
register
TRA register
(timer)
TIPF1 to TIPF0 bits
= 01b
= 10b
f8
f1
= 11b
f32
TIOSEL = 0
TIOSEL = 1
Count control
circle
TMOD2 to TMOD0 = 001b
TOPCR bit
Underflow signal
Measurement completion
signal
TIPF1 to TIPF0 bits
= other than
000b
= 00b
INT1/TRAIO (P1_7) pin
TEDGSEL = 1
TEDGSEL = 0
= 100b
fC32
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 159 of 580
REJ09B0324-0200
Figure 14.2 Registers TRACR and TRAIOC
Timer RA Control Register(4)
Symbol Address After Reset
TRA CR 0100h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
Timer RA count start bit(1)
Timer RA count forcible stop
bit(2)
In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
Set to 0 in timer mode, pulse output mode, and event counter mode.
Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
TUNDF
When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values af ter
a reset.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Ref er to 14.1.6 Notes on Timer RA.
—
(b7-b6)
b7 b6 b5 b4 b3 b2
When this bit is set to 1, the count is f orcibly
stopped. When read, its content is 0.
—
(b3)
b1 b0
—
—
RW
TEDGF
0 : Active edge not received
1 : Active edge received
(end of measurement period)
Active edge judgment
flag(3, 5)
Timer RA underflow flag(3, 5) 0 : No underflow
1 : Underflow
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
TCSTF
RW
RW
RO
TSTA RT
0 : Count stops
1 : During count
0 : Count stops
1 : Count starts
Timer RA count status flag(1)
TSTOP
Timer RA I/O Control Registe
r
Symbol Address Af ter Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit RW
TIPF0 RW
TOENA RW
TRAIO input filter select bits
TIPF1
Function varies depending on operating mode.
—
TEDGSEL RW
TOPCR RW
TRAIO polarity sw itch bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b6)
TRAIO output control bit
TRAO output enable bit
b7 b6 b5 b4 b3 b2
TIOSEL
b1 b0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 160 of 580
REJ09B0324-0200
Figure 14.3 Registers TRAMR, TRAPRE, and TRA
Timer RA Mode Register(1)
Symbol Address After Reset
TRA MR 0102h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
TCKCUT
TCK1
b3 b2
—
(b3)
b1 b0
RW
Timer RA count source
select bits
b6 b5 b4
0 0 0 : f1
0 0 1 : f8
0 1 0 : fOCO
0 1 1 : f2
1 0 0 : fC32
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
b7 b6 b5 b4
RW
TMOD1 RW
TMOD0
Timer RA operating mode
select bits
b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
0 1 1 : Pulse w idth measurement mode
1 0 0 : Pulse period measurement mode
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
TMOD2 RW
—
TCK0 RW
When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
RW
Timer RA count source
cutoff bit
0 : Provides count source
1 : Cuts off count source
TCK2
Timer RA Prescaler Register
Symbol Address After Reset
TRA PRE 0103h FFh(1)
Mode Function Setting Range RW
NOTE:
1.
RW
Pulse w idth
measurement mode
b0
Timer mod e RW
b7
Counts an internal count source 00h to FFh
Pulse output mode RWCounts an internal count source 00h to FFh
Counts internal count source
When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Event counter mode Counts an external count source 00h to FFh RW
00h to FFh RW
Pulse period
measurement mode 00h to FFh
Timer RA Register
Symbol Address After Reset
TRA 0104h FFh(1)
Mode Function Setting Range RW
NOTE:
1.
00h to FFh
b7
When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
b0
All modes Counts on underf low of timer RA prescaler
register RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 161 of 580
REJ09B0324-0200
14.1.1 Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 14.3 Timer Mode
Specifications).
Figure 14.4 sh ow s TRAIOC Register in Timer Mode.
Figure 14.4 TRAIOC Register in Timer Mode
Table 14.3 Timer Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function
Programmable I/O port, or INT1 interrupt input
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Timer RA I/O Control Register
Symbol Address Af ter Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Set to 0 in timer mode.
RW
TRAIO polarity sw itch bit
0
Set to 0 in timer mode.
TRAIO output control bit
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0 RW
TIPF1
00
b7 b6 b5 b4 b3 b2
TIOSEL
b1 b0
00
TEDGSEL
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 162 of 580
REJ09B0324-0200
14.1.1.1 Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WR ITE instruction is executed.
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Figure 14.5 Operating Example of Timer RA when Count er Value is Rewritten during Count
Operation
Count source
Reloads register of
timer RA prescaler
IR bit in TRAIC
register 0
Counter of
timer RA prescaler
Reloads register of
timer RA
Counter of timer RA
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
After writing, the reload register is
written to at the first count source.
Reload at
second count
source
Reload at
underflow
After writing, the reload register is
written to at the first underflow.
Reload at the second underflow
The IR bit remains unchanged until underflow is
generated by a new value.
05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h
New value (01h)Previous value
New value (25h)Previous value
03h 24h02h 25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 163 of 580
REJ09B0324-0200
14.1.2 Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with i nverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 14.4 Pulse Output Mode
Specifications).
Figure 14.6 shows TRAIOC Register in Pulse Output Mode.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Table 14.4 Pulse Outp ut Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function
Pulse output, programmable output port, or INT1 interrupt(1)
TRAO pin function Programmable I/O port or inverted output of TRAIO(1)
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1 .1.1 T i mer W ri te Control
during Count Operation).
Select functions • TRAIO output polarity switch function
The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse
output.(1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO pin
(selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
•INT1
/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 164 of 580
REJ09B0324-0200
Figure 14.6 TRAIOC Register in Pulse Output Mode
Timer RA I/O Control Registe
r
Symbol Address Af ter Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____
/TRAIO pin (P1_5)
b3 b2
0 : Po r t P3_ 0
1 : TRAO output (inverted TRAIO output from P3_0)
TIOSEL
b1 b0
0 : TRAIO output starts at “H”
1 : TRAIO output starts at “L”
b7 b6 b5 b4
00
TIPF1
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0
TRAIO output control bit
TEDGSEL RW
TRAIO polarity sw itch bit
RW
RW
0 : TRAIO output
1 : Port P1_7 or P1_5
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Set to 0 in pulse output mode.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 165 of 580
REJ09B0324-0200
14.1.3 Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are cou nted (refer to Table 14.5 Event
Counter Mode Specifications).
Figure 14.7 show s TRAIOC Register in Event Counter Mode.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Table 14.5 Event Counter Mode Specifications
Item Specification
Count source External signal which is input to TRAIO pin (active edge selectable by a program)
Count operations • Decrement
• When the timer underflows, the contents of the reload register are reloaded and
the count is continued.
Divide ratio 1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function
Count source input (INT1 interrupt input)
TRAO pin function Programmable I/O port or pulse output(1)
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 T imer Write Control
during Count Operation).
Select functions •NT1
input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the count
source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register)(1).
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter
and select the sampling frequency.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 166 of 580
REJ09B0324-0200
Figure 14.7 TRAIOC Register in Event Counter Mode
Timer RA I/O Control Registe
r
Symbol Address Af ter Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
NOTE:
1.
—
When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
TRAIO output control bit Set to 0 in event counter mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
TIPF1
—
(b7-b6)
RW
TEDGSEL RW
TRAIO polarity sw itch bit
RW
TIPF0
RW
TOPCR RW
b3 b2b7 b6 b5 b4
0 : Po r t P3_0
1 : TRAO output
TIOSEL
b1 b0
0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”
1 : Starts counting at falling edge of the TRAIO
input or TRAIO starts output at “H”
0
TOENA
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 167 of 580
REJ09B0324-0200
14.1.4 Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.6 Pulse Width Measurement Mode Specifications).
Figure 14.8 shows TRAIOC Reg ister in Pulse Width Measurement Mode and Figure 14.9 shows an Operating
Example of Pulse Width Measurement Mode.
Table 14.6 Pulse Width Measurement Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• Continuously counts the selected signal only when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 T imer Write
Control during Count Operation).
Select functions • Measurement level select
• The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 168 of 580
REJ09B0324-0200
Figure 14.8 TRAIOC Register in Pulse Width Measurement Mode
Timer RA I/O Control Registe
r
Symbol Address Af ter Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
b3 b2
TIOSEL
b1 b0
0 : TRAIO input starts at “L”
1 : TRAIO input starts at “H”
00
b7 b6 b5 b4
—
TOPCR RW
TOENA RW
RW
TIPF0
RW
TRAIO output control bit
TEDGSEL RW
TRAIO polarity sw itch bit
TIPF1
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0 in pulse w idth measurement mode.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 169 of 580
REJ09B0324-0200
Figure 14.9 Operating Example of Pulse Width Measurement Mode
FFFFh
n
0000h
Content of counter (hex)
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
Count start
Count stop
Underflow
Period
TSTART bit in
TRACR register
1
0
Measured pulse
(TRAIO pin input)
1
0
TEDGF bit in
TRACR register
1
0
TUNDF bit in
TRACR register
1
0
• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Set to 1 by program
IR bit in TRAIC
register
1
0
Set to 0 by program
Count stop
Count start
Set to 0 when interrupt request is acknowledged, or set by program
Count start
Set to 0 by program
The above applies under the following conditions.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 170 of 580
REJ09B0324-0200
14.1.5 Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.7 Pulse Period Measurement Mode Specifications).
Figure 14.10 the shows TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an
Operating Example of Pulse Period Measurement Mode.
NOTE:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to
the TRAIO pin, the input may be ignored.
Table 14.7 Pulse Period Measurement Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO, fC32
Count operations • Decrement
• After the active edge of the measured pulse is input, the contents of the read-
out buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input)
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Select functions • Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measurement period of
the input pulse.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 171 of 580
REJ09B0324-0200
Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode
Timer RA I/O Control Register
Symbol Address After Reset
TRA IOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ /TRAIO select bit 0 : INT1
_
____ /TRAIO pin (P1_7)
1 : INT1
_
____ /TRAIO pin (P1_5)
NOTE:
1.
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select
bits(1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0 in pulse period measurement mode.
TEDGSEL RW
TRAIO polarity sw itch bit
—
TOPCR RW
TOENA RW
RW
TIPF0
RW
TRAIO output control bit
TIPF1
b7 b6 b5 b4
When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
b3 b2
TIOSEL
b1 b0
0 : Measures measurement pulse from one
rising edge to next rising edge
1 : Measures measurement pulse from one
f alling edge to next falling edge
00
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 172 of 580
REJ09B0324-0200
Figure 14.11 Operating Example of Pu lse Period Measurement Mode
Underflow signal of
timer RA prescaler
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh
0Dh
0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h
TSTART bit in
TRACR register
1
0
1
0
1
0
TEDGF bit in
TRACR register
1
0
Measurement pulse
(TRAIO pin input)
Contents of TRA
1
0
Contents of read-out
buffer(1)
IR bit in TRAIC
register
TUNDF bit in
TRACR register
Set to 1 by program
Starts counting
TRA reloads
TRA read(3)
Retained
(Note 2)
Set to 0 by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
0Eh
TRA reloads
Retained
Set to 0 when interrupt request is acknowledged, or set by program
Set to 0 by program
Underflow
(Note 2)
(Note 4)
(Note 6)
(Note 5)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 173 of 580
REJ09B0324-0200
14.1.6 Notes on Timer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR regi ster, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instru ction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with tim er RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (duri ng count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continu ously written during count operation (TCSTF bit is set to 1), all ow
three or more cycles of the count source clock for each write interval.
• When the TRA register is cont inuously writt en during cou nt operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 174 of 580
REJ09B0324-0200
14.2 Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 14.8 to 14.11 the
Specifications of Each Mode).
Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 and 14.15 show the registers associated with
timer RB.
Timer RB has four operation modes listed as follows:
•Timer mode: The timer counts an internal count source (peripheral
function clock or timer RA underflows ).
•Programmable waveform generation mode: The timer outputs pulses of a given width successively.
•Programmable one-shot generation mode: The timer outputs a one-shot pulse.
•Programmable wait one-shot generation mode: The timer outputs a delayed one-shot pulse.
Figure 14.12 Block Diagram of Timer RB
INT0PL bit
= 00b
= 01b
= 11b
f8
f1
= 10b
Timer RA underflow
TCK1 to TCK0 bits
TCSTF bit
TRBPRE register
(prescaler)
Timer RB interrupt
INT0 interrupt
TCSTF bit
Toggle flip-flop
Q
QCLR
CK
TOPL = 1
TOPL = 0
TRBO pin
TOCNT = 0
TOCNT = 1
P3_1 bit in P3 register
f2 TMOD1 to TMOD0 bits
= 10b or 11b
TOSSTF bit
Polarity
select
INOSEG bit
Input polarity
selected to be one
edge or both edges
Digital filter
INT0 pin
INT0EN bit
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
Counter
Reload
register
Counter (timer RB)
Reload
register
TRBPR
register
Data bus
TRBSC
register
Reload
register
TCKCUT bit
INOSTG bit
TCSTF: Bit in TRBCR register
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
(Timer)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 175 of 580
REJ09B0324-0200
Figure 14.13 Registers TRBCR and TRBOCR
Timer RB Control Registe
r
Symbol Address Af ter Reset
TRBCR 0108h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
0 : Count stops
1 : During count(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RO
—
(b7-b3) —
TCSTF Timer RB count status flag(1)
TSTOP RW
b3 b2
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
b1 b0
0 : Count stops
1 : Count starts
b7 b6 b5 b4
Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable one-
shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has
been acknow ledged.
Timer RB count start bit(1)
Timer RB count forcible stop
bit(1, 2)
Ref er to 14.2.5 Notes on Timer RB.
TSTA RT RW
Timer RB One-Shot Control Register(2)
Symbol Address Af ter Reset
TRBOCR 0109h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b2
0 : One-shot stopped
1 : One-shot operating (Including w ait period)
b1 b0
TOSSP
TOSSTF
TOSST
b7 b6 b5 b4 b3
RW
RW
Timer RB one-shot start bit When this bit is set to 1, one-shot trigger
generated. When read, its content is 0.
Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot
pulses (including programmable w ait one-shot
pulses) stops. When read, its content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB one-shot status
flag(1)
When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0.
This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable w ait one-shot generation mode).
RO
—
(b7-b3) —
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 176 of 580
REJ09B0324-0200
Figure 14.14 Registers TRBIOC and TRBMR
Timer RB I/O Control Registe
r
Symbol Address Af ter Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
TOPL Timer RB output level select
bit
Timer RB output sw itch bit
b7 b6 b5 b4 b3 b2
INOSEG
b1 b0
INOSTG
TOCNT
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit
—
(b7-b4) —
Function varies depending on operating mode. RW
RW
RW
RW
One-shot trigger control bit
Timer RB Mode Registe
r
Symbol Address After Reset
TRBMR 010Bh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
(b6) —
Timer RB count source
select bits(1)
b5 b4
0 0 : f1
0 1 : f8
1 0 : Timer RA underflow
1 1 : f2
TCK1
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
TCK0 RW
Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR
register set to 0 (count stops).
RW
Timer RB count source
cutoff bit(1)
0 : Provides count source
1 : Cuts off count source RWTCKCUT
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB w rite control bit(2) 0 : Write to reload register and counter
1 : Write to reload register only
—
b7 b6 b5 b4
RW
TMOD1 RW
Timer RB operating mode
select bits(1)
b1 b0
0 0 : Timer mode
0 1 : Programmable w aveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable w ait one-shot generation mode
b3 b2
TWRC
b1 b0
—
(b2)
TMOD0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 177 of 580
REJ09B0324-0200
Figure 14.1 5 Registe rs T RBPRE, TRBSC, and TRBPR
Timer RB Secondary Register(3, 4)
Symbol Address After Reset
TRBSC 010Dh FFh
Mode Function Setting Range RW
NOTES:
1.
2.
3.
4. To w rite to the TRBSC register, perform the follow ing steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.
Programmable w ait one-shot
generation mode
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
00h to FFh WO(2)
The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
WO(2)
Counts timer RB prescaler underflow s(1) 00h to FFh
Programmable one-shot
generation mode
Disabled 00h to FFh —
Programmable w avef orm
generation mode
b7 b0
Timer mod e —
Disabled 00h to FFh
Timer RB Prescaler Register(1)
Symbol Address After Reset
TRBPRE 010Ch FFh
Mode Function Setting Range RW
NOTE:
1.
Counts an internal count source or timer RA
underflow s
00h to FFh RW
b0
Timer mode
b7
RW
Counts an internal count source or timer RA
underflow s
00h to FFh
When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Programmable w aveform
generation mode RW
Counts an internal count source or timer RA
underflow s
00h to FFh
Programmable one-shot
generation mode
Counts an internal count source or timer RA
underflow s
00h to FFh RW
Programmable w ait one-shot
generation mode
Timer RB Primary Register(2)
Symbol Address After Reset
TRBPR 010Eh FFh
Mode Function Setting Range RW
NOTES:
1.
2.
Programmable w ait one-shot
generation mode
Counts timer RB prescaler underflow s
(w ait period w idth is counted)
00h to FFh RW
b0b7
Timer mode RW
Counts timer RB prescaler underflow s 00h to FFh
When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Programmable w aveform
generation mode RW
Counts timer RB prescaler underflow s(1) 00h to FFh
Programmable one-shot
generation mode
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
00h to FFh RW
The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 178 of 580
REJ09B0324-0200
14.2.1 Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
14.8 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 14.16 shows TRBIOC Register in Timer Mode.
Figure 14.16 TRBIOC Register in Timer Mode
Table 14.8 Timer Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
Divide ratio 1/(n+1)(m+1)
n: setting value in TRBPRE register, m: setting value in TRBPR register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing
When timer RB underflows [timer RB interrupt].
TRBO pin function Programmable I/O port
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 14.2.1.1 T imer Write Control during Count Operation.)
Timer RB I/O Control Registe
r
Symbol Address Af ter Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit
—
(b7-b4) —
b3 b2
INOSEG
b1 b0
00
INOSTG
b7 b6 b5 b4
TOCNT RW
00
TOPL Timer RB output level select
bit
Timer RB output sw itch bit
RW
RW
One-shot trigger control bit
Set to 0 in timer mode. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 179 of 580
REJ09B0324-0200
14.2.1.1 Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload regist er.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 1 4.17 shows an Operating Example of Timer RB when Counter
Value is Rewritten during Count Operation.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 180 of 580
REJ09B0324-0200
Figure 14.17 Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
Count source
Reloads register of
timer RB prescaler
IR bit in TRBIC
register 0
Counter of
timer RB prescaler
Reloads register of
timer RB
Counter of timer RB
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
After writing, the reload register is
written with the first count source.
Reload with
the second
count source
Reload on
underflow
After writing, the reload register is
written on the first underflow.
Reload on the second
underflow
The IR bit remains unchanged until underflow
is generated by a new value.
When the TWRC bit is set to 0 (write to reload register and counter)
Count source
Reloads register of
timer RB prescaler
IR bit in TRBIC
register
Counter of
timer RB prescaler
Reloads register of
timer RB
Counter of timer RB
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
After writing, the reload register is
written with the first count source.
Reload on
underflow
After writing, the reload register is
written on the first underflow.
Reload on
underflow
Only the prescaler values are updated,
extending the duration until timer RB underflow.
When the TWRC bit is set to 1 (write to reload register only)
05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h
03h 00h02h 01h 25h
New value (25h)Previous value
New value (01h)Previous value
New value (01h)Previous value
05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h
New value (25h)Previous value
03h 24h02h 25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 181 of 580
REJ09B0324-0200
14.2.2 Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC a re counted alternately (refer to Table
14.9 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting
value in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 14.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows an
Operating Example of Timer RB in Programmable Waveform Generation Mode.
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after
writing to the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
•When count starts.
•When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following
primary period.
Table 14.9 Programmable Waveform Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement
• When the timer underflows, it reloads the contents of the primary reload and
secondary reload registers alternately before the count continues.
Width and period of
output waveform
Primary period: (n+1)(m+1)/fi
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing
In half a cycle of the count source, after timer RB underflows during the
secondary period (at the same time as the TRBO output change) [timer RB
interrupt]
TRBO pin function Programmable output port or pulse output
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE(1).
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is
stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(2)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level during primary and
secondary periods.
• TRBO pin output switch function
Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the
TRBIOC register.(3)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 182 of 580
REJ09B0324-0200
Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode
Figure 14.19 Operating Example of Timer RB in Programmable Waveform Generation Mode
Timer RB I/O Control Registe
r
Symbol Address Af ter Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
b3 b2
INOSEG
b1 b0
INOSTG
b7 b6 b5 b4
RW
TOCNT RW
00
TOPL
Timer RB output level select
bit
0 : Outputs “H” for primary period
Outputs “L” for secondary period
Outputs “L” w hen the timer is stopped
1 : Outputs “L” for primary period
Outputs “H” for secondary period
Outputs “H” w hen the timer is stopped
Timer RB output sw itch bit 0 : Outputs timer RB w avef orm
1 : Outputs value in P3_1 port latch
—
(b7-b4) —
RW
RW
One-shot trigger control bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit
Set to 0 in programmable w aveform generation
mode.
1
0
1
0
IR bit in TRBIC
register
1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBO pin output
TOPL bit in TRBIO
register
Set to 1 by program
Set to 0 when interrupt
request is acknowledged,
or set by program.
The above applies under the following conditions.
TSTART bit in TRBCR
register
1
0
01h 00h 02h
Timer RB secondary reloads Timer RB primary reloads
Set to 0 by program
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
02h 01h 00h 01h 00h
Primary period Primary periodSecondary period
Waveform
output starts Waveform output inverted Waveform output starts
Initial output is the same level
as during secondary period.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 183 of 580
REJ09B0324-0200
14.2.3 Programmable One-shot Generation Mode
In programmable o ne-shot generat ion mode, a on e-shot pulse is o utput from the TRBO pin by a p rogram or an
external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable One-Shot Generation
Mode Specifications). When a trigger is generated, the timer starts operating from the point only once for a
given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.
Figure 14.20 shows TRBIO C Register in Programmabl e One-Shot Generation Mode. Figure 14.21 sho ws an
Operating Example of Programmable One-Shot Generation Mode.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
Table 14.10 Programmable One-Shot Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse
output time
(n+1)(m+1)/fi
fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2)
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (count stops).
• When the TSTOP bit in the TRBCR register is set to 1 (count forcibly stops).
Interrupt request
generation timing
In half a cycle of the count source, after the timer underflows (at the same time as
the TRBO output ends) [timer RB interrupt]
TRBP pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload)(1).
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 184 of 580
REJ09B0324-0200
Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode
Timer RB I/O Control Register
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
0 : INT0
_
____
pin one-shot trigger disabled
1 : INT0
_
____
pin one-shot trigger enabled
NOTE:
1. Refer to 14.2.3.1 One-Shot Trigger Selection.
Nothing is assigned. If necessary, set to 0.
When read, its content is 0.
One-Shot Trigger Polarity
Select Bit(1)
—
(b7-b4) —
b3 b2
INOSEG
b1 b0
0
INOSTG
b7 b6 b5 b4
RW
TOCNT RW
TOPL
Timer RB Output Level
Select Bit
0 : Outputs one-shot pulse “H”
Outputs “L” w hen the timer is stopped
1 : Outputs one-shot pulse “L”
Outputs “H” w hen the timer is stopped
Timer RB Output Sw itch Bit Set to 0 in programmable one-shot generation
mode.
RW
RW
One-Shot Trigger Control
Bit(1)
0 : Falling edge trigger
1 : Rising edge trigger
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 185 of 580
REJ09B0324-0200
Figure 14.21 Operating Example of Programmable One-Shot Generation Mode
TOSSTF bit in TRBOCR
register
INT0 pin input
1
0
1
0
IR bit in TRBIC
register
1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBIO pin output
TOPL bit in
TRBIOC register
Set to 1 by program
Set to 1 by setting 1 to
TOSST bit in TRBOCR
register
Set to 0 when interrupt request is
acknowledged, or set by program.
The above applies under the following conditions.
TSTART bit in TRBCR
register
1
0
1
0
01h 00h 01h 00h 01h
Count starts Timer RB primary reloads Count starts Timer RB primary reloads
Set to 0 by program
Waveform output starts Waveform output ends Waveform output starts Waveform output ends
Set to 0 when
counting ends
Set to 1 by INT0 pin
input trigger
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 186 of 580
REJ09B0324-0200
14.2.3.1 One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
•1 is written to the TOSST bit in the TRBOCR register by a program.
•Trigger input from the INT0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot gen erati on
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs w hile the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making th e following settings:
•Set the PD4_5 bit in the PD4 register to 0 (input port).
•Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
•Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
•Set the INT0EN bit in the INTEN register to 0 (enabled).
•After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
•Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.
•If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
•If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 187 of 580
REJ09B0324-0200
14.2.4 Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 14.11 Programmable Wait One-Shot
Generation Mode Specifications). When a trigge r is generated from that point, t he timer outp uts a pulse on ly
once for a given length of time equal to the setting value in the TRBSC register after waiting for a gi ven leng th
of time equal to the setting value in the TRBPR register.
Figure 14.22 shows TRBIOC Register in Pro grammable Wait One-Shot G eneration Mode. Fig ure 14.2 3 shows
an Operating Example of Programmable Wait One-Shot Generation Mode.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 188 of 580
REJ09B0324-0200
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and
TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
Table 14.11 Programmable Wait One-Shot Generatio n Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the
contents of timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the
contents of timer RB primary before the count completes and the TOSSTF
bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
Wait time (n+1)(m+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, m Value set in the TRBPR register
(2)
One-shot pulse output time (n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the
next trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
Count stop conditions
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (count starts).
• When the TSTOP bit in the TRBCR register is set to 1 (count forcibly
stops).
Interrupt request
generation timing
In half a cycle of the count source after timer RB underflows during
secondary period (complete at the same time as waveform output from the
TRBO pin) [timer RB interrupt].
TRBO pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot
trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot
trigger enabled): external trigger (INT0 interrupt input)
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count
stops, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(1)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-
shot pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 189 of 580
REJ09B0324-0200
Figure 14.22 TRBIOC Register in Programmable Wait One- Shot Generation Mode
Timer RB I/O Control Register
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bit Name Function RW
0 : INT0
_
____
pin one-shot trigger disabled
1 : INT0
_
____ pin one-shot trigger enabled
NOTE:
1.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
One-shot trigger polarity
select bit(1)
—
(b7-b4) —
Ref er to 14.2.3.1 One-Shot Trigger Selection.
b3 b2
INOSEG
b1 b0
0
INOSTG
b7 b6 b5 b4
RW
TOCNT RW
TOPL
Timer RB output level select
bit
0: Outputs one-shot pulse “H”.
Outputs “L” w hen the timer stops or during
w ait.
1: Outputs one-shot pulse “L”.
Outputs “H” w hen the timer stops or during
w ait.
Timer RB output sw itch bit Set to 0 in programmable w ait one-shot generation
mode.
RW
RW
One-shot trigger control bit(1)
0 : Falling edge trigger
1 : Rising edge trigger
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 190 of 580
REJ09B0324-0200
Figure 14.23 Operating Example of Programmable Wait One-Shot Generation Mode
TOSSTF bit in TRBOCR
register
INT0 pin input
1
0
1
0
IR bit in TRBIC
register
1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBIO pin output
TOPL bit in
TRBIOC register
Set to 1 by program
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
Set to 0 when interrupt request is
acknowledged, or set by program.
The above applies under the following conditions.
TSTART bit in TRBCR
register
1
0
1
0
01h 00h 00h 01h
Count starts Timer RB secondary reloads Timer RB primary reloads
Set to 0 by program
Wait starts Waveform output starts Waveform output ends
Set to 0 when
counting ends
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
04h 03h 02h 01h
Wait
(primary period)
One-shot pulse
(secondary period)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 191 of 580
REJ09B0324-0200
14.2.5 Notes on Timer RB
•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer val ue may be updated duri ng the period when th ese two registers are bei ng
read.
•In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR
register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in
programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer
count value before the timer stops.
•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit.
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elap sed. If th e TOSSP bit is written to 1 d uring the peri od
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
14.2.5.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 192 of 580
REJ09B0324-0200
14.2.5.2 Programmable waveform generation mode
The following three workarounds should be performe d in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operat ion (TCSTF bit is set to 1 ), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 14.24 and 14.25.
The following shows the detailed workaround examp les.
•Workaround example (a):
As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interru pt routine. These
write operations must be completed by the beginni ng of period A.
Figure 14.24 Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
IR bit in
TRBIC register
Secondary period
(b)
Interrupt
sequence
Instruction in
interrupt routine
Interrupt request is
acknowledged
(a)
Interrupt request
is generated
Ensure sufficient time
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 193 of 580
REJ09B0324-0200
•Workaround example (b):
As shown in Figure 14.25 detect the start of the primary period by th e TRBO pin output level and w rite to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’ s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicat es the TRBO pin output value.
Figure 14.25 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
14.2.5.3 Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuousl y during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
•When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then the primary register immediately.
(ii) (iii)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 194 of 580
REJ09B0324-0200
14.2.5.4 Programmable wait one-shot generation mode
The following three workarounds should be performe d in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 195 of 580
REJ09B0324-0200
14.3 Timer RC
14.3.1 Overview
Timer RC is a 16-bit timer with four I/O pins.
Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.12 lists the Timer RC Operation Clock.
Table 14.13 lists the Timer RC I/O Pins, and Figure 14.26 shows a Timer RC Block Diagram.
Timer RC has three modes.
•Timer mode
- Input capture function The counter value is captured to a register , using an external signal as the trigger.
- Output compare function M atches between the counter and register values are detected. (Pin output state
changes when a match is detected.)
The following two modes use the output compare function.
•PWM mode Pulses of a given wid th are out put continuously.
•PWM2 mode A one-shot waveform or PWM waveform is output following the trigger after
the wait time has elapsed.
Input capture function, output compare function, and PWM mode settings may be specified independently for
each pin.
In PWM2 mode waveforms are output based on a combination of the counter or the regi ster.
Table 14.12 Timer RC Operation Clock
Condition Timer RC Operation Clock
Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in
TRCCR1 register are set to a value from 000b to 101b)
f1
Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set
to 110b)
fOCO40M
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 196 of 580
REJ09B0324-0200
Figure 14.26 Timer RC Block Diagram
Table 14.13 Timer RC I/O Pins
Pin Name I/O Function
TRCIOA(P5_1)
TRCIOB(P5_2)
TRCIOC(P5_3)
TRCIOD(P5_4)
I/O Function differs according to the mode. Refer to descriptions of
individual modes for details
TRCCLK(P5_0) Input External clock input
TRCTRG(P5_1) Input PWM2 mode external trigger input
TRCMR register
Data bus
TRCCR1 register
TRCIER register
TRCSR register
TRCIOR0 register
TRC register
TRCGRA register
TRCGRB register
TRCGRC register
TRCGRD register
TRCCR2 register
TRCDF register
TRCOER register
Timer RC control circuit
INT0
TRCCLK
Count source
select circuit
f1, f2, f4, f8, f32,
fOCO40M
Timer RC interrupt
request
TRCIOR1 register TRCIOB
TRCIOC
TRCIOD
TRCIOA/TRCTRG
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 197 of 580
REJ09B0324-0200
14.3.2 Registers Associated with Timer RC
Table 14.14 lists the Registers Associated with Timer RC. Figures 14.27 to 14.37 show details of the registers
associated with timer RC.
− : Invalid
Table 14.14 Registers Associated with Timer RC
Address Symbol
Mode
Related Information
Timer
PWM PWM2
Input
Capture
Function
Output
Compare
Function
0008h MSTCR Valid Valid Valid Valid Module operation enable register
Figure 14.27 MSTCR Register
0120h TRCMR Valid Valid Valid Valid Timer RC mode register
Figure 14.28 TRCMR Register
0121h TRCCR1 Valid Valid Valid Valid Timer RC control register 1
Figure 14.29 TRCCR1 Register
Figure 14.50 TRCCR1 Register for Output
Compare Function
Figure 14.53 TRCCR1 Register in PWM Mode
Figure 14.57 TRCCR1 Register in PWM2 Mode
0122h TRCIER Valid Valid Valid Valid Timer RC interrupt enable register
Figure 14.30 TRCIER Register
0123h TRCSR Valid Valid Valid Valid Timer RC status register
Figure 14.31 TRCSR Register
0124h TRCIOR0 Valid Valid −−Timer RC I/O control register 0, timer RC I/O
control register 1
Figure 14.37 Registers TRCIOR0 and TRCIOR1
Figure 14.44 TRCIOR0 Register for Input
Capture Function
Figure 14.45 TRCIOR1 Register for Input
Capture Function
Figure 14.48 TRCIOR0 Register for Output
Compare Function
Figure 14.49 TRCIOR1 Register for Output
Compare Function
0125h TRCIOR1
0126h
0127h
TRC Valid Valid Valid Valid Timer RC counter
Figure 14.32 TRC Register
0128h
0129h
TRCGRA Valid Valid Valid Valid Timer RC general registers A, B, C, and D
Figure 14.33 Registers TRCGRA, TRCGRB,
TRCGRC, and TRCGRD
012Ah
012Bh
TRCGRB
012Ch
012Dh
TRCGRC
012Eh
012Fh
TRCGRD
0130h TRCCR2 −−−Valid Timer RC control register 2
Figure 14.34 TRCCR2 Register
0131h TRCDF Valid −−Valid Timer RC digital filter function select register
Figure 14.35 TRCDF Register
0132h TRCOER −Valid Valid Valid Timer RC output master enable register
Figure 14.36 TRCOER Register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 198 of 580
REJ09B0324-0200
Figure 14.2 7 MSTCR Regist e r
Figure 14.28 TRCMR Register
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
Timer RC Mode Register(1)
Symbol Address Af ter Reset
TRCMR 0120h 01001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
RW
TSTA RT RW
TRC count start bit 0 : Count stops
1 : Count starts
PWM mode of TRCIOB select bit(2) 0 : Timer mode
1 : PWM mode
TRCGRC register function select
bit(3)
PWM mode of TRCIOC select bit(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
(b6)
BFC
b7 b6 b5 b4
RW
RW
PWMB
0 : General register
1 : Buffer register of TRCGRA register
TRCGRD register function select
bit
0 : General register
1 : Buffer register of TRCGRB register
0 : Timer mode
1 : PWM mode RW
PWMD PWM mode of TRCIOD select bit(2)
b3 b2
BFD
b1 b0
PWMC
These bits are enabled w hen the PWM2 bit is set to 1 (timer mode or PWM mode).
3. Set the BFC bit to 0 (general register) in PWM2 mode.
0 : Timer mode
1 : PWM mode RW
PWM2 PWM2 mode select bit 0 : PWM 2 mode
1 : Timer mode or PWM mode RW
For notes on PWM2 mode, ref er to 14.3.9.5 TRCMR Register in PWM2 Mode.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 199 of 580
REJ09B0324-0200
Figure 14.29 TRCCR1 Register
Timer RC Control Register 1
Symbol Address After Reset
TRCCR1 0121h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
b3 b2
TOD
b1 b0
TOA
b7 b6 b5 b4
RW
TOB RW
TRCIOA output level select bit(1)
TRCIOB output level select bit(1)
Function varies according to the
operating mode (function).(2)
Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
TOC RW
RW
RW
RW
TRCIOD output level select bit(1)
CCLR RW
TRCIOC output level select bit(1)
The TRC counter performs free-running operation for the input capture f unction of the timer mode independent of the
CCLR bit setting.
Count source select bits(1) b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA r egis ter
Bits CCLR, TOA, TOB, TOC and TOD are disabled for the input capture function of the timer mode.
TCK0
TCK1 RW
TRC counter clear select bit(2, 3)
TCK2
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 200 of 580
REJ09B0324-0200
Figure 14.3 0 TRCIER Regist er
Timer RC Interrupt Enable Register
Symbol Address After Reset
TRCIER 0122h 01110000b
Bit Symbol Bit Name Function RW
b3 b2
IMIED
b1 b0b7 b6 b5 b4
RW
IMIEB RW
Input capture / compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture / compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
IMIEC RW
Overf low interrupt enable bit 0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
—
(b6-b4) —
RWOVIE
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
Input capture / compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Input capture / compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 201 of 580
REJ09B0324-0200
Figure 14.31 TRCSR Register
Timer RC Status Register
Symbol Address After Reset
TRCSR 0123h 01110000b
Bit Symbol Bit Name Function RW
NOTE:
1.
—
(b6-b4) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWOVF
Overflow flag [Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
Refer to the table below .
Input capture / compare match flag
C
IMFC RW
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
Refer to the table below .
RW
Input capture / compare match flag
D
RW
IMFB RW
Input capture / compare match flag
A
Input capture / compare match flag
B
IMFA
b7 b6 b5 b4
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
b3 b2
IMFD
b1 b0
Input capture Function Output Compare
Function
TRCIOA pin input edge(1)
TRCIOB pin input edge(1)
TRCIOC pin input edge(1)
TRCIOD pin input edge(1)
NOTES:
1.
2.
Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).
Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA
and TRCGRB).
Bit Symbol
IMFA
IMFB
IMFC
IMFD
OVF
When the values of the registers TRC and TRCGRC
matc h .(2)
When the values of the registers TRC and TRCGRD
matc h .(2)
PWM2 Mode
When the TRC register overflow s.
When the values of the registers TRC and TRCGRA match.
When the values of the registers TRC and TRCGRB match.
Timer Mode
PWM Mo de
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 202 of 580
REJ09B0324-0200
Figure 14.32 TRC Register
Figure 14.33 Registe rs TRCG RA, TRCGRB, TRCGRC, and TRCGRD
Timer RC Counter(1)
Symbol Address After Reset
TRC 0127h-0126h 0000h
Setting Range RW
NOTE:
1.
Function
Count a count source. Count operation is incremented.
When an overf low occurs, the OVF bit in the TRCSR register is set to 1.
0000h to FFFFh
RW
Access the TRC register in 16-bit units. Do not access it in 8-bit units.
b0b7
(b8)
b0
(b15)
b7
Timer RC General Register A, B, C and D(1)
Symbol Address After Reset
TRCGRA
TRCGRB
TRCGRC
TRCGRD
0129h-0128h
012Bh-012Ah
012Dh-012Ch
012Fh-012Eh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
(b8)
b0
(b15)
b7 b0b7
RW
Function
Function varies according to the operating mode.
Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 203 of 580
REJ09B0324-0200
Figure 14.34 TRCCR2 Register
Timer RC Control Register 2
Symbol Address After Reset
TRCCR2 0130h 00011111b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
RW
RW
TRCTRG input edge select bits(3) b7 b6
0 0 : Disable the trigger input from the
TRCTRG pin
0 1 : Rising edge selected
1 0 : Falling edge selected
1 1 : Both edges selected
b7 b6 b5 b4 b3 b2
TCEG0
b1 b0
CSEL
In timer mode and PWM mode these bits are disabled.
In timer mode and PWM mode this bit is disabled (the count operation continues independent of the CSEL bit setting).
TCEG1
For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode.
—
(b4-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
TRC count operation select
bit(1, 2)
0 : Count continues at compare match w ith
the TRCGRA register
1 : Count stops at compare match w ith
the TRCGRA register
RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 204 of 580
REJ09B0324-0200
Figure 14.35 TRCDF Register
Timer RC Digital Filter Function Select Register
Symbol Address After Reset
TRCDF 0131h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
TRCIOC pin digital filter function
select bit(1)
DFCK1 RW
DFTRG TRCTRG pin digital filter f unction
select bit(2) RW
RW
DFB RW
DFA TRCIOA pin digital filter function
select bit(1)
TRCIOB pin digital filter function
select bit(1)
0 : Function is not used
1 : Function is used
RW
RW
TRCIOD pin digital filter function
select bit(1)
b7 b6 b5 b4 b3 b2
DFD
b1 b0
DFC
These bits are enabled for the input capture function.
These bits are enabled w hen in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or
11b (TRCTRG trigger input enabled).
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock select bits for digital filter
function(1, 2)
—
(b5)
DFCK0 RW
—
b7 b6
0 0 : f32
0 1 : f8
1 0 : f1
1 1 : Count source (clock selected by
bits TCK2 to TCK0 in the
TRCCR1 register)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 205 of 580
REJ09B0324-0200
Figure 14.36 TRCOER Register
Timer RC Output Master Enable Register
Symbol Address After Reset
TRCOER 0132h 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____ of pulse output forced 0 : Pulse output forced cutoff input disabled
cutof f signal input enabled 1 : Pulse output forced cutoff input enabled
bit (Bits EA, EB, EC, and ED are set to 1
(disable output) w hen “L” is applied to the
INT0
_
____ pin)
NOTE:
1.
—
(b6-b4)
These bits are disabled for input pins set to the input capture function.
RW
—
TRCIOD output disable bit(1) 0 : Enable output
1 : Disable output (The TRCIOD pin is
used as a programmable I/O port.)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
PTO
TRCIOC output disable bit(1) 0 : Enable output
1 : Disable output (The TRCIOC pin is
used as a programmable I/O port.)
EC RW
RW
EB RW
TRCIOA output disable bit(1) 0 : Enable output
1 : Disable output (The TRCIOA pin is
used as a programmable I/O port.)
TRCIOB output disable bit(1) 0 : Enable output
1 : Disable output (The TRCIOB pin is
used as a programmable I/O port.)
b7 b6 b5 b4 b3 b2
ED
b1 b0
EA
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 206 of 580
REJ09B0324-0200
Figure 14.3 7 Registe rs T RCIO R0 an d TR CIO R 1
Timer RC I/O Control Register 0(1)
Symbol Address After Reset
TRCIOR0 0124h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOB0
IOB1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRB mode select bit(3)
The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
—
(b7)
b3 b2
IOA 3
b1 b0
IOA 2
b7 b6 b5 b4
RW
RW
RW
IOA 1
IOA0 TRCGRA control bits Function varies according to the operating mode
(function).
TRCGRB control bits Function varies according to the operating mode
(function).
The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
IOB2 RW
TRCGRA mode select bit(2) 0 : Output compare function
1 : Input capture function RW
TRCGRA input capture input
sw itch bit(4)
0 : fOCO128 signal
1 : TRCIOA pin input RW
0 : Output compare f unction
1 : Input capture function
Timer RC I/O Control Register 1(1)
Symbol Address After Reset
TRCIOR1 0125h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
RWFunction varies according to the operating mode
(function).
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOD0
IOD1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRD mode select bit(3) 0 : Output compare function
1 : Input capture function
b3 b2
—
(b3)
b1 b0
IOC2
b7 b6 b5 b4
RW
RW
IOC1
IOC0 TRCGRC control bits Function varies according to the operating mode
(function).
The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRCGRC mode select bit(2) 0 : Output compare function
1 : Input capture function RW
—
—
(b7)
IOD2 RW
TRCGRD control bits
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 207 of 580
REJ09B0324-0200
14.3.3 Common Items for Multiple Modes
14.3.3.1 Count Source
The method of selecting the count source is common to all modes.
Table 14.15 lists the Count Source Selection, and Figure 14 .38 shows a Count Source Block Diagram.
Figure 14.38 Count Source Block Diagram
The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC
operation clock (see Table 14.12 Timer RC Operation Clock).
To select fOCO40M as the count so urce, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip
oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M).
Table 14.15 C ount Source Selection
Count Source Selection Method
f1, f2, f4, f8, f32 Count source selected using bits TCK2 to TCK0 in TRCCR1 register
fOCO40M FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) and bits
TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)
External signal input
to TRCCLK pin
Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge
of external clock) and PD5_0 bit in PD5 register is set to 0 (input mode)
TCK2 to TCK0
TRC register
TCK2 to TCK0: Bits in TRCCR1 register
f1
f2
f4
f8
f32
= 001b
= 010b
= 011b
= 000b
= 110b
= 100b
Count source
TRCCLK = 101b
fOCO40M
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 208 of 580
REJ09B0324-0200
14.3.3.2 Buffer Operation
Bits BFC and BFD in the TRCM R register are used to select the TRCGRC or TRC GRD register as the buffer
register for the TRCGRA or TRCGRB register.
•Buffer register for TRCGRA register: TRCGRC register
•Buffer register for TRCGRB register: TRCGRD register
Buffer operation differs depending on the mode .
Table 14.16 lists the Buffer Operation in Each Mode, Figure 14.39 shows the Buffer Operation for Input
Capture Function, and Figure 14 .40 shows the Buffer Operation for Output Compare Functi on.
Figure 14.39 Buffer Operation for Input Capture Function
Table 14.16 Buffer Operation in Each Mode
Function, Mode Transfer Timing Transfer Destination Register
Input capture function Input capture signal input Contents of TRCGRA (TRCGRB)
register are transferred to buffer
register
Output compare function Compare match between TRC
register and TRCGRA (TRCGRB)
register
Contents of buffer register are
transferred to TRCGRA (TRCGRB)
register
PWM mode
PWM2 mode • Compare match between TRC
register and TRCGRA register
• TRCTRG pin trigger input
Contents of buffer register (TRCGRD)
are transferred to TRCGRB register
m
Transfer
n
n-1 n+1
TRCIOA input
TRC register
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).
m
Transfer
n
TRCGRC
register
TRCGRA
register TRC
TRCIOA input
(input capture signal)
TRCGRA register
TRCGRC register
(buffer)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 209 of 580
REJ09B0324-0200
Figure 14.40 Buffer Operation for Output Compare Function
Make the following settings in timer mod e .
•To use the TRCGRC register as the buffer register for the TRCGRA register:
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
•To use the TRCGRD register as the buffer register for the TRCGRB register:
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare
match with the TRC register occurs.
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin
or TRCIOD pin.
mnTRCGRA register
m-1 m+1
TRC register
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).
n
Transfer
TRCGRC register
(buffer)
m
TRCIOA output
TRCGRC
register
TRCGRA
register Comparator TRC
Compare match signal
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 210 of 580
REJ09B0324-0200
14.3.3.3 Digit a l Filter
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register .
Figure 14.41 shows a Block Diagram of Dig ital Filter.
Figure 14.41 Block Diagram of Digital Filter
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
Match detect
circuit
Edge detect
circuit
DFj (or DFTRG)
Sampling clock
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
(or TCEG1 to TCEG0)
DFCK1 to DFCK0
TRCIOj input signal
(or TRCTRG input
signal)
Clock cycle selected by
TCK2 to TCK0
(or DFCK1 to DFCK0)
Sampling clock
TRCIOj input signal
(or TRCTRG input signal)
Input signal after passing
through digital filter
If fewer than three matches occur,
the matches are treated as noise
and no transmission is performed.
Maximum signal transmission
delay is five sampling clock
pulses.
Three matches occur and a
signal change is confirmed.
f32
f8
f1
j = A, B, C, or D
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG1 to TCEG0: Bits in TRCCR2 register
C
DQ
Latch
C
DQ
Latch
Timer RC operation clock
f1 or fOCO40M
Count source
= 00b
= 01b
= 10b
= 11b
TCK2 to TCK0
1
0
= 001b
= 010b
= 011b
= 000b
= 100b
= 101b
f1
f32
TRCCLK
f8
f4
f2
fOCO40M = 110b
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 211 of 580
REJ09B0324-0200
14.3.3.4 Forced Cutoff of Pulse Output
When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from
the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a
programmable I/O port by means of input to the INT0 pin.
A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be
set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output
enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1
(timer RC output disabled, TRCIOj outp ut pin functions as the programmable I/O port). When one or two
cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 14.12 Timer RC
Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.
Make the following settings to use this function.
•Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H”
output). (Refer to 7. Programmable I/O Ports.)
•Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
•Set the PD4_5 bit in the PD4 register to 0 (input mode).
•Select the INT0 digital filter by means of bi ts INT0F1 to INT0F0 in the INTF register.
•Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and
a change in the INT0 pin input (refer to 12.6 Notes on Interrupts).
For details on interrupts, refer to 12. Interrupts.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 212 of 580
REJ09B0324-0200
Figure 14.42 Forced Cutoff of Pulse Output
INT0 input TRCIOA
PTO bit
D
S
Q
EA bit
EA bit
write value
TRCIOB
D
S
Q
EB bit
EB bit
write value
TRCIOC
D
S
Q
EC bit
EC bit
write value
TRCIOD
D
S
Q
ED bit
ED bit
write value
EA, EB, EC, ED, PTO: Bits in TRCOER register
Timer RC
output data
Port P1_1
output data
Port P1_1
input data
Timer RC
output data
Port P1_2
output data
Port P1_2
input data
Timer RC
output data
Port P3_4
output data
Port P3_4
input data
Timer RC
output data
Port P3_5
output data
Port P3_5
input data
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 213 of 580
REJ09B0324-0200
14.3.4 Timer Mode (Input Capture Function)
This functi on measur es the wi dt h or peri od of an exter nal signal. An external signal input to the TRCIOj (j = A,
B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj
register (input capture). The input capture function, or any other mode or function, can be selected for each
individual pin.
The TRCGRA register can also select fOC O128 signal as input-capture trigger input.
Table 14.17 lists the Specifications of Input Capture Function, Figure 14.43 sh ows a Block Diagram of Input
Capture Function, Figures 14.44 and 14.4 5 show registers associated with the input capture fu nction, Table
14.18 lists the Functions of TRCGRj Regist er when Using Inpu t Capture Functio n, and Figure 14.46 shows an
Operating Example of Input Capture Function.
j = A, B, C, or D
Table 14.17 Specifications of Input Capture Function
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Count operation Increment
Count period 1/fk × 65,536 fk: Count source frequency
Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register.
Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register.
The TRC register retains a value before count stops.
Interrupt request generation
timing
• Input capture (valid edge of TRCIOj input or fOCO128 signal edge)
• The TRC register overflows.
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
Programmable I/O port or input capture input (selectable individually by
pin)
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read by reading TRC register.
Write to timer The TRC register can be written to.
Select functions • Input capture input pin select
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input capture input valid edge selected
Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 1 4 .3.3.2 Buffer Opera ti on .)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRCGRA register.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 214 of 580
REJ09B0324-0200
Figure 14.43 Block Diagram of Input Capture Function
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.
TRCGRA
register TRC register
Input capture signal(3)
TRCGRC
register
TRCGRB
register
TRCGRD
register
TRCIOB
(Note 1)
(Note 2)
TRCIOC
TRCIOD
Input capture signal
Input capture signal
Input capture signal
Divided
by 128 IOA3 = 0
IOA3 = 1
fOCO fOCO128
TRCIOA
IOA3: Bit in TRCIOR0 register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 215 of 580
REJ09B0324-0200
Figure 14.44 TRCIOR0 Register for Input Capture Function
Timer RC I/O Control Register 0
Symbol Address After Reset
TRCIOR0 0124h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
TRCGRB control bits b5 b4
0 0 : Input capture to the TRCGRB register
at the rising edge
0 1 : Input capture to the TRCGRB register
at the falling edge
1 0 : Input capture to the TRCGRB register
at both edges
1 1 : Do not set.
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOB0
IOB1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRB mode select bit(2) Set to 1 (input capture) in the input capture
function.
RW
b3 b2
IOA 3
b1 b0
1
IOA 2
1
b7 b6 b5 b4
RW
RW
IOA 1
IOA 0
TRCGRA control bits b1 b0
0 0 : Input capture to the TRCGRA register
at the rising edge
0 1 : Input capture to the TRCGRA register
at the falling edge
1 0 : Input capture to the TRCGRA register
at both edges
1 1 : Do not set.
The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
TRCGRA mode select bit(1) Set to 1 (input capture) in the input capture
function. RW
TRCGRA input capture input
sw itch bit(3)
0 : fOCO128 signal
1 : TRCIOA pin input RW
—
(b7)
IOB2 RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 216 of 580
REJ09B0324-0200
Figure 14.45 TRCIOR1 Register for Input Capture Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Table 14.18 Functions of TRCGRj Register when Using Input Capture Function
Register Setting Register Function Input Capture
Input Pin
TRCGRA −General register. Can be used to read the TRC register value
at input capture.
TRCIOA
TRCGRB TRCIOB
TRCGRC BFC = 0 General register. Can be used to read the TRC register value
at input capture.
TRCIOC
TRCGRD BFD = 0 TRCIOD
TRCGRC BFC = 1 Buffer registers. Can be used to hold transferred value from
the general register. (Refer to 14.3.3.2 Buffer Operation.)
TRCIOA
TRCGRD BFD = 1 TRCIOB
Timer RC I/O Control Register 1
Symbol Address After Reset
TRCIOR1 0125h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
IOD0
IOD1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRD mode select bit(2) Set to 1 (input capture) in the input capture
function.
RW
—
(b7)
IOD2 RW
TRCGRD control bits b5 b4
0 0 : Input capture to the TRCGRD register
at the rising edge
0 1 : Input capture to the TRCGRD register
at the falling edge
1 0 : Input capture to the TRCGRD register
at both edges
1 1 : Do not set.
b3 b2
—
(b3)
b1 b0
1
IOC2
1
b7 b6 b5 b4
RW
RW
IOC1
IOC0
TRCGRC control bits b1 b0
0 0 : Input capture to the TRCGRC register
at the rising edge
0 1 : Input capture to the TRCGRC register
at the falling edge
1 0 : Input capture to the TRCGRC register
at both edges
1 1 : Do not set.
TRCGRC mode select bit(1) Set to 1 (input capture) in the input capture
function. RW
—
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 217 of 580
REJ09B0324-0200
Figure 14.46 Operating Example of Input Capture Function
TRC register
count value
FFFFh
0006h
TSTART bit in
TRCMR register
65536
TRCGRA register
0000h
1
0
TRCIOA input
TRCGRC register
IMFA bit in
TRCSR register
OVF bit in
TRCSR register
Set to 0 by a program
Transfer
0003h0006h
0006h
Transfer
1
0
1
0
TRCCLK input
count source
The above applies under the following conditions:
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
0003h
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 218 of 580
REJ09B0324-0200
14.3.5 Timer Mode (Output Compare Function)
This function detects when the contents of the TRC regist er (counter) and t he TRCGRj register (j = A, B, C, or
D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The
output compare function, or other mode or function, can be selected for each individual pin.
Table 14.19 lists the Specifications of Output Compare Function , Figure 14.47 shows a Block Diagram of
Output Compare Fu nction, Figures 14.4 8 to 14.50 sho w registers associated with the outp ut compare function ,
Table 14.2 0 lists the Functions of TRCGRj Re gister when Using Outp ut Compar e Function, and Figure 14 .51
shows an Operating Example of Output Compare Function.
j = A, B, C, or D
Table 14.19 Specifications of Output Compare Function
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Count operation Increment
Count period • The CCLR bit in the TRCCR1 register is set to 0 (free running
operation): 1/fk × 65,536
fk: Count source frequency
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to
0000h at TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
Waveform output timing Compare match
Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register.
Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops,
the TRC register retains a value before count stops.
Interrupt request generation
timing
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
Programmable I/O port or output compare output (selectable individually
by pin)
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer The count value can be read by reading the TRC register.
Write to timer The TRC register can be written to.
Select functions • Output compare output pin selected
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Compare match output level select
“L” output, “H” output, or toggle output
• Initial output level select
Sets output level for period from count start to compare match
• Timing for clearing the TRC register to 0000h
Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 1 4 .3.3.2 Buffer Opera ti on .)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff
of Pulse Output.)
• Can be used as an internal timer by disabling timer RC output
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 219 of 580
REJ09B0324-0200
Figure 14.47 Block Diagram of Output Compare Function
TRCIOA Output
control
Comparator TRCGRA
TRC
TRCIOC
TRCGRC
TRCIOB
TRCGRB
TRCIOD
TRCGRD
Output
control
Output
control
Output
control
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Comparator
Comparator
Comparator
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 220 of 580
REJ09B0324-0200
Figure 14.48 TRCIOR0 Register for Output Compare Function
Timer RC I/O Control Register 0
Symbol Address After Reset
TRCIOR0 0124h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
TRCGRA mode select bit(1) Set to 0 (output compare) in the output compare
function. RW
TRCGRA input capture input
sw itch bit
Set to 1. RW
RW
RW
IOA 1
IOA 0
TRCGRA control bits b1 b0
0 0 : Disable pin output by compare
match (TRCIOA pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRA register
1 0 : “H” output by compare match in
the TRCGRA register
1 1 : Toggle output by compare match
in the TRCGRA register
b7 b6 b5 b4
0
b3 b2
IOA 3
b1 b0
10
IOA 2
—
(b7)
IOB2 RW
TRCGRB control bits b5 b4
0 0 : Disable pin output by compare
match (TRCIOB pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRB register
1 0 : “H” output by compare match in
the TRCGRB register
1 1 : Toggle output by compare match
in the TRCGRB register
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOB0
IOB1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRB mode select bit(2) Set to 0 (output compare) in the output compare
function.
RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 221 of 580
REJ09B0324-0200
Figure 14.49 TRCIOR1 Register for Output Compare Function
Timer RC I/O Control Register 1
Symbol Address After Reset
TRCIOR1 0125h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOD0
IOD1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRD mode select bit(2) Set to 0 (output compare) in the output compare
function.
RW
—
(b7)
IOD2 RW
TRCGRD control bits b5 b4
0 0 : Disable pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRD register
1 0 : “H” output by compare match in
the TRCGRD register
1 1 : Toggle output by compare match
in the TRCGRD register
b3 b2
—
(b3)
b1 b0
0
IOC2
0
b7 b6 b5 b4
RW
RW
IOC1
IOC0
TRCGRC control bits b1 b0
0 0 : Disable pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRC register
1 0 : “H” output by compare match in
the TRCGRC register
1 1 : Toggle output by compare match
in the TRCGRC register
TRCGRC mode select bit(1) Set to 0 (output compare) in the output compare
function. RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 222 of 580
REJ09B0324-0200
Figure 14.50 TRCCR1 Register for Output Compare Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Table 14.20 Functions of TRCGRj Register when Using Output Compare Function
Register Setting Register Function Output Compare
Output Pin
TRCGRA −General register. Write a compare value to one of these
registers.
TRCIOA
TRCGRB TRCIOB
TRCGRC BFC = 0 General register. Write a compare value to one of these
registers.
TRCIOC
TRCGRD BFD = 0 TRCIOD
TRCGRC BFC = 1 Buffer register. Write the next compare value to one of
these registers. (Refer to 14.3.3.2 Buffer Operation.)
TRCIOA
TRCGRD BFD = 1 TRCIOB
Timer RC Control Register 1
Symbol Address After Reset
TRCCR1 0121h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2. If the pin function is set for w avef orm output (refer to Tables 7.43 to 7.50), the initial output level is output w hen the
TRCCR1 register is set.
b3 b2
TOD
b1 b0b7 b6 b5 b4
TRCIOC output level select bit(1, 2)
b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
TCK0
TCK1
RW
TOB RW
TRCIOA output level select bit(1, 2)
TRCIOB output level select bit(1, 2)
TOA
Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
TOC RW
RW
RW
RW
TRCIOD output level select bit(1, 2)
CCLR
0 : Initial output “L”
1 : Initial output “H”
Count source select bits(1)
RW
TRC counter clear select bit
TCK2
RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 223 of 580
REJ09B0324-0200
Figure 14.51 Operating Example of Output Compare Function
Output level held
m
n
p
TRC register value
Count source
m+1 m+1
TSTART bit in
TRCMR register
1
0
TRCIOA output
IMFA bit in
TRCSR register
1
0
n+1
TRCIOB output “H” output at
compare match
Set to 0 by a program
IMFB bit in
TRCSR register
1
0
Initial output “L”
Initial output “L”
TRCIOC output
Set to 0 by a program
IMFC bit in
TRCSR register
1
0
Initial output “H”
“L” output at compare match
P+1
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
Count
restarts
Count
stops
Output level held
Set to 0 by a program
• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until
compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).
Output level held
Output inverted at
compare match
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 224 of 580
REJ09B0324-0200
14.3.6 PWM Mode
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA
register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer
mode.)
Table 14.21 lists the Specifications of PWM Mode, Figure 14.52 shows a Block Diagram of PWM Mode,
Figure 14.53 shows the register associated with the PWM mode, Table 14.22 lists the Functions of TRCGRj
Register in PWM Mode, and Figures 14.54 and 14.55 show Operating Examples of PWM Mode.
j = A, B, C, or D
Table 14.21 Specifications of PWM Mode
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Count operation Increment
PWM waveform PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive width: 1/fk × (n + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register.
Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
Interrupt request generation
timing
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
TRCIOA pin function Programmable I/O port
TRCIOB, TRCIOC, and
TRCIOD pin functions
Programmable I/O port or PWM output (selectable individually by pin)
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer The count value can be read by reading the TRC register.
Write to timer The TRC register can be written to.
Select functions • One to three pins selectable as PWM output pins per channel
One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable by individual pin
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced
Cutoff of Pulse Output.)
m+1
n+1 m-n (“L” is active level)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 225 of 580
REJ09B0324-0200
Figure 14.52 Block Diagram of PWM Mode
TRCIOB
Output
control
Comparator TRCGRA
TRC
Compare match signal
TRCGRB
TRCIOC
TRCGRC
TRCGRD
TRCIOD
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
(Note 1)
(Note 2)
Compare match signal
Compare match signal
Compare match signal
Comparator
Comparator
Comparator
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 226 of 580
REJ09B0324-0200
Figure 14.53 TRCCR1 Register in PWM Mode
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.
Table 14.22 Functions of TRCGRj Register in PWM Mode
Register Setting Register Function PWM Output Pin
TRCGRA −General register. Set the PWM period. −
TRCGRB −General register. Set the PWM output change point. TRCIOB
TRCGRC BFC = 0 General register. Set the PWM output change point. TRCIOC
TRCGRD BFD = 0 TRCIOD
TRCGRC BFC = 1 Buffer register. Set the next PWM period. (Refer to 14.3.3.2
Buffer Operation.)
−
TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to
14.3.3.2 Buffer Operation.)
TRCIOB
Timer RC Control Register 1
Symbol Address After Reset
TRCCR1 0121h 00h
Bit Symbol Bit Name Function RW
j
= B, C or
D
NOTES:
1.
2. If the pin function is set for w aveform output (ref er to Tables 7.4 5 to 7.50), the initial output level is output w hen the
TRCCR1 register is set.
b3 b2
TOD
b1 b0b7 b6 b5 b4
TRCIOC output level s elect bit(1, 2)
Disabled in PWM mode
TOA RW
TOB RW
TRCIOA output level select bit(1)
TRCIOB output level selec t bit(1, 2)
Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
TOC RW
RW
RW
RW
TRCIOD output level s elect bit(1, 2)
CCLR
0 : Active level “H”
(Initial output “L”
“H” output by compare match in
the TRCGRj register
“L” output by compare match in
the TRCGRA register
1 : Active level “L”
(Initial output “H”
“L” output by compare match in
the TRCGRj register
“H” output by compare match in
the TRCGRA register
RW
RW
TRC counter clear select bit
TCK2
Count source select bits(1) b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (f ree-running operation)
1 : Clear by compare match in the
TRCGRA regis ter
TCK0
TCK1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 227 of 580
REJ09B0324-0200
Figure 14.54 Operating Example of PWM Mode
m
n
p
TRC register value
Count source
m+1
n+1
TRCIOC output
q
m-n
p+1 m-p
m-qq+1
TRCIOD output
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
q: TRCGRD register setting value
Inactive level is “L”Active level is “H”
Active level is “L”
“L” initial output until
compare match
“H” initial output until
compare match
Set to 0 by a program
Set to 0 by a program Set to 0 by a program
TRCIOB output
IMFA bit in
TRCSR register
1
0
IMFB bit in
TRCSR register
1
0
IMFC bit in
TRCSR register
1
0
IMFD bit in
TRCSR register
1
0
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”).
Set to 0 by a program
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 228 of 580
REJ09B0324-0200
Figure 14.55 Operating Example of PWM Mode (Duty 0% and Duty 100%)
Rewritten by
a program
m
p
q
TRC register value
n
m: TRCGRA register setting value
Set to 0 by a program
Rewritten by a program
0000h
q
Duty 0%
TRCGRB register
IMFA bit in
TRCSR register
1
0
IMFB bit in
TRCSR register
1
0
TSTART bit in
TRCMR register
TRCIOB output
p (p>m)n
1
0
m
p
TRC register value
n
0000h
TRCGRB register
IMFA bit in
TRCSR register
1
0
IMFB bit in
TRCSR register
1
0
TSTART bit in
TRCMR register
TRCIOB output
pn
1
0
m
The above applies under the following conditions:
• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).
• The TOB bit in the TRCCR1 register is set to 1 (active level is “L”).
TRCIOB output does not switch to “L” because
no compare match with the TRCGRB register
has occurred
If compare matches occur simultaneously with registers TRCGRA and
TRCGRB, the compare match with the TRCGRB register has priority.
TRCIOB output switches to “L”. (In other words, no change).
TRCIOB output switches to “L” at compare match with the
TRCGRB register. (In other words, no change).
Set to 0 by a program
Set to 0 by a program
Duty 100%
Set to 0 by a program
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 229 of 580
REJ09B0324-0200
14.3.7 PWM2 Mode
This mode outputs a sin gle PWM waveform. After a given wait duration has elapsed followi ng the trigger, the
pin output switches to active level. Then, after a given duration, the output switches back to inactive level.
Furthermore, the counter stops at the same time the output returns to inactive level, maki ng it possible to use
PWM2 mode to output a programmable wait one-shot waveform.
Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with
it.
Figure 14.56 shows a Block Diagram of PWM2 Mode, Table 14.23 lists the Specifications of PWM2 Mode,
Figure 14.57 shows the register associated with PWM2 mode, Tabl e 14.24 lists the Functions of TRCGRj
Register in PWM2 Mode, and Figures 14.58 to 14.60 show Operating Examples of PWM2 Mode.
Figure 14.56 Block Diagram of PWM2 Mode
TRCTRG Input
control
TRCIOB Output
control
Comparator TRCGRATRC
TRCGRD
register
Compare match signal
Comparator TRCGRB
Comparator TRCGRC
NOTE:
1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register).
Count clear signal
Trigger signal
(Note 1)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 230 of 580
REJ09B0324-0200
j = A, B, C, or D
Table 14.23 Specifications of PWM2 Mode
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin
Count operation Increment TRC register
PWM waveform PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
Count start conditions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before count stops.
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
Interrupt request
generation timing
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
TRCIOA/TRCTRG pin
function
Programmable I/O port or TRCTRG input
TRCIOB pin function PWM output
TRCIOC and TRCIOD pin
functions
Programmable I/O port
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
Read from timer The count value can be read by reading the TRC register.
Write to timer The TRC register can be written to.
Select functions • External trigger and valid edge selected
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM
output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cu toff of Pulse
Output.)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
m+1
TRCTRG input
TRCIOB output
(TRCTRG: Rising edge, active level is “H”)
n-p
n+1
p+1 p+1
n+1
n-p
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 231 of 580
REJ09B0324-0200
Figure 14.57 TRCCR1 Register in PWM2 Mode
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. Do not set the TRCGRB and TRCGRC registers to the same value.
Table 14.24 Functions of TRCGRj Register in PWM2 Mode
Register Setting Register Function PWM2 Output Pin
TRCGRA −General register. Set the PWM period. TRCIOB pin
TRCGRB −General register. Set the PWM output change point.
TRCGRC BFC = 0 General register. Set the PWM output change point (wait time
after trigger).
TRCGRD BFD = 0 (Not used in PWM2 mode) −
TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to
14.3.3.2 Buffer Operation.)
TRCIOB pin
Timer RC Control Register 1
Symbol Address After Reset
TRCCR1 0121h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2. If the pin function is set for w aveform output (refer to Table s 7.45 and 7.46), the initial output lev el is output w hen
the TRCCR1 register is set.
TRC counter clear select bit
TCK2
Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
CCLR
Count source select bits(1) b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match in the
TRCGRA register
TCK0
TCK1
TOC RW
RW
RW
RW
TRCIOD output level select bit(1)
RW
0 : Active level “H”
(Initial output “L”
“H” output by compare match in the
TRCGRC register
“L” output by compare match in the
TRCGRB register
1 : Active level “L”
(Initial output “H”
“L” output by compare match in the
TRCGRC register
“H” output by compare match in the
TRCGRB register
RW
RW
TOB RW
TRCIOA output level select bit(1)
TRCIOB output level select bit(1, 2)
TRCIOC output level select bit(1)
Disabled in the PWM2 mode
Disabled in the PWM2 mode
b7 b6 b5 b4 b3 b2
TOD
b1 b0
TOA
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 232 of 580
REJ09B0324-0200
Figure 14.58 Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)
Set to 0 by a program Set to 0 by a program
TRC register value
Count source
m+1
n+1
0000h
FFFFh
p+1
TRCIOB output
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
m
n
p
TSTART bit in
TRCMR register
1
0
Count stops
because the
CSEL bit is
set to 1
“L” initial output
“H” output at TRCGRC
register compare match “L” output at TRCGRB
register compare match
IMFA bit in
TRCSR register
1
0
Set to 0 by a program
IMFB bit in
TRCSR register
CSEL bit in
TRCCR2 register
1
0
Set to 1 by
a program
1
0
IMFC bit in
TRCSR register
1
0
Transfer
TRCGRB register
TRCGRD register nNext data
Transfer
n
Transfer from buffer register to general register
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Set to 0000h
by a program
Previous value held if the
TSTART bit is set to 0
TSTART bit
is set to 0
TRC register cleared
at TRCGRA register
compare match
p+1
“H” output at TRCGRC register
compare match
No change
No change
Return to initial output
if the TSTART bit is
set to 0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 233 of 580
REJ09B0324-0200
Figure 14.59 Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
Set to 0 by
a program
TRC register value
Count source
m+1
n+1
0000h
FFFFh
p+1
TRCIOB output
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
m
n
p
TSTART bit in
TRCMR register
1
0
Count stops
because the
CSEL bit is
set to 1
“L” initial output
“H” output at
TRCGRC register
compare match
IMFA bit in
TRCSR register
1
0
Set to 0 by
a program
IMFB bit in
TRCSR register
CSEL bit in
TRCCR2 register
1
0
1
0
IMFC bit in
TRCSR register
1
0
Transfer
TRCGRB register
TRCGRD register Next data
Transfer
n
Transfer from buffer register to general register
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the
TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
Set to 0000h
by a program
Previous value
held if the
TSTART bit is
set to 0
The TSTART
bit is set to 0
TRC register cleared
at TRCGRA register
compare match
Return to initial value if the
TSTART bit is set to 0
TRC register (counter)
cleared at TRCTRG pin
trigger input
TRCTRG input Count starts
TSTART bit
is set to 1
n+1
p+1 p+1
“L” output at
TRCGRB register
compare match
Inactive level so
TRCTRG input is
enabled
Active level so TRCTRG
input is disabled
Set to 0 by
a program Set to 0 by
a program
n
Transfer
n
n
Transfer
Transfer from buffer register to general register
n
Set to 1 by
a program
Changed by a program
Count starts at
TRCTRG pin
trigger input
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 234 of 580
REJ09B0324-0200
Figure 14.60 Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
• TRCGRC register setting value greater than TRCGRA
register setting value
m
n
TRC register value
p
Set to 0 by a
program
0000h
IMFB bit in
TRCSR register
1
0
IMFC bit in
TRCSR register
1
0
TSTART bit in
TRCMR register
TRCIOB output
1
0
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
p+1
IMFA bit in
TRCSR register
1
0
“L” initial
output
No compare match with
TRCGRB register, so
“H” output continues
“H” output at TRCGRC register
compare match
m+1
• TRCGRB register setting value greater than TRCGRA
register setting value
m
p
TRC register value
n
0000h
IMFB bit in
TRCSR register
1
0
IMFC bit in
TRCSR register
1
0
TSTART bit in
TRCMR register
TRCIOB output
1
0
n+1
IMFA bit in
TRCSR register
1
0
“L” initial
output
“L” output at
TRCGRB register
compare match
with no change.
No compare match
with TRCGRC register,
so “L” output continues
m+1
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 235 of 580
REJ09B0324-0200
14.3.8 Timer RC Interrupt
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single
TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 14.25 lists the Registers Associated with Timer RC Interrupt, and Figure 14.61 is a Timer RC Interrupt
Block Diagram.
Figure 14.61 Timer RC Interrupt Block Diagram
Like other maskable interrupts, the timer RC interru pt is controlled by the comb inat ion of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RC interrupt) is generated from multiple i nterrupt request sources.
•The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to
1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
•The IR bit is set to 0 (no interrup t request) when the bit in the TRCSR reg ister or the corresponding bit in
the TRCIER register is set to 0, or both are set to 0. In other words, the i nterrupt request is not maintai ned
if the IR bit is once set to 1 but the interrupt is not acknowledged.
•If after the IR bit is set to 1 another interrup t source is triggered, the IR bit rem ains set to 1 and does not
change.
•If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the
interrupt request.
•The bits in the TRCSR register are not automatically set to 0 when an interrupt is ackn owledged. Set th em
to 0 within the interrupt r outine. Refer to Figure 14.31 TRCSR Register, for the procedure for setting
these bits to 0.
Refer to Figure 14.30 TRCIER Register, for details of the TRCIER register.
Refer to 12.1.6 Interrupt Control, for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
Table 14.25 R eg is te rs As so c ia ted with Timer RC Interrupt
Timer RC Status Register Timer RC Interrupt Enable Register Timer RC Interrupt Control Register
TRCSR TRCIER TRCIC
Timer RC interrupt request
(IR bit in TRCIC register)
IMFA bit
IMIEA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
OVF bit
OVIE bit
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 236 of 580
REJ09B0324-0200
14.3.9 Notes on Timer RC
14.3.9.1 TRC Register
•The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
•Reading from the TRC register immediat ely after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example MOV.W #XXXXh, TRC ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.W TRC,DATA ;Read
14.3.9.2 TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions .
Program Example MOV.B #XXh, TRCSR ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.B TRCSR,DATA ;Read
14.3.9.3 Count Source Switching
•Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
•After switching the count source from fOCO40M to another clock, allow a min imu m of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
14.3.9.4 Input Capture Function
•The pulse width of the input capture sign al shoul d be three cycles or more of the timer RC operation clock
(refer to Table 14.12 Timer RC Operation Clock).
•The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
14.3.9.5 TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 237 of 580
REJ09B0324-0200
14.4 Timer RD
Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins.
The operation clock of timer RD is f1 or fOC O40M. Table 14.26 lists the Timer RD Operation Clocks.
Figure 14.62 shows a Block Diagram of Timer RD. Timer RD has 5 modes:
• Timer mode
- Input capture function Transfer the counter value to a register with an external signal as the
trigger
- Output compare function Detect register value matches with a counter
(Pin output can be changed at detection)
The following 4 modes use the output compare function.
• PWM mode Outp ut pulse of any width continuously
• Reset synchronous PWM mode Output three-phase waveforms (6) without sawtooth wave m odul ation
and dead time
• Complem entary PWM mode Output three-phase waveforms (6) with triangular wav e modulation and
dead time
• PWM3 mod e O utput PWM waveforms (2) with a fixed period
In the input capture function, output compare function, and PWM mode, channels 0 and 1 have the equivalent
functions, and functions or modes can be selected individually for each pin. Also, a combination of these functions
and modes can be used in 1 channel.
In reset synchronous PWM mode, complementary PWM mode, and PW M3 mode, a waveform is output with a
combination of counters and registers in channels 0 and 1.
Tables 14.27 to 14.35 list the Pin Functions of timer RD.
Table 14.26 Timer RD Operation Clocks
Condition Operation Clock of Timer RD
The count source is f1, f2, f4, f8, f32, or TRDCLK input
(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to a value from 000b
to 101b).
f1
The count source is fOCO40M
(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b).
fOCO40M
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 238 of 580
REJ09B0324-0200
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_0 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function) and external clock
input (TRDCLK).
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_1 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_2 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.27 Pin Functions TRDIOA0/TRDCLK(P2_0)
Register TRDOER1 TRDFCR TRDIORA0 Function
Bit EA0 PWM3 STCLK
CMD1, CMD0
IOA3 IOA2_IOA0
Setting
value
0 0 0 00b X XXXb PWM3 mode waveform output
0 1 0 00b 1 001b, 01Xb Timer mode waveform output (output compare
function)
X
1 0 00b X 1XXb Timer mode trigger input (input capture function)(1)
1 1 XXb X 000b External clock input (TRDCLK)(1)
Other than above I/O port
Table 14.28 Pin Functions TRDIOB0(P2_1)
Register TRDOER1 TRDFCR TRDPMR TRDIORA0 Function
Bit EB0 PWM3 CMD1, CMD0 PWMB0 IOB2_IOB0
Setting
value
0X
1
X
b
X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 0 00b X XXXb PWM3 mode waveform output
0 1 00b 1 XXXb PWM mode waveform output
0 1 00b 0
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 0 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
Table 14.29 Pin Functions TRDIOC0(P2_2)
Register TRDOER1 TRDFCR TRDPMR
TRDIORC0
Function
Bit EC0 PWM3
CMD1, CMD0
PWMC0 IOC2_IOC0
Setting
value
0X
1
X
b
X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 1 00b 1 XXXb PWM mode waveform output
0 1 00b 0
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 0 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 239 of 580
REJ09B0324-0200
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_3 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_4 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_5 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.30 Pin Functions TRDIOD0(P2_3)
Register TRDOER1 TRDFCR TRDPMR
TRDIORC0
Function
Bit ED0 PWM3
CMD1, CMD0
PWMD0 IOD2_IOD0
Setting
value
0X
1
X
b
X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 1 00b 1 XXXb PWM mode waveform output
0 1 00b 0
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 0 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
Table 14.31 Pin Functions TRDIOA1(P2_4)
Register TRDOER1 TRDFCR TRDIORA1 Function
Bit EA1 PWM3 CMD1, CMD0 IOA2_IOA0
Setting
value
0X
1
X
b
XXXb Complementary PWM mode waveform output
0 X 01b XXXb Reset synchronous PWM mode waveform output
0 1 00b
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
Table 14.32 Pin Functions TRDIOB1(P2_5)
Register TRDOER1 TRDFCR TRDPMR
TRDIORA1
Function
Bit EB1 PWM3
CMD1, CMD0
PWMB1 IOB2_IOB0
Setting
value
0X
1
X
b
X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 1 00b 1 XXXb PWM mode waveform output
0 1 00b 0
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 0 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 240 of 580
REJ09B0324-0200
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_6 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_7 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
X: can be 0 or 1, no change in outcome
Table 14.33 Pin Functions TRDIOC1(P2_6)
Register TRDOER1 TRDFCR TRDPMR
TRDIORC1
Function
Bit EC1 PWM3
CMD1, CMD0
PWMC1 IOC2_IOC0
Setting
value
0X
1
X
b
X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 1 00b 1 XXXb PWM mode waveform output
0 1 00b 0
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 0 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
Table 14.34 Pin Functions TRDIOD1(P2_7)
Register TRDOER1 TRDFCR TRDPMR
TRDIORC1
Function
Bit ED1 PWM3
CMD1, CMD0
PWMD1 IOD2_IOD0
Setting
value
0X
1
X
b
X XXXb Complementary PWM mode waveform output
0 X 01b X XXXb Reset synchronous PWM mode waveform output
0 1 00b 1 XXXb PWM mode waveform output
0 1 00b 0
001b, 01
X
b
Timer mode waveform output (output compare function)
X 1 00b 0 1XXb
Timer mode trigger input (input capture function)
(1)
Other than above I/O port
Table 14.35 Pin Functions INT0(P4_5)
Register TRDOER2 INTEN PD4 Function
Bit PTO INT0PL INT0EN PD4_5
Setting
value
10
1
0 Pulse output forced cutoff signal input
Other than above I/O port or INT0 interrupt input
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 241 of 580
REJ09B0324-0200
Figure 14.62 Block Diagram of Timer RD
TRDi register
Data bus
TRDGRAi register
TRDGRBi register
TRDGRCi register
TRDGRDi register
TRDCRi register
TRDIORAi register
TRDIORCi register
TRDSRi register
TRDIERi register
TRDPOCRi register
TRDSTR register
TRDMR register
TRDPMR register
TRDFCR register
TRDOER1 register
TRDOER2 register
TRDOCR register
Timer RD control
circuit
INT0
TRDIOA0/TRDCLK
TRDIOB0
TRDIOC0
TRDIOD0
TRDIOB1
TRDIOC1
TRDIOD1
TRDIOA1
Count source
select circuit
f1, f2, f4, f8, f32,
fOCO40M
Channel 0 interrupt
request
Channel 1 interrupt
request
A/D trigger
Channel i
i = 0 or 1
TRDDFi register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 242 of 580
REJ09B0324-0200
14.4.1 Count Sources
The count source selection method is the same in all modes. However, in PWM3 mode, the external clock
cannot be selected.
i = 0 or 1
NOTE:
1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V.
Figure 14.63 Block Diagram of Count Source
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation
clock of timer RD (refer to Table 14.26 Timer RD Operation Clocks).
When selecting fOCO40M for the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed on-
chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M).
Table 14.36 C ount Source Selection
Count Source Selection
f1, f2, f4, f8, f32 The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
fOCO40M(1) The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator
frequency).
Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).
External signal input
to TRDCLK pin
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
TRDCLK/
TRDIOA0
TCK2 to TCK0
TRDi register
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
f1
f2
f4
f8
f32
= 001b
= 010b
= 011b
= 000b
= 101b
= 100b
Valid edge
selected
CKEG1 to CKEG0
TRDIOA0 I/O or programmable I/O port
Count source
STCLK = 1
STCLK = 0
fOCO40M = 110b
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 243 of 580
REJ09B0324-0200
14.4.2 Buffer Operation
The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the
TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi
in the TRDMR register.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
Buffer operation depends on the mode. Table 14.37 lists the Buffer Operation in Each Mode.
i = 0 or 1
Figure 14.64 Buffer Operation in Input Capture Function
Table 14.37 Buffer Operation in Each Mode
Function and Mode Transfer Timing Transfer Register
Input capture function Input capture signal input Transfer content in TRDGRAi
(TRDGRBi) register to buffer register
Output compare function Compare match with TRDi register
and TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
PWM mode
Reset synchronous PWM
mode
Compare match withTRD0 register
and TRDGRA0 register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Complementary PWM
mode
• Compare match with TRD0 register
and TRDGRA0 register
• TRD1 register underflow
Transfer content in buffer register to
registers TRDGRB0, TRDGRA1, and
TRDGRB1
PWM3 mode Compare match with TRD0 register
and TRDGRA0 register
Transfer content in buffer register to
registers TRDGRA0, TRDGRB0,
TRDGRA1, and TRDGRB1
m
Transfer
n
TRDGRAi register
n-1 n+1
TRDIOAi input
TRDi register
i = 0 or 1
The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).
m
Transfer
TRDGRCi register
(buffer)
n
TRDGRCi register
(buffer)
TRDGRAi
register TRDi
TRDIOAi input
(input capture signal)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 244 of 580
REJ09B0324-0200
Figure 14.65 Buffer Operation in Output Compare Function
Perform the following for the timer mode (inpu t capture and output compare functions).
When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.
When using the TRDGRDi register as the buffer register of the TRDGRBi register
• Set the IOD3 bit in the TRDIORDi regi ster to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using
registers TRDGRCi and TRDGRDi as the buffer register in the input capture function.
When also using registers TRDGRCi and TRDGRDi as buffer registers for the output compare function, reset
synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi
register are set to 1 by a compare match with the TRDi register.
mnTRDGRAi register
m-1 m+1
TRDi register
i = 0 or 1
The above applies under the following conditions:
• BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (“L” output by the compare match).
n
Transfer
TRDGRCi register
(buffer)
m
TRDIOAi output
TRDGRCi register
(buffer)
TRDGRAi
register Comparator TRDi
Compare match signal
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 245 of 580
REJ09B0324-0200
14.4.3 Synchronous Operation
The TRD1 register is synchronized with the TRD0 register.
• Synchronous preset
When the SYNC bit in the TRDMR register i s set to 1 (synch ronous operat ion), the data is written to bo th
the TRD0 and TRD1 registers after writing to the TRDi regi st er.
• Synchronous clear
When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register
are set to 01 1b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register
is set to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi
register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0
register is set to 0000h.
Figure 14.66 Synchronous Operation
Value in
TRD0 register
TRDIOA0 input
nn is set
n writing
Value in
TRD1 register
n
Set to 0000h with TRD0 register
Set to 0000h by input capture
The above applies under the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).
Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with
the TRD0 register).
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input)
The PWM 3 bit in the TRDFCR register is set to 1.
n is set
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 246 of 580
REJ09B0324-0200
14.4.4 Pulse Output Forced Cutoff
In the output compare function , PWM mode, reset synchrono us PWM mo de, complem entary PWM mo de, and
PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable
I/O port by the INT0 pin input, and pulse output can be cut off.
The pins used for output in these functions or modes can function as the out put pin of timer RD when the
applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the
TRDOER2 register to 1 (INT0 of pulse output forced cutoff signal input enabled), all bits in the TRDOER1
register are set to 1 (disable timer RD output, the TRDIOji output pin is used as the programmable I/O port)
after “L” is applied to the INT0 pin. The TRDIOji outpu t pin is set to the p rogrammable I/ O port after “L” is
applied to the IN T0 pin and waiting for 1 to 2 cycl es of the timer RD operation cl ock (refer to Table 14.26
Timer RD Operation Clocks).
Set as below when using this function:
• Set the pin status (high impedance, “L” or “H” output) to pulse output forced cutoff by registers P2 and
PD2.
• Set the INT0EN bit in the INTEN register to 1 (enable INT0 input) and the IN T0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF regi ster.
• Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0).
According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in
the INT0IC register is set to 1 (inter rupt request). Refer to 12. Interrupts for details of interrupts.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 247 of 580
REJ09B0324-0200
Figure 14.67 Pulse Output Forced Cutoff
INT0 input TRDIOA0
PTO bit
D
S
Q
EA0 bit
TRDIOB0
D
S
Q
EB0 bit
TRDIOC0
D
S
Q
EC0 bit
TRDIOD0
D
S
Q
ED0 bit
TRDIOA1
D
S
Q
EA1 bit
TRDIOB1
D
S
Q
EB1 bit
TRDIOC1
D
S
Q
EC1 bit
TRDIOD1
D
S
Q
ED1 bit
Port P2_0
output data
Port P2_0
input data
Port P2_1
output data
Port P2_1
input data
Port P2_2
output data
Port P2_2
input data
Port P2_3
output data
Port P2_3
input data
Port P2_4
output data
Port P2_4
input data
Port P2_5
output data
Port P2_5
input data
Port P2_6
output data
Port P2_6
input data
Port P2_7
output data
Port P2_7
input data
PTO: Bit in TRDOER2 register
EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register
EA0 bit
writing value
EB0 bit
writing value
EC0 bit
writing value
ED0 bit writing
value
EA1 bit writing
value
EB1 bit writing
value
EC1 bit
writing value
ED1 bit
writing value
Timer RD
output data
Timer RD
output data
Timer RD
output data
Timer RD
output data
Timer RD
output data
Timer RD
output data
Timer RD
output data
Timer RD
output data
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 248 of 580
REJ09B0324-0200
14.4.5 Input Capture Function
The input capture function measures the external signal width and period. The content of the TRDi register
(counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C, or D)
pin external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and
TRDGRji register , the input capture function, or any other mode or function, can be selected for each individual
pin.
The TRDGRA0 register can also select fOCO128 signal as input-captu re trigger input.
Figure 14.68 shows a Block Diagram of Input Capture Function, Table 14.38 lists the Input Capture Function
Specifications. Fig ures 14.69 to 14.8 0 show the Register s Associated with Input Capture Function, and Figure
14.81 shows an Operating Example of Input Capture Functio n.
Figure 14.68 Block Diagram of Input Capture Function
i = 0 or 1
NOTE 1: When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the
TRDGRAi register).
NOTE 2: When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the
TRDGRBi register).
TRDGRAi
register TRDi register
Input capture signal
TRDIOAi(3)
TRDGRCi
register
TRDGRBi
register
Input capture signal
TRDGRDi
register
TRDIOBi
(Note 1)
(Note 2)
TRDIOCi
TRDIODi
NOTE 3: The trigger input of the TRDGRA0 register
can select the TRDIOA0 pin input or
fOCO128 signal.
TRDIOA0
Divided
by 128 IOA3 = 0
IOA3 = 1
fOCO fOCO128
Input capture
signal
Input capture signal
Input capture signal
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 249 of 580
REJ09B0324-0200
i = 0 or 1, j = either A, B, C, or D
Table 14.38 Input Capture Function Specifications
Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Count operations Increment
Count period When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b
(free-running operation).
1/fk × 65536 fk: Frequency of count source
Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop condition 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
Interrupt request generation
timing
• Input capture (valid edge of TRDIOji input or fOCO128 signal edge)
• TRDi register overflows
TRDIOA0 pin function Programmable I/O port, input-capture input, or TRDCLK (external clock)
input
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
Programmable I/O port, or input-capture input (selectable by pin)
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read by reading the TRDi register.
Write to timer • When the SYNC bit in the TRDMR register is set to 0 (channels 0 and
1 operate independently).
Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and
1 operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to
the TRDi register.
Select functions • Input-capture input pin selected
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or
TRDIODi.
• Input-capture input valid edge selected
The rising edge, falling edge, or both the rising and falling edges
• The timing when the TRDi register is set to 0000h
At overflow or input capture
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Digital filter
The TRDIOji input is sampled, and when the sampled input level match
as 3 times, the level is determined.
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRDGRA0 register.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 250 of 580
REJ09B0324-0200
Figure 14.6 9 MSTCR Regist e r
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 251 of 580
REJ09B0324-0200
Figure 14.70 Registers TRDSTR and TRDMR in Input Capture Function
Timer RD Start Register(1)
Symbol Address Af ter Reset
TRDSTR 0137h 11111100b
Bit Symbol Bit Name Function RW
NOTE:
1.
RW
TSTA RT1 RW
TRD1 count start flag 0 : Count stops
1 : Count starts
TRD0 count start flag 0 : Count stops
1 : Count starts
—
(b7-b4)
CSEL0
11
TSTA RT0
b7 b6 b5 b4
Set to 1 in the input capture function.
TRD1 count operation select bit Set to 1 in the input capture function.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Ref er to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
TRD0 count operation select bit
b3 b2
CSEL1
b1 b0
Timer RD Mode Register
Symbol Address After Reset
TRDMR 0138h 00001110b
Bit Symbol Bit Name Function RW
b3 b2
BFD0
b1 b0
SYNC
b7 b6 b5 b4
RW
—
(b3-b1) —
Timer RD synchronous bit 0 : Registers TRD0 and TRD1
operate independently
1 : Registers TRD0 and TRD1
operate synchronously
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
TRDGRD0 register function select
bit
0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register function select
bit
0 : General register
1 : Buffer register of TRDGRA1 register RW
TRDGRC0 register function select
bit
0 : General register
1 : Buffer register of TRDGRA0 register
BFC0 RW
RW
BFC1
BFD1 TRDGRD1 register function select
bit
0 : General register
1 : Buffer register of TRDGRB1 register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 252 of 580
REJ09B0324-0200
Figure 14.71 TRDPMR Register in Input Capture Function
Timer RD PWM Mode Register
Symbol Address After Reset
TRDPMR 0139h 10001000b
Bit Symbol Bit Name Function RW
b3 b2
—
(b3)
b1 b0
000
PWMB0
b7 b6 b5 b4
000
RW
PWMC0 RW
PWM mode of TRDIOB0 select bit Set to 0 (timer mode) in the input capture
function.
PWM mode of TRDIOC0 select bit Set to 0 (timer mode) in the input capture
function.
PWM mode of TRDIOD0 select bit Set to 0 (timer mode) in the input capture
function.
PWMD0 RW
—
PWM mode of TRDIOB1 select bit Set to 0 (timer mode) in the input capture
function.
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Set to 0 (timer mode) in the input capture
function.
—
(b7) —
PWMB1
PWMC1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWM mode of TRDIOC1 select bit Set to 0 (timer mode) in the input capture
function.
PWMD1 PWM mode of TRDIOD1 select bit
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 253 of 580
REJ09B0324-0200
Figure 14.72 TRDFCR Register in Input Capture Function
Timer RD Function Control Register
Symbol Address After Reset
TRDFCR 013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
STCLK External clock input select bit 0 : External clock input disabled
1 : External clock input enabled RW
RW
PWM3 RW
ADTRG
ADEG
A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in the input capture
function. RW
PWM3 mode select bit(2) Set this bit to 1 (other than PWM3 mode) in
the input capture f unction.
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
This bit is disabled in the input capture
function.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
This bit is disabled in the input capture
function.
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in the input capture
function.
RW
CMD1 RW
Combination mode select bits(1) Set to 00b (timer mode, PWM mode, or
PWM3 mode) in the input capture function.
CMD0
b7 b6 b5 b4
1
When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
OLS1
b1 b0
00
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 254 of 580
REJ09B0324-0200
Figure 14.73 Registers TRDDF0 to TRDDF1 in Input Capture Function
Timer RD Digital Filter Function Select Register i (i = 0 or 1)
Symbol Address After Reset
TRDDF0
TRDDF1
013Eh
013Fh
00h
00h
Bit Symbol Bit Name Function RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock select bits for digital filter
function
DFCK1 RW
b7 b6
0 0 : f32
0 1 : f8
1 0 : f1
1 1 : Count source (clock selected by
bits TCK2 to TCK0 in the
TRDCRi register)
RW
RW
TRDIOD pin digital filter function
select bit
0 : Function is not used
1 : Function is used
TRDIOC pin digital filter function
select bit
0 : Function is not used
1 : Function is used
RW
DFB RW
DFA TRDIOA pin digital filter function
select bit
0 : Function is not used
1 : Function is used
TRDIOB pin digital filter function
select bit
0 : Function is not used
1 : Function is used
b7 b6 b5 b4 b3 b2
DFD
b1 b0
DFC
—
(b5-b4)
DFCK0 RW
—
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 255 of 580
REJ09B0324-0200
Figure 14.74 Registers TRDCR0 to TRDC R1 in Input Capture Function
Timer RD Control Register i (i = 0 or 1)
Symbol Address After Reset
TRDCR0
TRDCR1
0140h
0150h
00h
00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
synchronously).
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
RW
CKEG1
CCLR0 RW
b7 b6 b5
0 0 0 : Disable clear (free-running
operation)
0 0 1 : Clear by input capture in the
TRDGRAi register
0 1 0 : Clear by input capture in the
TRDGRBi register
0 1 1 : Synchronous clear (clear
simultaneously w ith other
channel counter)(3)
1 0 0 : Do not set.
1 0 1 : Clear by input capture in the
TRDGRCi register
1 1 0 : Clear by input capture in the
TRDGRDi register
1 1 1 : Do not set.
TRDi counter clear select bits
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
b3 b2
CKEG0
b1 b0
TCK2
b7 b6 b5 b4
RW
RW
RW
CCLR2
CCLR1 RW
Count source select bits b2 b1 b0
0 0 0 : f 1
0 0 1 : f 2
0 1 0 : f 4
0 1 1 : f 8
1 0 0 : f 32
1 0 1 : TRDCLK input(1)
1 1 0 : f OCO40M
1 1 1 : Do not set.
External clock edge select bits(2) b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
RW
TCK1 RW
TCK0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 256 of 580
REJ09B0324-0200
Figure 14.75 Registers TRDIORA0 to TRDIORA1 in Input Capture Function
Timer RD I/O Control Register Ai (i = 0 or 1)
Symbol Address After Reset
TRDIORA 0
TRDIORA 1
0141h
0151h
10001000b
10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
To select 1 (the TRDGRDi register is used as a buff er register of the TRDGRBi register) for this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
Set to 1 (input capture) in the input capture
function.
RW
—
(b7)
IOB2 RW
TRDGRB c ontr ol bits b5 b4
0 0 : Input capture to the TRDGRBi register
at the rising edge
0 1 : Input capture to the TRDGRBi register
at the falling edge
1 0 : Input capture to the TRDGRBi register
at both edges
1 1 : Do not set.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
IOB0
IOB1 RW
b3 b2
IOA 3
b1 b0
1
IOA 2
1
b7 b6 b5 b4
RW
RW
IOA 1
IOA 0
TRDGRA control bits b1 b0
0 0 : Input capture to the TRDGRAi register
at the rising edge
0 1 : Input capture to the TRDGRAi register
at the falling edge
1 0 : Input capture to the TRDGRAi register
at both edges
1 1 : Do not set.
The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1.
The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture f unction).
TRDGRA mode select bit(1) Set to 1 (input capture) in the input capture
function. RW
Input capture input sw itch
bit(3, 4)
0 : fOCO128 Signal
1 : TRDIOA0 pin input RW
To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
TRDGRB mode select bit(2)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 257 of 580
REJ09B0324-0200
Figure 14.76 Registers TRDIORC0 to TRDIORC1 in Input Capture Function
Timer RD I/O Control Register Ci (i = 0 or 1)
Symbol Address Af ter Reset
TRDIORC0
TRDIORC1
0142h
0152h
10001000b
10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
TRDGRC mode select bit(1) Set to 1 (input capture) in the input capture
function. RW
TRDGRC register f unction
select bit
Set to 1 (general register or buffer register) in
the input capture f unction. RW
RW
RW
IOC1
IOC0
TRDGRC c ontr ol bits b1 b0
0 0 : Input capture to the TRDGRCi register
at the rising edge
0 1 : Input capture to the TRDGRCi register
at the falling edge
1 0 : Input capture to the TRDGRCi register
at both edges
1 1 : Do not set.
b7 b6 b5 b4
11
b3 b2
IOC3
b1 b0
11
IOC2
To select 1 (the TRDGRDi register is used as a buff er register of the TRDGRBi register) f or this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
TRDGRD mode select bit(2) Set to 1 (input capture) in the input capture
function.
RW
IOD3
IOD2 RW
TRDGRD c ontr ol bits b5 b4
0 0 : Input capture to the TRDGRDi register
at the rising edge
0 1 : Input capture to the TRDGRDi register
at the falling edge
1 0 : Input capture to the TRDGRDi register
at both edges
1 1 : Do not set.
TRDGRD register f unction
select bit
To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
RW
IOD0
IOD1 RW
Set to 1 (general register or buffer register) in
the input capture f unction.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 258 of 580
REJ09B0324-0200
Figure 14.77 Registers TRDSR0 to TRDSR1 in Input Capture Function
Timer RD Status Register i (i = 0 or 1)
Symbol Address After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWOV F
UDF Underf low flag(1) This bit is disabled in the input capture f unction. RW
Input capture/compare match
flag C
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
Input edge of TRDIOCi pin(4)
Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
IMFC RW
RW
Input capture/compare match
flag D
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
Input edge of TRDIODi pin(4)
Overf low flag [Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
When the TRDi register overflow s
RW
IMFB RW
Input capture/compare match
flag A
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
TRDSR0 register:
fOCO128 signal edge w hen the IOA3 bit in the
TRDIORA0 register is set to 0 (fOCO128 signal)
TRDIOA0 pin input edge w hen the IOA3 bit in the
TRDIORA0 register is set to 1 (TRDIOA0 input)(3)
TRDSR1 register:
Input edge of TRDIOA1 pin(3)
Input capture/compare match
flag B
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
Input edge of TRDIOBi pin(3)
IMFA
b7 b6 b5 b4
Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register
Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).
Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register.
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even
if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
b3 b2
IMFD
b1 b0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 259 of 580
REJ09B0324-0200
Figure 14.78 Registers TRDIER0 to TRDIER1 in Input Capture Function
Figure 14.79 Registers TRD0 to TRD1 in Input Capture Function
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol Bit Name Function RW
RWOVIE
—
(b7-b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the IMFC bit
1 : Enable interrupt (IMIC) by the IMFC bit
IMIEC RW
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the IMFD bit
1 : Enable interrupt (IMID) by the IMFD bit
Overf low /underflow interrupt
enable bit
0 : Disable interrupt (OVI) by the OVF bit
1 : Enable interrupt (OVI) by the OVF bit
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the IMFA bit
1 : Enable interrupt (IMIA) by the IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the IMFB bit
1 : Enable interrupt (IMIB) by the IMFB bit
IMIEA
b7 b6 b5 b4 b3 b2
IMIED
b1 b0
Timer RD Counter i (i = 0 or 1)(1)
Symbol Address After Reset
TRD0
TRD1
0147h-0146h
0157h-0156h
0000h
0000h
Setting Range RW
NOTE:
1.
(b8)
b0
(b15)
b7
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
b0b7
Function
Count the count source. Count operation is incremented.
When an overf low occurs, the OVF bit in the TRDSRi register is set to 1.
0000h to FFFFh
RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 260 of 580
REJ09B0324-0200
Figure 14.80 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Input Capture Function
The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR,
TRDPOCR0, and TRDPOCR1.
i = 0 or 1, j = either A, B, C, or D
BFCi, BFDi: Bits in TRDMR register
Set the pulse width o f the input captu re signal applied to the TRDIOji pin t o 3 cycles or more of t he timer RD
operation clock (refer to Table 14.26 Timer RD Operation Clocks) for no digital filter (the DFj bit in the
TRDDFi register set to 0).
Table 14.39 TRDGRji Register Functions in Input Capture Function
Register Setting Register Function Input-Capture Input Pin
TRDGRAi −General register
The value in the TRDi register can be read at input
capture.
TRDIOAi
TRDGRBi TRDIOBi
TRDGRCi BFCi = 0 General register
The value in the TRDi register can be read at input
capture.
TRDIOCi
TRDGRDi BFDi = 0 TRDIODi
TRDGRCi BFCi = 1 Buffer register
The value in the TRDi register can be read at input
capture. (Refer to 14.4.2 Buffer Operation)
TRDIOAi
TRDGRDi BFDi = 1 TRDIOBi
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
Symbol Address After Reset
TRDGRA 0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA 1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
(b8)
b0
(b15)
b7 b0b7
RW
Function
Ref er to Table 1 4.3 9 TRDGRji Regi ster Func tions in I nput Capture Func tion
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 261 of 580
REJ09B0324-0200
Figure 14.81 Operating Example of Input Capture Function
Set to 0 by a program
Transfer
i = 0 or 1
The above applies under the following conditions:
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (the TRDi register set to 0000h by TRDGRAi register input capture).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input for the count source).
Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge for the count source).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input).
The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register).
Count value
in TRDi register
FFFFh
0009h
0006h
TSTARTi bit in
TRDSTR register
65536
TRDGRAi register
0000h
1
0
TRDIOAi input
TRDGRCi register
IMFA bit in
TRDSRi register
OVF bit in
TRDSRi register
0009h0006h
0006h
1
0
1
0
TRDCLK input
count source
Transfer
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 262 of 580
REJ09B0324-0200
14.4.5.1 Digit a l Filter
The TRDIOji input is sampled, and w hen the sampled input level matches 3 times, its level is determined.
Select the digital filter function and sampl ing clock by the TRDDFi register.
Figure 14.82 Block Diagram of Digital Filter
Clock period selected by
bits TCK2 to TCK0 or
bits DFCK1 to DFCK0
Sampling clock
TRDIOji input signal
Input signal through
digital filtering
Transmission cannot be
performed without 3-time match
because the input signal is
assumed to be noise.
Signal transmission delayed
up to 5-sampling clock
Recognition of the
signal change with
3-time match
i = 0 or 1, j = either A, B, C, or D
TCK0 to TCK2: Bits in TRDCRi register
DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
Match
detection
circuit
Edge detection
circuit
DFj
Sampling clock
IOA2 to IOA0
IOB2 to IOB0
IOC3 to IOC0
IOD3 to IOD0
DFCK1 to DFCK0
TRDIOji input signal
f32
f8
f1
C
DQ
Latch
C
DQ
Latch
Timer RD operation clock
f1, fOCO40M)
Count source
= 101b
= 100b
= 011b
= 110b
= 010b
= 001b
fOCO40M
f4
f2
f8
f32
TRDCLK
f1 = 000b
= 00b
= 01b
= 10b
= 11b
TCK2 to TCK0
1
0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 263 of 580
REJ09B0324-0200
14.4.6 Output Compare Function
This function detects matches (compare match) between the content of the TRDGRji (j = either A, B, C, or D)
register and the content of the TRDi (i = 0 or 1) register. When the content matches, a user-set level is output
from the TRDIOji pi n. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji
register, the output compare function, or any other mode or function, can be selected for each individual pin.
Figure 14.83 shows a Block Diagram of Output Compare Function, Table 14.40 lists the Out put Compare
Function Specifications. Figures 14.84 to 14.96 list the registers associated with output compare function, and
Figure 14.97 shows an Operating Example of Output Compare Function.
Figure 14.83 Block Diagram of Output Compare Function
TRDIOA0 Output
control
Comparator TRDGRA0
TRD0
TRDIOC0 Output
control
Comparator TRDGRC0
Compare match signal
TRDIOB0 Output
control
Comparator TRDGRB0
TRDIOD0 Output
control
Comparator TRDGRD0
Channel 0
TRDIOA1 Output
control
Comparator TRDGRA1
TRD1
TRDIOC1 Output
control
Comparator TRDGRC1
TRDIOB1 Output
control
Comparator TRDGRB1
TRDIOD1 Output
control
Comparator TRDGRD1
Channel 1
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Compare match signal
IOC3 = 0 in
TRDIORC0 register
IOC3 = 1
IOD3 = 0 in
TRDIORD0 register
IOD3 = 1
IOC3 = 0 in
TRDIORC1 register
IOC3 = 1
IOD3 = 0 in
TRDIORD1 register
IOD3 = 1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 264 of 580
REJ09B0324-0200
i = 0 or 1, j = either A, B, C, or D
Table 14.40 Output Compare Function Specifications
Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Count operations Increment
Count period • When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running
operation)
1/fk × 65536 fk: Frequency of count source
• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the TRDi
register to 0000h at the compare match in the TRDGRji register).
Frequency of count source x (n+1)
n: Setting value in the TRDGRji register
Waveform output timing Compare match
Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the
CSELi bit in the TRDSTR register is set to 1.
The output compare output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
compare match in the TRDGRAi register.
The output compare output pin holds level after output change by the compare
match.
Interrupt request generation
timing
• Compare match (content of the TRDi register matches content of the TRDGRji
register.)
• TRDi register overflows
TRDIOA0 pin function Programmable I/O port, output-compare output, or TRDCLK (external clock) input
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
Programmable I/O port or output-compare output (Selectable by pin)
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
Read from timer The count value can be read by reading the TRDi register.
Write to timer • When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate
independently).
Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate
synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Select functions • Output-compare output pin selected
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
• Output level at the compare match selected
“L” output, “H” output, or output level inversed
• Initial output level selected
Set the level at period from the count start to the compare match.
• Timing to set the TRDi register to 0000h
Overflow or compare match in the TRDGRAi register
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Synchronous operation (Refer to 14.4.3 Sync hronous Operation.)
• Output pin in registers TRDGRCi and TRDGRDi changed
The TRDGRCi register can be used as output control of the TRDIOAi pin and the
TRDGRDi register can be used as output control of the TRDIOBi pin.
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output Forced
Cutoff.)
• Timer RD can be used as the internal timer without output.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 265 of 580
REJ09B0324-0200
Figure 14.8 4 MSTCR Regist e r
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 266 of 580
REJ09B0324-0200
Figure 14.85 Registers TRDSTR and TRDMR in Output Compare Function
Timer RD Mode Register
Symbol Address After Reset
TRDMR 0138h 00001110b
Bit Symbol Bit Name Function RW
NOTE:
1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1)
register, set the BFji bit in the TRDMR register to 0.
RWBFC1
BFD1 TRDGRD1 register function select
bit(1)
0 : General register
1 : Buffer register of TRDGRB1 register RW
TRDGRC0 register function select
bit(1)
0 : General register
1 : Buffer register of TRDGRA0 register
BFC0 RW
RW
TRDGRD0 register function select
bit(1)
0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register function select
bit(1)
0 : General register
1 : Buffer register of TRDGRA1 register
RW
—
(b3-b1) —
Timer RD synchronous bit 0 : Registers TRD0 and TRD1
operate independently
1 : Registers TRD0 and TRD1
operate synchronously
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b7 b6 b5 b4 b3 b2
BFD0
b1 b0
SYNC
Timer RD Start Register(1)
Symbol Address Af ter Reset
TRDSTR 0137h 11111100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
b3 b2
CSEL1
b1 b0
TSTA RT0
b7 b6 b5 b4
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
TSTA RT1 RW
TRD1 count start flag(5) 0 : Count stops(3)
1 : Count starts
TRD0 count start flag(4) 0 : Count stops(2)
1 : Count starts
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Timer RD.
TRD0 count operation
select bit
0 : Count stops at the compare match w ith the
TRDGRA0 register
1 : Count continues af ter the compare match
w ith the TRDGRA0 register
CSEL0 RW
RW
TRD1 count operation
select bit
0 : Count stops at the compare match w ith the
TRDGRA1 register
1 : Count continues af ter the compare match
w ith the TRDGRA1 register
—
—
(b7-b4)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 267 of 580
REJ09B0324-0200
Figure 14.86 TRDPMR Register in Output Compare Function
Timer RD PWM Mode Register
Symbol Address After Reset
TRDPMR 0139h 10001000b
Bit Symbol Bit Name Function RW
—
(b7) —
PWMB1
PWMC1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWM mode of TRDIOC1 select bit Set to 0 (timer mode) in the output
compare function.
PWMD1 PWM mode of TRDIOD1 select bit
PWM mode of TRDIOD0 select bit Set to 0 (timer mode) in the output
compare function.
PWMD0 RW
—
PWM mode of TRDIOB1 select bit Set to 0 (timer mode) in the output
compare function.
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Set to 0 (timer mode) in the output
compare function.
RW
PWMC0 RW
PWM mode of TRDIOB0 select bit Set to 0 (timer mode) in the output
compare function.
PWM mode of TRDIOC0 select bit Set to 0 (timer mode) in the output
compare function.
000
b7 b6 b5 b4 b3 b2
—
(b3)
b1 b0
000
PWMB0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 268 of 580
REJ09B0324-0200
Figure 14.87 TRDFCR Register in Output Compare Function
Timer RD Function Control Register
Symbol Address After Reset
TRDFCR 013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
OLS1
b1 b0
001
b7 b6 b5 b4
RW
CMD1 RW
Combination mode select bits(1) Set to 00b (timer mode, PWM mode, or
PWM3 mode) in the output compare
function.
CMD0
Normal-phase output level select bit
(in reset synchronous PWM mode or
c omplementar y PWM mode)
This bit is disabled in the output compare
function.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level select bit
(in reset synchronous PWM mode or
c omplementar y PWM mode)
This bit is disabled in the output compare
function.
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in the output compare
function. RW
PWM3 RW
ADTRG
ADEG A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in the output compare
function. RW
PWM3 mode s ele c t bit(2) Set this bit to 1 (other than PWM3 mode) in
the output compare function.
STCLK External clock input select bit 0 : External clock input disabled
1 : External clock input enabled RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 269 of 580
REJ09B0324-0200
Figure 14.88 Registers TRDOER1 to TRDOER2 in Output Compare Function
Timer RD Output Master Enable Register 1
Symbol Address After Reset
TRDOER1 013Bh FFh
Bit Symbol Bit Name Function RW
ED1 RW
EA 1
EB1 RW
TRDIOD1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
TRDIOB1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
EC1
RW
TRDIOA1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
RW
TRDIOD0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
TRDIOC1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
TRDIOC0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
EC0 RW
RW
EB0 RW
TRDIOA0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA0 pin is
used as a programmable I/O port.)
TRDIOB0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
b7 b6 b5 b4 b3 b2
ED0
b1 b0
EA 0
Timer RD Output Master Enable Register 2
Symbol Address Af ter Reset
TRDOER2 013Ch 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____
of pulse output forced 0 : Pulse output forced cutoff input disabled
cutof f signal input enabled 1 : Pulse output forced cutoff input enabled
bit(1) (All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
applied to the INT0
_
____
pin.)
NOTE:
1.
—
(b6-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWPTO
b7 b6 b5 b4
Ref er to 14.4.4 Pulse Output Forced Cutoff.
b3 b2 b1 b0
—
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 270 of 580
REJ09B0324-0200
Figure 14.89 TRDOCR Register in Output Compare Function
Timer RD Output Control Register(1, 2)
Symbol Address After Reset
TRDOCR 013Dh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2. If the pin function is set for w avef orm output (refer to Tables 14.27 to 14.34), the initial output level is output w hen
the TRDOCR regis ter is s et.
TOA 1
TOB1 RW
TRDIOD1 initial output level select bit
0 : “L”
1 : “H”
TRDIOB1 initial output level select bit
TOC1 TRDIOC1 initial output level select bit
TRDIOC0 initial output level select bit
Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stopped).
TOC0 RW
RW
TRDIOA1 initial output level select bit
RW
RW
TRDIOD0 initial output level select bit
TOD1 RW
RW
TOB0 RW
TRDIOA0 output level select bit 0 : Initial output “L”
1 : Initial output “H”
TRDIOB0 output level select bit 0 : Initial output “L”
1 : Initial output “H”
001
b7 b6 b5 b4 b3 b2
TOD0
b1 b0
TOA 0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 271 of 580
REJ09B0324-0200
Figure 14.90 Registers TRDCR0 to TRDCR1 in Output Compare Function
Timer RD Control Register i (i = 0 or 1)
Symbol Address Af ter Reset
TRDCR0
TRDCR1
0140h
0150h
00h
00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
RW
TCK1 RW
TCK0
RW
RW
RW
CCLR2
CCLR1 RW
Count source select bits b2 b1 b0
0 0 0 : f 1
0 0 1 : f 2
0 1 0 : f 4
0 1 1 : f 8
1 0 0 : f 32
1 0 1 : TRDCLK input(1)
1 1 0 : f OCO40M
1 1 1 : Do not set.
External clock edge select
bits(2)
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
b7 b6 b5 b4 b3 b2
CKEG0
b1 b0
TCK2
This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate
synchronously).
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
RW
CKEG1
CCLR0 RW
b7 b6 b5
0 0 0 : Disable clear (free-running operation)
0 0 1 : Clear by compare match w ith the
TRDGRAi register
0 1 0 : Clear by compare match w ith the
TRDGRBi register
0 1 1 : Synchronous clear (clear
simultaneously w ith other channel
counter)(3)
1 0 0 : Do not set.
1 0 1 : Clear by compare match w ith the
TRDGRCi register
1 1 0 : Clear by compare match w ith the
TRDGRDi register
1 1 1 : Do not set.
TRDi counter clear select
bits
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 272 of 580
REJ09B0324-0200
Figure 14.91 Registers TRDIORA0 to TRDIORA1 in Output Compare Function
Timer RD I/O Control Register Ai (i = 0 or 1)
Symbol Address After Reset
TRDIORA 0
TRDIORA 1
0141h
0151h
10001000b
10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. To select 1 (the TRDGRDi register is used as a buf fer register of the TRDGRBi register) f or this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
—
IOB0
IOB1 RW
To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
TRDGRB mode select bit(2) Set to 0 (output compare) in the output compare
function.
RW
b3 b2
IOA 3
b1 b0
10
IOA 2
0
b7 b6 b5 b4
—
(b7)
IOB2 RW
TRDGRB c ontr ol bits b5 b4
0 0 : Disable pin output by the compare match
(TRDIOBi pin functions as programmable
I/O port)
0 1 : “L” output at compare match
w ith the TRDGRBi register
1 0 : “H” output at compare match
w ith the TRDGRBi
1 1 : Toggle output by compare match
w ith the TRDGRBi register
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
IOA 1
IOA 0
TRDGRA c ontrol bits b1 b0
0 0 : Disable pin output by the compare match
(TRDIOAi pin functions as programmable
I/O port)
0 1 : “L” output at compare match w ith
the TRDGRAi register
1 0 : “H” output at compare match w ith
the TRDGRAi register
1 1 : Toggle output by compare match
w ith the TRDGRAi register
TRDGRA mode select bit(1) Set to 0 (output compare) in the output compare
function. RW
Input capture input sw itch
bit
Set to 1. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 273 of 580
REJ09B0324-0200
Figure 14.92 Registers TRDIORC0 to TRDIORC1 in Output Compare Function
Timer RD I/O Control Register Ci (i = 0 or 1)
Symbol Address After Reset
TRDIORC0
TRDIORC1
0142h
0152h
10001000b
10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
IOC2
To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
TRDGRD mode select bit(2) Set to 0 (output compare) in the output compare
function.
IOD3
IOD2 RW
TRDGRD register f unction
select bit
0 : TRDIOB output register
(Refer to 14.4.6.1 Cha nging Output Pins in
Registers TRDGRCi (i = 0 or 1) and
TRDGRDi.)
1 : General register or buffer register
RW
b3 b2
IOC3
b1 b0
0
RW
TRDGRD c ontr ol bits b5 b4
0 0 : Disable pin output by compare match
0 1 : “L” output at compare match w ith
the TRDGRDi register
1 0 : “H” output at compare match w ith
the TRDGRDi register
1 1 : Toggle output by compare match
w ith the TRDGRDi register
b7 b6 b5 b4
0
RW
RW
IOC1
IOC0
TRDGRC c ontr ol bits b1 b0
0 0 : Disable pin output by compare match
0 1 : “L” output at compare match w ith
the TRDGRCi register
1 0 : “H” output at compare match w ith
the TRDGRCi register
1 1 : Toggle output by compare match
w ith the TRDGRCi register
To select 1 (the TRDGRDi register is used as a buff er register of the TRDGRBi register) f or this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
TRDGRC mode select bit(1) Set to 0 (output compare) in the output compare
function. RW
TRDGRC register f unction
select bit
0 : TRDIOA output register
(Refer to 14.4.6.1 Changing O utput Pins in
Registers TRDGRCi (i = 0 or 1) and
TRDGRDi.)
1 : General register or buffer register
RW
IOD0
IOD1
RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 274 of 580
REJ09B0324-0200
Figure 14.93 Registers TRDSR0 to TRDSR1 in Output Compare Function
Timer RD Status Register i (i=0 or 1)
Symbol Address After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWOVF
UDF Underflow f lag(1) This bit is disabled in the output compare function. RW
Input capture/compare match
flag C
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register(3).
Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
IMFC RW
RW
Input capture/compare match
flag D
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register(3).
Overf low flag [Source f or setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
RW
IMFB RW
Input capture/compare match
flag A
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
Input capture/compare match
flag B
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
IMFA
b7 b6 b5 b4
Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
b3 b2
IMFD
b1 b0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 275 of 580
REJ09B0324-0200
Figure 14.94 Registers TRDIER0 to TRDIER1 in Output Compare Function
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol Bit Name Function RW
RWOVIE
—
(b7-b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
IMIEC RW
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Overf low /underflow interrupt enable
bit
0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
b7 b6 b5 b4 b3 b2
IMIED
b1 b0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 276 of 580
REJ09B0324-0200
Figure 14.95 Registers TRD0 to TRD1 in Output Compare Function
Figure 14.96 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRD GRDi in Output Compare Function
The following registers are disabled in the output comp are function: TRDDF0, TRDDF1, TRDPOCR0, and
TRDPOCR1.
i = 0 or 1, j = either A, B, C, or D
BFji: Bit in TRDMR register IOj3: Bit in TRDIORCi register
Table 14.41 TRDGRji Register Function in Output Compare Function
Register Setting Register Function Output-Compare
Output Pin
BFji IOj3
TRDGRAi −−General register. Write the compare value. TRDIOAi
TRDGRBi TRDIOBi
TRDGRCi 0 1 General register. Write the compare value. TRDIOCi
TRDGRDi TRDIODi
TRDGRCi 1 1 Buffer register. Write the next compare value
(Refer to 14.4.2 Buffer Operation.)
TRDIOAi
TRDGRDi TRDIOBi
TRDGRCi 0 0 TRDIOAi output control (Refer to 14.4.6.1 Changing
Output Pins in Regis ters TRDGRCi (i = 0 or 1) and
TRDGRDi.)
TRDIOAi
TRDGRDi TRDIOBi
Timer RD Counter i (i = 0 or 1)(1)
Symbol Address After Reset
TRD0
TRD1
0147h-0146h
0157h-0156h
0000h
0000h
Setting Range RW
NOTE:
1.
(b8)
b0
(b15)
b7
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
b0b7
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
0000h to FFFFh
RW
Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1)
Symbol Address After Reset
TRDGRA 0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA 1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
RW
Function
Ref er to Ta ble 14.41 TRDGRji Regi ster Func tion i n Output Compare Func tion
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
b0b7
(b8)
b0
(b15)
b7
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 277 of 580
REJ09B0324-0200
Figure 14.97 Operating Example of Output Compare Function
m
n
p
Value in TRDi register
m+1 m+1
TSTARTi bit in
TRDSTR register
1
0
TRDIOAi output
IMFA bit in
TRDSRi register
1
0
n+1
TRDIOBi output
IMFB bit in
TRDSRi register
1
0
TRDIOCi output
IMFC bit in
TRDSRi register
1
0
Initial output “H”
“L” output by compare match
Set to 0 by a program
Count source
i = 0 or 1 M: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register).
The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output).
m
n
p
m+1 m+1
n+1
P+1
Count
stops
Count
restarts
Output level
held
Output level
held
Output level
held
Set to 0 by a program
Set to 0 by a program
“H” output by compare match
Output inverted by compare match
Initial output “L”
Initial output “L”
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output “L” to compare match), the TOCi bit is set to 1 (initial output “H” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi “H” output at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi “L” output at TRDGRCi register compare match).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 278 of 580
REJ09B0324-0200
14.4.6.1 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi
The TRDGRCi register can be used for output control of the TRDIO Ai pin, and t he TRDGRDi regist er can be
used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:
• TRDIOAi output is controlled by the values in registers TRDGRAi and TRDGRCi.
• TRDIOBi output is controlled by the values in registers TRDGRBi and TRDGRD i.
Change output pins in registers TRDGRCi and TRDGRDi as follows:
• Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register.
• Set the BFji bit in th e TRDMR re gister to 0 (general register).
• Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers
TRDGRDi and TRDGRBi.
Figure 14.99 shows an Operating Examp le When TRDGRCi Register is Used for Out put Control of TRDIOA i
Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 279 of 580
REJ09B0324-0200
Figure 14.98 Changing Output Pins in Registers TRDGRCi and TRDGRDi
TRDIOA0 Output
control
Comparator TRDGRA0
TRD0
TRDIOC0 Output
control
Comparator TRDGRC0
Compare match signal
TRDIOB0 Output
control
Comparator TRDGRB0
TRDIOD0 Output
control
Comparator TRDGRD0
Channel 0
TRDIOA1 Output
control
Comparator TRDGRA1
TRD1
TRDIOC1 Output
control
Comparator TRDGRC1
TRDIOB1 Output
control
Comparator TRDGRB1
TRDIOD1 Output
control
Comparator TRDGRD1
Channel 1
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Compare match signal
IOC3 = 0 in
TRDIORC0 register
IOC3 = 1
IOD3 = 0 in
TRDIORD0 register
IOD3 = 1
IOC3 = 0 in
TRDIORC1 register
IOC3 = 1
IOD3 = 0 in
TRDIORD1 register
IOD3 = 1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 280 of 580
REJ09B0324-0200
Figure 14.99 Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi
Pin and TRDGRDi Register is Us ed for Output Control of TRDIOBi Pin
Set to 0 by a programSet to 0 by a program
Value in TRDi register
Count source
TRDIOAi output
FFFFh
TRDIOBi output
m: Value set in TRDGRAi register
n: Value set in TRDGRCi register
p: Value set in TRDGRBi register
q: Value set in TRDGRDi register
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer register).
Bits EAi and EBi in the TRDOER1 register are set to 0 (enable TRDIOAi and TRDIOBi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 0000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output “L” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted at TRDGRCi register compare match).
Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted at TRDGRDi register compare match).
i = 0 or 1
m
n
p
m+1
n+1
q
0000h
m-n
p+1
p-qq+1
IMFA bit in
TRDSRi register
1
0
IMFC bit in
TRDSRi register
1
0
Set to 0 by a program
Output inverted by compare match
Initial output “L”
IMFB bit in
TRDSRi register
1
0
IMFD bit in
TRDSRi register
1
0
Initial output “L”
Set to 0 by a program
Output inverted by compare match
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 281 of 580
REJ09B0324-0200
14.4.7 PWM Mode
In PWM mode, a PWM waveform is output. Up to 3 PWM waveforms with the same period can be output by 1
channel. Also, up to 6 PWM waveforms with the same period can be output by synchronizing channels 0 and 1.
Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and TRDGRji
register, the PWM mode, or any other mode or function, can be selected for each individual pin. (However,
since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used
for other modes.)
Figure 14.100 shows a Block Diagram of PWM Mod e, and Table 14.42 lists t he PWM Mode Speci fications.
Figures 14.101 to 14.111 show the regist ers associated with PWM mode, and Fi gures 14.112 and 14.113 show
the Operations of PWM Mode.
Figure 14.100 Block Diagram of PWM Mode
TRDIOBi
Output
control
TRDGRAi
TRDi
Compare match signal
TRDGRBi
TRDIOCi
TRDGRCi
TRDGRDi
TRDIODi
(Note 1)
(Note 2)
i = 0 or 1
NOTES:
1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the
buffer register of the TRDGRAi register).
2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the
buffer register of the TRDGRBi register).
Compare match signal
Compare match signal
Compare match signal
Comparator
Comparator
Comparator
Comparator
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 282 of 580
REJ09B0324-0200
i = 0 or 1
Table 14.42 PWM Mode Specifications
Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Count operations Increment
PWM waveform PWM period: 1/fk x (m+1)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
fk: Frequency of count source
m: Value set in the TRDGRAi (i = 0 or 1) register
n: Value set in the TRDGRji (j = B, C, or D) register
Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count
stops at the compare match in the TRDGRAi register.
The PWM output pin holds level after output change by compare
match.
Interrupt request generation
timing
• Compare match (The content of the TRDi register matches content of
the TRDGRji register.)
• TRDi register overflows
TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input
TRDIOA1 pin function Programmable I/O port
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOB1, TRDIOC1, TRDIOD1
pin functions
Programmable I/O port or pulse output (selectable by pin)
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer The count value can be read by reading the TRDi register.
Write to timer The value can be written to the TRDi register.
Select functions • 1 to 3 PWM output pins selected per 1 channel
Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
• The active level selected by pin.
• Initial output level selected by pin.
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output
Forced Cutoff.)
m+1
n+1 m-n (When “L” is selected as the active level)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 283 of 580
REJ09B0324-0200
Figure 14.101 MST CR Register
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 284 of 580
REJ09B0324-0200
Figure 14.102 Registers TRDSTR and TRDMR in PWM Mode
Timer RD Start Register(1)
Symbol Address After Reset
TRDSTR 0137h 11111100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
b3 b2
CSEL1
b1 b0
TSTA RT0
b7 b6 b5 b4
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
TSTA RT1 RW
TRD1 count start flag(5) 0 : Count stops(3)
1 : Count starts
TRD0 count start flag(4) 0 : Count stops(2)
1 : Count starts
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Ref er to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
TRD0 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
CSEL0 RW
RW
TRD1 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
—
—
(b7-b4)
Timer RD Mode Register
Symbol Address After Reset
TRDMR 0138h 00001110b
Bit Symbol Bit Name Function RW
RW
BFC1
BFD1 TRDGRD1 register function
select bit
0 : General register
1 : Buffer register of TRDGRB1 register
RW
TRDGRD0 register function
select bit
0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register function
select bit
0 : General register
1 : Buffer register of TRDGRA1 register RW
TRDGRC0 register function
select bit
0 : General register
1 : Buffer register of TRDGRA0 register
BFC0 RW
RW
—
(b3-b1) —
Timer RD synchronous bit 0 : Registers TRD0 and TRD1 operate
independently
1 : Registers TRD0 and TRD1 operate
synchronously
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b7 b6 b5 b4 b3 b2
BFD0
b1 b0
SYNC
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 285 of 580
REJ09B0324-0200
Figure 14.103 TRDPMR Register in PWM Mode
Timer RD PWM Mode Register
Symbol Address After Reset
TRDPMR 0139h 10001000b
Bit Symbol Bit Name Function RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWM mode of TRDIOC1 select bit 0 : Timer mode
1 : PWM mode
PWMD1 PWM mode of TRDIOD1 select bit 0 : Timer mode
1 : PWM mode
—
(b7) —
PWMB1
PWMC1 RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWM mode of TRDIOD0 select bit 0 : Timer mode
1 : PWM mode
PWMD0 RW
—
PWM mode of TRDIOB1 select bit 0 : Timer mode
1 : PWM mode
RW
RW
RW
PWMC0 RW
PWM mode of TRDIOB0 select bit 0 : Timer mode
1 : PWM mode
PWM mode of TRDIOC0 select bit 0 : Timer mode
1 : PWM mode
b7 b6 b5 b4 b3 b2
—
(b3)
b1 b0
PWMB0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 286 of 580
REJ09B0324-0200
Figure 14.104 TRDFCR Register in PWM Mode
Timer RD Function Control Register
Symbol Address After Reset
TRDFCR 013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b3 b2
OLS1
b1 b0
001
b7 b6 b5 b4
RW
CMD1 RW
Combination mode select bits(1) Set to 00b (timer mode, PWM mode, or
PWM3 mode) in PWM mode.
CMD0
Normal-phase output level select Bit
(in reset synchronous PWM mode or
c omplementar y PWM mode)
This bit is disabled in PWM mode.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level select bit
(in reset synchronous PWM mode or
c omplementar y PWM mode)
This bit is disabled in PWM mode.
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in PWM mode. RW
PWM3 RW
ADTRG
ADEG A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in PWM mode. RW
PWM3 mode select bit(2) Set this bit to 1 (other than PWM3 mode) in
PWM mode.
When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
STCLK External clock input select bit 0 : External clock input disabled
1 : External clock input enabled RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 287 of 580
REJ09B0324-0200
Figure 14.105 Registers TRDOER1 to TRDOER2 in PWM Mode
Timer RD Output Master Enable Register 1
Symbol Address After Reset
TRDOER1 013Bh FFh
Bit Symbol Bit Name Function RW
ED1 RW
EA 1
EB1 RW
TRDIOD1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
TRDIOB1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
EC1
RW
TRDIOA1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
RW
TRDIOD0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
TRDIOC1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
TRDIOC0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
EC0 RW
RW
EB0 RW
TRDIOA0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA0 pin is
used as a programmable I/O port.)
TRDIOB0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
b7 b6 b5 b4 b3 b2
ED0
b1 b0
EA 0
Timer RD Output Master Enable Register 2
Symbol Address Af ter Reset
TRDOER2 013Ch 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____ of pulse output forced 0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
applied to the INT0
_
____ pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
b3 b2 b1 b0
—
b7 b6 b5 b4
—
(b6-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWPTO
cutof f signal input enabled bit(1)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 288 of 580
REJ09B0324-0200
Figure 14.106 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
Timer RD Output Control Register(1)
Symbol Address After Reset
TRDOCR 013Dh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
TOA 1
TOB1 RW
TRDIOD1 initial output level select bit(2)
TRDIOB1 initial output level select bit(2)
TOC1 TRDIOC1 initial output level select bit(2)
0 : Initial output is inactive
level
1 : Initial output is active level
Set this bit to 0 (enable output) in
PWM mode.
Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
TOC0 RW
RW
TRDIOA1 initial output level select bit
RW
RW
0 : Inactive level
1 : Active level
TRDIOD0 initial output level select bit(2)
TOD1 RW
RW
TOB0 RW
TRDIOA0 output level select bit Set this bit to 0 (enable output) in
PWM mode.
TRDIOB0 output level select bit(2)
TRDIOC0 initial output level select bit(2)
TOA 0
b7 b6 b5 b4
0
If the pin function is set for w aveform output (refer to Tables 14.28 to 14.30 and Tables 14.32 to 14.34), the initial
output level is output w hen the TRDOCR register is set.
b3 b2
TOD0
b1 b0
0
Timer RD Control Register i (i = 0 or 1)
Symbol Address After Reset
TRDCR0
TRDCR1
0140h
0150h
00h
00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
RW
TCK1 RW
TCK0
RW
RW
RW
CCLR2
CCLR1 RW
Count source select bits b2 b1 b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input(1)
1 1 0 : fOCO40M
1 1 1 : Do not set.
External clock edge select bits(2) b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
b7 b6 b5 b4
001
b3 b2
CKEG0
b1 b0
TCK2
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
RW
CKEG1
CCLR0 RWSet to 001b (the TRDi register cleared at
compare match w ith TRDGRAi register) in PWM
mode.
TRDi counter clear select bits
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 289 of 580
REJ09B0324-0200
Figure 14.107 Registers TRDSR0 to TRDSR1 in PWM Mode
Timer RD Status Register i (i=0 or 1)
Symbol Address After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten.
b3 b2
IMFD
b1 b0b7 b6 b5 b4
RW
IMFB RW
Input capture/compare match
flag A
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
Input capture/compare match
flag B
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
IMFA
Input capture/compare match
flag C
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register(3).
Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
IMFC RW
RW
Input capture/compare match
flag D
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register(3).
Overf low flag [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWOVF
UDF Underflow f lag(1) This bit is disabled in PWM mode. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 290 of 580
REJ09B0324-0200
Figure 14.1 08 Register s TRDIER0 to TRDIER1 in PWM Mo de
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol Bit Name Function RW
b3 b2
IMIED
b1 b0b7 b6 b5 b4
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
IMIEC RW
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Overf low /underflow interrupt enable
bit
0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RWOVIE
—
(b7-b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 291 of 580
REJ09B0324-0200
Figure 14.1 09 Register s TRDPOCR0 to TRDPOCR1 in PWM Mode
Figure 14.110 Registers TRD0 to TRD1 in PWM Mode
Timer RD PWM Mode Output Level Control Register i (i = 0 or 1)
Symbol Address Af ter Reset
TRDPOCR0
TRDPOCR1
0145h
0155h
11111000b
11111000b
Bit Symbol Bit Name Function RW
b3 b2
—
(b7-b3)
b1 b0
POL D
b7 b6 b5 b4
RW
POL C RW
PWM mode output level control bit
B
0 : “L” active TRDIOBi output level is
selected
1 : “H” active TRDIOBi output level is
selected
PWM mode output level control bit
C
0 : “L” active TRDIOCi output level is
selected
1 : “H” active TRDIOCi output level is
selected
POL B
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWM mode output level control bit
D
0 : “L” active TRDIODi output level is
selected
1 : “H” active TRDIODi output level is
selected
RW
Timer RD Counter i (i = 0 or 1)(1)
Symbol Address After Reset
TRD0
TRD1
0147h-0146h
0157h-0156h
0000h
0000h
Setting Range RW
NOTE:
1.
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
0000h to FFFFh
RW
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
b0b7
(b8)
b0
(b15)
b7
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 292 of 580
REJ09B0324-0200
Figure 14.111 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM Mode
The following registers are disabled in the PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0,
TRDIORA1, and TRDIORC1.
i = 0 or 1
BFCi, BFDi: Bits in TRDMR register
Table 14.43 TRDGRji Register Functions in PWM Mode
Register Setting Register Function PWM Output Pin
TRDGRAi −General register. Set the PWM period −
TRDGRBi −General register. Set the changing point of PWM output TRDIOBi
TRDGRCi BFCi = 0 General register. Set the changing point of PWM output TRDIOCi
TRDGRDi BFDi = 0 TRDIODi
TRDGRCi BFCi = 1 Buffer register. Set the next PWM period
(Refer to 14.4.2 Buffer Operation.)
−
TRDGRDi BFDi = 1 Buffer register. Set the changing point of the next PWM
output
(Refer to 14.4.2 Buffer Operation.)
TRDIOBi
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
Symbol Address After Reset
TRDGRA 0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA 1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
(b8)
b0
(b15)
b7 b0b7
RW
Function
Ref er to Table 14.43 TRDGRji Register Function s in PWM Mod e.
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 293 of 580
REJ09B0324-0200
Figure 14.112 Operating Example of PWM Mode
m
n
p
Value in TRDi register
Count source
m+1
n+1
TRDIOCi output
q
m-n
p+1 m-p
m-qq+1
TRDIODi output
m: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
q: Value set in TRDGRDi register
Inactive level “L”
Active level “H”
Inactive level “H”
Active level “L”
Set to 0 by a program Set to 0 by a program
Set to 0 by a program
TRDIOBi output
IMFA bit in
TRDSRi register
1
0
IMFB bit in
TRDSRi register
1
0
IMFC bit in
TRDSRi register
1
0
IMFD bit in
TRDSRi register
1
0
i = 0 or 1
Set to 0 by a program
The above applies under the following conditions:
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (enable TRDIOBi, TRDIOCi and TRDIODi pin outputs).
Bits TOBi and TOCi in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1 (active level).
The POLB bit in the TRDPOCRi register is set to 1 (active level “H”), bits POLC and POLD are set to 0 (active level “L”).
Initial output “L”
to compare match
Initial output “H”
to compare match
Initial output “L”
to compare match
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 294 of 580
REJ09B0324-0200
Figure 14.113 Operating Example of PWM Mode (Duty 0%, Du ty 100%)
m
p
q
Value in TRDi register
n
m: Value set in TRDGRAi register
Set to 0 by a program
Rewrite by a program
0000h
q
Duty 0%
TRDGRBi register
IMFA bit in
TRDSRi register
1
0
IMFB bit in
TRDSRi register
1
0
TSTARTi bit in
TRDSTR register
TRDIOBi output
p (p>m)n
Since no compare match in the TRDGRBi register is
generated, “L” is not applied to the TRDIOBi output
1
0
m
p
Value in TRDi register
n
0000h
TRDGRBi register
IMFA bit in
TRDSRi register
1
0
IMFB bit in
TRDSRi register
1
0
TSTARTi bit in
TRDSTR register
TRDIOBi output
pn
1
0
“L” is applied to TRDIOBi output at compare match
with the TRDGRBi register with no change.
m
i = 0 or 1
The above applies under the following conditions:
The EBi bit in the TRDOER1 register is set to 0 (enable TRDIOBi output).
The POLB bit in the TRDPOCRi register is set to 0 (active level “L”).
Rewrite by a program
Set to 0 by a program
Set to 0 by a program
When compare matches with registers TRDGRAi and TRDGRBi are generated
simultaneously, the compare match with the TRDGRBi register has priority.
“L” is applied to the TRDIOBi output without any change.
Duty 100%
Set to 0 by a program
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 295 of 580
REJ09B0324-0200
14.4.8 Reset Synchronous PWM Mode
In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period
(three-phase, sawtooth wave modulation, and no dead time).
Figure 14.114 shows a Block Diagram o f Reset Synchronous PWM Mode, and Table 14.44 lists the Reset
Synchronous PWM Mode Specifications. Figures 14.115 to 14.123 show the registe rs associated with reset
synchronous PWM mode and Figure 14.124 shows an Operat ing Exam ple of Reset Synchron ous PWM Mode.
Refer to Figure 14.113 Operating Example of PWM Mode (Duty 0%, Duty 100%) for an operating
example of PWM Mode with duty 0% and duty 100%.
Figure 14.114 Block Diagram of Reset Synchronous PWM Mode
Period TRDIOC0
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
PWM1
PWM2
PWM3
Waveform control
TRDGRB0
register
TRDGRA1
register
TRDGRB1
register
Normal-phase
Counter-phase
TRDGRA0
register
TRDGRD0
register
TRDGRC1
register
TRDGRD1
register
TRDGRC0
register
Buffer(1)
Normal-phase
Counter-phase
Normal-phase
Counter-phase
NOTE:
1.When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 296 of 580
REJ09B0324-0200
j = either A, B, C, or D
Table 14.44 Reset Synchronous PWM Mode Specifications
Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Count operations The TRD0 register is incremented (the TRD1 register is not used).
PWM waveform PWM period : 1/fk × (m+1)
Active level width of normal-phase : 1/fk × (m-n)
Active level width of counter-phase: 1/fk × (n+1)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output),
Value set in the TRDGRA1 register (PWM2 output),
Value set in the TRDGRB1 register (PWM3 output)
Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
stops at the compare match in the TRDGRA0 register.
The PWM output pin holds level after output change at compare
match.
Interrupt request generation
timing
• Compare match (the content of the TRD0 register matches content
of registers TRDGRj0, TRDGRA1, and TRDGRB1).
• The TRD0 register overflows
TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input
TRDIOB0 pin function PWM1 output normal-phase output
TRDIOD0 pin function PWM1 output counter-phase output
TRDIOA1 pin function PWM2 output normal-phase output
TRDIOC1 pin function PWM2 output counter-phase output
TRDIOB1 pin function PWM3 output normal-phase output
TRDIOD1 pin function PWM3 output counter-phase output
TRDIOC0 pin function Output inverted every PWM period
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
Read from timer The count value can be read by reading the TRD0 register.
Write to timer The value can be written to the TRD0 register.
Select functions • The active level of normal-phase and counter-phase and initial
output level selected individually.
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse
Output Forced Cutoff.)
m+1
Normal-phase
n+1 (When “L” is selected as the active level)
Counter-phase
m-n
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 297 of 580
REJ09B0324-0200
Figure 14.115 MST C R Regi st e r
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 298 of 580
REJ09B0324-0200
Figure 14.116 Registers TRDSTR and TRDMR in Reset Synchronous PWM Mode
Timer RD Start Register(1)
Symbol Address After Reset
TRDSTR 0137h 11111100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
b3 b2
CSEL1
b1 b0
TSTA RT0
b7 b6 b5 b4
RW
TSTA RT1 RW
TRD1 count start flag(5) 0 : Count stops(3)
1 : Count starts
TRD0 count start flag(4) 0 : Count stops(2)
1 : Count starts
TRD0 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
CSEL0 RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Timer RD.
RW
TRD1 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
—
Timer RD Mode Register
Symbol Address After Reset
TRDMR 0138h 00001110b
Bit Symbol Bit Name Function RW
b3 b2
BFD0
b1 b0
0
SYNC
b7 b6 b5 b4
RW
—
(b3-b1) —
Timer RD synchronous bit Set this bit to 0 (registers TRD0 and TRD1
operate independently) in reset synchronous
PWM mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
TRDGRD0 register function select
bit
0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register function select
bit
0 : General register
1 : Buffer register of TRDGRA1 register RW
TRDGRC0 register function select
bit
0 : General register
1 : Buffer register of TRDGRA0 register
BFC0 RW
RW
BFC1
BFD1 TRDGRD1 register function select
bit
0 : General register
1 : Buffer register of TRDGRB1 register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 299 of 580
REJ09B0324-0200
Figure 14.117 TRDFCR Register in Reset Synchronous PWM Mode
Timer RD Function Control Register
Symbol Address After Reset
TRDFCR 013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or
complementary PWM mode in spite of the setting of the TRDPMR register.
STCLK External clock input select bit 0 : External clock input disabled
1 : External clock input enabled RW
RW
PWM3 RW
ADTRG
ADEG A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in reset synchronous
PWM mod e. RW
PWM3 mode s ele c t bit(3) This bit is disabled in reset synchronous
PWM mod e.
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
0 : Initial output “H”
Active level “L”
1 : Initial output “L”
Active level “H”
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
0 : Initial output “H”
Active level “L”
1 : Initial output “L”
Active level “H”
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in reset synchronous
PWM mod e.
RW
CMD1 RW
Combination mode select bits(1, 2) Set to 01b (reset synchronous PWM
mode) in reset synchronous PWM mode.
CMD0
b7 b6 b5 b4
When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
OLS1
b1 b0
01
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 300 of 580
REJ09B0324-0200
Figure 14.118 Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode
Timer RD Output Master Enable Register 1
Symbol Address After Reset
TRDOER1 013Bh FFh
Bit Symbol Bit Name Function RW
ED1 RW
EA 1
EB1 RW
TRDIOD1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
TRDIOB1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
EC1
RW
TRDIOA1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
RW
TRDIOD0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
TRDIOC1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
TRDIOC0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
EC0 RW
RW
EB0 RW
TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is
used as a programmable I/O port) in reset
synchronous PWM mode.
TRDIOB0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
b7 b6 b5 b4 b3 b2
ED0
b1 b0
1
EA 0
Timer RD Output Master Enable Register 2
Symbol Address Af ter Reset
TRDOER2 013Ch 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____ of pulse output forced 0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
applied to the INT0
_
____ pin.)
NOTE:
1.
b3 b2 b1 b0b7 b6 b5 b4
Ref er to 14.4.4 Pulse Output Forced Cutoff.
—
—
(b6-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWPTO
cutof f signal input enabled bit(1)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 301 of 580
REJ09B0324-0200
Figure 14.119 TRDCR0 Register in Reset Synchronous PWM Mode
Timer RD Control Register 0(3)
Symbol Address After Reset
TRDCR0 0140h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
RW
TCK1 RW
TCK0
RW
RW
RW
CCLR2
CCLR1 RW
Count source select bits b2 b1b0
0 0 0 : f 1
0 0 1 : f 2
0 1 0 : f 4
0 1 1 : f 8
1 0 0 : f 32
1 0 1 : TRDCLK input(1)
1 1 0 : f OCO40M
1 1 1 : Do not set.
External clock edge select bits(2) b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
b7 b6 b5 b4
001
b3 b2
CKEG0
b1 b0
TCK2
The TRDCR1 register is not used in reset synchronous PWM mode.
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
RW
CKEG1
CCLR0 RWSet to 001b (TRD0 register cleared at compare
match w ith TRDGRA0 register) in reset
synchronous PWM mode.
TRD0 counter clear select bits
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 302 of 580
REJ09B0324-0200
Figure 14.120 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode
Timer RD Status Register i (i = 0 or 1)
Symbol Address After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
• This bit remains unchanged if 1 is w ritten to it.
b3 b2
IMFD
b1 b0b7 b6 b5 b4
RW
IMFB RW
Input capture/compare match
flag A
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
Input capture/compare match
flag B
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
IMFA
Input capture/compare match
flag C
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register(3).
Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
IMFC RW
RW
Input capture/compare match
flag D
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register(3).
Overf low flag [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWOVF
UDF Underflow f lag(1) This bit is disabled in reset synchronous PWM
mode. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 303 of 580
REJ09B0324-0200
Figure 14.121 Registers TRDIER0 to TRDIER1 in Reset Synchronous PWM Mode
Figure 14.122 TRD0 Registrar in Reset Synchronous PWM Mode
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol Bit Name Function RW
RWOVIE
—
(b7-b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Overf low /underflow interrupt enable
bit
0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
IMIEC RW
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
b7 b6 b5 b4 b3 b2
IMIED
b1 b0
Timer RD Counter 0(1, 2)
Symbol Address After Reset
TRD0 0147h-0146h 0000h
Setting Range RW
NOTES:
1.
2.
(b8)
b0
(b15)
b7 b0b7
The TRD1 register is not used in reset synchronous PWM mode.
Function
Count a count source. Count operation is incremented.
When an overf low occurs, the OVF bit in the TRDSR0 register is set to 1.
0000h to FFFFh
RW
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 304 of 580
REJ09B0324-0200
Figure 14 .1 23
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Reset Synchronous PWM Mode
The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Table 14.45 TRDGRji Register Functions in Reset Synchronous PWM Mode
Register Setting Register Function PWM Output Pin
TRDGRA0 −General register. Set the PWM period. (Output inverted every PWM
period and TRDIOC0 pin)
TRDGRB0 −General register. Set the changing point of
PWM1 output.
TRDIOB0
TRDIOD0
TRDGRC0 BFC0 = 0 (These registers are not used in reset
synchronous PWM mode.)
−
TRDGRD0 BFD0 = 0
TRDGRA1 −General register. Set the changing point of
PWM2 output.
TRDIOA1
TRDIOC1
TRDGRB1 −General register. Set the changing point of
PWM3 output.
TRDIOB1
TRDIOD1
TRDGRC1 BFC1 = 0 (These points are not used in reset
synchronous PWM mode.)
−
TRDGRD1 BFD1 = 0
TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period.
(Refer to 14.4.2 Buffer Operation.)
(Output inversed every PWM
period and TRDIOC0 pin)
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of
the next PWM1 output.
(Refer to 14.4.2 Buffer Operation.)
TRDIOB0
TRDIOD0
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of
the next PWM2 output.
(Refer to 14.4.2 Buffer Operation.)
TRDIOA1
TRDIOC1
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of
the next PWM3 output.
(Refer to 14.4.2 Buffer Operation.)
TRDIOB1
TRDIOD1
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
Symbol Address After Reset
TRDGRA 0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA 1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
(b8)
b0
(b15)
b7 b0b7
RW
Function
Ref er to Ta ble 14.45 TRDGRji Regi ster Func tions in Reset Synchronous PWM Mode.
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 305 of 580
REJ09B0324-0200
Figure 14.124 Operating Example of Reset Synchronous PWM Mode
Initial output “H”
Active level “L”
m
n
p
Value in TRD0 register
Count source
m+1
TRDIOD0 output
q
m-n
TRDIOD1 output
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRDGRA1 register
q: Value set in TRDGRB1 register
Active level “L”
Set to 0 by a program
TRDIOB0 output
IMFA bit in
TRDSR0 register
1
0
IMFB bit in
TRDSR0 register
1
0
IMFA bit in
TRDSR1 register
1
0
IMFB bit in
TRDSR1 register
1
0
TSTARTi bit in
TRDSTR register
1
0
n+1
TRDIOC1 output
TRDIOA1 output
m-q
m-p
TRDIOB1 output
TRDIOC0 output
p+1
Initial output “H”
i = 0 or 1
The above applies under the following conditions:
Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output level “H”, active level “L”).
0000h
Set to 0 by a program
Set to 0 by a program Set to 0 by a program
Transfer from the buffer register to the
general register during buffer operation
Transfer from the buffer register to the
general register during buffer operation
q+1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 306 of 580
REJ09B0324-0200
14.4.9 Complementary PWM Mode
In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period
(three-phase, triangular wave modulation, and with dead time).
Figure 14.125 shows a Block Diagram of Complementary PWM Mode, and Table 14.46 lists the
Complementary PWM Mode Specifications. Figures 14.126 to 14.135 show the Registers Associated with
Complementary PWM Mode, Figure 14.136 shows Output Model of Complementary PWM Mode and Figure
14.137 shows Operating Example of Complementary PWM Mode.
Figure 14.125 Block Diagram of Complementary PWM Mode
Period TRDIOC0
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
PWM1
PWM2
PWM3
Waveform control
TRDGRB0
register
TRDGRA1
register
TRDGRB1
register
Normal-phase
Counter-phase
TRDGRA0
register
TRDGRD0
register
TRDGRC1
register
TRDGRD1
register
Buffer
Normal-phase
Counter-phase
Normal-phase
Counter-phase
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 307 of 580
REJ09B0324-0200
i = 0 or 1, j = either A, B, C, or D
NOTE:
1. After a count starts, the PWM period is fixed.
Table 14.46 Complementary PWM Mode Specifications
Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count
source) as bits TCK2 to TCK0 in the TRDCR0 register.
Count operations Increment or decrement
Registers TRD0 and TRD1 are decremented with the compare match in registers
TRD0 and TRDGRA0 during increment operation. The TRD1 register value is
changed from 0000h to FFFFh during decrement operation, and registers TRD0 and
TRD1 are incremented.
PWM operations PWM period: 1/fk × (m+2-p) × 2(1)
Dead time: p
Active level width of normal-phase: 1/fk × (m-n-p+1) × 2
Active level width of counter-phase: 1/fk × (n+1-p) × 2
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output)
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
p: Value set in the TRD0 register
Count start condition 1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.
Count stop conditions 0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
(The PWM output pin holds output level before the count stops.)
Interrupt request generation
timing
• Compare match (The content of the TRDi register matches content of the TRDGRji
register.)
• The TRD1 register underflows
TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input
TRDIOB0 pin function PWM1 output normal-phase output
TRDIOD0 pin function PWM1 output counter-phase output
TRDIOA1 pin function PWM2 output normal-phase output
TRDIOC1 pin function PWM2 output counter-phase output
TRDIOB1 pin function PWM3 output normal-phase output
TRDIOD1 pin function PWM3 output counter-phase output
TRDIOC0 pin function Output inverted every 1/2 period of PWM
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input
Read from timer The count value can be read by reading the TRDi register.
Write to timer The value can be written to the TRDi register.
Select functions • Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output Forced
Cutoff.)
• The active level of normal-phase and counter-phase and initial output level
selected individually
• Transfer timing from the buffer register selected
• A/D trigger generated
n+1
Normal-phase
(When “L” is selected as the active level)
Counter-phase
m+2-p
n+1-p pm-p-n+1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 308 of 580
REJ09B0324-0200
Figure 14.126 MST CR Register
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 309 of 580
REJ09B0324-0200
Figure 14.127 TRDSTR Register in Complementary PWM Mode
Timer RD Start Register(1)
Symbol Address After Reset
TRDSTR 0137h 11111100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
b3 b2
CSEL1
b1 b0
TSTA RT0
b7 b6 b5 b4
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
TSTA RT1 RW
TRD1 count start flag(5) 0 : Count stops(3)
1 : Count starts
TRD0 count start flag(4) 0 : Count stops(2)
1 : Count starts
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Ref er to 14.4.12.1
TRDSTR Register of Notes on Timer RD.
TRD0 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
CSEL0 RW
RW
TRD1 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
—
—
(b7-b4)
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 310 of 580
REJ09B0324-0200
Figure 14.128 TRDMR Register in Complementary PWM Mode
Timer RD Mode Register
Symbol Address After Reset
TRDMR 0138h 00001110b
Bit Symbol Bit Name Function RW
b3 b2
BFD0
b1 b0
0
SYNC
b7 b6 b5 b4
0
RW
—
(b3-b1) —
Timer RD synchronous bit Set this bit to 0 (registers TRD0 and TRD1
operate independently) in complementary
PWM mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDGRC0 register f unction select bit Set this bit to 0 (general register) in
c omplementar y PWM mode .
BFC0 RW
RW
TRDGRD0 register f unction select bit 0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register f unction select bit 0 : General register
1 : Buffer register of TRDGRA1 register RWBFC1
BFD1
TRDGRD1 register f unction select bit 0 : General register
1 : Buffer register of TRDGRB1 register RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 311 of 580
REJ09B0324-0200
Figure 14.129 TRDFCR Register in Complementary PWM Mode
Timer RD Function Control Register
Symbol Address After Reset
TRDFCR 013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
OLS1
b1 b0b7 b6 b5 b4
RW
CMD1 RW
Combination mode select bits(1,2) b1 b0
1 0 : Complementary PWM mode
(transfer f rom the
buffer register to the general
register at the underflow in
the TRD1 register)
1 1 : Complementary PWM mode
(transfer f rom the
buffer register to the general
register at the compare match w ith
registers TRD0 and TRDGRA0.)
Other than above : Do not set.
CMD0
Normal-phase output level select bit
(in reset synchronous PWM mode or
c omplementar y PWM mod e)
0 : Initial output “H”
Active level “L”
1 : Initial output “L”
Active level “H”
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level select bit
(in reset synchronous PWM mode or
c omplementar y PWM mod e)
0 : Initial output “H”
Active level “L”
1 : Initial output “L”
Active level “H”
A/D trigger enable bit
(in complementary PWM mode)
0 : Disable A/D trigger
1 : Enable A/D trigger(3) RW
PWM3 RW
ADTRG
ADEG
A/D trigger edge select bit
(in complementary PWM mode)
0 : A/D trigger is generated at
compare match betw een registers
TRD0 and TRDGRA0
1 : A/D trigger is generated at underflow
in the TRD1 register
RW
PWM3 mode select bit(4) This bit is disabled in complementary PWM
mode.
Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).
When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of
the TRDPMR register.
STCLK External clock input select bit 0 : External clock input disabled
1 : External clock input enabled RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 312 of 580
REJ09B0324-0200
Figure 14.130 Registe rs T RDO ER1 to TR DOE R 2 in Comp le me ntary PWM Mode
Timer RD Output Master Enable Register 1
Symbol Address After Reset
TRDOER1 013Bh FFh
Bit Symbol Bit Name Function RW
b3 b2
ED0
b1 b0
1
EA 0
b7 b6 b5 b4
RW
EB0 RW
TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is
used as a programmable I/O port) in
c omplementar y PWM mode.
TRDIOB0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
TRDIOC0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
EC0 RW
RW
TRDIOA1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
RW
TRDIOD0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
ED1 RW
EA 1
EB1 RW
TRDIOD1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
TRDIOB1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
EC1
TRDIOC1 output disable bit 0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
Timer RD Output Master Enable Register 2
Symbol Address Af ter Reset
TRDOER2 013Ch 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____ of pulse output forced 0 : Pulse output forced cutoff input disabled
cutof f signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
applied to the INT0
_
____ pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
b3 b2 b1 b0
—
b7 b6 b5 b4
—
(b6-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWPTO
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 313 of 580
REJ09B0324-0200
Figure 14.131 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode
Timer RD Control Register i (i = 0 or 1)
Symbol Address Af ter Reset
TRDCR0
TRDCR1
0140h
0150h
00h
00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
RW
TCK1 RW
TCK0
RW
RW
RW
CCLR2
CCLR1 RW
Count source select bits(2) b2 b1 b0
0 0 0 : f 1
0 0 1 : f 2
0 1 0 : f 4
0 1 1 : f 8
1 0 0 : f 32
1 0 1 : TRDCLK input(1)
1 1 0 : f OCO40M
1 1 1 : Do not set.
External clock edge select bits(2,3) b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
b7 b6 b5 b4
000
b3 b2
CKEG0
b1 b0
TCK2
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
RW
CKEG1
CCLR0 RW
Set to 000b (disable clearing (free-running
operation)) in complementary PWM mode.
TRDi counter clear select bits
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 314 of 580
REJ09B0324-0200
Figure 14.132 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode
Timer RD Status Register i (i = 0 or 1)
Symbol Address After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
• This bit remains unchanged if 1 is w ritten to it.
RWOVF
UDF
Underflow f lag(1) [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRD1 register underflow s.
RW
Input capture/compare match flag C [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRCi
register(3).
Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
IMFC RW
RW
Input capture/compare match flag D [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRDi
register(3).
Overf low flag [Source f or setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
RW
IMFB RW
Input capture/compare match flag A [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRAi
register.
Input capture/compare match flag B [Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRBi
register.
IMFA
b7 b6 b5 b4 b3 b2
IMFD
b1 b0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 315 of 580
REJ09B0324-0200
Figure 14.1 33 Registe r s TRDIER0 to TRDIER1 in Complementary PWM Mode
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol Bit Name Function RW
b3 b2
IMIED
b1 b0b7 b6 b5 b4
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
IMIEC RW
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Overf low /underflow interrupt enable
bit
0 : Disable interrupt (OVI) by the
OVF and UDF bits
1 : Enable interrupt (OVI) by the
OVF and UDF bits
RWOVIE
—
(b7-b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 316 of 580
REJ09B0324-0200
Figure 14.134 Registers TRD0 to TRD1 in Complementary PWM Mode
Figure 14.135 Registers TRDGRAi, TRDGRBi, TRDGRC1, and TRDGRDi in Complementary PWM Mode
The following registers are dis abled in the complementary PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
Timer RD Counter 0(1)
Symbol Address After Reset
TRD0 0147h-0146h 0000h
Setting Range RW
NOTE:
1.
(b8)
b0
(b15)
b7
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
b0b7
Function
Set the dead time.
Count a count source. Count operation is incremented or decremented.
When an overf low occurs, the OVF bit in the TRDSR0 register is set to 1.
0000h to FFFFh
RW
Timer RD Counter 1(1)
Symbol Address After Reset
TRD1 0157h-0156h 0000h
Setting Range RW
NOTE:
1.
Function
Select 0000h.
Count a count source. Count operation is incremented or decremented.
When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1.
0000h to FFFFh
RW
Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
b0b7
(b8)
b0
(b15)
b7
Timer RD General Registers Ai, Bi, C1, and Di (i = 0 or 1)(1, 2)
Symbol Address After Reset
TRDGRA 0
TRDGRB0
TRDGRD0
TRDGRA 1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTES:
1.
2.
(b8)
b0
(b15)
b7 b0b7
The TRDGRC0 register is not used in complementary PWM mode.
RW
Function
Ref er to Table 14.47 TRDGRji Register Functions in Complementary PW M Mode.
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 317 of 580
REJ09B0324-0200
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count
operation starts (prohibited item), use the TRDGRD0, TRDGRC 1, or TRDGRD1 register as a buffer register.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1
to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
Table 14.47 TRDGRji Register Functions in Complementary PWM Mode
Register Setting Register Function PWM Output Pin
TRDGRA0 −General register. Set the PWM period at initialization.
Setting range: Setting value or above in TRD0 register
FFFFh - TRD0 register setting value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
(Output inverted every half
period of TRDIOC0 pin)
TRDGRB0 −General register. Set the changing point of PWM1 output at
initialization.
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDIOB0
TRDIOD0
TRDGRA1 −General register. Set the changing point of PWM2 output at
initialization.
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDIOA1
TRDIOC1
TRDGRB1 −General register. Set the changing point of PWM3 output at
initialization.
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDIOB1
TRDIOD1
TRDGRC0 −This register is not used in complementary PWM mode. −
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM1 output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Set this register to the same value as the TRDGRB0 register
for initialization.
TRDIOB0
TRDIOD0
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM2 output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Set this register to the same value as the TRDGRA1 register
for initialization.
TRDIOA1
TRDIOC1
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM3 output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Set this register to the same value as the TRDGRB1 register
for initialization.
TRDIOB1
TRDIOD1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 318 of 580
REJ09B0324-0200
Figure 14.136 Output Model of Complementary PWM Mode
Value in TRDi register
TRDIOD0 output
0000h
Value in TRDGRA0
register
Value in TRDGRB0
register
Value in TRDGRA1
register
Value in TRDGRB1
register
TRDIOB0 output
TRDIOC1 output
TRDIOA1 output
TRDIOD1 output
TRDIOB1 output
TRDIOC0 output
Value in TRD0 register
Value in TRD1 register
i = 0 or 1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 319 of 580
REJ09B0324-0200
Figure 14.137 Operating Example of Complementary PWM Mode
m+2-p
p
n+1
n+1-p pn+1-p
n
n
n
m-p-n+1
m
n
Value in TRDi register
Count source
TRDIOD0 output
p
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRD0 register
TRDIOB0 output
IMFA bit in
TRDSR0 register
1
0
TRDGRB0 register
Bits TSTART0 and TSTART1
in TRDSTR register
1
0
TRDIOC0 output
0000h
m+1
(m-p-n+1) × 2
Width of normal-
phase active level
Dead
time
(n+1-p) × 2
Width of counter-phase active level
Set to
FFFFh
1
0
UDF bit in
TRDSR1 register
1
0
Following data
Modify with a program
TRDGRD0 register
Transfer (when bits CMD1 to CMD0 are set to 11b) Transfer (when bits CMD1 to CMD0
are set to 10b)
Value in TRD1 register
Value in TRD0 register
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
The above applies under the following conditions:
Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)
Set to 0 by a program
Active level “L”
Initial output “H”
Initial output “H”
Set to 0 by a program
Set to 0 by a program
IMFB bit in
TRDSR0 register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 320 of 580
REJ09B0324-0200
14.4.9.1 Transfer Timing from Buffer Register
• Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or
TRDGRB1 register.
When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the
TRD1 register underflows.
When bits CMD1 to CMD0 are set to 11b, the content is transferred at compare match between registers
TRD0 and TRDGRA0.
14.4.9.2 A/D Trigger Generation
Compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion
start trigger of the A/D converter. The trigger is selected by bits ADEG and ADTRG in the TRDFCR register.
Also, set the ADCAP bit in the ADCON0 register to 1 (starts by timer RD).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 321 of 580
REJ09B0324-0200
14.4.10 PWM3 Mode
In this mode, 2 PWM waveforms are output with the same period.
Figure 14.138 shows a Block D iagram of PW M3 Mode, and Table 14.48 lists the PWM3 Mode Specifications.
Figures 14.13 9 to 14 .14 9 sh ow the re g iste rs as so cia ted with PWM3 mode, an d Figure 14.150 shows an Operating
Example of PWM3 Mode.
Figure 14.138 Block Diagram of PWM3 Mode
TRDIOA0 Output
control
TRDGRC0
Compare match signal
TRDIOB0 Output
control
Comparator TRDGRA0
TRD0
TRDGRC1
Compare match signal
Comparator TRDGRA1
TRDGRD0
Comparator TRDGRB0
TRDGRD1
Comparator TRDGRB1
Compare match signal
Compare match signal
Buffer
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 322 of 580
REJ09B0324-0200
i = 0 or 1, j = either A, B, C, or D
Table 14.48 PWM3 Mode Specific at io n s
Item Specification
Count sources f1, f2, f4, f8, f32, fOCO40M
Count operations The TRD0 register is incremented (the TRD1 is not used).
PWM waveform PWM period: 1/fk × (m+1)
Active level width of TRDIOA0 output: 1/fk × (m-n)
Active level width of TRDIOB0 output: 1/fk × (p-q)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
stops at compare match with the TRDGRA0 register.
The PWM output pin holds level after output change by compare
match.
Interrupt request generation
timing
• Compare match (The content of the TRDi register matches content
of the TRDGRji register.)
• The TRD0 register overflows
TRDIOA0, TRDIOB0 pin
functions
PWM output
TRDIOC0, TRDIOD0, TRDIOA1
to TRDIOD1 pin functions
Programmable I/O port
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
Read from timer The count value can be read by reading the TRD0 register.
Write to timer The value can be written to the TRD0 register.
Select functions • Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse
Output Forced Cutoff.)
• Buffer Operation (Refer to 14.4.2 Buffer Operation.)
• Active level selectable by pin
m+1
TRDIOA0 output
TRDIOB0 output
(When “H” is selected as the active level)
p-q
m-n
n+1
p+1
q+1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 323 of 580
REJ09B0324-0200
Figure 14.139 MST CR Register
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 324 of 580
REJ09B0324-0200
Figure 14.140 TRDSTR Register in PWM3 Mode
Timer RD Start Register(1)
Symbol Address Af ter Reset
TRDSTR 0137h 11111100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Timer RD.
RW
TRD1 count operation select bit
[this bit is not used in PWM3 mode]
0 : Count stops at the compare match
w ith the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
—
TRD0 count operation select bit 0 : Count stops at the compare match
w ith the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
CSEL0 RW
RW
TSTA RT1 RW
TRD1 count start flag(5) 0 : Count stops(3)
1 : Count starts
TRD0 count start flag(4) 0 : Count stops(2)
1 : Count starts
b7 b6 b5 b4 b3 b2
CSEL1
b1 b0
TSTA RT0
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 325 of 580
REJ09B0324-0200
Figure 14.141 TRDMR Register in PWM3 Mode
Timer RD Mode Register
Symbol Address Af ter Reset
TRDMR 0138h 00001110b
Bit Symbol Bit Name Function RW
RW
BFC1
BFD1 TRDGRD1 register function select
bit
0 : General register
1 : Buffer register of TRDGRB1 register
TRDGRC0 register function select
bit
0 : General register
1 : Buffer register of TRDGRA0 register
BFC0 RW
RW
TRDGRD0 register function select
bit
0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register function select
bit
0 : General register
1 : Buffer register of TRDGRA1 register RW
RW
—
(b3-b1) —
Timer RD synchronous bit Set this bit to 0 (TRD0 and TRD1 operate
independently) in PWM3 mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b7 b6 b5 b4 b3 b2
BFD0
b1 b0
SYNC
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 326 of 580
REJ09B0324-0200
Figure 14.142 TRDFCR Register in PWM3 Mode
Timer RD Function Control Register
Symbol Address Af ter Reset
TRDFCR 013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
OLS1
b1 b0
0000
b7 b6 b5 b4
RW
CMD1 RW
Combination mode select bits(1) Set to 00b (timer mode, PWM mode, or
PWM3 mo de) in PWM3 mode.
CMD0
Normal-phase output level select bit
(enabled in reset synchronous PWM
mode or complementary PWM mode)
This bit is disabled in PWM3 mode.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level select bit
(enabled in reset synchronous PWM
mode or complementary PWM mode)
This bit is disabled in PWM3 mode.
A/D trigger enable bit
(enabled in complementary PWM mode)
This bit is disabled in PWM3 mode.
RW
PWM3 RW
ADTRG
ADEG
A/D trigger edge select bit
(enabled in complementary PWM mode)
This bit is disabled in PWM3 mode.
RW
PWM3 mode select bit(2) Set this bit to 0 (PWM3 mode) in PWM3
mode.
STCLK External clock input select bit Set this bit to 0 (external clock input
disabled) in PWM3 mode. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 327 of 580
REJ09B0324-0200
Figure 14.143 Registers TRDOER1 to TRDOER2 in PWM3 Mode
Timer RD Output Master Enable Register 1
Symbol Address After Reset
TRDOER1 013Bh FFh
Bit Symbol Bit Name Function RW
ED1 RW
EA 1
EB1 RW
TRDIOD1 output disable bit
TRDIOB1 output disable bit
EC1 TRDIOC1 output disable bit
TRDIOD0 output disable bit RW
TRDIOA1 output disable bit
RW
RW
Set these bits to 1 (programmable I/O port)
in PWM3 mode.
TRDIOC0 output disable bitEC0 RW
RW
EB0 RW
TRDIOA0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOA0 pin is
used as a programmable I/O port.)
TRDIOB0 output disable bit 0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
1111
b7 b6 b5 b4 b3 b2
ED0
b1 b0
11
EA 0
Timer RD Output Master Enable Register 2
Symbol Address Af ter Reset
TRDOER2 013Ch 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____ of pulse output forced 0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
applied to the INT0
_
____ pin.)
NOTE:
1.
b3 b2 b1 b0b7 b6 b5 b4
Ref er to 14.4.4 Pulse Output Forced Cutoff.
—
—
(b6-b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RWPTO
cutof f signal input enabled
bit(1)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 328 of 580
REJ09B0324-0200
Figure 14.144 TRDOCR Register in PWM3 Mode
Timer RD Output Control Register(1)
Symbol Address After Reset
TRDOCR 013Dh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2. If the pin function is set for w aveform output (ref er to Tables 14.27 and 14.28), the initial output level is output w hen
the TRDOCR register is set.
TOA 1
TOB1 RW
TRDIOD1 initial output level
select bit
TRDIOB1 initial output level
select bit
TOC1 TRDIOC1 initial output level
select bit
These bits are disabled in PWM3 mode.TRDIOC0 initial output level
select bit
Write to the TRDOCR register w hen both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0 (count
stops).
TOC0 RW
RW
TRDIOA1 initial output level
select bit
RW
RW
TRDIOD0 initial output level
select bit
TOD1 RW
RW
TOB0 RW
TRDIOA0 output level select
bit(2)
0 : Active level “H”,
initial output “L”,
output “H” at compare match w ith the
TRDGRA1register,
output “L” at compare match w ith the
TRDGRA0 register
1 : Active level “L”,
initial output “H”,
output “L” at compare match w ith the
TRDGRA1register,
output “H” at compare match w ith the
TRDGRA0 register
TRDIOB0 output level select
bit(2)
0 : Active level “H”,
initial output “L”,
output “H” at compare match w ith the
TRDGRB1register,
output “L” at compare match w ith the
TRDGRB0 register
1 : Active level “L”,
initial output “H”,
output “L” at compare match w ith the
TRDGRB1register,
output “H” at compare match w ith the
TRDGRB0 register
b7 b6 b5 b4 b3 b2
TOD0
b1 b0
TOA 0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 329 of 580
REJ09B0324-0200
Figure 14.145 TRDCR0 Register in PWM3 Mode
Timer RD Control Register 0(2)
Symbol Address After Reset
TRDCR0 0140h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2. The TRDCR1 register is not used in PWM3 mode.
RW
TCK1 RW
TCK0
RW
RW
RW
CCLR2
CCLR1
Count source select bits b2 b1b0
0 0 0 : f 1
0 0 1 : f 2
0 1 0 : f 4
0 1 1 : f 8
1 0 0 : f 32
1 0 1 : Do not set.
1 1 0 : f OCO40M
1 1 1 : Do not set.
External clock edge select bits(1) These bits are disabled in PWM3 mode.
b7 b6 b5 b4
001
b3 b2
CKEG0
b1 b0
TCK2
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
RW
CKEG1
CCLR0 RWSet to 001b (the TRD0 register cleared at
compare match w ith TRDGRA0 register) in
PWM3 mode.
TRD0 counter clear select bits
RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 330 of 580
REJ09B0324-0200
Figure 14.146 Registers TRDSR0 to TRDSR1 in PWM3 Mode
Timer RD Status Register i (i = 0 or 1)
Symbol Address After Reset
TRDSR0 0143h 11100000b
TRDSR1 0153h 11000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
• This bit remains unchanged if 1 is w ritten to it.
RW
RW
Input capture/compare match flag D [Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRDi
register(2).
OVF
Input capture/compare match flag C [Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRCi
register(2).
IMFC
Overf low flag [Source f or setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the TRDi register overflow s.
RW
IMFB RW
Input capture/compare match flag A [Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRAi
register.
Input capture/compare match flag B [Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRBi
register.
IMFA
RW
b7 b6 b5 b4 b3 b2
IMFD
b1 b0
UDF Underflow f lag(1) This bit is disabled in PWM3 mode. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 331 of 580
REJ09B0324-0200
Figure 14.147 Registers TRDIER0 to TRDIER1 in PWM3 Mode
Figure 14.148 TRD0 Register in PWM3 Mode
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0 0144h 11100000b
TRDIER1 0154h 11100000b
Bit Symbol Bit Name Function RW
OVIE
—
(b7-b5) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
IMIEC RW
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Overf low /underflow interrupt enable
bit
0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
b7 b6 b5 b4 b3 b2
IMIED
b1 b0
Timer RD Counter 0(1, 2)
Symbol Address After Reset
TRD0 0147h-0146h 0000h
Setting Range RW
NOTES:
1.
2.
Function
Count a count source. Count operation is incremented.
When an overf low occurs, the OVF bit in the TRDSR0 register is set to 1.
0000h to FFFFh
RW
b7
The TRD1 register is not used in PWM3 mode.
(b8)
b0
(b15)
b7
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
b0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 332 of 580
REJ09B0324-0200
Figure 14.1 49 Registe r s T RDG RAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM3 Mode
The following registers are disabled in the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1,
TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
Symbol Address After Reset
TRDGRA 0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA 1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
(b8)
b0
(b15)
b7 b0b7
RW
Function
Ref er to Table 14.49 TRDGRji Register Fu nctions in PWM3 mode.
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 333 of 580
REJ09B0324-0200
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as
buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the
TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1
may be set to 1 (buffer register).
Table 14.49 TRDGRji Register Functions in PWM3 Mode
Register Setting Register Function PWM Output Pin
TRDGRA0 −General register. Set the PWM period.
Setting range: Value set in TRDGRA1 register or above
TRDIOA0
TRDGRA1 General register. Set the changing point (the active level
timing) of PWM output.
Setting range: Value set in TRDGRA0 register or below
TRDGRB0 General register. Set the changing point (the timing that
returns to initial output level) of PWM output.
Setting range: Value set in TRDGRB1 register or above
Value set in TRDGRA0 register or below
TRDIOB0
TRDGRB1 General register. Set the changing point (active level timing) of
PWM output.
Setting range: Value set in TRDGRB0 register or below
TRDGRC0 BFC0 = 0 (These registers is not used in PWM3 mode.) −
TRDGRC1 BFC1 = 0
TRDGRD0 BFD0 = 0
TRDGRD1 BFD1 = 0
TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRC1 register or above
TRDIOA0
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRC0 register or below
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRD1 register or above,
setting value or below in TRDGRC0 register.
TRDIOB0
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRD0 register or below
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 334 of 580
REJ09B0324-0200
Figure 14.150 Operating Example of PWM3 Mode
Value in TRD0 register
Count source
TRDIOA0 output
0000h
FFFFh
TRDIOB0 output
m: Value set in TRDGRA0 register
n: Value set in TRDGRA1 register
p: Value set in TRDGRB0 register
q: Value set in TRDGRB1 register
m
n
p
q
TSTART0 bit in
TRDSTR register
1
0
Set to 0 by a program Set to 0 by a program
m+1
n+1 m-n
p+1
q+1 p-q
Count stop
Output “H” at compare
match with the
TRDGRA1 register
Set to 0 by a programSet to 0 by a program
Set to 0 by a program
Transfer
m
m Following data
Transfer
m
Output “L” at compare match
with the TRDGRA0 register
Transfer from buffer register to
general register
Transfer from buffer register to
general register
Initial output “L”
j = either A or B
The above applies under the following conditions:
• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by compare match with the
TRDGRj1 register, output “L” at compare match with the TRDGRj0 register).
• The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).
CSEL0 bit in
TRDSTR register
1
0
IMFA bit in
TRDSR0 register
1
0
IMFB bit in
TRDSR0 register
1
0
TRDGRA0 register
TRDGRC0 register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 335 of 580
REJ09B0324-0200
14.4.11 Timer RD Interrupt
T imer RD generate s the timer RD interrupt request based on 6 sources for each channel. The timer RD interrupt
has 1 TRDiIC register (bits IR, and ILVL0 to ILVL2), and 1 vector for each channel. Table 14.50 lists the
Registers Associated with Timer RD Interrupt, and Figure 14.151 shows a Block Diagram of Timer RD
Interrupt.
Figure 14.151 Block Diagram of Timer RD Interrupt
As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit,
bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a
combination of multiple int errupt request sources, the following differences from other maskable interrupts
apply:
• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable
interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the
TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore,
even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
maintained.
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is
determined by the TRDSRi register.
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set
each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions
of the registers used in the different modes (Figures 14.77, 14.93, 14.107, 14.120, 14.132, and 14.146).
Table 14.50 R eg is te rs As soc ia t ed with Timer RD Interrupt
Timer RD
Status Register
Timer RD
Interrupt Enable Register
Timer RD
Interrupt Control Register
Channel 0 TRDSR0 TRDIER0 TRD0IC
Channel 1 TRDSR1 TRDIER1 TRD1IC
Timer RD interrupt request
(IR bit in TRDiIC register)
IMFA bit
IMIEA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Channel i
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 336 of 580
REJ09B0324-0200
Refer to Registers TRDSR0 to TRDSR1 in each mode (Figures 14.77, 14.93, 14.107, 14.120, 14.132, and
14.146) for the TRDSRi register. Refer to Registers TRDIER0 to TR DIER1 in each mode (Figures 14.78,
14.94, 14.108, 14.121, 14.133, and 14.147) for the TRDIERi regist er.
Refer to 12.1.6 Interrupt Control for information on the TRDiIC register and 12.1.5.2 Relocatable Vector
Tables for the interrupt vectors.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 337 of 580
REJ09B0324-0200
14.4.12 Notes on Timer RD
14.4.12.1 TRDSTR Register
•Set the TRDSTR register using the MOV instruction.
•When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
•Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is se to 0.
•To stop counting by a program, set t he TSTARTi bit after setting the CSELi bit to 1. Although the CSELi
bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 inst ruction), the count cannot be
stopped.
•Table 14.51 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji
(j = A, B, C, or D) pin with the timer RD output.
14.4.12.2 TRDi Register (i = 0 or 1)
•When writing the valu e to th e TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting t he TRDi register to 0000h overla ps with the tim ing for writing the value to
the TRDi register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the
TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
•When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example MOV.W #XXXXh, TRD0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.W TRD0,DATA ;Reading
14.4.12.3 TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example MOV.B #XXh, TRDSR0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.B TRDSR0,DATA ;Reading
Table 14.51 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Count Stop TRDIOji Pin Output when Count Stops
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count
stops.
Hold the output level immediately before the
count stops.
When the CSELi bit is set to 0, the count stops at compare match of
registers TRDi and TRDGRAi.
Hold the output level after output changes by
compare match.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 338 of 580
REJ09B0324-0200
14.4.12.4 Count Source Switch
•Switch the count source after the count stops.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi regist er.
•When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO 40M.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi regist er.
(3) Wait 2 or more cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
14.4.12.5 Input Capture Function
•Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.26 Timer RD Operation Clocks).
•The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD
operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or
D) (no digital filter).
14.4.12.6 Reset Synchronous PWM Mode
•When reset synchronous PWM mode is used for moto r control, make sure OLS0 = OLS1.
•Set to reset synchronous PWM mode by the following pro cedure:
Change procedure
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
14.4.12.7 Complementary PWM Mode
•When complementary PWM mode is used for moto r control, make sure OLS0 = OLS1.
•Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
timing from the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Change procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
•Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values wri tten to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGR A1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 339 of 580
REJ09B0324-0200
•If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
Figure 14.152 Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Complementary PWM Mode
No change
IMFA bit in
TRDSR0 register
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Count value in TRD0
register
Setting value in
TRDGRA0
register m
m+1
Set to 0 by a program
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 11b
(transfer from the buffer register to the
general register at compare match of
between registers TRD0 and
TRDGRA0).
1
0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 340 of 580
REJ09B0324-0200
•The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to
CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at
underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During
FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this
time, the OVF bit remains unchanged.
Figure 14.153 Operation when TRD1 Register Underflows in Complementary PWM Mode
No change
UDF bit in
TRDSR0 register
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Count value in TRD0
register
Set to 0 by a program
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 10b
(transfer from the buffer register to the
general register when the TRD1 register
underflows).
OVF bit in
TRDSR0 register
FFFFh
1
0
1
0
0
1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 341 of 580
REJ09B0324-0200
•Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:
Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is
transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1
to CMD0.
Figure 14.154 Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
Complementary PWM Mode
0000h
TRDGRD0 register
TRDIOB0 output
n3
n2
m+1
n3
n2
n1
n2 n1
n3
n2 n2 n1n1TRDGRB0 register
Transfer
Transfer at
underflow of TRD1
register because of
n3 > m
Transfer at
underflow of TRD1
register because
of first setting to
n2 < m
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
Count value in TRD0
register
Count value in TRD1
register
Transfer with timing set by
bits CMD1 to CMD0
Transfer with timing set by
bits CMD1 to CMD0
Transfer Transfer Transfer
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 342 of 580
REJ09B0324-0200
When the value in the buffer register is set to 0000h:
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register , and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general regi ster. Af ter that, the valu e is transferred with the
timing selected by bits CMD1 to CMD0 .
Figure 14.155 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM
Mode
14.4.12.8 Count Source fOCO40M
•The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
0000h
TRDGRD0 register
TRDIOB0 output
n1
m+1
n2
n1
0000h n1
0000h
n1 n1n2TRDGRB0 register
Transfer
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in TRDGRD0
register is set to
0000h.
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001h ≤ n1 < m
Transfer with timing
set by bits CMD1 to
CMD0
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
Count value in TRD0 register
Count value in TRD1 register
Transfer with timing
set by bits CMD1 to
CMD0
Transfer Transfer Transfer
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 343 of 580
REJ09B0324-0200
14.5 Timer RE
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes:
•Real-time cloc k mode Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of
the week.
•Output compare mode Count a count source and detect compare matches.
The count source for timer RE is the operating clock that regulates the timing of timer operations.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 344 of 580
REJ09B0324-0200
14.5.1 Real-Time Clock Mode
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 14.156
shows a Block Diagram of Real-Time Clock Mode and Table 14.52 lists the Real-Time Clock Mode
Specifications. Figures 14.157 to 14.161 and 14.163 to 14.164 show the Registers Associated with Real-Time
Clock Mode. Table 14.53 lists the Interrupt Sources, Figure 14.162 shows the Definition of Time
Representation and Figure 14.165 shows the Operating Example in Real-Time Clock Mode.
Figure 14.156 Block Diagram of Real-Time Clock Mode
TREWK
register
TREHR
register
TREMIN
register
TRESEC
register
H12_H24
bit
PM
bit
MNIE
HRIE
WKIE
000
DYIE
SEIE
Timer RE
interrupt
INT
bit
BSY
bit
8-bit counter4-bit counter
Overflow
(1s)
Overflow
1/2
(1/256)(1/16)
fC4
H12_H24, PM, INT: Bits in TRECR1 register
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Timing
control
Data bus
Overflow Overflow
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 345 of 580
REJ09B0324-0200
Table 14.52 Real-Time Clock Mode Specifications
Item Specification
Count source fC4
Count operation Increment
Count start condition 1 (count starts) is written to TSTART bit in TRECR1 register
Count stop condition 0 (count stops) is written to TSTART bit in TRECR1 register
Interrupt request generation
timing
Select any one of the following:
• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
TREO pin function Programmable I/O ports or output of f2, f4, or f8
Read from timer When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN,
and TREHR are represented by the BCD code.
Write to timer When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
Select function • 12-hour mode/24-hour mode switch function
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 346 of 580
REJ09B0324-0200
Figure 14.157 TRESEC Register in Real-Time Clock Mode
Figure 14.158 TREMIN Register in Real-Time Clock Mode
Timer RE Second Data Register
Symbol Address After Reset
TRESEC 0118h 00h
Bit Symbol Bit Name Function Setting
Range RW
Timer RE busy flag
2nd digit of second count bits When counting 0 to 5, 60 seconds
are counted.
0 to 5
(BCD
code)
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RW
b3 b2
SC03
b1 b0
1st digit of second count bits
RW
b7 b6 b5 b4
SC00 RW
SC01 RW
Count 0 to 9 every second. When the
digit moves up, 1 is added to the 2nd
digit of second.
0 to 9
(BCD
code)
SC02 RW
RW
SC10 RW
SC11
BSY RO
SC12
Timer RE Minute Data Register
Symbol Address After Reset
TREMIN 0119h 00h
Bit Symbol Bit Name Function Setting
Range RW
Timer RE busy flag
2nd digit of minute count bits When counting 0 to 5, 60 minutes are
counted.
0 to 5
(BCD
code)
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RW
b3 b2
MN03
b1 b0
RW
b7 b6 b5 b4
MN00 RW1st digit of minute count bits
MN01 RW
Count 0 to 9 every minute. When the
digit moves up, 1 is added to the 2nd
digit of minute.
0 to 9
(BCD
code)
MN02 RW
RW
MN10 RW
MN11
BSY RO
MN12
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 347 of 580
REJ09B0324-0200
Figure 14.159 TREHR Register in Real-Time Clock Mode
Figure 14.160 TREWK Register in Real-Time Clock Mode
Timer RE Hour Data Register
Symbol Address After Reset
TREHR 011Ah 00h
Bit Symbol Bit Name Function Setting
Range RW
HR02 RW
RW
HR10 RW
HR11
BSY RO
—
(b6)
HR00 RW1st digit of hour count bits
HR01 RW
Count 0 to 9 every hour. When the
digit moves up, 1 is added to the 2nd
digit of hour.
0 to 9
(BCD
code)
b7 b6 b5 b4
—
b3 b2
HR03
b1 b0
RW
Timer RE busy flag This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
2nd digit of hour count bits Count 0 to 1 w hen the H12_H24 bit is
set to 0 (12-hour mode).
Count 0 to 2 w hen the H12_H24 bit is
set to 1 (24-hour mode).
0 to 2
(BCD
code)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE Day of Week Data Register
Symbol Address After Reset
TREWK 011Bh 00h
Bit Symbol Bit Name Function RW
b3 b2
—
(b6-b3)
b1 b0
WK0
b7 b6 b5 b4
RW
WK1 RW
Day of w eek count bits b2 b1 b0
0 0 0 : Sunday
0 0 1 : Monday
0 1 0 : Tuesday
0 1 1 : Wednesday
1 0 0 : Thursday
1 0 1 : Friday
1 1 0 : Saturday
1 1 1 : Do not set.
WK2 RW
—
BSY RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 348 of 580
REJ09B0324-0200
Figure 14.161 TRECR1 Register in Real-Time Clock Mode
Figure 14.162 Definition of Time Representation
Timer RE Control Register 1
Symbol Address After Reset
TRECR1 011Ch 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
RW
RW
H12_H24 Operating mode select bit 0 : 12-hour mode
1 : 24-hour mode RW
Interrupt request timing bit Set to 1 in real-time clock mode.
PM
A.m./p.m. bit When the H12_H24 bit is set to 0
(12-hour mode)(1)
0 : a.m.
1 : p.m.
When the H12_H24 bit is set to 1 (24-hour
mode), its value is undefined.
TRERST
Timer RE reset bit When setting this bit to 0, after setting it to 1, the
f ollow ings w ill occur.
• Regis ters TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
TREO pin output enable bit 0 : Disable clock output
1 : Enable clock output
This bit is automatically modified w hile timer RE counts.
TOENA RW
RW
TSTA RT Timer RE count start bit 0 : Count stops
1 : Count starts RW
—
TCSTF RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag 0 : Count stopped
1 : Counting
b7 b6 b5 b4 b3 b2
INT
b1 b0
—
(b0)
Noon
H12_H24 bit = 1
(24-hour mode)
Contents of PM bit 0 (a.m.) 1 (p.m.)
Contents of
TREHR Register H12_H24 bit = 0
(12-hour mode)
Contents in TREWK register 000 (Sunday)
0 1 2 3 4 5 7 9 11 13 15 176 8 10 12 14 16
0 1 2 3 4 5 7 9 11 1356810 024
H12_H24 bit = 1
(24-hour mode)
Contents of PM bit 1 (p.m.)
Contents of
TREHR Register H12_H24 bit = 0
(12-hour mode)
Contents in TREWK register 000 (Sunday)
18 19 20 21 22 23 1 30 2 ⋅⋅⋅
6 7 8 9 10 11 1 30 2
Date changes
⋅⋅⋅
⋅⋅⋅0 (a.m.)
001 (Monday) ⋅⋅⋅
PM bit and H12_H24 bits: Bits in TRECR1 register
The above applies to the case when count starts from a.m. 0 on Sunday.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 349 of 580
REJ09B0324-0200
Figure 14.163 TRECR2 Register in Real-Time Clock Mode
Table 14.53 Interrupt Sources
Factor Interrupt Source Interrupt Enable Bit
Periodic interrupt
triggered every week
Value in TREWK register is set to 000b (Sunday)
(1-week period)
WKIE
Periodic interrupt
triggered every day
TREWK register is updated (1-day period) DYIE
Periodic interrupt
triggered every hour
TREHR register is updated (1-hour period) HRIE
Periodic interrupt
triggered every minute
TREMIN register is updated (1-minute period) MNIE
Periodic interrupt
triggered every second
TRESEC register is updated (1-second period) SEIE
Timer RE Control Register 2
Symbol Address After Reset
TRECR2 011Dh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b3 b2
DY IE
b1 b0
SEIE
b7 b6 b5 b4
0
RW
MNIE RW
Periodic interrupt triggered every
minute enable bit(1)
0 : Disable periodic interrupt triggered
every minute
1 : Enable periodic interrupt triggered
every minute
Periodic interrupt triggered every
second enable bit(1)
0 : Disable periodic interrupt triggered
every second
1 : Enable periodic interrupt triggered
every second
Periodic interrupt triggered every
hour enable bit(1)
0 : Disable periodic interrupt triggered
every hour
1 : Enable periodic interrupt triggered
every hour
Do not set multiple enable bits to 1 (enable interrupt).
HRIE RW
RW
Periodic interrupt triggered every day
enable bit(1)
0 : Disable periodic interrupt triggered
every day
1 : Enable periodic interrupt triggered
every day
COMIE Compare match interrupt enable bit
RW
RW
—
(b7-b6) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Set to 0 in real-time clock mode.
WKIE
Periodic interrupt triggered every
w eek enable bit(1)
0 : Disable periodic interrupt triggered
every w eek
1 : Enable periodic interrupt triggered
every w eek
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 350 of 580
REJ09B0324-0200
Figure 14.164 TRECSR Register in Real-Time Clock Mode
Timer RE Count Source Select Register
Symbol Address After Reset
TRECSR 011Eh 00001000b
Bit Symbol Bit Name Function RW
NOTE:
1.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
RW
RCS6 RW
RCS5
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock output select bits(1) b6 b5
0 0 : f2
0 1 : f4
1 0 : f8
1 1 : Do not set.
4-bit counter select bit Set to 0 in real-time clock mode.
Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
RCS2 RW
RW
—
(b7) —
Real-time clock mode select bit Set to 1 in real-time clock mode.
RW
RCS1 RW
Count source select bits Set to 00b in real-time clock mode.
b7 b6 b5 b4 b3 b2
RCS3
b1 b0
0010
RCS0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 351 of 580
REJ09B0324-0200
Figure 14.165 Operating Example in Real-Time Clock Mode
IR bit in TREIC register
03
IR bit in TREIC register
Bits WK2 to WK0 in
TREWK register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every second))
(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every minute))
1
0
PM bit in
TRECR1 register
Bits HR11 to HR00 in
TREHR register (Not changed)
Set to 0 by acknowledgement
of interrupt request
or a program
04
Bits MN12 to MN00 in
TREMIN register
58 59 00
BSY bit
Approx.
62.5 ms
Bits SC12 to SC00 in
TRESEC register
1s
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Approx.
62.5 ms
1
0
1
0
(Not changed)
(Not changed)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 352 of 580
REJ09B0324-0200
14.5.2 Output Compare Mode
In output compa re mode, the inte rnal count source d ivided by 2 is cou nted using the 4-b it or 8-bit counter an d
compare value match is detected with the 8-bit counter. Figure 14.166 shows a Block Diagram of Output
Compare Mode and Table 14.54 lists the Output Compare Mode Specifications. Figures 14.167 to 14.171 show
the registers associated with output compare mode, and Figure 14.172 shows the Operating Ex ample in Output
Compare Mode.
Figure 14.166 Block Diagram of Output Compare Mode
TOENA bit
TREO pin
fC4
f32
f4
f8
4-bit
counter
8-bit
counter
TRESEC
TREMIN
1/2
RCS2 = 1
RCS2 = 0
COMIE bit Timer RE interrupt
f2
Match
signal
= 00b
= 01b
= 10b
= 11b
RCS1 to RCS0
RCS6 to RCS5
= 00b
= 01b
= 10b
= 11b
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
TQ
R
Reset
TRERST bit
Data bus
Comparison
circuit
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 353 of 580
REJ09B0324-0200
Table 14.54 Output Compare Mode Specifications
Item Specification
Count sources f4, f8, f32, fC4
Count operations • Increment
• When the 8-bit counter content matches with the TREMIN register
content, the value returns to 00h and count continues.
The count value is held while count stops.
Count period • When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register
Count stop condition 0 (count stops) is written to the TSTART bit in the TRECR1 register
Interrupt request generation
timing
When the 8-bit counter content matches with the TREMIN register content
TREO pin function Select any one of the following:
• Programmable I/O ports
• Output f2, f4, or f8
• Compare output
Read from timer When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Write to timer Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
Select functions • Select use of 4-bit counter
• Compare output function
Every time the 8-bit counter value matches the TREMIN register value,
TREO output polarity is reversed. The TREO pin outputs “L” after reset
is deasserted and the timer RE is reset by the TRERST bit in the
TRECR1 register. Output level is held by setting the TSTART bit to 0
(count stops).
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 354 of 580
REJ09B0324-0200
Figure 14.167 TRESEC Register in Output Compare Mode
Figure 14.168 TREMIN Register in Output Compare Mode
Timer RE Counter Data Register
Symbol Address After Reset
TRESEC 0118h 00h
RW
b3 b2 b1 b0
RO
b7 b6 b5 b4
Function
8-bit counter data can be read.
Although Timer RE stops counting, the count value is held.
The TRESEC register is set to 00h at the compare match.
Timer RE Compare Data Register
Symbol Address After Reset
TREMIN 0119h 00h
RW
b3 b2 b1 b0
RW
b7 b6 b5 b4
Function
8-bit compare data is stored.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 355 of 580
REJ09B0324-0200
Figure 14.169 TRECR1 Register in Output Compare Mode
Figure 14.170 TRECR2 Register in Output Compare Mode
Timer RE Control Register 1
Symbol Address After Reset
TRECR1 011Ch 00h
Bit Symbol Bit Name Function RW
b3 b2
INT
b1 b0
0
—
(b0)
b7 b6 b5 b4
00
—
TCSTF RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag 0 : Count stopped
1 : Counting
RW
TSTA RT Timer RE count start bit 0 : Count stops
1 : Count starts RW
Interrupt request timing bit Set to 0 in output compare mode.
PM A.m./p.m. bit
TREO pin output enable bit 0 : Disable clock output
1 : Enable clock output
TOENA RW
TRERST
Timer RE reset bit When setting this bit to 0, after setting it to 1, the
f ollow ing w ill occur.
• Re g is t er s TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and
TSTART in the TRECR1 register are
set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
RW
RW
H12_H24 Operating mode select bit RW
Set to 0 in output compare mode.
Timer RE Control Register 2
Symbol Address After Reset
TRECR2 011Dh 00h
Bit Symbol Bit Name Function RW
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Disable compare match interrupt
1 : Enable compare match interrupt
WKIE Periodic interrupt triggered every
w eek enable bit
Set to 0 in output compare mode.
Periodic interrupt triggered every
hour enable bit
HRIE RW
RW
Periodic interrupt triggered every
day enable bit
COMIE Compare match interrupt enable bit
RW
RW
—
(b7-b6)
RW
MNIE RW
Periodic interrupt triggered every
minute enable bit
Periodic interrupt triggered every
second enable bit
0
b7 b6 b5 b4 b3 b2
DY IE
b1 b0
0000
SEIE
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 356 of 580
REJ09B0324-0200
Figure 14.171 TRECSR Register in Output Compare Mode
Timer RE Count Source Select Register
Symbol Address After Reset
TRECSR 011Eh 00001000b
Bit Symbol Bit Name Function RW
NOTE:
1.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
RW
RCS6 RW
RCS5
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock output select bits(1) b6 b5
0 0 : f2
0 1 : f4
1 0 : f8
1 1 : Compare output
4-bit counter select bit 0 : Not used
1 : Used
Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
RCS2 RW
RW
—
(b7) —
Real-time clock mode select bit Set to 0 in output compare mode.
RW
RCS1 RW
Count source select bits b1 b0
0 0 : f4
0 1 : f8
1 0 : f32
1 1 : fC4
b7 b6 b5 b4 b3 b2
RCS3
b1 b0
0
RCS0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 357 of 580
REJ09B0324-0200
Figure 14.172 Operating Example in Output Compare Mode
2 cycles of maximum count source
00h
8-bit counter content
(hexadecimal number)
Count starts
Time
TSTART bit in
TRECR1 register
1
0
IR bit in
TREIC register
1
0
The above applies under the following conditions.
TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Set to 1 by a program
Set to 0 by acknowledgement of interrupt request
or a program
TREMIN register
setting value
Matched
TREO output 1
0
TCSTF bit in
TRECR1 register
1
0
Output polarity is inverted
when the compare matches
Matched Matched
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 358 of 580
REJ09B0324-0200
14.5.3 Notes on Timer RE
14.5.3.1 Starting and Stopping Count
Timer RE has the TSTART bit f or instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counti ng and the TCSTF bit is set to 1 ( count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTA RT bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
14.5.3.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
•Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
•Bits H12_H24, PM, and INT in TRECR1 register
•Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 14.173 shows a Setting Example in Real-Time Clock Mode.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 359 of 580
REJ09B0324-0200
Figure 14.173 Setting Example in Real-Time Clock Mode
Stop timer RE operation
TCSTF in
TRECR1 register = 0?
TSTART in TRECR1 register = 0
TRERST in TRECR1 register = 1
TRERST in TRECR1 register = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2 register
TSTART in TRECR1 register = 1
TCSTF in
TRECR1 register = 1?
TREIC register←00h
(disable timer RE interrupt)
Setting of TREIC register (IR bit←0,
select interrupt priority level)
Timer RE register
and control circuit reset
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Start timer RE operation
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 360 of 580
REJ09B0324-0200
14.5.3.3 Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated befo re another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
•Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
•Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
•Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms whil e the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
•Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat unti l the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 361 of 580
REJ09B0324-0200
14.6 Timer RF
Timer RF is a 16-bit timer. The count source for timer RF is the operating clock that regulates the timing of timer
operations. Figure 14.174 shows a Block Diagram of Timer RF. Figure 14.175 shows a Block Diagram of CMP
Waveform Generation Unit. Figure 14.176 sh ows a Block Diag ram of CMP Waveform Output Unit.
Timer RF has two modes: input capture mode and output compare mode. Figures 14.177 to 14.180 show the Timer
C-associated registers.
Figure 14.174 Block Diagram of Timer RF
= 01b
= 10b
f8
f1
Digital
filter
= 11b
f32
TIPF1 to TIPF0
TRFM0 register
Data bus
= other than
00b
= 00b
Edge
detection
= 00b
= 01b
f8
f1
= 10b
f32
TCK1 to TCK0
TSTART CCLR = 1
CCLR = 0
Capture signal
Timer RF
interrupt
Compare 1
interrupt
Timer RF counter
clear signal
TSTART, TCK0 to TCK1: Bits in TRFCR0 register
TIPF0 to TIPF1, CCLR: Bits in TRFCR1 register
TRFI
Compare 0
interrupt
Sampling clock
TRF register
TRFM1 register
CMP
waveform
generation
unit
Capture interrupt
TRFO00
TRFO01
TRFO02
TRFO10
TRFO11
TRFO12
Capture, Compare 0 register
Counter
Compare 1 register
Comparator
Comparator
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
CMP waveform
output unit
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 362 of 580
REJ09B0324-0200
Figure 14.175 Block Diagram of CMP Waveform Generation Unit
Figure 14.176 Block Diagram of CMP Waveform Output Unit
TRFC14
CMP output
(internal signal)
TRFC14 to TRFC17: Bits in TRFC1 register
Latch
DQ
= 11b
= 10b
“L”
“H”
= 01b
Inverted
TRFC17 to TRFC16
= 01b
= 10b
“L”
“H” = 11b
TRFC15 to TRFC14
T
TRFC15
Compare 0 interrupt signal
TRFC16
TRFC17
R
Reset
Compare 1 interrupt signal
Inverted
Inverted
CMP output
(Internal signal)
TRFOUT6 = 0
TRFOUT6 = 1
TRFOUT0 = 1
TRFOUT0 = 0
TRFO00
P8_0 bit
This diagram is a block diagram of the TRFO00 waveform output unit.
The TRFO01 to TRFO02 and TRFO10 to TRFO12 waveform output units have the same configuration.
TRFOUT0 and TRFOUT6: Bits in TRFOUT register
P8_0: Bit in P8 register
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 363 of 580
REJ09B0324-0200
Figure 14.177 Registers TRF, TRFM0, and TRFM1
Compare 1 Register(1)
Symbol Address After Reset
TRFM1 029Fh-029Eh FFFFh
Function Setting Range RW
NOTE:
1.
Mode
Output compare mode
(b8)
b0
(b15)
b7 b0b7
0000h to FFFFh RW
Access the TRFM1 register in 16-bit units.
Store the value compared w ith TRF
register (counter)
Capture and Compare 0 Register(1)
Symbol Address After Reset
TRFM0 029Dh-029Ch 0000h(2)
Function Setting Range RW
NOTES:
1.
2.
3.
Mode
b7
When setting a value in the TRFM0 register, set the TMOD bit in the TRFCR1 register to 1 (output compare mode).
When the TMOD bit is set to 0 (input capture mode), no value can be w ritten.
(b8)
b0
(b15)
b7 b0
―
When the active edge of the measured
pulse is input, store the value in the TRF
register
When the TMOD bit in the TRFCR1 register is set to 1, the value is set to FFFFh.
Access the TRFM0 register in 16-bit units.
Input capture mode
RW
Output compare mode(3) Store the value compared w ith TRF
register (counter)
0000h to FFFFh
RO
Timer RF Register(1)
Symbol Address After Reset
TRF 0291h-0290h 0000h
RW
NOTE:
1. Access the TRF register in 16-bit units.
(b8)
b0
(b15)
b7
Function
Count source increment .
0000h can be read w hen the TSTART bit is set to 0 (count stops).
Count value can be read w hen the TSTART bit is set to 1 (count starts).
RO
b0b7
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 364 of 580
REJ09B0324-0200
Figure 14 .1 78 TRFCR 0 Re gi st er
Timer RF Control Register 0
Symbol Address After Reset
TRFCR0 029Ah 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b4 b3
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Do not set.
RW
RW
TRFC04 RW
TRFC03
0 : TRFC06 bit disabled
Holds output level before count stops
1 : TRFC06 bit enabled
Capture polarity select bits(1)
RW
b7 b6 b5 b4
0
b3 b2 b1 b0
TCK0 RW
Timer RF count start bit 0 : Count stops
1 : Count starts
Timer RF count source select
bits(1)
b2 b1
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Do not set.
TCK1 RW
TSTA RT RW
Rew rite this bit w hen the TSTART bit is set to 0 (count stops).
CMP output select bit 0 w hen
count stops
TRFC05
TRFC06 CMP output select bit 1 w hen
count stops
0 : “L” output w hen count stops
1 : “H” output w hen count stops
—
(b7)
Reserved bit Set to 0. RW
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 365 of 580
REJ09B0324-0200
Figure 14 .1 79 TRFCR 1 Re gi st er
Figure 14.180 TRFOUT Register
Timer RF Control Register 1
Symbol Address After Reset
TRFCR1 029Bh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4. When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0)
and set the IR bit to 0 (no interrupt requested).
RW
TRF register count operation
select bit(2, 3)
Compare 0 output select
bits(2)
b5 b4 CMP output w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
RW
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
0 : Input capture mode(2, 4)
1 : Output compare mode
RW
RW
RW
TRFC15
TIPF0
TMOD Timer RF operation mode
select bit(3)
CCLR
TRFC14
TRFI f ilter select bits(1)
b7 b6 b5 b4 b3 b2
0 : Free-running operation
1 : Set TRF register to 0000h w hen compare
1 is matched.
b1 b0
TIPF1
When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0.
When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD.
RW
TRFC17
TRFC16
Compare 1 output select
bits(2)
b7 b6 CMP output w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined.
Timer RF Output Control Register
Symbol Address After Reset
TRFOUT 02FFh 00h
Bit Symbol Bit Name Function RW
TRFOUT3 TRFO10 output enable bit
RW
RW
RW
TRFO00 to TRFO02 output invert
bit RW
0 : Output disabled
1 : Output enabled
0 : Output not inverted
1 : Output inverted
RW
TRFOUT2 RW
RW
TRFO02 output enable bit
TRFO00 output enable bit
TRFO01 output enable bit
b7 b6 b5 b4 b3 b2 b1 b0
TRFOUT1
TRFOUT0
TRFOUT7
TRFOUT6
RW
TRFO12 output enable bitTRFOUT5
TRFO11 output enable bit
TRFO10 to TRFO12 output invert
bit
TRFOUT4
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 366 of 580
REJ09B0324-0200
14.6.1 Input Capture Mode
In input capture mode, th e edge of the TRFI pi n input signal is used as a trigger to latch the timer value and the
width or the period of external signal is measured. The TRFI input is equipped with a digital filter, and this
prevents errors caused by noise or the like from occurring. Table 14.55 shows the Input Capture Mode
Specifications. Figure 14.181 shows an Operating Example in Input Capture Mode.
Table 14.55 Input Capture Mode Specifications
Item Specification
Count sources f1, f8, f32
Count operations • Increment
• Transfer the value in the TRF register to the TRFM0 register at the valid
edge of the measured pulse.
Count period 1/fk × 65536 fk: Frequency of count source
Count start condition The TSTART bit in the TRFCR0 register is set to 1 (count starts).
Count stop condition The TSTART bit in the TRFCR0 register is set to 0 (count stops).
Interrupt request
generation timing
• The valid edge of TRFI input [capture interrupt]
• When timer RF overflows [timer RF interrupt]
TRFI pin function Measured pulse input
TRFO00 to TRFO02,
TRFO11 to TRFO12 pin
functions
Programmable I/O port
Counter value reset timing In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
Read from timer • The count value can be read out by reading the TRF register.
• The count value at the measured pulse valid edge input can be read out by
reading the TRFM0 register.
Write to timer Write to the TRF and TRFM0 registers is disabled.
Select functions • TRFI polarity selected
Selects the valid edge of the measured pulse.
(Bits TRFC03 to TRFC04 in the TRFCR0 register.)
• Digital filter function
The TRFI input is sampled, and when the sampled input level matches as
three times, the level is determined.
Selects the sampling clock of the digital filter.
(Bits TIPF0 to TIPF1 in the TRFCR1 register.)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 367 of 580
REJ09B0324-0200
Figure 14.181 Operating Example in Input Capture Mode
FFFFh
0000h
Counter contents (hex)
Count starts
Overflow
Time
TSTART bit in
TRFCR0 register
1
0
Measured pulse
(TRFI pin input)
1
0
The above applies under the following conditions.
Bits TRFC04 to TRFC03 in TRFCR0 register = 01b (Capture input polarity is set for falling edge.)
← Measurement value 2
Measurement
value 3
Set to 1 by a program
Measured
value 1
TRFM0 register Measured value 2 Measured
value 3
IR bit in
TRFIC register
1
0
IR bit in
CAPIC register
1
0
Set to 0 when interrupt request is acknowledged, or set by a program.
When the count
stops, the value
is set to 0000h.
Set to 0 by
a program
Undefined Undefined
Measurement value 2 -
measurement value 1
(10000h - measurement value 2) +
measurement value 3
Set to 0 when interrupt request is
acknowledged, or set by a program.
The delay caused by digital filter and
one count source cycle delay (max.).
←
← Measurement value1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 368 of 580
REJ09B0324-0200
14.6.1.1 Digit a l Filter
The TRFI input is sampled, and when the sampled input level matches three times, its level is determined.
Select the digital filter function and sam pl ing clock by the TRFCR1 register.
Figure 14.182 Block Diagram of Digital Filter
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
Match
detection
circuit
Edge
detection
circuit
Sampling clock
TMOD
TRFC04 to TRFC03
TIPF1 to TIPF0
TRFI input
signal
Clock period selected by
bits TIPF1 to TIPF0
Sampling clock
TRFI input signal
Input signal
through digital
filtering
Transmission cannot be performed
without three times match because the
input signal is assumed to be noise.
Signal transmission delayed
up to five sampling clock
Recognition of the
signal change with
three times match
f1
f8
f32
TRFC03 to TRFC04: Bits in TRFCR0 register
TIPF0 to TIPF1 and TMOD: Bits in TRFCR1 register
C
DQ
Latch
C
DQ
Latch
Count source
= 01b
= 10b
= 11b
= 01b, 10b, 11b
= 00b
TIPF1 to TIPF0
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 369 of 580
REJ09B0324-0200
14.6.2 Output Compare Mode
In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0 match)
or TRFM1 (compare 1 match) register, a user-set level is output mode from the output-compare output pin.
Table 14.56 shows the Output Compare Mode Specifications. Table 14.57 shows the Output in Output
Compare Mode (Example of TRFO00 Pin). Figure 14.183 shows an Operating Example in Output Compare
Mode. Figure 14.184 shows the Operating Example in Output Compare Mode (“L” and “H” Held Output in
Count Stops).
Table 14.56 Output Compare Mode Specifications
Item Specification
Count sources f1, f8, f32
Count operations Increment
PWM waveform PWM period: 1/fk × (n + 1)
“L” level width: 1/fk × (m + 1)
“H” level width: 1/fk × (n - m)
fk: Frequency of count source
m: Value set in the TRFM0 register
n: Value set in the TRFM1 register
Count start condition The TSTART bit in the TRFCR0 register is set to 1 (count starts).
Count stop condition The TSTART bit in the TRFCR0 register is set to 0 (count stops).
Interrupt request
generation timing
• When compare 0 match is generated [compare 0 interrupt]
• When compare 1 match is generated [compare 1 interrupt]
• When time RF overflows [timer RF interrupt].
TRFO00 to TRFO12 pins
function
Programmable I/O port or output-compare output
Counter value reset timing In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
• The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to
0000h at compare 1 match) in the compare 1 matches.
Read from timer • The count value can be read out by reading the TRF register.
• The value in the compare register can be read out by reading registers
TRFM0 and TRFM1.
Write to timer Write to the TRF register is disabled
Select functions • Output-compare output pin selected
Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to
TRFO12 (bits TRFOUT0 to TRFOUT5 in the TRFOUT register).
• Output level at the compare match
Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the
TRFCR1 register).
• Output level inverted
Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7
in the TRFOUT register).
• Output level at the count stops
Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0
register).
• Timing to set the TRF register to 0000h
Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the
TRFCR1 register).
It applies under the following conditions.
• CMP output “H” when compare 0 is matched
• CMP output “L” when compare 1 is matched
• CMP output not inverted
n + 1
n - mm + 1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 370 of 580
REJ09B0324-0200
X: 0 or 1
Table 14.57 Output in Output Compare Mode (Example of TRFO00 Pin)
TRFO00 Output
Bit Setting Value
TRFCR0 Register TRFOUT Register P8 Register
TRFC06 TRFC05 TSTART TRFOUT6 TRFOUT0 P8_0
Counting CMP output X X 1 0 1 1
Inverted output of
CMP output
XX1 1 1 1
“L” output X X 1 0 1 0
“H” output X X 1 1 1 0
Count
stops
Holds output level
before count stops
X00 X 1 1
“L” output 0 1 0 X 1 1
“H” output 1 1 0 X 1 1
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 371 of 580
REJ09B0324-0200
Figure 14.183 Operating Example in Output Compare Mode
Value set in
TRFM1 register
0000h
Counter content (hex)
Count starts
Match
Time
TSTART bit in
TRFCR0 register
1
0
IR bit in
CMP0IC register
1
0
Set to 1 by a program
IR bit in
CMP1IC register
1
0
Value set in
TRFM0 register
Match Match
TRFO00 output 1
0
1
0
TRFO10 output
Set to 0 when interrupt request is acknowledged,
or set by a program.
Set to 0 when interrupt request is
acknowledged, or set by a program.
When the count
stops, the value
is set to 0000h.
TRFC05 bit in TRFCR0 register = 1, TRFC06 bit in TRFCR0 register = 0 (“L” output when count stops)
CCLR bit in TRFCR1 register = 1 (TRF register is set to 0000h at compare 1 match occurrence)
TMOD bit in TRFCR1 register = 1 (output compare mode)
Bits TRFC15 to TRFC14 in TRFCR1 register = 11b (CMP output level is set to “H” at compare 0 match)
Bits TRFC17 to TRFC16 in TRFCR1 register = 10b (CMP output level is set to “L” at compare 1 match)
TRFOUT6 bit in TRFOUT register = 0 (not inverted)
TRFOUT7 bit in TRFOUT register = 1 (inverted)
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
P8_0 bit in P8 register = 1 (“H”)
P8_3 bit in P8 register = 1 (“H”)
The above applies under the following conditions.
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 372 of 580
REJ09B0324-0200
Figure 14.184 Operating Example in Output Compare Mode (“L” and “H” Held Output in Count
Stops)
In output compare mode, the same PWM waveform is output from all of pins TRFO00 to TRFO02 and
TRFO10 to TRFO12 during coun t operation. Note that the output wavefo rm can be inverted for pi ns TRFO00
to TRFO02 or for pins TRFO10 to TRFO12. The o utput can also be fixed at “L” or “H” for individ ual pins for
a given period.
The behavior when count operation st ops can be selected from the following two options: the output level
before the count stops is maintained, or output is fixed at “L” or “H”.
The values in the compare i register can be read by reading the TRFMi (i = 0 or 1) register. Writing to the
TRFMi register causes the values to be stored in the compare i register in the following timing:
• If the TSTART bit is set to 0 (count stops)
Values are stored simultaneously with the write to the TRFMi register.
• If the TSTART bit is set to 1 (count starts) and the CCLR bit in the TRFCR1 register is set to 0 (free running)
Values are stored when the TRF register (counter) overflows.
• If the TSTART bit is set to 1 and the CCLR bit is set to 1 (TRF register set to 0000h at com pare 1 match)
Values are stored when the compare 1 and TRF register (counter) values match.
Set to 0 by program
1
0
1
0
TRFO00 output
Set to 1 by program
P8_0 bit in
P8 register
TRFO10 output
P8_3 bit in
P8 register
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
TRFOUT6 bit in TRFOUT register = 0 (TRFO00 to TRFO02 output not inverted)
TRFOUT7 bit in TRFOUT register = 1 (TRFO10 to TRFO12 output inverted)
TSTART bit in TRFCR0 register = 1 (count starts)
The above applies under the following conditions.
CMP output
(internal signal)
R8C/2A Group, R8C/2B Group 14. Timers
Rev.2.00 Nov 26, 2007 Page 373 of 580
REJ09B0324-0200
14.6.3 Notes on Timer RF
• Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W 0290H,R0 ; Read out timer RF
• In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 374 of 580
REJ09B0324-0200
15. Serial Interface
The serial interface consists of three channels (UART0 to UART2). Each UARTi (i = 0 to 2) has an exclusive timer to
generate the transfer clock and operates independently.
Figure 15.1 shows a UARTi (i = 0 to 2) Block Diagram. Figure 15.2 shows a UARTi Transm it/Receive Unit. Figure
15.3 shows a Block Diagram of CLK1 and CLK2 Pin Switching Un it.
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figures 15.4 to 15.8 show the regist ers associated with UARTi.
Figure 15.1 U ARTi (i = 0 to 2) Block Diag ram
= 01b
f8
f1
= 10b
CLK1 to CLK0 = 00b
RXDj
f32
1/16
1/16
1/2
1/(n0+1)
UART reception
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock
synchronous type
Reception control
circuit
Transmission
control circuit
CKDIR = 0
CKDIR = 1
Receive
clock
Transmit
clock
Transmit/
receive
unit
U0BRG register
CKDIR = 0
Internal
External
CKDIR = 1
UARTj (j = 0 or 2)
TXDj
CLK
polarity
switch
circuit
CLKj
Clock
synchronous type
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
RXD1
Transmit/
receive
unit
UART1
TXD1
TXD1EN
= 01b
f8
f1
= 10b
CLK1 to CLK0 = 00b
f32
1/16
1/16
1/2
1/(n0+1)
UART reception
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock
synchronous type
Reception control
circuit
Transmission
control circuit
CKDIR = 0
CKDIR = 1
Receive
clock
Transmit
clock
U1BRG register
CKDIR = 0
Internal
External
CKDIR = 1
Clock
synchronous type
Clock synchronous type
(when external clock is selected)
CLK
polarity
switch
circuit
CLK1 (P6_5)
CLK1 (P0_5)
= 00b
= 01b
= 10b
CLK11PSEL to CLK10PSEL
CKDIR: Bit in UiMR register
CLK0 to CLK1: Bits in UiC0 register
CLK10PSEL to CLK11PSEL: Bits in U1SR register
U1PINSEL: Bit in PMR register
i = 0 to 2
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 375 of 580
REJ09B0324-0200
Figure 15.2 UARTi Transmit/Receive Unit
RXDi
1SP
2SP
SP SP PAR
PRYE = 0
PAR
disabled
PAR
enabled
PRYE = 1
UART UART (9 bits)
D7 D6 D5 D4 D3 D2 D1 D0
UARTi receive register
UiRB register
0000000D8
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
D7 D6 D5 D4 D3 D2 D1 D0 UiTB register
D8
TXDi
1SP
2SP
SP SP PAR
UARTi transmit register
0
i = 0 to 2
SP: Stop bit
PAR: Parity bit
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
Clock
synchronous
type UART (7 bits)
Clock
synchronous
type
UART (7 bits)
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UART (9 bits)
UART
PRYE = 1
PAR
enabled
PAR
disabled
PRYE = 0
Clock
synchronous
type
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 376 of 580
REJ09B0324-0200
Figure 15.3 Block Diagram of CLK1 and CLK2 Pin Switching Unit
CLK11PSEL = 0
CLK11PSEL = 1
CLK11PSEL
Clock synchronous
type (UART1)
CLK11PSEL
Clock synchronous
type (UART2)
CLK11PSEL = 1
CLK11PSEL = 0
CLK2
CLK1
P0_5
CLK11PSEL
CLK10PSEL
P6_5
CLK11PSEL
CLK10PSEL
CLK11PSEL
Clock synchronous type
CLK10PSEL, CLK11PSEL: Bits in U1SR register
CLK polarity
switch
CLK polarity
switch
CLK polarity
switch
CLK polarity
switch
CLK polarity
switch
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 377 of 580
REJ09B0324-0200
Figure 15.4 Registers U0MR to U2MR and U0BRG to U2BRG
UARTi Transmit/Receive Mode Register (i = 0 to 2)
Symbol Address After Reset
U0MR 00A0h 00h
U1MR 00A8h 00h
U2MR 0160h 00h
Bit Symbol Bit Name Function RW
Internal/external clock select bit 0 : Internal clock
1 : External clock
Stop bit length select bit
—
(b7)
Reserved bit RW
Odd/even parity select bit Enable w hen PRYE = 1
0 : Odd parity
1 : Even parity
PRY E Parity enable bit 0 : Parity disabled
1 : Parity enabled RW
Set to 0.
SMD2 RW
RW
STPS RW
0 : 1 stop bit
1 : 2 stop bits
CKDIR
PRY RW
Serial I/O mode select bits b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
SMD1
b7 b6 b5 b4
0
b0
SMD0 RW
b3 b2 b1
RW
UARTi Bit Rate Register (i = 0 to 2)(1, 2, 3)
Symbol Address After Reset
U0BRG 00A1h Undefined
U1BRG 00A9h Undefined
U2BRG 0161h Undefined
Setting Range RW
NOTES:
1.
2.
3.
b0
Use the MOV instruction to w rite to this register.
WO
Write to this register w hile the serial I/O is neither transmitting nor receiving.
00h to FFh
Function
Assuming the set value is n, UiBRG divides the count source by n+1
After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
b7
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 378 of 580
REJ09B0324-0200
Figure 15.5 Registers U0TB to U2TB and U0C0 to U2C0
UARTi Transmit/Receive Control Register 0 (i = 0 to 2)
Symbol Address After Reset
U0C0 00A4h 00001000b
U1C0 00ACh 00001000b
U2C0 0164h 00001000b
Bit Symbol Bit Name Function RW
NOTE:
1.
b3 b2
TXEPT
b1 b0
0
CLK0
—
Reserved bit
b7 b6 b5 b4
—
(b2)
CKPOL
CLK1 RW
BRG count source select
bits(1)
b1 b0
0 0 : Selects f1
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
RW
RW
RO
—
(b4)
CLK polarity select bit 0 : Transmit data is output at f alling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
Set to 0.
Transmit register empty
flag
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
If the BRG count source is sw itched, set the UiBRG register again.
RW
Data output select bit 0 : TXDi pin is for CMOS output
1 : TXDi pin is f or N-channel open-drain output
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
NCH
UARTi Transmit Buffer Register (i = 0 to 2)(1, 2)
Symbol Address After Reset
U0TB 00A3h-00A2h Undef ined
U1TB 00ABh-00AAh Undefined
U2TB 0163h-0162h Undefined
RW
NOTES:
1.
2.
(b15)
b7
(b8)
b0 b0b7
When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
Use the MOV instruction to w rite to this register.
Function
WO
—
Transmit data
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
(b8-b0)
—
(b15-b9)
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 379 of 580
REJ09B0324-0200
Figure 15.6 Registers U0C1 to U2C1 and U0RB to U2RB
UARTi Transmit/Receive Control Register 1 (i = 0 to 2)
Symbol Address After Reset
U0C1 00A5h 00000010b
U1C1 00ADh 00000010b
U2C1 0165h 00000010b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UARTi transmit interrupt cause
select bit
0 : Transmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1) RW
UiRRM UARTi continuous receive mode
enable bit(2)
0 : Disables continuous receive mode
1 : Enables continuous receive mode RW
The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
—
(b7-b6)
RO
RW
RI Receive complete flag(1) 0 : No data in UiRB register
1 : Data in UiRB register
RE
RW
TI RO
0 : Data in UiTB register
1 : No data in UiTB register
TE
—
Receive enable bit
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Transmit enable bit 0 : Disables transmission
1 : Enables transmission
Transmit buffer empty flag
0 : Disables reception
1 : Enables reception
UiIRS
UARTi Receive Buffer Register (i = 0 to 2)(1)
Symbol Address After Reset
U0RB 00A7h-00A6h Undefined
U1RB 00AFh-00AEh Undefined
U2RB 0167h-0166h Undefined
RW
NOTES:
1.
2.
—
—
(b7-b0) —
Function
Receive data (D7 to D0) RO
Receive data (D8) RO
—
(b8) —
b0b7
(b15)
b7
(b8)
b0
Bit Symbol Bit Name
OER Overrun error flag(2) 0 : No overrun error
1 : Overrun error RO
0 : No parity error
1 : Parity error RO
FER Framing error flag(2) 0 : No framing error
1 : Framing error RO
Nothing is assigned. If necessary, set to 0.
When read, the content is undef ined.
—
(b11-b9)
Read out the UiRB register in 16-bit units.
Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
ROSUM Error sum flag(2) 0 : No error
1 : Error
PER Parity error flag(2)
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 380 of 580
REJ09B0324-0200
Figure 15.7 U1SR Register
Figure 15.8 PM R Re gi st er
UART1 Function Select Register
Symbol Address Af ter Reset
U1SR 00F5h 000000XXb
Bit Symbol Bit Name Function RW
RW
RW
CLK11PSEL
CLK10PSEL
b3 b2
0 0 : CLK1 pin is not selected.
0 1 : Selects CLK1 (P0_5)
1 0 : Selects CLK1 (P6_5)
1 1 : Do not set.
—
b7 b6 b5 b4
—
b3 b2 b1 b0
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b4)
CLK1 pin select bits
—
(b1-b0)
Nothing is assigned. If necessary, set to 0 or 1.
When read, the content is undefined.
Port Mode Registe
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ pin select bit
INT2
_
____ pin select bit
IICSEL RW
0 : Selects SSU function
1 : Selects I
2C bus function
0 : Selects P6_6
1 : Selects P3_2
To use the UART1, set to 1.
Set to 0.
RW
SSU / I2C bus sw itch bit
RW
b0
RW
Reserved bits
U1PINSEL UART1 enable bit
INT2SEL
—
(b6-b5)
INT1SEL 0 : Selects P1_5, P1_7
1 : Selects P3_6
b3 b2
0
b1
0
b7 b6 b5 b4
00
RW
—
(b3-b2)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 381 of 580
REJ09B0324-0200
15.1 Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode(1).
i = 0 to 2
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Table 15.1 Clock Synchronous Serial I/O Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLKi pin
Transmit start conditions • Before transmission starts, the following requirements must be met(1)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Receive start conditions • Before reception starts, the following requirements must be met(1)
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected
- The UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- The UiIRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
Error detection • Overrun error(2)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
Select functions • CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the UiRB register.
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 382 of 580
REJ09B0324-0200
i = 0 to 2
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Register Bit Function
UiTB 0 to 7 Set data transmission
UiRB 0 to 7 Data reception can be read
OER Overrun error flag
UiBRG 0 to 7 Set bit rate
UiMR SMD2 to SMD0 Set to 001b
CKDIR Select the internal clock or external clock
UiC0 CLK1 to CLK0 Select the count source in the UiBRG register
TXEPT Transmit register empty flag
NCH Select TXDi pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to 1 to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to 1 to enable reception
RI Reception complete flag
UiIRS Select the UARTi transmit interrupt source
UiRRM Set this bit to 1 to use continuous receive mode
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 383 of 580
REJ09B0324-0200
Table 15.3 lists the I/O Pin Functions in Clock Sy nchronous Serial I/O Mode. The TXDi pin outputs “H” level
between the operating mode selection of UAR Ti (i = 0 to 2) and transfer start. (If the NCH bit is set to 1 (N-channel
open-drain output), this pin is in a high-impedance state.)
Table 15.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name Function Selection Method
TXD0 (P1_4) Output serial data (Outputs dummy data when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD1 (P6_6) Output serial data U1PINSEL bit in PMR register = 1
(Outputs dummy data when performing reception only)
RXD1 (P6_7) Input serial data U1PINSEL bit in PMR register = 1
PD6_7 bit in PD6 register = 0
(P6_7 can be used as an input port when performing
transmission only)
CLK1 (P0_5
or P6_5)
Output transfer clock • When CLK1 (P0_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 01b (P0_5)
CKDIR bit in U1MR register = 0
• When CLK1 (P6_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 10b (P6_5)
CKDIR bit in U1MR register = 0
Input transfer clock • When CLK1 (P0_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 01b (P0_5)
PD0_5 bit in PD0 register = 0
CKDIR bit in U1MR register = 1
• When CLK1 (P6_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 10b (P6_5)
PD6_5 bit in PD6 register = 0
CKDIR bit in U1MR register = 1
TXD2 (P6_3) Output serial data (Outputs dummy data when performing reception only)
RXD2 (P6_4) Input serial data PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
CLK2 (P6_5) Output transfer clock CKDIR bit in U2MR register = 0
Input transfer clock CKDIR bit in U2MR register = 1
PD6_6 bit in PD6 register = 0
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 384 of 580
REJ09B0324-0200
Figure 15.9 Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Transfer clock
D0
TE bit in UiC1
register
TXDi
• Example of transmit timing (when internal clock is selected)
Set data in UiTB register
Transfer from UiTB register to UARTi transmit register
TC
CLKi
TCLK Stop pulsing because the TE bit is set to 0
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
TC=TCLK=2(n+1)/fi
fi: Frequency of UiBRG count source (f1, f8, f32)
n: Setting value to UiBRG register
The above applies under the following settings:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
D0
Set to 0 when interrupt request is acknowledged, or set by a program
Write dummy data to UiTB register
Transfer from UiTB register to UARTi transmit register
1/fEXT
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
Receive data is taken in
Read out from UiRB register
Transfer from UARTi receive register to
UiRB register
TI bit in UiC1
register
1
0
1
0
1
0
1
0
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
Set to 0 when interrupt request is acknowledged, or set by a program
• Example of receive timing (when external clock is selected)
RE bit in UiC1
register
TE bit in UiC1
register
TI bit in UiC1
register
1
0
1
0
1
0
RI bit in UiC1
register
IR bit in SiRIC
register
1
0
1
0
CLKi
RXDi
The above applies under the following settings:
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
The following conditions are met when “H” is applied to the CLKi pin before receiving data:
• TE bit in UiC1 register = 1 (enables transmit)
• RE bit in UiC1 register = 1 (enables receive)
• Write dummy data to the UiTB register
fEXT: Frequency of external clock
i = 0 to 2
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 385 of 580
REJ09B0324-0200
15.1.1 Polarity Select Function
Figure 15.1 0 shows the Transfer Clock Polarity. Use the CKPOL bi t in the UiC0 (i = 0 to 2) register to select
the transfer clock polarity.
Figure 15.10 Transfer Clock Polarity
15.1.2 LSB First/MSB First Select Function
Figure 15.11 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 to 2) register to select the
transfer format.
Figure 15.11 Transfer Format
CLKi(1)
D0TXDi
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
edge and input receive data at the rising edge of the transfer clock)
D1 D2
NOTES:
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
D3 D4 D5 D6 D7
D0RXDi D1 D2 D3 D4 D5 D6 D7
CLKi(2)
D0TXDi D1 D2 D3 D4 D5 D6 D7
D0RXDi D1 D2 D3 D4 D5 D6 D7
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
edge and input receive data at the falling edge of the transfer clock)
i = 0 to 2
CLKi
D0
TXDi
• When UFORM bit in UiC0 register = 0 (LSB first)(1)
D1 D2 D3 D4 D5 D6 D7
D0RXDi D1 D2 D3 D4 D5 D6 D7
CLKi
D7
TXDi D6 D5 D4 D3 D2 D1 D0
RXDi
• When UFORM bit in UiC0 register = 1 (MSB first)(1)
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
D7 D6 D5 D4 D3 D2 D1 D0
i = 0 to 2
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 386 of 580
REJ09B0324-0200
15.1.3 Continuous Receive Mode
Continuous receive mode is selected by setting the UiRRM (i = 0 to 2) bit in the U iC1 regist er to 1 (ena bles
continuous receive mode). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data
in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a
program.
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 387 of 580
REJ09B0324-0200
15.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmi ssion and reception after setting the desired bit rate and transfer dat a format.
Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode.
i = 0 to 2
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Table 15.4 UART Mode Specifications
Item Specification
Transfer data formats • Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
Transfer clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
Transmit start conditions • Before transmission starts, the following are required
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
Receive start conditions • Before reception starts, the following are required
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
Interrupt request
generation timing
• When transmitting, one of the following conditions can be selected
- UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UARTi
transmit register
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when reception ends).
Error detection • Overrun error(1)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 388 of 580
REJ09B0324-0200
i = 0 to 2
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;
bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer
data is 8 bits long.
Table 15.5 Registers Used and Settings for UART Mode
Register Bit Function
UiTB 0 to 8 Set transmit data(1)
UiRB 0 to 8 Receive data can be read(1, 2)
OER,FER,PER,SUM Error flag
UiBRG 0 to 7 Set a bit rate
UiMR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long
Set to 101b when transfer data is 8 bits long
Set to 110b when transfer data is 9 bits long
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
TXEPT Transmit register empty flag
NCH Select TXDi pin output mode
CKPOL Set to 0
UFORM LSB first or MSB first can be selected when transfer data is 8 bits
long. Set to 0 when transfer data is 7 or 9 bits long.
UiC1 TE Set to 1 to enable transmit
TI Transmit buffer empty flag
RE Set to 1 to enable receive
RI Receive complete flag
UiIRS Select the source of UARTi transmit interrupt
UiRRM Set to 0
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 389 of 580
REJ09B0324-0200
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 to 2) operating mode is selected, the
TXDi pin outputs “H ” level. (If the NCH bit is set to 1 (N-channel open-drain ou tput), this pin is in a high-
impedance state) until transfer starts.)
Table 15.6 I/O Pin Functions in UART Mode
Pin name Function Selection Method
TXD0 (P1_4) Output serial data (Cannot be used as a port when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD1 (P6_6) Output serial data U1PINSEL bit in PMR register = 1
(Cannot be used as a port when performing reception only)
RXD1 (P6_7) Input serial data U1PINSEL bit in PMR register = 1
PD6_7 bit in PD6 register = 0
(P6_7 can be used as an input port when performing
transmission only)
CLK1 (P0_5
or P6_5)
Programmable I/O Port Bits CLK11PSEL to CLK10PSEL in U1SR register = 00b
(CLK1 pin is not selected)
Input transfer clock • When CLK1 (P0_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 01b (P0_5)
PD0_5 bit in PD0 register = 0
CKDIR bit in U1MR register = 1
• When CLK1 (P6_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 10b (P6_5)
PD6_5 bit in PD6 register = 0
CKDIR bit in U1MR register = 1
TXD2 (P6_3) Output serial data (Cannot be used as a port when performing reception only)
RXD2 (P6_4) Input serial data PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
CLK2 (P6_5) Programmable I/O Port CKDIR bit in U2MR register = 0
Input transfer clock CKDIR bit in U2MR register = 1
PD6_6 bit in PD6 register = 0
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 390 of 580
REJ09B0324-0200
Figure 15.12 Transmit Timing in UART Mode
D0
TC
D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST
D0
TC
D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST
Transfer clock
TE bit in UiC1
register
TXDi
Set to 0 when interrupt request is acknowledged, or set by a program
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
Write data to UiTB register
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 to 2
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
Start
bit Parity
bit
Stop pulsing
because the TE bit is set to 0
TXDi
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
TI bit in UiC1
register
1
0
1
0
1
0
1
0
TXEPT bit in
UiC0 register
IR bit SiTIC
register
Stop
bit
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
1
0
Stop
bit
Stop
bit
Start
bit
Transfer clock
TE bit in UiC1
register
TI bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
1
0
1
0
1
0
Transfer from UiTB register to UARTi transmit register
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 to 2
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 391 of 580
REJ09B0324-0200
Figure 15.13 Receive Timing Example in UART Mode
UiBRG output
Set to 0 when interrupt request is accepted, or set by a program
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
The above timing diagram applies when the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
i = 0 to 2
UiC1 register
RE bit
Start bit
Stop bit
D0 D1 D7
RXDi
Transfer clock
Determined to be “L” Receive data taken in
Reception triggered when transfer clock
is generated by falling edge of start bit Transferred from UARTi receive
register to UiRB register
UiC1 register
RI bit
SiRIC register
IR bit
1
0
1
0
1
0
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 392 of 580
REJ09B0324-0200
15.2.1 Bit Rate
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 to 2) register.
Figure 15.1 4 Calcula ti on Formu la of UiBRG (i = 0 to 2) Register Setting Value
i = 0 to 2
Table 15.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected)
Bit Rate
(bps)
BRG
Count
Source
System Clock = 20 MHz System Clock = 8 MHz
UiBRG
Setting Value
Actual Time
(bps) Error (%) UiBRG
Setting Value
Actual
Time (bps) Error (%)
1200 f8 129 (81h) 1201.92 0.16 51 (33h) 1201.92 0.16
2400 f8 64 (40h) 2403.85 0.16 25 (19h) 2403.85 0.16
4800 f8 32 (20h) 4734.85 -1.36 12 (0Ch) 4807.69 0.16
9600 f1 129 (81h) 9615.38 0.16 51 (33h) 9615.38 0.16
14400 f1 86 (56h) 14367.82 -0.22 34 (22h) 14285.71 -0.79
19200 f1 64 (40h) 19230.77 0.16 25 (19h) 19230.77 0.16
28800 f1 42 (2Ah) 29069.77 0.94 16 (10h) 29411.76 2.12
31250 f1 39 (27h) 31250.00 0.00 15 (0Fh) 31250.00 0.00
38400 f1 32 (20h) 37878.79 -1.36 12 (0Ch) 38461.54 0.16
51200 f1 23 (17h) 52083.33 1.73 9 (09h) 50000.00 -2.34
UART mode
• Internal clock selected
UiBRG register setting value = fj
Bit Rate × 16 - 1
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
• External clock selected
fEXT
Bit Rate × 16 - 1
fEXT: Count source frequency of the UiBRG register (external clock)
UiBRG register setting value =
i = 0 to 2
R8C/2A Group, R8C/2B Group 15. Serial Interface
Rev.2.00 Nov 26, 2007 Page 393 of 580
REJ09B0324-0200
15.3 Notes on Serial Interface
•When reading data from the UiRB (i = 0 to 2) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
•When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit un its.
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 394 of 580
REJ09B0324-0200
16. Clock Synchronous Serial Interface
The clock synchronous serial interface is configured as follows.
Clock synchronous serial interface
The clock synchronous serial interface uses the registers at addresses 00B8h to 0 0BFh. Registers, bits, symbols, and
functions vary even for the same addresses depending on the mode. Refer to the regi st er diagrams of each functio n for
details.
Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the
options of the transfer clock, clock output format, and data outpu t format .
16.1 Mode Selection
The clock synchronous serial interface has four modes.
Table 16.1lists the Mode Selections. Refer to 16.2 Clock Synchronous Serial I/ O with Chip Select (S SU) and the
sections that follow for details of each mode.
Clock synchronous serial I/O with chip select (SSU) Clock synchro nous communication mode
4-wire bus communication mode
I2C bus Interface I2C bus interface mode
Clock synchronous seri al mode
Table 16.1 Mode Selections
IICSEL Bit
in PMR
Register
Bit 7 in 00B8h
(ICE Bit in ICCR1
Register)
Bit 0 in 00BDh
(SSUMS Bit in SSMR2
Register, FS Bit in
SAR Register)
Function Mode
0 0 0 Clock synchronous
serial I/O with chip
select
Clock synchronous
communication mode
0 0 1 4-wire bus communication mode
11 0 I2C bus interface I2C bus interface mode
1 1 1 Clock synchronous serial mode
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 395 of 580
REJ09B0324-0200
16.2 Clock Synchronous Serial I/O with Chip Select (SSU)
Clock synchronous serial I/O with chip select supports clock synchronous serial data communication .
Table 16.2 shows a Clock Synchrono us Serial I/O with Chip Select Sp ecifications and Fi gure 16.1 shows a Blo ck
Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16 .10 show clock synchronous serial
I/O with chip select associated registers.
NOTE:
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
Operating modes • Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Master/slave device Selectable
I/O pins SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
Transfer clocks • When the MSS bit in the SSCRH register is set to 0 (operates as slave
device), external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected.
Receive error detection • Overrun error
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
Multimaster error
detection
• Conflict error
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Interrupt requests 5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error)(1).
Select functions • Data transfer direction
Selects MSB-first or LSB-first
• SSCK clock polarity
Selects “L” or “H” level when clock stops
• SSCK clock phase
Selects edge of data change and data download
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 396 of 580
REJ09B0324-0200
Figure 16.1 Block Diagram of Clock Synchronous Serial I/O wit h Chip Select
Figure 16.2 MSTCR Register
SSMR register
Data bus
Transmit/receive
control circuit
SSCRL register
SSCRH register
SSER register
SSSR register
SSMR2 register
SSTDR register
SSTRSR register
SSRDR register
Selector
Multiplexer
SSO
SSI
SCS
SSCK
Interrupt requests
(TXI, TEI, RXI, OEI, and CEI)
Internal clock
generation
circuit
f1
Internal clock (f1/i)
i = 4, 8, 16, 32, 64, 128, or 256
Module Operation Enable Register
Symbol Address After Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 397 of 580
REJ09B0324-0200
Figure 16.3 SSCRH Register
SS Control Register H
Symbol Address After Reset
SSCRH 00B8h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 (operates as master device).
The MSS bit is set to 0 (operates as slave device) w hen the CE bit in the SSSR register is set to 1 (conf lict error
occurs).
RSSTP
Receive single stop bit(3) 0 : Maintains receive operation af ter
receiving 1 byte of data
1 : Completes receive operation after
receiving 1 byte of data
RW
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
The set clock is used w hen the internal clock is selected.
—
Master/slave device select bit(2) 0 : Operates as slave device
1 : Operates as master device RWMSS
—
(b4-b3) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
CKS1
CKS2
Transfer clock rate select bits(1) b2 b1 b0
0 0 0 : f1/256
0 0 1 : f1/128
0 1 0 : f1/64
0 1 1 : f1/32
1 0 0 : f1/16
1 0 1 : f1/8
1 1 0 : f1/4
1 1 1 : Do not set.
CKS0 RW
RW
RW
The RSSTP bit is disabled w hen the MSS bit is set to 0 (operates as slave device).
b7 b6 b5 b4 b3 b2 b1 b0
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 398 of 580
REJ09B0324-0200
Figure 16.4 SSCRL Register
SS Control Register L
Symbol Address After Reset
SSCRL 00B9h 01111101b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
—
(b0) —
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SRES
Clock synchronous
serial I/O w ith chip
select control part
reset bit
When this bit is set to 1, the clock synchronous serial
I/O w ith chip select control block and SSTRSR register
are reset.
The values of the registers(1) in the clock synchronous
serial I/O w ith chip select register are maintained.
RW
b3 b2 b1 b0b7 b6 b5 b4
—
(b3-b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
SOLP
SOL w rite protect bit(2) The output level can be changed by the SOL bit w hen
this bit is set to 0.
The SOLP bit remains unchanged even if 1 is w ritten to
it. When read, the content is 1.
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0. —
SOL
Serial data output value
setting bit
When read
0 : The serial data output is set to “L”.
1 : The serial data output is set to “H”.
When w ritten(2,3)
0 : The data output is “L” after the serial data output.
1 : The data output is “H” after the serial data output.
RW
Do not w rite to the SOL bit during data transfer.
The data output after serial data is output can be changed by w riting to the SOL bit before or after transfer. When
w riting to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction.
Registers SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 399 of 580
REJ09B0324-0200
Figure 16.5 SSMR Register
SS Mode Register
Symbol Address After Reset
SSMR 00BAh 00011000b
Bit Symbol Bit Name Function RW
Res er v ed bit
NOTE:
1.
1
MSB first/LSB first select bit
MLS
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
(b3)
—
(b4)
CPHS
b3 b2 b1 b0b7 b6 b5 b4
SSCK clock phase select bit(1) 0 : Change data at odd edge
(Dow nload data at even edge)
1 : Change data at even edge
(Dow nload data at odd edge)
CPOS SSCK clock polarity select bit(1)
RO
BC1
BC2
Bits counter 2 to 0 b2 b1 b0
0 0 0 : 8 bits left
0 0 1 : 1 bit left
0 1 0 : 2 bits left
0 1 1 : 3 bits left
1 0 0 : 4 bits left
1 0 1 : 5 bits left
1 1 0 : 6 bits left
1 1 1 : 7 bits left
BC0
RO
RO
0 : “H” w hen clock stops
1 : “L” w hen clock stops
Set to 1.
When read, the content is 1.
RW
RW
RW
—
RW
0 : Transf ers data MSB first
1 : Transf ers data LSB first
Ref er to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
and CPOS bits.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 400 of 580
REJ09B0324-0200
Figure 16.6 SSER Register
SS Enable Register
Symbol Address After Reset
SSER 00BBh 00h
Bit Symbol Bit Name Function RW
b0b3 b2 b1
CEIE
b7 b6 b5 b4
RW
RW
RW
—
Conflict error interrupt enable bit 0 : Disables conf lict error interrupt request
1 : Enables conflict error interrupt request
—
(b2-b1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RE
TE
TEIE Transmit end interrupt enable bit RW
RIE
TIE
Transmit interrupt enable bit 0 : Disables transmit data empty interrupt
request
1 : Enables transmit data empty interrupt
request
0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
RW
Receive enable bit 0 : Disables receive
1 : Enables receive
Transmit enable bit 0 : Disables transmit
1 : Enables transmit
0 : Disables receive data f ull and overrun
error interrupt request
1 : Enables receive data full and overrun
error interrupt request
Receive interrupt enable bit
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 401 of 580
REJ09B0324-0200
Figure 16.7 SSSR Register
SS Status Register(7)
Symbol Address After Reset
SSSR 00BCh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
b0
Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0.
The RDRF bit is set to 0 w hen readin
g
out the data from the SSRDR re
g
ister.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TDRE
Transmit data empty(1, 5, 6) 0 : Data is not transferred from registers SSTDR to
SSTRSR
1 : Data is transferred from registers SSTDR to
SSTRSR
RW
b3 b2 b1b7 b6 b5 b4
RDRF Receive data register full
(1,4)
—
(b1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
0 : No data in SSRDR register
1 : Data in SSRDR r egis ter
ORER
—
(b4-b3)
RW
RW
—
Conflict error flag(1) 0 : No conflict errors generated
1 : Conflict errors generated(2)
CE
—
Bits TEND and TDRE are set to 0 w hen w ritin
g
data to the SSTDR re
g
ister.
Overrun error flag(1) 0 : No overrun errors generated
1 : Overrun errors generated(3)
TEND
Transmit end(1, 5) 0 : The TDRE bit is set to 0 w hen transmitting
the last bit of transmit data
1 : The TDRE bit is set to 1 w hen transmitting
the last bit of transmit data
RW
RW
When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive
operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the
ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1.
The TDRE bit is set to 1 w hen the TE bit in the SSER re
g
ister is set to 1
(
transmit enabled
)
.
When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set
to 1 if “L” is applied to the SCS
_
____ pin input. Refer to 16.2.7 SCS
_
____ Pin Control and A rbi tration for more information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operates as slave device) and the SCS
_
____ pin input changes the level from “L” to “H” during
transfer, the CE bit is set to 1.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 402 of 580
REJ09B0324-0200
Figure 16.8 SSMR2 Register
SS Mode Register 2
Symbol Address After Reset
SSMR2 00BDh 00h
Bit Symbol Bit Name Function RW
SCS
_
____ pin open drain output 0 : CMOS output
select bit 1 : N-channel open-drain output
SCS
_
____ pin select bits(2) b5 b4
0 0 : Functions as port
0 1 : Functions as SCS
_
____ input pin
1 0 : Functions as SCS
_
____ output pin(3)
1 1 : Functions as SCS
_
____ output pin(3)
NOTES:
1.
2.
3.
4.
5. The SSI pin and SSO pin corresponding port direction bits are set to 0 (input mode) w hen the SOOS bit is set to 0
(CMOS output).
The BIDE bit is disabled w hen the SSUMS bit is set to 0 (clock synchronous communication mode).
RWBIDE
Bidirectional mode enable bit(1, 4) 0 : Standard mode (communication using 2
pins of data input and data output)
1 : Bidirectional mode (communication using
1 pin of data input and data output)
Thi
s
bi
t
f
unct
i
ons as t
h
e
SCS
i
nput p
i
n
b
e
f
ore start
i
ng trans
f
er.
(clock synchronous communication mode).
RW
RW
RW
RW
RW
RW
0 : Clock synchronous communication mode
1 : Four-w ire bus communication mode
SSCK pin open drain output
select bit
0 : CMOS output
1 :N-channel open-drain output
CSS1
Clock synchronous serial I/O w ith
chip select mode select bit(1)
Serial data pin open output drain
select bit(1)
0 : CMOS output(5)
1 : N-channel open-drain output
CSS0
SOOS
SCKOS
SSUMS
CSOS
b2 b1b7 b6 b5 b4 b0
Ref er to 16.2.2.1 Association between Data I/O Pins and S S S hift Register for information on combinations of
data I/O pins.
The SCS
_
____ pin functions as a port, regardless of the values of bits CSS0 and CSS1 w hen the SSUMS bit is set to 0
SCKS SSCK pin select bit 0 : Functions as port
1 : Functions as serial clock pin RW
b3
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 403 of 580
REJ09B0324-0200
Figure 16.9 Registers SSTDR and SSRDR
Figure 16.1 0 PMR Regi st er
SS Transmit Data Register
Symbol Address After Reset
SSTDR 00BEh FFh
RW
b3b7 b6 b5 b4 b2
RW
b1
Function
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from
the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
b0
SS Receive Data Register
Symbol Address After Reset
SSRDR 00BFh FFh
RW
NOTE:
1. The SSRDR register retains the data received bef ore an overrun error occurs (ORER bit in the SSSR register set to 1
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Store the receive data.(1)
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
RO
Function
b7 b6 b5 b4 b3 b2 b1 b0
Port Mode Registe
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ pin select bit
INT2
_
____ pin select bit
IICSEL RW
0 : Selects SSU function
1 : Selects I
2C bus function
0 : Selects P6_6
1 : Selects P3_2
To use the UART1, set to 1.
Set to 0.
RW
SSU / I2C bus sw itch bit
RW
b0
RW
Reserved bits
U1PINSEL UART1 enable bit
INT2SEL
—
(b6-b5)
INT1SEL 0 : Selects P1_5, P1_7
1 : Selects P3_6
b3 b2
0
b1
0
b7 b6 b5 b4
00
RW
—
(b3-b2)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 404 of 580
REJ09B0324-0200
16.2.1 Transfer Clock
The transfer clock can be selected from among se ven intern al clocks (f1/ 256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using clock synchronous serial I/O with chi p select, set the SCKS bit in the SSMR2 register to 1 and
select the SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
16.2.1.1 Association between Transfer Clock Polarity, Phase, and Data
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 16.11 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 405 of 580
REJ09B0324-0200
Figure 16.11 Association between Transfer Clock Polarity, Phase, and Transfer Data
SSCK
b0
SSO, SSI
• SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd
edge), and CPOS bit = 0 (“H” when clock stops)
b1 b2 b3 b4 b5 b6 b7
SSCK
CPOS = 0
(“H” when clock stops)
b0SSO, SSI
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge)
b1 b2 b3 b4 b5 b6 b7
SSCK
CPOS = 1
(“L” when clock stops)
SCS
SSCK
CPOS = 0
(“H” when clock stops)
SSO, SSI
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge)
SSCK
CPOS = 1
(“L” when clock stops)
SCS
b0 b1 b2 b3 b4 b5 b6 b7
CPHS and CPOS: Bits in SSMR register, SSUMS: Bits in SSMR2 register
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 406 of 580
REJ09B0324-0200
16.2.2 SS Shift Register (SSTRSR)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferr ed to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
16.2.2.1 Association between Data I/O Pins and SS Shift Register
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUM S bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 16.12 shows the Association between Data I/O Pins and SSTRSR Register.
Figure 16.12 Association between Data I/O Pins and SSTRSR Register
SSTRSR register SSO
SSI
• SSUMS = 0
(clock synchronous communication mode)
SSTRSR register SSO
SSI
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 0 (operates
as slave device)
SSTRSR register SSO
SSI
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
SSTRSR register SSO
SSI
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 1 (bidirectional mode)
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 407 of 580
REJ09B0324-0200
16.2.3 Interrupt Requests
Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock
synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.
Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests.
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
If the generation condit ions in Tabl e 16.3 are met, a clock syn chro nous serial I/O w ith chip select interrupt request
is generated. Set each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transm it data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
Table 16.3 Clock Synchronous Serial I/O with Chip Select Interrupt Requests
Interrupt Request Abbreviation Generation Condition
Transmit data empty TXI TIE = 1, TDRE = 1
Transmit end TEI TEIE = 1, TEND = 1
Receive data full RXI RIE = 1, RDRF = 1
Overrun error OEI RIE = 1, ORER = 1
Conflict error CEI CEIE = 1, CE = 1
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 408 of 580
REJ09B0324-0200
16.2.4 Communication Modes and Pin Functions
Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication
mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Table 16.4 shows the Association between Comm unication Modes and I/O Pins.
NOTES:
1. This pin can be used as a programmable I/O port.
2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode.
SSUMS and BIDE: Bits in SSMR2 register
MSS: Bit in SSCRH register
TE and RE: Bits in SSER register
Table 16.4 Association between Communication Modes and I/O Pins
Communication Mode Bit Setting Pin State
SSUMS BIDE MSS TE RE SSI SSO SSCK
Clock synchronous
communication mode
0Disabled001Input
−(1) Input
10−(1) Output Input
1 Input Output Input
101Input
−(1) Output
10−(1) Output Output
1 Input Output Output
4-wire bus
communication mode
10 001−(1) Input Input
1 0 Output −(1) Input
1 Output Input Input
101Input
−(1) Output
10−(1) Output Output
1 Input Output Output
4-wire bus
(bidirectional)
communication mode(2)
11 001−(1) Input Input
10−(1) Output Input
101−(1) Input Output
10−(1) Output Output
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 409 of 580
REJ09B0324-0200
16.2.5 Clock Synchronous Communication Mode
16.2.5.1 Initialization in Clock Synchronous Communication Mode
Figure 16.13 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in
the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or
reception.
Set the TE bit to 0 and the RE bit to 0 before changing the communicati on mode or format.
Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR
register.
Figure 16.13 Initialization in Clock Synchronous Communication Mode
Start
SSMR2 register SSUMS bit ← 0
SSCRH register Set bits CKS0 to CKS2
Set RSSTP bit
SSSR register ORER bit ← 0(1)
SSER register RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
SSER register RE bit ← 0
TE bit ← 0
SSMR2 register SCKS bit ← 1
Set SOOS bit
SSCRH register Set MSS bit
SSMR register CPHS bit ← 0
CPOS bit ← 0
Set MLS bit
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 410 of 580
REJ09B0324-0200
16.2.5.2 Dat a Transmission
Figure 16.14 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode). During data transmission, the clock synchronous
serial I/O with chip select operates as described below.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and
data. When clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized
with the input clock.
When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE
bit is automatically set to 0 (data not tran sferred from registers SSTDR to SSTRSR) and the data is transferred
from registers SSTDR to SSTRSR.
After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When
the TIE bit in the SSER register is set to 1, the TXI in terrupt request is g enerated. When one frame of data is
transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and
transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND
bit in the SSSR register is set to 1 (the TDRE bit is set to 1 w hen the last b it of t he transmit d ata is transmitt ed )
and the state is retained. The TEI in terrupt request is generated when the TEIE bit i n t he SSER register is set to
1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 16.15 shows a Sample Flowch art of Da ta Transmission (Clock Synchronous Communication Mode).
Figure 16.14 Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode)
SSCK
b0
SSO
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at
odd numbers), and CPOS = 0 (“H” when clock stops)
b1 b7b0 b1b7
1 frame
TDRE bit in
SSSR register 0
1
TEND bit in
SSSR register 0
1
TEI interrupt request
generation
Write data to SSTDR register
Processing
by program
1 frame
TXI interrupt request generation
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 411 of 580
REJ09B0324-0200
Figure 16.15 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)
Start
Initialization
Read TDRE bit in SSSR register
SSSR register TEND bit ← 0(1)
End
TDRE = 1 ?
Write transmit data to SSTDR register
Data
transmission
continues?
Read TEND bit in SSSR register
TEND = 1 ?
No
Yes
Yes
No
No
Yes
SSER register TE bit ← 0
(1)
(2)
(3)
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
(2) Determine whether data transmission continues.
(3) When data transmission is completed, the TEND
bit is set to 1. Set the TEND bit to 0 and the TE bit
to 0 and complete transmit mode.
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 412 of 580
REJ09B0324-0200
16.2.5.3 Dat a Reception
Figure 16.16 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode).
During data reception, clock synchronous serial I/O with chip select operates as described below. When the
clock synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and
inputs data. When clock synchronous serial I/O with chip select is set as a slave device, it inputs data
synchronized with the input clock.
When clock synchronous serial I/O with chip select is s et as a master device, it outputs a receive clock and starts
receiving by performing dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, th e ORER b it in t he SSSR register is set to 1 (ove rrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm
that the ORER bit is set to 0 before restarting receive.
Figure 16.17 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
Figure 16.16 Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode)
SSCK
b0
SSI
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at
even edges), and CPOS bit = 0 (“H” when clock stops)
b0b7
1 frame
RDRF bit in
SSSR register 0
1
RSSTP bit in
SSCRH register 0
1
Dummy read in
SSRDR register
Processing
by program
RXI interrupt request
generation
b0
b7 b7
1 frame
RXI interrupt request
generation
Read data in SSRDR
register
Read data in
SSRDR register
Set RSSTP bit to 1
RXI interrupt request
generation
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 413 of 580
REJ09B0324-0200
Figure 16.17 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode)
Start
Initialization
Dummy read of SSRDR register
Read receive data in SSRDR register
Read ORER bit in SSSR register
Last data
received?
Read RDRF bit in SSSR register
RDRF = 1 ?
No
Yes
Yes
No
No
Yes
(1)
(2)
(3)
(1) After setting each register in the clock synchronous
serial I/O with chip select register, a dummy read of
the SSRDR register is performed and the receive
operation is started.
(2) Determine whether it is the last 1 byte of data to be
received. If so, set to stop after the data is received.
(3) If a receive error occurs, perform error
(6) Processing after reading the ORER bit. Then set
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
(4) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
ORER = 1 ?
End
Read receive data in SSRDR register
Read ORER bit in SSSR register
Read RDRF in SSSR register
RDRF = 1 ?
No
Yes
ORER = 1 ?
SSER register RE bit ← 0
SSCRH register RSSTP bit ← 0
SSCRH register RSSTP bit ← 1
Overrun
error
processing
No
Yes
(4)
(5)
(6)
(7)
(7) Confirm that the RDRF bit is set to 1. When the
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.
(5)Before the last 1 byte of data is received, set the
RSSTP bit to 1 and stop after the data is
received.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 414 of 580
REJ09B0324-0200
16.2.5.4 Dat a Transmission/Reception
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is
transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 16.18 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 415 of 580
REJ09B0324-0200
Figure 16.18 Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Communication Mode)
Start
Initialization
Read TDRE bit in SSSR register
SSSR register TEND bit ← 0(1)
End
TDRE = 1 ?
Write transmit data to SSTDR register
Data
transmission(2)
continues?
No
Yes
Yes
No
SSER register RE bit ← 0
TE bit ← 0
(1)
(2)
(3)
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
receive mode.
Read receive data in SSRDR register
Read RDRF bit in SSSR register
RDRF = 1 ?
No
Yes
(4)
(2) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
(3) Determine whether the data transmission
continues
(5)
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Read TEND bit in SSSR register
TEND = 1 ?
Yes
No
(6)
(4) When the data transmission is completed, the
TEND bit in the SSSR register is set to 1.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 416 of 580
REJ09B0324-0200
16.2.6 Operation in 4-Wire Bus Communication Mode
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line,
and a chip select line is used for communication. This mode includes bidirectional mode in which the data input
line and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and
the BIDE bit in the SSMR2 register. For det ails, refer to 16.2.2.1 Association between Data I/O Pins and SS
Shift Register . In this mode , clock polarity, phase, and data set tings are p erfo rmed by bit s CPOS an d C PHS in
the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and
Data.
When this MCU is set as the master device, the chip select line controls output. When clock sync hro nous serial
I/O with chip select is set as a slave device, the chip select line controls input. When it is set as the master
device, the chip select line controls output of the SCS pin or controls output of a general port according to the
setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets
the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b .
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is
performed MSB-first.
16.2.6.1 Initialization in 4-Wire Bus Communication Mode
Figure 16.19 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive
operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0
(receive disabled), and initialize the clock synchro nous serial I/O with chip select.
To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.
Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR
register.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 417 of 580
REJ09B0324-0200
Figure 16.19 Initialization in 4-Wire Bus Communication Mode
Start
SSMR2 register SSUMS bit ← 1
SSSR register ORER bit ← 0(1)
SSER register RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
SSER register RE bit ← 0
TE bit ← 0
(2) Set the BIDE bit to 1 in bidirectional mode and
set the I/O of the SCS pin by bits CSS0 and
CSS1.
(1) (1) The MLS bit is set to 0 for MSB-first transfer.
The clock polarity and phase are set by bits
CPHS and CPOS.
(2)
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
SSMR2 register SCKS bit ← 1
Set bits SOOS, CSS0 to
CSS1, and BIDE
SSCRH register Set MSS bit
SSMR register Set bits CPHS and CPOS
MLS bits ← 0
SSCRH register Set bits CKS0 to CKS2
Set RSSTP bit
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 418 of 580
REJ09B0324-0200
16.2.6.2 Dat a Transmission
Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation durin g Data
Transmission (4-Wire Bus Communicatio n Mode). During the data transmit operation , clock synchronous
serial I/O with chip select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data in synchroni zation with the input clock while the SCS pin is “L”.
When the transmit data is writ ten to the SSTDR register after set ting the TE bit to 1 (transmit enab led), the
TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the
data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from
registers SSTDR to SSTRSR), transmission star ts. When the TIE bit in the SSER register is set to 1, a TXI
interrupt request is generated.
After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR
to SSTRSR and transmission of th e next frame is started. If the 8th bit is transm itted while TDRE is set to 1,
TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted , the TDRE bit is set
to 1) and the stat e is retained. If the TEIE bit in the SSER reg ister is set to 1 (tran smit-end inte rrupt requests
enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is
held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the
SSTDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while
the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in
high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16 .15
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 419 of 580
REJ09B0324-0200
Figure 16.20 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode)
TDRE bit in
SSSR register 0
1
TEND bit in
SSSR register 0
1
Data write to SSTDR register
Processing
by program
SSCK
b0SSO
• CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops)
b7
SCS
(output)
SSCK
• CPHS bit = 1 (data change at even edges) and CPOS bit = 0 (“H” when clock stops)
CPHS, CPOS: Bits in SSMR register
1 frame
TDRE bit in
SSSR register 0
1
TEND bit in
SSSR register 0
1
Data write to SSTDR register
Processing
by program
1 frame
High-impedance
b0b7
High-impedance
SCS
(output)
TXI interrupt request is
generated
b7 b0SSO
1 frame 1 frame
b6 b6
TXI interrupt request is
generated
TEI interrupt request is
generated
b6 b7 b0b6
TEI interrupt request is
generated
TXI interrupt request is
generated
TXI interrupt request is
generated
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 420 of 580
REJ09B0324-0200
16.2.6.3 Dat a Reception
Figure 16.21 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation durin g Data
Reception (4-Wire Bus Communication Mode). During data reception, clock synchronous serial I/O with chip
select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives “L” input.
When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a
dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF
bit is automatical ly set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, th e ORER b it in t he SSSR register is set to 1 (ove rrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the
SSMR register. Figure 16.21 shows when bits RDRF and ORER are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some
point during the frame.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16 .17
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 421 of 580
REJ09B0324-0200
Figure 16.21 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode)
SSCK
b0SSI
• CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)
b7
SCS
(output)
SSCK
• CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)
CPHS and CPOS: Bit in SSMR register
1 frame
RDRF bit in
SSSR register 0
1
RSSTP bit in
SSCRH register 0
1
Dummy read in
SSRDR register
Processing
by program
1 frame
High-impedance
b0b7
High-impedance
SCS
(output)
b7 b0
Data read in SSRDR
register
RXI interrupt request
is generated
RXI interrupt request
is generated
Data read in SSRDR
register
RXI interrupt request
is generated
b0b7b0b7
b7 b0SSI
1 frame
RDRF bit in
SSSR register 0
1
RSSTP bit in
SSCRH register 0
1
Dummy read in
SSRDR register
Processing
by program
1 frame
Data read in SSRDR
register
RXI interrupt request
is generated
RXI interrupt request
is generated RXI interrupt request
is generated
Set RSSTP
bit to 1
Data read in SSRDR
register
Set RSSTP
bit to 1
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 422 of 580
REJ09B0324-0200
16.2.7 SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output p in), set th e MSS bit i n the SSCRH regi ster to 1 (operat es as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If clock synchronous
serial I/O with chip select detects that the synchronized internal SCS signal is held “L” in this period, the CE bit
in the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 16.22 shows the Arbitration Check Timing.
Future transmit operatio ns are not performed wh ile the CE bit is set to 1. Set the CE bit to 0 (no con flict error)
before starting transmission.
Figure 16.22 Arbitration Check Timing
Data write to
SSTDR register
Maximum time of SCS internal
synchronization
During arbitration detection
High-impedance
SCS input
Internal SCS
(synchronization)
MSS bit in
SSCRH register
Transfer start
CE
SCS output
0
1
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 423 of 580
REJ09B0324-0200
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 424 of 580
REJ09B0324-0200
16.3 I2C bus Interface
The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the
Philips I2C bus.
Table 16.5 lists the I2C bus Interface Specifications, Figure 16.23 shows a Block Diagram of I 2C bus interface, and
Figure 16.24 shows the External Circuit Connection Exam ple of Pins SCL and SDA. Figures 16.25 to 16.33 show
the registers associated with the I2C bus interface.
* I2C bus is a trademark of Koninklijke Philip s Electronics N. V.
NOTE:
1. All sources use one interrupt vector for I2C bus interface.
Table 16.5 I2C bus Interface Specifications
Item Specification
Communication formats •I
2C bus format
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
- Start/stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (N-channel open-drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
I/O pins SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks • When the MST bit in the ICCR1 register is set to 0
The external clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1
The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next data
item is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
Interrupt sources •I
2C bus format .................................. 6 sources(1)
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection.
• Clock synchronous serial format ...... 4 sources(1)
Transmit data empty, transmit ends, receive data full and overrun error
Select functions •I
2C bus format
- Selectable output level for acknowledge signal during reception
• Clock synchronous serial format
- MSB-first or LSB-first selectable as data transfer direction
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 425 of 580
REJ09B0324-0200
Figure 16.23 Block Diagram of I2C bus interface
ICCR1 register
Data bus
ICCR2 register
ICMR register
ICDRT register
SAR register
ICSR register
Address comparison
circuit
Output
control
SCL
Interrupt request
(TXI, TEI, RXI, STPI, NAKI)
Transfer clock
generation
circuit
ICDRS register
ICDRR register
Bus state judgment
circuit
Arbitration judgment
circuit
ICIER register
Interrupt generation
circuit
Transmit/receive
control circuit
Noise
canceller
SDA Output
control
f1
Noise
canceller
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 426 of 580
REJ09B0324-0200
Figure 16.24 External Circuit Connection Example of Pins SCL and SDA
Figure 16.2 5 MSTCR Regist e r
SCL
SDA
SCL input
SCL output
SDA input
SDA output
(Master)
VCC VCC
SCL
SDA
SCL input
SCL output
SDA input
SDA output
(Slave 1)
SCL
SDA
SCL input
SCL output
SDA input
SDA output
SCL
SDA
(Slave 2)
Module Operation Enable Register
Symbol Address Af ter Reset
MSTCR 0008h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
—
—
(b7-b6)
—
Timer RD operation enable bit
SSU, I2C bus operation enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
0: Disable(2)
1: Enable
Timer RC operation enable bit
RW
—
(b2-b0)
MSTIIC
b7 b6 b5 b4
0: Disable(3)
1: Enable
0: Disable(1)
1: Enable
b3 b2
MSTTRC
b1 b0
MSTTRD
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 427 of 580
REJ09B0324-0200
Figure 16.26 ICCR1 Register
IIC bus Control Register 1
Symbol Address After Reset
ICCR1 00B8h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6. In multimaster operation use the MOV instruction to set bits TRS and MST.
When the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
RWICE
IIC bus interface enable bit 0 : This module is halted
(Pins SCL and SDA are set to port f unction)
1 : This module is enabled for transfer
operations
(Pins SCL and SDA are bus drive state)
Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate Examples for the
transfer rate. This bit is used for maintaining of the setup time in transmit mode of slave mode. The time is 10Tcyc
w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
RW
TRS
Transmit clock select bits 3 to
0(1)
b3 b2 b1 b0
0 0 0 0 : f 1/28
0 0 0 1 : f 1/40
0 0 1 0 : f 1/48
0 0 1 1 : f 1/64
0 1 0 0 : f 1/80
0 1 0 1 : f 1/100
0 1 1 0 : f 1/112
0 1 1 1 : f 1/128
1 0 0 0 : f 1/56
1 0 0 1 : f 1/80
1 0 1 0 : f 1/96
1 0 1 1 : f 1/128
1 1 0 0 : f 1/160
1 1 0 1 : f 1/200
1 1 1 0 : f 1/224
1 1 1 1 : f 1/256
b5 b4
0 0 : Slave Receive Mode(4)
0 1 : Slave Transmit Mode
1 0 : Master Receive Mode
1 1 : Master Transmit Mode
RW
MST RW
RW
Transfer/receive select
bit(2, 3, 6)
CKS2
CKS3
CKS0
CKS1
RW
RW
b1b7 b6 b5 b4 b3 b2
Master/slave select bit(5, 6)
In master mode w ith the I2C bus format, w hen arbitration is lost, bits MST and TRS are set to 0
and the IIC enters slave receive mode.
When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit
is set to 0 and the IIC enters slave receive mode.
b0
Rew rite the TRS bit betw een transfer frames.
RCV D
Receive disable bit After reading the ICDRR register w hile the TRS bit
is set to 0
0 : Maintains the next receive operation
1 : Disables the next receive operation
RW
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 428 of 580
REJ09B0324-0200
Figure 16.27 ICCR2 Register
IIC bus Control Register 2
Symbol Address After Reset
ICCR2 00B9h 01111101b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
RO
RW
—
IIC control part reset bit
—
(b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
IICRST RW
When hang-up occurs due to communication failure
during I2C bus interface operation, w rite 1, to reset the
control block of the I2C bus interface w ithout setting
ports or initializing registers.
b0b3 b2 b1b7 b6 b5 b4
—
(b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SCLO SCL monitor flag 0 : SCL pin is set to “L”
1 : SCL pin is set to “H”
Do not w rite during a transfer operation.
SDAOP
SDAO RW
When read
0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
When w ritten(1,2)
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
(“H” output via external pull-up resistor)
SDA output value control
bit
SDAO w rite protect bit When rew rite to SDAO bit, w rite 0 simultaneously(1).
When read, the content is 1.
BBSY
Bus busy bit(4)
SCP
Start/stop condition
generation disable bit
When w riting to the to BBSY bit, w rite 0
simultaneously(3).
When read, the content is 1.
Writing 1 is invalid.
RW
When read
0 : Bus is in released state
(SDA signal changes from “L” to “H” w hile SCL
signal is in “H” state)
1 : Bus is in occupied state
(SDA signal changes from “H” to “L” w hile SCL
signal is in “H” state)
When w ritten(3)
0 : Generates stop condition
1 : Generates start condition
RW
This bit is disabled w hen the clock synchronous serial format is used.
This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV
instruction simultaneously. Execute the same w ay w hen the start condition is regenerating.
When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 429 of 580
REJ09B0324-0200
Figure 16.28 ICMR Register
IIC bus Mode Register
Symbol Address After Reset
ICMR 00BAh 00011000b
Bit Symbol Bit Name Function RW
MSB-first/LSB-first select
bit
NOTES:
1.
2.
3.
4.
5.
6.
MLS RW
RW
BC1
BC2
Bits counter 2 to 0 I2C bus f ormat (remaining transfer bit count w hen
read out and data bit count of next transf er w hen
w ritten)(1,2).
b2 b1 b0
0 0 0 : 9 bits(3)
0 0 1 : 2 bits
0 1 0 : 3 bits
0 1 1 : 4 bits
1 0 0 : 5 bits
1 0 1 : 6 bits
1 1 0 : 7 bits
1 1 1 : 8 bits
Clock synchronous serial format (w hen read, the
remaining transfer bit count and w hen w ritten
000b).
b2 b1 b0
0 0 0 : 8 bits
0 0 1 : 1 bit
0 1 0 : 2 bits
0 1 1 : 3 bits
1 0 0 : 4 bits
1 0 1 : 5 bits
1 1 0 : 6 bits
1 1 1 : 7 bits
BC0
RW
RW
0
BCWP
BC w rite protect bit
b7 b6 b5 b4 b3 b2 b1 b0
When rew riting bits BC0 to BC2, w rite 0
simultaneously(2,4).
When read, the content is 1.
RW
The setting value is enabled in master mode of the I2C bus format. It is disabled in slave mode of the I2C
bus format or w hen the clock synchronous serial format is used.
0 : No w ait
(Transfer data and acknow ledge bit
consecutively)
1 : Wait
(After the clock falls for the final
data bit, “L” period is extended for tw o
transfer clocks cycles)
Set to 0. RW
RW
0 : Data transfer w ith MSB-first(6)
1 : Data transfer w ith LSB-f irst
—
(b5)
WAIT
Set to 0 w hen the I2C bus f ormat is used.
When w riting to bits BC0 to BC2, w rite 0 to the BCWP bit using the MOV instruction.
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1. —
Rew rite betw een transfer f rames. When w riting values other than 000b, w rite w hen the SCL signal is “L”.
After data including the acknow ledge bit is transferred, these bits are automatically set to 000b. When the start
condition is detected, these bits are automatically set to 000b.
Do not rew rite w hen the clock synchronous serial format is used.
Res er v ed bit
Wait insertion bit(5)
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 430 of 580
REJ09B0324-0200
Figure 16.29 ICIER Register
IIC bus Interrupt Enable Register
Symbol Address After Reset
ICIER 00BBh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
Transmit acknow ledge
select bit
0 : 0 is transmitted as acknow ledge bit in
receive mode.
1 : 1 is transmitted as acknow ledge bit in
receive mode.
b0b3 b2 b1
NA KIE
b7 b6 b5 b4
ACKE
Transmit end interrupt
enable bit
STIE
ACKBT RW
RW
ROACKBR
RW
Receive acknow ledge bit 0 : Acknow ledge bit received from
receive device in transmit mode is set to 0.
1 : Acknow ledge bit received from
receive device in transmit mode is set to 1.
RIE
Receive interrupt enable
bit
0 : Disables receive data full and overrun
error interrupt request
1 : Enables receive data f ull and overrun
error interrupt request(1)
RW
Acknow ledge bit judgment
select bit
0 : Value of receive acknow ledge bit is ignored
and continuous transfer is performed.
1 : When receive acknow ledge bit is set to 1,
continuous transf er is halted.
RW
Stop condition detection
interrupt enable bit
0 : Disables stop condition detection interrupt
request
1 : Enables stop condition detection interrupt
request(2)
0 : Disables NACK receive interrupt request and
arbitration lost/overrun error interrupt request
1 : Enables NACK receive interrupt request and
arbitration lost/overrun error interrupt request(1)
NACK receive interrupt
enable bit
Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set
to 0.
0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
RW
RW
An overrun error interrupt request is generated w hen the clock synchronous format is used.
TIE
Transmit interrupt enable
bit
0 : Disables transmit data empty interrupt request
1 : Enables transmit data empty interrupt request
TEIE
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 431 of 580
REJ09B0324-0200
Figure 16.3 0 ICSR Register
IIC bus Status Register(7)
Symbol Address After Reset
ICSR 00BCh 0000X000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
STOP Stop condition detection
flag(1)
When the stop condition is detected after the frame
is transferred, this flag is set to 1. RW
The RDRF bit is set to 0 w hen reading data from the ICDRR register.
Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register.
When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interf ace
monitors the SDA pin and the data w hich the I2C bus Interface transmits is different, the AL flag is set to 1 and the
bus is occupied by another master.
RWRDRF Receive data register
full
(1,5)
When the 9th clock cycle of the SCL signal in the I
2C
bus format occurs w hile the TDRE bit is set to 1, this
flag is set to 1.
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
No acknow ledge detection
flag(1,4)
This flag is enabled in slave receive mode of the I2C bus f or mat.
Each bit is set to 0 by reading 1 before w riting 0.
NA CKF When no acknow ledge is detected from the receive
device after transmission, this flag is set to 1. RW
RW
When receive data is transferred f rom in registers
ICDRS to ICDRR , this f lag is set to 1.
TEND
Transmit end(1,6)
RW
RW
General call address
recognition flag(1,2)
When the general call address is detected, this flag
is set to 1.
Arbitration lost
flag/overrun error flag(1)
When the I2C bus f ormat is used, this flag indicates
that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1(3).
• When the internal SDA signal and SDA pin
level do not match at the rise of the SCL signal
in master transmit mode
• When the start condition is detected and the
SDA pin is held “H” in master transmit/receive
mode
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
• When the last bit of the next data item is
received w hile the RDRF bit is set to 1
Slave address recognition
flag(1)
This flag is set to 1 w hen the first frame follow ing
start condition matches bits SVA0 to SVA6 in the
SAR register in slave receive mode. (Detect the
slave address and generate call address)
RWAAS
AL
ADZ
b2 b1b7 b6 b5 b4
When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
b0
The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is
set to 1, transf er is halted).
TDRE
Transmit data empty(1,6) In the follow ing cases, this f lag is set to 1.
• Data is transf erred f rom registers ICDRT to ICDRS
and the ICDRT register is empty
• When setting the TRS bit in the ICCR1
register to 1 (transmit mode)
• When generating the start condition
(including retransmit)
• When changing from slave receive mode to
slave transmit mode
RW
b3
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 432 of 580
REJ09B0324-0200
Figure 16.31 Registers SAR and ICDRT
IIC bus Transmit Data Registe
r
Symbol Address After Reset
ICDRT 00BEh FFh
RW
b0b7 b6 b5 b4 b3 b2 b1
RW
Function
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-f irst) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
Slave Address Register
Symbol Address After Reset
SAR 00BDh 00h
Bit Symbol Bit Name Function RW
b7 b6 b0b1b5 b3 b2b4
Format select bit 0 : I
2C bus format
1 : Clock synchronous serial format RWFS
RW
Slave address 6 to 0 Set an address different from that of the other
slave devices w hich are connected to the I2C
bus. When the 7 high-order bits of the first frame
transmitted after the starting condition match bits
SVA0 to SVA6 in slave mode of the I2C bus
format, the MCU operates as a slave device.
RW
RW
RW
RW
SVA2
SVA0
RW
SVA3
SVA1
SVA6
SVA5
SVA4
RW
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 433 of 580
REJ09B0324-0200
Figure 16.32 Registers ICDRR and ICDRS
Figure 16.33 P M R Re gi ster
IIC bus Receive Data Register
Symbol Address After Reset
ICDRR 00BFh FFh
RW
b7 b6 b5 b4 b3 b2 b1 b0
Store receive data
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
RO
Function
IIC bus Shift Register
Symbol
ICDRS
RW
b7 b6 b5 b4 b3 b2 b1 b0
This register is used to transmit and receive data.
The transmit data is transf erred from registers ICRDT to the ICDRS and data is transmitted
from the SDA pin w hen transmitting.
After 1 byte of data received, data is transferred from registers ICDRS to ICDRR w hile
receiving.
—
Function
Port Mode Registe
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
____ pin select bit
INT2
_
____ pin select bit
IICSEL RW
0 : Selects SSU function
1 : Selects I
2C bus function
0 : Selects P6_6
1 : Selects P3_2
To use the UART1, set to 1.
Set to 0.
RW
SSU / I2C bus sw itch bit
RW
b0
RW
Reserved bits
U1PINSEL UART1 enable bit
INT2SEL
—
(b6-b5)
INT1SEL 0 : Selects P1_5, P1_7
1 : Selects P3_6
b3 b2
0
b1
0
b7 b6 b5 b4
00
RW
—
(b3-b2)
Reserved bits Set to 0. RW
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 434 of 580
REJ09B0324-0200
16.3.1 Transfer Clock
When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL
pin. When the MST bit in the IC CR1 register is set to 1, the transfer cl ock is the internal clock sel ected by bits
CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin.
Table 16.6 lists the Transfer Rate Examples.
Table 16.6 Transfer Rate Examples
ICCR1 Register Transfer
Clock
Transfer Rate
CKS3 CKS2 CKS1 CKS0 f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz
0 0 0 0 f1/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz
1 f1/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz
1 0 f1/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz
1 f1/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz
1 0 0 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 f1/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz
1 0 f1/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz
1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 0 0 0 f1/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz
1 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 0 f1/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz
1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 0 0 f1/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz
1 f1/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz
1 0 f1/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz
1 f1/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 435 of 580
REJ09B0324-0200
16.3.2 Interrupt Requests
The I2C bus interface has six interrupt requests when the I2C bus format is used and four i nterrupt requests
when the clock synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I2C bus Interface.
Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source
bit by bit is necessary.
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
When the generation conditions listed in Table 16.7 are met, an I2C bus interface interrupt request is generated.
Set the interrupt generat ion conditio ns to 0 by the I2C bus interface interrupt routine. However, bits TDRE and
TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is t ransferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by
further setting the TDRE bit to 0, 1 additional byte may be transmitted.
Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Table 16.7 Interrupt Requests of I2C bus Interface
Interrupt Request Generation Condition
Format
I2C bus
Clock
Synchronous
Serial
Transmit data empty TXI TIE = 1 and TDRE = 1 Enabled Enabled
Transmit ends TEI TEIE = 1 and TEND = 1 Enabled Enabled
Receive data full RXI RIE = 1 and RDRF = 1 Enabled Enabled
Stop condition detection STPI STIE = 1 and STOP = 1 Enabled Disabled
NACK detection NAKI NAKIE = 1 and AL = 1 (or
NAKIE = 1 and NACKF = 1)
Enabled Disabled
Arbitration lost/overrun error Enabled Enabled
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 436 of 580
REJ09B0324-0200
16.3.3 I2C bus Interface Mode
16.3.3.1 I2C bus Format
Setting the FS bit in the SAR register to 0 enables communication in I2C bus fo rmat.
Figure 16.34 shows the I2C bus Format and Bus Timing. The 1st frame following the start condition consists of
8 bits.
Figure 16.34 I2C bus Format and Bus Timing
SR/W ADATA AA/A P
171 1 n1 1 1
1 m
(a) I2C bus format (FS = 0)
Transfer bit count (n = 1 to 8)
Transfer frame count (m = from 1)
SR/W ADATA A/A P
171 1 n1 1 1
1m1
(b) I2C bus format (when start condition is retransmitted, FS = 0)
Upper: Transfer bit count (n1, n2 = 1 to 8)
Lower: Transfer frame count (m1, m2 = 1 or more)
SLA
SLA A/A
1
S
1
R/W ADATA
71 1 n2
SLA
1m2
SDA
SCL
SSLA R/W A DATA A DATA A P
1 to 7 8 9 1 to 7 8 9 1 to 7 8 9
(1) I2C bus format
(2) I2C bus timing
Explanation of symbols
S : Start condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
SLA : Slave address
R/W : Indicates the direction of data transmit/receive
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
A : Acknowledge
The receive device sets the SDA signal to “L”.
DATA : Transmit / receive data
P : Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 437 of 580
REJ09B0324-0200
16.3.3.2 Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.35 and 16.36 show the Operatin g Timing in Master Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in master transmit mode are as follows.
(1) Set the STOP bit in the ICSR register to 0 to reset it. Then set the ICE bit in the ICCR1 register to 1
(transfer operation enabled). Then set bits WAIT and MLS in the ICMR register and set bits CKS0 to
CKS3 in the ICCR1 register (initi al setting).
(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set bits TRS and MST in the
ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY bit
and 0 to the SCP bit by the MOV instructio n.
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers
ICDRT to ICD RS), write transmit data to the ICDRT register (data in which a slave address and R/W
are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0, data is transferred
from register s IC DRT to ICDRS, and the TDRE bit is set to 1 again.
(4) When transmission of 1 byte of data is com pleted while the TDRE bit is set to 1, the TEND bit in the
ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER
register, and confirm that the slave is selected. Write the 2nd byte of data to the ICDRT register. Since
the slave device is not acknowledged when the ACKBR bit is set to 1, generate th e stop condition . The
stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV
instruction. The SCL signal is held “L” until data is availabl e and the stop con dit ion is generated.
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is
set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to
1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive
acknowledge bit is set to 1, transfer is halted). Then generate the stop conditi on before setting bits
TEND and NACKF to 0.
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 438 of 580
REJ09B0324-0200
Figure 16.35 Operating Timing in Master Transmit Mode (I2C bus Interf ac e M od e ) (1)
Figure 16.36 Operating Timing in Master Transmit Mode (I2C bus Interf ac e M od e ) (2)
SDA
(master output)
SCL
(master output) 12 8967453
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6
12
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRT register
ICDRS register
R/W
Slave address
Address + R/W
Processing
by program
(2) Instruction of
start condition
generation
(3) Data write to ICDRT
register (1st byte)
A
(4) Data write to ICDRT
register (2nd byte)
(5) Data write to ICDRT
register (3rd byte)
Data 2
Address + R/W
Data 1
Data 1
SDA
(master output)
SCL
(master output) 12 8967453
b7 b6 b5 b4 b3 b2 b1 b0
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRT register
ICDRS register
Data n
Processing
by program
(6) Generate stop condition and
set TEND bit to 0
(3) Data write to ICDRT
register
A/A
(7) Set to slave receive mode
9
A
Data n
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 439 of 580
REJ09B0324-0200
16.3.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 16.37 and 16.38 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master
receive mode by setting the TRS bit in the ICCR1 register to 0. Also, set the TDRE bit in the ICSR
register to 0.
(2) When performing the dummy read of the ICDRR register and starting the receive operation, the receive
clock is output in synchronization with the internal clock and data is received. The master device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle of the receive clock.
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the
9th clock cycle. At this time, when reading the ICDRR register, the received data can be read and the
RDRF bit is set to 0 simultaneously.
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set
to 1. If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit
is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (disables
the next receive operation) before reading the ICDRR register , stop condition generation is enabled after
the next receive operation.
(6) When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop
condition.
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0
(maintain the following receive operation).
(8) Return to slave receive mode.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 440 of 580
REJ09B0324-0200
Figure 16.37 Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1)
SDA
(master output)
SCL
(master output) 1
8967453
b7 b6 b5 b4 b3 b2 b1 b0 b7
12
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRR register
ICDRS register Data 1
Processing
by program
(1) Set TEND and TRS bits to 0 before
setting TDRE bits to 0
A
(2) Read ICDRR register
Data 1
9
TRS bit in
ICCR1 register
1
0
RDRF bit in
ICSR register
1
0
A
(3) Read ICDRR register
Master transmit mode Master receive mode
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 441 of 580
REJ09B0324-0200
Figure 16.38 Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2)
SDA
(master output)
SCL
(master output) 12 8967453
b7 b6 b5 b4 b3 b2 b1 b0
SDA
(slave output)
1
0
RCVD bit in
ICCR1 register
1
0
ICDRR register
ICDRS register Data n-1
Processing
by program
(6) Stop condition
generation
A/A
(8) Set to slave receive mode
9
A
Data n
RDRF bit in
ICSR register
Data n
Data n-1
(5) Set RCVD bit to 1 before
reading ICDRR register
(7) Read ICDRR register before
setting RCVD bit to 0
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 442 of 580
REJ09B0324-0200
16.3.3.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 16.39 and 16.40 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bi ts CKS0 to C KS3 in the ICCR 1 regist er (in iti al setting ). Set bits TRS an d MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1,
and the mode is switched to sl ave transmit mode automat ically. Continu ous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
(3) When the TDRE bit in the ICDRT register is set to 1 after w riting the last transmit data to the ICDRT
register , wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR
register to end the process.
(5) Set the TDRE bit to 0.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 443 of 580
REJ09B0324-0200
Figure 16.39 Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1)
SDA
(master output)
SCL
(master output) 1
8967453
b7 b6 b5 b4 b3 b2 b1 b0 b7
12
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRR register
ICDRS register Data 1
Processing
by program
A
Data 2
9
TRS bit in
ICCR1 register
1
0
A
Slave transmit mode
Slave receive mode
SCL
(slave output)
ICDRT register Data 1
(1) Data write to ICDRT
register (data 1)
(2) Data write to ICDRT
register (data 2)
Data 2
(2) Data write to ICDRT
register (data 3)
Data 3
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 444 of 580
REJ09B0324-0200
Figure 16.40 Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2)
SDA
(slave output)
SCL
(master output) 12 8967453
b7 b6 b5 b4 b3 b2 b1 b0
SDA
(master output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRT register
ICDRS register
Data n
Processing
by program
(3) Set the TEND bit to 0
A
9
A
Data n
Slave receive
mode
Slave transmit mode
TRS bit in
ICCR1 register
1
0
ICDRR register
(4) Dummy read of ICDRR register
after setting TRS bit to 0 (5) Set TDRE bit to 0
SCL
(slave output)
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 445 of 580
REJ09B0324-0200
16.3.3.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.41 and 16.42 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bi ts CKS0 to C KS3 in the ICCR 1 regist er (in iti al setting ). Set bits TRS an d MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set in the ACKBT bit in the IC IER register to the SDA pin at the rise of the 9 th clock
cycle. Since the RDRF bit in the ICSR register is set to 1 simultan eously, perform the dummy read (the
read data is unnecessary because it indicates the slave address and R/W).
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the
RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of
the acknowledge signal returned to the master device before reading the ICDRR register takes affect
from the following transfer frame.
(4) Reading the last byte is performed by readin g the ICDRR register in like manner.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 446 of 580
REJ09B0324-0200
Figure 16.4 1 Operating Timing in Slav e Re ce iv e Mo de (I2C bus Interface Mode) (1)
Figure 16.4 2 Operating Timing in Slav e Re ce iv e Mo de (I2C bus Interface Mode) (2)
SDA
(master output)
SCL
(master output) 1
8967453
b7 b6 b5 b4 b3 b2 b1 b0 b7
12
SDA
(slave output)
ICDRR register
ICDRS register Data 1
Processing
by program
A
(2) Dummy read of ICDRR register
Data 1
9
RDRF bit in
ICSR register
1
0
A
(2) Read ICDRR register
SCL
(slave output)
Data 2
SDA
(master output)
SCL
(master output) 8967453
b7 b6 b5 b4 b3 b2 b1 b0
12
SDA
(slave output)
ICDRR register
ICDRS register Data 1
Processing
by program
A
(3) Read ICDRR register
Data 1
9
RDRF bit in
ICSR register
1
0
A
(4) Read ICDRR register
SCL
(slave output)
Data 2
(3) Set ACKBT bit to 1
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 447 of 580
REJ09B0324-0200
16.3.4 Clock Synchronous Serial Mode
16.3.4.1 Clock Synchronous Serial Format
Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication.
Figure 16.43 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between successive falling edges of the SCL clock, and data is determined at the
rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during transfer standby.
Figure 16.43 Transfer Format of Clock Synchronous Serial Format
SCL
b0
SDA b1 b2 b3 b4 b5 b6 b7
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 448 of 580
REJ09B0324-0200
16.3.4.2 Transmit Operation
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 16.44 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mod e).
The transmit procedure and operation in transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the
ICCR1 register to 1.
(3) Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by
writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. Continuous
transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. When
switching from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
Figure 16.44 Operating Timing in Transmit Mode (Clock Synchronous Serial Mode )
SDA
(output)
SCL 87
b7b1
b0
12
ICDRT register
ICDRS register
Processing
by program
1781
b6 b7 b0 b6 b0
TDRE bit in
ICSR register
1
0
TRS bit in
ICCR1 register
1
0
Data 1 Data 2 Data 3
Data 1 Data 2 Data 3
(2) Set TRS bit to 1
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 449 of 580
REJ09B0324-0200
16.3.4.3 Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.45 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
output.
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is comp let e d.
Figure 16.45 Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
SDA
(input)
SCL 87
b7b1
b0
12
ICDRR register
ICDRS register
Processing
by program
1781
b6 b7 b0 b6 b0
RDRF bit in
ICSR register
1
0
MST bit in
ICCR1 register
1
0
Data 1 Data 2
(2) Set MST bit to 1
(when transfer clock is output)
(3) Read ICDRR register
2
TRS bit in
ICCR1 register
1
0
Data 2 Data 3Data 1
(3) Read ICDRR register
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 450 of 580
REJ09B0324-0200
16.3.5 Examples of Register Setting
Figures 16.46 to 16.49 show Examples of Register Setting Wh en Using I2C bus interface.
Figure 16.46 Example of Register Setting in Master Transmit Mode (I2C bus Interface Mode)
Start
Initial setting
Read BBSY bit in ICCR2 register
End
BBSY = 0 ?
Write transmit data to ICDRT register
Transmit
mode ?
Master receive
mode
TEND = 1 ?
No
Yes
Yes
No
(1) Judge the state of the SCL and SDA lines
(2) Set to master transmit mode
(3) Generate the start condition
(4) Set the transmit data of the 1st byte
(slave address + R/W)
(5) Wait for 1 byte to be transmitted
(6) Judge the ACKBR bit from the specified slave device
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait until the ICRDT register is empty
(9) Set the transmit data of the last byte
(10) Wait for end of transmission of the last byte
(11) Set the TEND bit to 0
(12) Set the STOP bit to 0
(13) Generate the stop condition
(14) Wait until the stop condition is generated
(15) Set to slave receive mode
Set the TDRE bit to 0
ICCR1 register TRS bit ← 1
MST bit ← 1
ICCR2 register SCP bit ← 0
BBSY bit ← 1
Read TEND bit in ICSR register
No
Read ACKBR bit in ICIER register
Yes
ACKBR = 0 ?
Write transmit data to ICDRT register
TDRE = 1 ?
Read TDRE bit in ICSR register
Last byte ?
Write transmit data to ICDRT register
TEND = 1 ?
Read TEND bit in ICSR register
ICSR register TEND bit ← 0
ICSR register STOP bit ← 0
ICCR2 register SCP bit ← 0
BBSY bit ← 0
Read STOP bit in ICSR register
STOP = 1 ?
ICCR1 register TRS bit ← 0
MST bit ← 0
ICSR register TDRE bit ← 0
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(12)
(10)
(13)
(14)
(11)
(9)
(15)
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
• Set the MSTIIC bit in the MSTCR register to 1.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 451 of 580
REJ09B0324-0200
Figure 16.47 Example of Register Setting in Master Receive Mode (I2C bus Interface Mode)
End
RDRF = 1 ?
Master receive mode
No
Yes
(1) Set the TEND bit to 0 and set to master receive mode.
Set the TDRE bit to 0(1,2)
(2) Set the ACKBT bit to the transmit device(1)
(3) Dummy read the ICDRR register(1)
(4) Wait for 1 byte to be received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte and set to disable
continuous receive operation (RCVD = 1)(2)
(8) Read the receive data of (last byte - 1)
(9) Wait until the last byte is received
(10) Set the STOP bit to 0
(11) Generate the stop condition
(12) Wait until the stop condition is generated
(13) Read the receive data of the last byte
(14) Set the RCVD bit to 0
(15) Set to slave receive mode
ICCR1 register TRS bit ← 0
Dummy read in ICDRR register
Read RDRF bit in ICSR register
Last receive
- 1 ?
ICSR register TEND bit ← 0
ICSR register STOP bit ← 0
ICCR2 register SCP bit ← 0
BBSY bit ← 0
Read STOP bit in ICSR register
STOP = 1 ?
ICSR register TDRE bit ← 0
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(12)
(10)
(13)
(14)
(11)
(9)
(15)
ICIER register ACKBT bit ← 0
No
Yes
Read ICDRR register
ICIER register ACKBT bit ← 1
ICCR1 register RCVD bit ← 1
Read ICDRR register
Read RDRF bit in ICSR register
RDRF = 1 ?
Read ICDRR register
ICCR1 register RCVD bit ← 0
ICCR1 register MST bit ← 0
No
Yes
Yes
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Processing step (8) is dummy read of the ICDRR register.
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 452 of 580
REJ09B0324-0200
Figure 16.48 Example of Register Setting in Slave Transmit Mode (I2C bus Interface Mode)
End
Write transmit data to ICDRT register
Slave transmit mode
No
Yes
(1) Set the AAS bit to 0
(2) Set the transmit data (except the last byte)
(3) Wait until the ICRDT register is empty
(4) Set the transmit data of the last byte
(5) Wait until the last byte is transmitted
(6) Set the TEND bit to 0
(7) Set to slave receive mode
(8) Dummy read the ICDRR register to release the
SCL signal
(9) Set the TDRE bit to 0
TDRE = 1 ?
Read TDRE bit in ICSR register
Last byte ?
Write transmit data to ICDRT register
TEND = 1 ?
Read TEND bit in ICSR register
ICSR register TEND bit ← 0
ICSR register AAS bit ← 0
ICCR1 register TRS bit ← 0
ICSR register TDRE bit ← 0
No
Yes
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Dummy read in ICDRR register
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 453 of 580
REJ09B0324-0200
Figure 16.49 Example of Register Set ting in Slave Receive Mode (I2C bus Interface Mode)
End
RDRF = 1 ?
Slave receive mode
No
Yes
(1) Set the AAS bit to 0(1)
(2) Set the ACKBT bit to the transmit device
(3) Dummy read the ICDRR register
(4) Wait until 1 byte is received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte(1)
(8) Read the receive data of (last byte - 1)
(9) Wait until the last byte is received
(10) Read the receive data of the last byte
Dummy read ICDRR register
Read RDRF bit in ICSR register
Last receive
- 1 ?
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(10)
(9)
ICIER register ACKBT bit ← 0
No
Yes
Read ICDRR register
ICIER register ACKBT bit ← 1
Read ICDRR register
Read RDRF bit in ICSR register
RDRF = 1 ?
Read ICDRR register
No
Yes
NOTE:
1. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7).
Processing step (8) is dummy read of the ICDRR register.
ICSR register AAS bit ← 0
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 454 of 580
REJ09B0324-0200
16.3.6 Noise Canceller
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.50 shows a Block Diagram of Noi se Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) i s sampl ed on f1 and tw o latch ou tputs match, the l evel is passed forward to the ne xt
circuit. When they do not match, the former value is retained.
Figure 16.50 Block Diagra m of No ise Can c el le r
C
DQ
Latch
C
DQ
Latch
Match
detection
circuit
SCL or SDA
input signal Internal SCL
or SDA signal
f1 (sampling clock)
Period of f1
f1 (sampling clock)
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 455 of 580
REJ09B0324-0200
16.3.7 Bit Synchronization Circuit
When setting the I2C bus interface to master mode, the high-level period may become shorter in the following
two cases:
•If the SCL signal is driven L level by a slave device
•If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL li ne.
Therefore, the SCL signal is monitored and com mu nication is synchronized bit by bit.
Figure 16.51 shows the Timing of Bit Synchronization Circuit and Table 16.8 li sts the Time between Changing
SCL Signal from “L” Output to High-Imp edance and Monitoring of SCL Signal.
Figure 16.51 Timing of Bit Synchronization Circuit
1Tcyc = 1/f1(s)
Table 16.8 Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring of SCL Signal
ICCR1 Register Time for Monitoring SCL
CKS3 CKS2
0 0 7.5Tcyc
1 19.5Tcyc
1017.5Tcyc
1 41.5Tcyc
VIH
Reference clock of
SCL monitor timing
SCL
Internal SCL
R8C/2A Group, R8C/2B Group 16. Clock Synchronous Serial Interface
Rev.2.00 Nov 26, 2007 Page 456 of 580
REJ09B0324-0200
16.3.8 Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
16.3.8.1 Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
•Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
•Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
16.3.8.2 Master Receive Mode
Either of the following actions must be performed to use th e I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 457 of 580
REJ09B0324-0200
17. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
17.1 Features
The hardware LIN has the features listed below.
Figure 17.1 shows a Block Diagram of Hardware LIN.
Master mode
•Generates Synch Break
•Detects bus collision
Slave mode
•Detects Synch Break
•Measures Synch Field
•Controls Synch Break and Synch Field signal inpu ts to UART0
•Detects bus collision
NOTE:
1.The WakeUp function is detected by INT1.
Figure 17.1 Block Diagram of Hardware LIN
Timer RA
UART0
Interrupt
control
circuit
Bus collision
detection
circuit
Synch Field
control
circuit
RXD0 input
control
circuit
RXD0 pin
TXD0 pin
LSTART bit
SBE bit
LINE bit Timer RA
interrupt
TIOSEL = 0
Hardware LIN
TIOSEL = 1
RXD data
Timer RA
underflow signal
BCIE, SBIE,
and SFIE bits UART0 transfer clock
UART0 TE bit
Timer RA output pulse
UART0 TXD data
MST bit
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 458 of 580
REJ09B0324-0200
17.2 Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 17.1.
Table 17.1 Pin Configuration
Name Abbreviation Input/Output Function
Receive data input RXD0 Input Receive data input pin of the hardware LIN
Transmit data output TXD0 Output Transmit data output pin of the hardware LIN
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 459 of 580
REJ09B0324-0200
17.3 Register Configuration
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 17.2 and 17.3.
•LIN Control Register 2 (LINCR2)
•LIN Control Register (LINCR)
•LIN Status Register (LINST)
Figure 17.2 Registers LINCR2 and LINCR
LIN Control Register
Symbol Address After Reset
LINCR 0106h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 17.5 Example of
Header Field Transmission Flowchart (1) and Figure 17.9 Example of Header Field Reception Flowchart
(2).)
Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
SBE
After setting the LSTART bit, confirm that the RXDSF flag is set to 1 bef ore Synch Break input starts.
0 : Unmasked after Synch Break is detected
1 : Unmasked after Synch Field measurement
is completed
RW
RXD0 input unmasking timing
select bit (effective only in slave
mode)
MST RW
LINE
SBIE
BCIE
RXDSF
LSTART
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
0 : Disables Synch Break detection interrupt
1 : Enables Synch Break detection interrupt
0 : Disables bus c ollision detection interrupt
1 : Enables bus collision detection interrupt
0 : RXD0 input enabled
1 : RXD0 input disabled
When this bit is set to 1, timer RA input is
enabled and RXD0 input is disabled.
When read, the content is 0.
RW
RW
RO
RW
RW
RXD0 input status flag
Synch Break detection start
bit(1)
b3 b2 b1 b0b7 b6 b5 b4
0 : Disables Synch Field measurement-
completed interrupt
1 : Enables Synch Field measurement-
completed interrupt
SFIE
Synch Field measurement-
completed interrupt enable bit
LIN operation start bit 0 : Causes LIN to stop
1 : Causes LIN to start operating(3) RW
LIN operation mode setting bit(2 ) 0 : Slave mode
(Synch Break detection circuit actuated)
1 : Master mode
(timer RA output OR’ed w ith TXD0)
LIN Control Register 2
Symbol Address After Reset
LINCR2 0105h 00h
Bit Symbol Bit Name Function RW
0 : Disables bus collision detection
1 : Enables bus collision detection
BCE Bus collision during Sync Break
transmission detection enable bit
—
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b2-b1)
Reserved bits Set to 0.
00
b4
RW
RW
b3 b2 b1 b0b7 b6 b5
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 460 of 580
REJ09B0324-0200
Figure 17.3 LINST Register
LIN Status Register
Symbol Address Af ter Reset
LINST 0107h 00h
Bit Symbol Bit Name Function RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
B2CLR
SBDCT
BCDCT
B0CLR
B1CLR
When this bit is set to 1, the BCDCT bit is set to
0.
When read, the content is 0.
Synch Break detection flag
Bus collision detection f lag
SFDCT bit clear bit
RO
SBDCT bit clear bit
BCDCT bit clear bit
1 show s Synch Break detected or Synch
Break generation completed.
1 show s Bus collision detected
When this bit is set to 1, the SFDCT bit is set to
0.
When read, the content is 0.
When this bit is set to 1, the SBDCT bit is set to
0.
When read, the content is 0.
b7 b6 b5 b4 b3 b2 b1 b0
—
(b7-b6) —
1 show s Synch Field measurement completed.
SFDCT Synch Field measurement-
completed flag RO
RW
RW
RW
RO
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 461 of 580
REJ09B0324-0200
17.4 Functional Description
17.4.1 Master Mode
Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 17.5 and 17.6 show an Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Figure 17.4 Typical Operation when Sending a Header Field
TXD0 pin
Synch Break
1
0
SBDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Synch Field IDENTIFIER
(1) (2) (3) (4) (5)
Set by writing 1 to the
B1CLR bit in the LINST
register
Cleared to 0 upon
acceptance of interrupt
request or by a program
The above applies under the following conditions:
LINE = 1, MST = 1, SBIE = 1
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 462 of 580
REJ09B0324-0200
Figure 17.5 Example of Header Field Transmission Flowchart (1)
Timer RA Set to timer mode
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
UART0 Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 Set the BRG count source (f1, f8, f32)
U0C0CLK0 to 1 bit
UART0 Set the bit rate
U0BRG register
Hardware LIN Set the LIN operation to stop
LINCR register LINE bit ← 0
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
Hardware LIN Set bus collision detection enabled
BCE bit in LINCR2 register ← 1
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 463 of 580
REJ09B0324-0200
Figure 17.6 Example of Header Field Transmission Flowchart (2)
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA Read the count status flag
TCSTF flag in TRACR register
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
The timer RA interrupt may be used
to terminate generation of Synch
Break.
Three to five cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
Transmit the ID field.
A
TCSTF = 1 ?
SBDCT = 1 ?
YES
TCSTF = 0 ?
YES
UART0 Communication via UART0
U0TB register ← ID field
NO
YES
NO
NO
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
Transmit the Synch Field.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
changed after writing 1 to the
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
Timer RA generates Synch Break.
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 464 of 580
REJ09B0324-0200
17.4.2 Slave Mode
Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
17.8 through Figure 17.10 show an Example of Header Field Reception Flowchart.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST regis ter to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the co unt value of timer RA
and set to UART 0 and registers TRAPRE and TRA of timer RA again.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Figure 17.7 Typical Operati on wh en Rec e iv in g a He ad e r Fi el d
RXD0 pin
Synch Break
1
0
RXD0 input for
UART0
1
0
RXDSF flag in the
LINCR register
1
0
Synch Field IDENTIFIER
(2) (3) (5) (6)
The above applies under the following conditions:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
(4)(1)
SBDCT flag in the
LINST register
1
0
SFDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Set by writing 1 to the
B0CLR bit in the LINST
register
Cleared to 0 when Synch
Field measurement
finishes
Measure this period
Set by writing 1 to
the B1CLR bit in
the LINST register
Cleared to 0 upon
acceptance of
interrupt request or
by a program
Set by writing 1 to
the LSTART bit in
the LINCR register
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 465 of 580
REJ09B0324-0200
Figure 17.8 Example of Header Field Reception Flowchart (1)
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Timer RA Set to pulse width measurement mode
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
Timer RA Set the pulse width measurement level low
TEDGSEL bit in the TRAIOC register ← 0
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in the TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in the TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in the LINCR register ← 0
Hardware LIN Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
Hardware LIN Set the LIN operation to start
LINE bit in the LINCR register ← 1
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 466 of 580
REJ09B0324-0200
Figure 17.9 Example of Header Field Reception Flowchart (2)
Timer RA Set to start a pulse width measurement
TSTART bit in the TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in the TRACR register
Hardware LIN Set to start Synch Break detection
LSTART bit in the LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
A
TCSTF = 1 ?
YES
RXDSF = 1 ?
YES
NO
NO
Timer RA waits until the timer starts
counting.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
SBDCT = 1 ?
YES
NO
B
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
Three to five cycles of the CPU clock
are required after the LSTART bit is set
to 1 before the RXDSF flag is set to 1.
After this, input to timer RA and UART0
is enabled.
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
Hardware LIN waits until the RXD0
input for UART0 is masked.
When Synch Break is detected, timer
RA is reloaded with the initially set
count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the initially
set count value and waits until the
next “L” level is input.
Three to five cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (unmasked after
Synch Break is detected), timer RA
can be used in timer mode after the
SBDCT flag in the LINST register is
set to 1 and the RXDSF flag is set to
0.
Zero to one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set to
1.
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 467 of 580
REJ09B0324-0200
Figure 17.10 Example of Header Field Reception Flowchart (3)
Hardware LIN Read the Synch Field measurement-
completed flag
SFDCT flag in the LINST register
UART0 Set the UART0 communication rate
U0BRG register
Communication via UART0
(The SBDCT flag is set when the
timer RA counter underflows upon
reaching the terminal count.)
B
SFDCT = 1 ?
YES
UART0 Communication via UART0
Clock asynchronous serial interface (UART) mode
Transmit ID field
NO
Hardware LIN measures the Synch
Field.
The interrupt of timer RA may be
used (the SBDCT flag is set when
the timer RA counter underflows
upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
completed), timer RA may be used
in timer mode after the SFDCT bit in
the LINST register is set to 1.
Set a communication rate based on
the Synch Field measurement
result.
YES
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 468 of 580
REJ09B0324-0200
17.4.3 Bus Collision Detection Function
The bus collision detection functio n can be us ed when UART0 is enabled for transmission (TE bit in the U0C1
register = 1). To detect a bus collision during Synch Break transmission, set the BCE bit in th e LINCR2 re gister
to 1 (bus collision detection enabled).
Figure 17.11 shows typical operation of th e hard ware LIN when a bus collision is detected.
Figure 17.11 Typical Operation when a Bus Collision is Detected
TXD0 pin 1
0
RXD0 pin 1
0
Transfer clock 1
0
LINE bit in the
LINCR register
1
0
TE bit in the U0C1
register
1
0
BCDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
Set by writing 1 to
the B2CLR bit in the
LINST register
Set to 1 by a program
Set to 1 by a program
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 469 of 580
REJ09B0324-0200
17.4.4 Hardware LIN End Processing
Figure 17.12 shows an Examp le of Hardware LIN Communication Completion Flow chart.
Use the following timing for hardware LIN end processing:
•If the hardware bus collision detection fun c tion is used
Perform hardware LIN end processing after checksum tran smission completes.
•If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Figure 17.12 Example of Hardware LIN Communication Completion Flowchart
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
UART0 Complete transmission via UART0
When the bus collision detection
function is not used, end
processing for the UART0
transmission is not required.
TCSTF = 0 ?
YES
NO
Set the timer to stop counting.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
After clearing hardware LIN
status flag, stop the
hardware LIN operation.
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
R8C/2A Group, R8C/2B Group 17. Hardware LIN
Rev.2.00 Nov 26, 2007 Page 470 of 580
REJ09B0324-0200
17.5 Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interru pts are
shared with timer RA.
Table 17.2 lists the Interrupt Requests of Hardware LIN.
Table 17.2 Interrupt Requests of Hardware LIN
Interrupt Request Status Flag Cause of Interrupt
Synch Break detection SBDCT Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period
during communication.
Synch Break generation
completed
Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Synch Field
measurement completed
SFDCT Generated when measurement for 6 bits of the Synch Field
by timer RA is completed.
Bus collision detection BCDCT Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 472 of 580
REJ09B0324-0200
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (VREF unconnected) so that no
current will flow from the VREF pin into the resisto r ladder. This helps to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter.
Figures 18.2 and 18.4 show the A/D converter-related registers.
NOTES:
1. The analog input voltage does not depend on use of a sample and hold function.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
When 2.2 V ≤ AVCC < 2.7 V, the frequency of φAD must be 5 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
3. In repeat mode 0, only 8-bit mode can be used.
Table 18.1 Performan ce of A/D converter
Item Performance
A/D conversion method Successive approximation (with capacitive coupling amplifier)
Analog input voltage(1) 0 V to AVCC
Operating clock φAD(2) 4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.2 V ≤ AVCC < 4.2 V f2, f4, fOCO-F
Resolution 8 bits or 10 bits selectable
Absolute accuracy AVCC = Vref = 5 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
AVCC = Vref = 2.2 V, φAD = 5 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
Operating mode One-shot mode and repeat mode 0(3)
Analog input pin 12 pins (AN0 to AN11)
A/D conversion start condition • Software trigger
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
•Capture
Timer RD interrupt request is generated while the ADST bit is set to 1
Conversion rate per pin • Without sample and hold function
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 473 of 580
REJ09B0324-0200
Figure 18.1 Block Diagram of A/D Converter
Comparator
AVSS
Data bus
Resistor ladder
VCUT = 0
VCUT = 1
VREF
Successive conversion register
AD0 register
ADCON0
Vcom
VIN
P1_0/AN8
P1_1/AN9
P1_2/AN10
P1_3/AN11
ADGSEL0 = 1
CH0 to CH2, CKS0: Bits in ADCON0 register
CKS1, VCUT: Bits in ADCON1 register
ADGSEL0: Bit in ADCON2 register
ADGSEL0 = 0
ADCAP = 1
Software trigger
Timer RD
interrupt request
ADCAP = 0
Trigger
P0_7/AN0 CH2 to CH0 = 000b
P0_6/AN1
P0_5/AN2
P0_4/AN3
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7
Decoder
CKS0 = 1
CKS1 = 1
CKS1 = 0
φAD
A/D conversion rate selection
CKS0 = 0
f2
f4
fOCO-F
f1
CKS0 = 1
CKS0 = 0
CH2 to CH0 = 001b
CH2 to CH0 = 010b
CH2 to CH0 = 011b
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 474 of 580
REJ09B0324-0200
Figure 18.2 Registers AD0 and ADCON2
A/D Register 0
Symbol Address After Reset
AD0 02C1h-02C0h Undefined
Function
RO
When BITS bit in ADCON1 register is set to 1
(10-bit mode).
When BITS bit in ADCON1 register is set to 0
(8-bit mode).
8 low -order bits in A/D conversion result A/D conversion result
RW
RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0. —
2 high-order bits in A/D conversion result When read, the content is 0.
b0b7
(b8)
b0
(b15)
b7
A/D Control Register 2(1)
Symbol Address After Reset
ADCON2 02D4h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
ADGSEL1 Reserved bit Set to 0. RW
A/D input group select bit(4) 0 : Port P0 group (AN0 to AN7)
1 : Port P1 group (AN8 to AN11)
ADGSEL0 RW
0 : Without sample and hold
1 : With sample and hold RW
If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined.
SMP A/D conversion method select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b5) —
—
(b2-b1) RW
Reserved bits Set to 0.
b7 b6 b5 b4
0
b3 b2 b1 b0
00
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 475 of 580
REJ09B0324-0200
Figure 18.3 ADCON0 Register
A/D Control Register 0(1)
Symbol Address After Reset
ADCON0 02D6h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
ADGSEL0 = 0 ADGSEL0 = 1
AN0
AN1
AN2
AN3
AN4 AN8
AN5 AN9
AN6 AN10
AN7 AN11
100b
101b
110b
111b
CH2 to CH0
000b Do not set.
001b
010b
011b
Set øAD frequency to 10 MHz or below .
The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit in the
ADCON2 register.
CKS0
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(3)
1 : Selects fOCO-F
RW
If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
When changing A/D operating mode, set the analog input pin again.
ADST A/D conversion start f lag 0 : Stops A/D conversion
1 : Starts A/D conversion RW
ADCAP
A/D conversion automatic
start bit
0 : Starts at softw are trigger (ADST bit)
1 : Starts at timer RD
(complementary PWM mode)
RW
0 : One-shot mode
1 : Repeat mode 0 RW
RW
MD1 RWReserved bit Set to 0.
CH1 RW
CH0
CH2 RW
Analog input pin select bits (Note 4)
MD0 A/D operating mode select
bit(2)
b7 b6 b5 b4
0
b3 b2 b1 b0
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 476 of 580
REJ09B0324-0200
Figure 18.4 ADCON1 Register
A/D Control Register 1(1)
Symbol Address After Reset
A DCON1 02D7h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. When the VCUT bit is set to 1 (connected) f rom 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
b3 b2
V CUT
b1 b0
00
Refer to the description of the CKS0 bit in the
ADCON0 register function
Frequency select bit 1
BITS
b7 b6 b5 b4
—
(b2-b1)
00 0
SCAN0
RW
If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undef ined.
CKS1 RW
RW
RW
—
(b6-b7)
Reserved bits
VREF connect bit(3) 0 : VREF not connected
1 : VREF connected
Reserved bit Set to 0. RW
Set the BITS bit to 0 (8-bit mode) in repeat mode 0.
Reserved bits Set to 0.
8/10-bit mode select bit(2) 0 : 8-bit mode
1 : 10-bit mode
RW
Set to 0.
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 477 of 580
REJ09B0324-0200
18.1 One-Shot Mode
In one-shot mode, the input voltage of one selected pin is A/D converted once.
Table 18.2 lists the One-Shot Mode Specifications. Figure 18.5 shows the ADCON0 Register in One-Shot Mode
and Figure 18.6 shows the ADCON1 Register in One-Shot Mod e.
Table 18.2 One-Shot Mode Specifications
Item Specification
Function The input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted once
Start condition • When the ADCAP bit is set to 0 (software trigger),
set the ADST bit to 1 (A/D conversion starts)
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
mode),
A compare match between registers TRD0 and TRDGRA0 or a TRD1
underflow is generated while the ADST bit is set to 1
Stop condition • A/D conversion completes (when the ADCAP bit is set to 0 (software
trigger), ADST bit is set to 0)
• Set the ADST bit to 0
Interrupt request generation
timing
A/D conversion completes
Input pin Select one of AN0 to AN11
Reading of A/D conversion
result
Read AD0 register
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 478 of 580
REJ09B0324-0200
Figure 18.5 ADCON0 Register in One-Shot Mode
A/D Control Register 0(1)
Symbol Address After Reset
ADCON0 02D6h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
ADGSEL0 = 0 ADGSEL0 = 1
AN0
AN1
AN2
AN3
AN4 AN8
AN5 AN9
AN6 AN10
AN7 AN11
Set øAD frequency to 10 MHz or below .
The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit in the
ADCON2 register.
CKS0
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(3)
1 : Selects fOCO-F
RW
If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
After changing the A/D operating mode, select the analog input pin again.
ADST A/D conversion start f lag 0 : Stops A/D conversion
1 : Starts A/D conversion RW
ADCAP
A/D conversion automatic
start bit
0 : Starts at softw are trigger (ADST bit)
1 : Starts at timer RD
(complementary PWM mode)
RW
0 : One-shot mode RW
RW
MD1 RWReserved bit Set to 0.
CH1 RW
CH0
CH2 RW
Analog input pin select bits (Note 4)
MD0 A/D operating mode select
bit(2)
b7 b6 b5 b4
00
b3 b2 b1 b0
CH2 to CH0
000b Do not set.
001b
010b
011b
100b
101b
110b
111b
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 479 of 580
REJ09B0324-0200
Figure 18.6 ADCON1 Register in One-Shot Mode
A/D Control Register 1(1)
Symbol Address After Reset
A DCON1 02D7h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
Reserved bit Set to 0. RW
RW
Set to 0.
Frequency select bit 1
1 : VREF connected
Reserved bits Set to 0.
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS RW
If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undef ined.
CKS1 RW
RW
RW
—
(b6-b7)
Reserved bits
VREF connect bit(2)
—
(b2-b1)
001 0
SCAN0
b7 b6 b5 b4
When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
b3 b2
V CUT
b1 b0
00
Refer to the description of the CKS0 bit in the
ADCON0 register function
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 480 of 580
REJ09B0324-0200
18.2 Repeat Mode 0
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.
Table 18.3 lists the Repeat Mode 0 Specifications. Figure 18.7 shows the ADCON0 Register in Repeat Mode 0 and
Figure 18.8 shows the ADCON1 Register in Repeat Mode 0.
Table 18.3 Repeat Mode 0 Specifications
Item Specification
Function The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted repeatedly
Start conditions • When the ADCAP bit is set to 0 (software trigger),
set the ADST bit to 1 (A/D conversion starts)
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
mode)), a compare match between registers TRD0 and TRDGRA0 or a
TRD1 underflow is generated while the ADST bit is set to 1
Stop condition Set the ADST bit to 0
Interrupt request generation
timing
Not generated
Input pin Select one of AN0 to AN11
Reading of result of A/D
converter
Read AD0 register
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 481 of 580
REJ09B0324-0200
Figure 18.7 ADCON0 Register in Repeat Mode 0
A/D Control Register 0(1)
Symbol Address Af ter Reset
ADCON0 02D6h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
ADGSEL0 = 0 ADGSEL0 = 1
AN0
AN1
AN2
AN3
AN4 AN8
AN5 AN9
AN6 AN10
AN7 AN11
MD1 Reserved bit Set to 0. RW
b0
1
b3 b2 b1
MD0 A/D operating mode select
bit(2)
b7 b6 b5 b4
0
1 : Repeat mode 0 RW
RW
CH1 RW
CH0
CH2 RW
Analog input pin select bits (Note 4)
ADCAP
A/D conversion automatic
start bit
0 : Starts at softw are trigger (ADST bit)
1 : Starts at timer RD
(complementary PWM mode)
RW
ADST A/D conversion start f lag 0 : Stops A/D conversion
1 : Starts A/D conversion RW
Set øAD frequency to 10 MHz or below .
The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit in the
ADCON2 register .
CKS0
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(3)
1 : Do not set.
RW
If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
After changing A/D operation mode, select the analog input pin again.
CH2 to CH0
000b Do not set.
001b
010b
011b
100b
101b
110b
111b
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 482 of 580
REJ09B0324-0200
Figure 18.8 ADCON1 Register in Repeat Mode 0
A/D Control Register 1(1)
Symbol Address After Reset
A DCON1 02D7h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
Reserved bit Set to 0. RW
—
(b2-b1)
Reserved bits Set to 0. RW
Set the BITS bit to 0 (8-bit mode) in repeat mode 0.
VREF connect bit(3) 1 : VREF connected
8/10-bit mode select bit(2) 0 : 8-bit mode
Set to 0.
Frequency select bit 1
BITS RW
If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undef ined.
CKS1 RW
RW
RW
—
(b6-b7)
Reserved bits
0
SCAN0
b7 b6 b5 b4
001
When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
b3 b2
V CUT
b1 b0
000
Refer to the description of the CKS0 bit in the
ADCON0 register function
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 483 of 580
REJ09B0324-0200
18.3 Sample and Hold
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases. The sample and hold function is available in all oper ating modes. Start A/D conversion after
selecting whether the sample and hol d cir c uit is to be used or no t.
Figure 18.9 shows a Timing Diagram of A/D Conversion.
Figure 18.9 Timing Diagram of A/D Conversion
18.4 A/D Conversion Cycles
Figure 18.10 shows the A/D Conversion Cycles.
Figure 18.10 A/D Conversion Cycles
Sampling time
4ø AD cycles
Sample and hold
disabled Conversion time of 1st bit 2nd bit
Comparison
time
Sampling time
2.5ø AD cycles
Comparison
time
Sampling time
2.5ø AD cycles
Comparison
time
* Repeat until conversion ends
Sampling time
4ø AD cycles
Sample and hold
enabled Conversion time of 1st bit 2nd bit
Comparison
time
Comparison
time
Comparison
time
* Repeat until conversion ends
Comparison
time
A/D Conversion Mode
Without Sample & Hold
Without Sample & Hold
With Sample & Hold
With Sample & Hold
8 bits
10 bits
8 bits
10 bits
Conversion
Time
Comparison
Time
Comparison
Time End process
Sampling
Time
End processConversion time at the 1st bit
Sampling
Time
Conversion time at the 2nd
bit and the follows
49φAD 4φAD 2.0φAD 2.5φAD 2.5φAD 8.0φAD
59φAD 4φAD 2.0φAD 2.5φAD 2.5φAD 8.0φAD
28φAD 4φAD 2.5φAD 0.0φAD 2.5φAD 4.0φAD
33φAD 4φAD 2.5φAD 0.0φAD 2.5φAD 4.0φAD
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 484 of 580
REJ09B0324-0200
18.5 Internal Equivalent Circuit of Analog Input
Figure 18.11 shows the Internal Equivalent Circuit of Analog Input.
Figure 18.11 Internal Equivalent Circuit of Analog Input
VCC
Parasitic Diode
Chopper-type
Amplifier
A/D Successive
Conversion Register
Comparison
voltage
VCC VSS
AN0
VSS
i = 12
AN11
VREF
AVSS
Vref
Comparison reference voltage
(Vref) generator
SW1 SW2
AVCC
AMP
SW3
AVSS
VIN
SW4
SW5
SW1
Parasitic Diode ON Resistor
Approx. 2kΩWiring Resistor
Approx. 0.2kΩ
ON Resistor
Approx. 0.6kΩ
ON Resistor
Approx. 2kΩWiring Resistor
Approx. 0.2kΩ
i Ladder-type
Switches
ON Resistor
Approx. 0.6kΩ
Analog Input
Voltage
Sampling
Control Signal
ON Resistor
Approx. 5kΩ
C = Approx.1.5pF
A/D Conversion
Interrupt Request
SW1 conducts only on the ports selected for analog input.
SW2 and SW3 are open when A/D conversion is not in progress;
their status varies as shown by the waveforms in the diagrams on the left.
SW4 conducts only when A/D conversion is not in progress.
SW5 conducts when compare operation is in progress.
Control signal
for SW2
Control signal
for SW3
Sampling Compari son
Connect to
Connect to
Connect to
Connect to
NOTE:
1. Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
i Ladder-type
Wiring Resistors
Resistor
ladder
Reference
Control Signal
ADCON2
register
b3 b0
b1
b2
ADCON0
register
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 485 of 580
REJ09B0324-0200
18.6 Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.12 has to be completed
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit m ode).
VC is generally
And when t = T,
Hence,
Figure 18.12 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN
and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-
(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode with out sample and hold. Output impedance R0
for sufficiently charging capacitor C within time T is determined as follows.
T = 0.25 µs, R = 2.8 kΩ, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,
is approximately 1.7 kΩ. maximum.
Figure 18.12 Analog Input Pin and External Sensor Equivalent Circuit
R0 R (2.8 kΩ)
C (6.0 pF)
VIN
VC
MCU
Sensor equivalent
circuit
NOTE:
1. The capacity of the terminal is assumed to be 4.5 pF.
R0 T
CX
Y
----ln•
-------------------–R–=
1
CR0 R+()
--------------------------–T
X
Y
----ln=
e 1
CR0 R+()
-------------------------- T–X
Y
----=
VC VIN X
Y
---- VIN VIN 1 X
Y
----–
=–=
VC VIN 1e 1
CR0 R+()
--------------------------– t
–
=
R0 0.25 10 6–
×
6.0 10 12–0.1
1024
------------ln•×
---------------------------------------------------–=2.8
3
×10–1.7 3
×10≈
R8C/2A Group, R8C/2B Group 18. A/D Converter
Rev.2.00 Nov 26, 2007 Page 486 of 580
REJ09B0324-0200
18.7 Notes on A/D Converter
•W rite to each bit (other tha n ADST bit) in the ADCON0 regis ter, each bit in the ADCON1 register , or the SMP
bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
•After changing the A/D operatin g mode, select an analog input pin again.
•When using the one- sh ot mo de, ensu re that A/D conversion is completed before reading the AD0 register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
•When using the repeat mode 0, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion .
Do not select the fOCO-F for the φAD.
•If the ADST bit in the ADCON0 register is set to 0 (A/D conv ersion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD0 register.
•Connect 0.1 µF capacitor between the VREF pin and AVSS pin.
•Do not enter stop mode during A/D conversion.
•Do not enter wait mode when the CM02 bi t in the CM0 regi ster is set to 1 (peripheral function clock stops in
wait mode) during A/D conversi on.
R8C/2A Group, R8C/2B Group 19. D/A Converter
Rev.2.00 Nov 26, 2007 Page 487 of 580
REJ09B0324-0200
19. D/A Converter
The D/A converters are 8-bit R-2R type units. There are two independent D/A converters.
D/A conversion is performed by writing to the DAi register (i = 0 or 1). To output the conversion result, set the DAiE
bit in the DACON register to 1 (output enabl ed). Before using D/A conversion, t he corresponding po rt direction bit
must be set to 0 (input mode). Setting the DAiE bit to 1 removes the pull-up from the correspon ding port.
The output analog voltage (V) is determined by the setting value n (n: decimal) of the DAi register.
V = Vref × n/ 256 (n = 0 to 255)
Vref: Reference voltage
Table 19.1 lists the D/A Converter Specifications. Figure 19.1 shows the Block Diagram of D/A Converter. Figure
19.2 shows the D/A converter rel ated registers. Figure 19.3 shows the D/A Converter Equivalent Circuit.
Figure 19.1 Block Diagram of D/A Converter
Table 19.1 D/A Convert er Specificat io n s
Item Performance
D/A conversion method R-2R method
Resolution 8 bits
Analog output pins 2 (DA0 and DA1)
DA0 register
R-2R resistor ladder DA0
DA1 register
R-2R resistor ladder DA1
DA0E bit
DA1E bit
0
1
0
1
Data bus
R8C/2A Group, R8C/2B Group 19. D/A Converter
Rev.2.00 Nov 26, 2007 Page 488 of 580
REJ09B0324-0200
Figure 19.2 Registers DA0 to DA1 and DACON
Figure 19.3 D/A Converter Equivalent Circuit
D/Ai Register (i = 0 or 1)(1)
Symbol
DA 0
DA 1
Setting Range RW
NOTE:
1.
b0b7
RW
After Reset
00h
Address
00DAh
00D8h
When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to
prevent current f rom flow ing into the R-2R resistor ladder to reduce unnecessary current consumption.
Function
Output value of D/A conversion 00h to FFh
00h
D/A Control Register(1)
Symbol
DA CON
Bit Symbol RW
NOTE:
1.
0 : Output disabled
1 : Output enabled
Address
00DCh
D/A1 output enable bit
—
(b7-b2) —
When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to
prevent current f rom flow ing into the R-2R resistor ladder to reduce unnecessary current consumption.
Bit Name Function
0 : Output disabled
1 : Output enabled
D/A0 output enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
DA 1E RW
RWDA 0E
After Reset
00h
b7 b6 b5 b4 b3 b2 b1 b0
VREF(2)
AVSS
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
DAi
MSB LSB
DAiE bit
DAi register
NOTES:
1. The above diagram applies when the value of the DAi register is 2Ah.
2. VREF is not affected by the setting of the VCUT bit in the ADCON1 register.
r
i = 0 to 1
0
0
1
1
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 489 of 580
REJ09B0324-0200
20. Flash Memory
20.1 Overview
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite,
standard serial I/O, and parallel I/O.
Table 20.1 lists the Flash Memory Performance.
NOTES:
1. Definition of programming and erasure endurance
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When
performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations
in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular
blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to
retain data on the erase count of each block and limit the number of erase operations to a certain number.
2. Blocks A and B are implemented only in the R8C/2B group.
3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Table 20.1 Flas h Memory Performance
Item Specification
Flash memory operating mode 3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Division of erase block Refer to Figure 20.1 and Fi gure 20.2
Programming method Byte unit
Erase method Block erase
Programming and erasure control method
(3) Program and erase control by software command
Rewrite control method Rewrite control for blocks 0 to 3 by FMR02 bit in FMR0 register
Rewrite control for block 0 by FMR15 bit and Block 1 by FMR16 bit in
FMR1 register
Number of commands 5 commands
Programming and
erasure
endurance(1)
Blocks 0 to 3 (program
ROM)
R8C/2A Group: 100 times; R8C/2B Group: 1,000 times
Blocks A and B (data
flash)(2)
10,000 times
ID code check function Standard serial I/O mode supported
ROM code protect Parallel I/O mode supported
Table 20.2 Flash Memory Rewrite Modes
Flash memory
Rewrite mode CPU Rewrite Mode Standard Serial I/O
Mode Parallel I/O Mode
Function User ROM area is rewritten by executing
software commands from the CPU.
EW0 mode: Rewritable in the RAM
EW1 mode: Rewritable in flash memory
User ROM area is
rewritten by a
dedicated serial
programmer.
User ROM area is
rewritten by a
dedicated parallel
programmer.
Areas which can
be rewritten
User ROM area User ROM area User ROM area
Operating mode Single chip mode Boot mode Parallel I/O mode
ROM Programmer None Serial programmer Parallel programmer
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 490 of 580
REJ09B0324-0200
20.2 Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash
Memory Block Diagram for R8C/2A Group. Figure 20.2 shows a Flash Memory Block Diagram for R8C/2B
Group.
The user ROM area of the R8C/2B Group contains an area (program ROM) which stores MCU operating programs
and blocks A and B (data flash) each 1 Kbyte in size.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite
enabled). When the FMR15 bit in the FMR1 regist er is set to 0 (rewrite enab led), block 0 is rewri table. When the
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable. When rewriting blocks 2 and 3 in CPU rewrite mode,
FMR02 bit is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot
ROM area and the user ROM area share the same address, but have separate memory areas.
Figure 20.1 Flash Memory Block Diagram for R8C/2A Group
Boot ROM area
(reserved area)(4)
8 Kbytes
0E000h
04000h
Block 0: 32 Kbytes(1)
0C000h
13FFFh
64 Kbytes ROM product
Block 1: 32 Kbytes(1)
Block 0: 16 Kbytes(1)
0BFFFh
0C000h
0FFFFh
48 Kbytes ROM product
Block 1: 32 Kbytes(1)
04000h
0BFFFh
0FFFFh
10000h
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled),
block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
2. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable (only for CPU rewrite mode).
3. The emulator debugger cannot be used by address 20000h to 23FFFh. Refer to 24. Notes on Emulator Debugger.
4. This area is for storing the boot program provided by Renesas Technology.
User ROM area
User ROM area
0FFFFh
Program
ROM
User ROM area
Block 0: 32 Kbytes(1)
0C000h
13FFFh
96 Kbytes ROM product
Block 1: 32 Kbytes(1)
04000h
0BFFFh
0FFFFh
10000h
Block 2: 32 Kbytes(2)
1BFFFh
14000h
Program
ROM
Block 0: 32 Kbytes(1)
0C000h
13FFFh
128 Kbytes ROM product
Block 1: 32 Kbytes(1)
04000h
0BFFFh
0FFFFh
10000h
Block 2: 32 Kbytes(2)
1BFFFh
14000h
User ROM area
Block 3: 32 Kbytes(2, 3)
23FFFh
1C000h
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 491 of 580
REJ09B0324-0200
Figure 20.2 Flash Memory Block Diagram for R8C/2B Group
Boot ROM area
(reserved area)(4)
8 Kbytes
0E000h
0FFFFh
User ROM area
Block 0: 32 Kbytes(1)
0C000h
13FFFh
Block B: 1 Kbyte
Block A: 1 Kbyte
02400h
02BFFh
64 Kbytes ROM product
04000h
Block 1: 32 Kbytes(1)
User ROM area
Block 0: 16 Kbytes(1)
0BFFFh
0C000h
0FFFFh
Block B: 1 Kbyte
Block A: 1 Kbyte
02400h
02BFFh
48 Kbytes ROM product
0FFFFh
10000h
0BFFFh
04000h
Block 1: 32 Kbytes(1)
Program
ROM
Data
flash
User ROM area
Block 0: 32 Kbytes(1)
0C000h
13FFFh
Block B: 1 Kbyte
Block A: 1 Kbyte
02400h
02BFFh
96 Kbytes ROM product
0FFFFh
10000h
0BFFFh
04000h
Block 1: 32 Kbytes(1)
Block 2: 32 Kbytes(2)
1BFFFh
14000h
Program
ROM
Data
flash
Block 0: 32 Kbytes(1)
0C000h
13FFFh
Block B: 1 Kbyte
Block A: 1 Kbyte
02400h
02BFFh
128 Kbytes ROM product
0FFFFh
10000h
0BFFFh
04000h
Block 1: 32 Kbytes(1)
Block 2: 32 Kbytes(2)
1BFFFh
14000h
User ROM area
Block 3: 32 Kbytes(2, 3)
23FFFh
1C000h
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite
enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
2. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable (only for CPU rewrite mode).
3. The emulator debugger cannot be used by address 20000h to 23FFFh. Refer to 24. Notes on Emulator Debugger.
4. This area is for storing the boot program provided by Renesas Technology.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 492 of 580
REJ09B0324-0200
20.3 Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten easily.
20.3.1 ID Code Check Function
This function is used in standard serial I/O mod e . Unless the flash memory is blank, the ID codes sent from the
programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do
not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of
data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh,
00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write
them to the flash memory.
Figure 20.3 Address for Stored ID Code
4 bytes
Address
NOTE:
1. The OFS register is assigned to 00FFFFh.
Refer to Figure 20.4 OFS Register for OFS register details.
ID1
ID2
ID3
ID4
ID5
ID6
ID7
(Note 1)
Undefined instruction vector
Overflow vector
BRK instruction vector
Address match vector
Oscillation stop detection/watchdog
timer/voltage monitor 1 and voltage
monitor 2 vector
Address break
Reset vector
(Reserved)
Single step vector
00FFDFh to 00FFDCh
00FFE3h to 00FFE0h
00FFE7h to 00FFE4h
00FFEBh to 00FFE8h
00FFEFh to 00FFECh
00FFF3h to 00FFF0h
00FFF7h to 00FFF4h
00FFFBh to 00FFF8h
00FFFFh to 00FFFCh
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 493 of 580
REJ09B0324-0200
20.3.2 ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode. Figure 20.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memo ry.
Once ROM code protect is enabled, the content in the i nternal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Figure 20.4 OFS Register
Option Function Select Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(3)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
—
(b6)
Reserved bit Set to 1. RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset).
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : ROM code protect disabled RW
ROMCR ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled RW
—
(b1) RW
Reserved bit Set to 1.
WDTON RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
111
b7 b6 b5 b4 b3 b2 b1 b0
—
(b4)
Reserved bit Set to 1. RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 494 of 580
REJ09B0324-0200
20.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area.
The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in
CPU rewrite mode. It performs an inter rupt process after the erase operation is halted temporarily. During erase-
suspend, the user ROM area can be read by a program.
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash m odule
has a program-suspend function which performs the interrupt process after the auto-program operation is
suspended. During program-suspend, the user ROM area can be read by a program.
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 20.3 lists
the Differences between EW0 Mode and EW1 Mode.
NOTE:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting
the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enabled).
When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable.
Table 20.3 Differences between EW0 Mode and EW1 Mode
Item EW0 Mode EW1 Mode
Operating mode Single-chip mode Single-chip mode
Areas in which a rewrite
control program can be
located
User ROM area User ROM area
Areas in which a rewrite
control program can be
executed
Necessary to transfer to any area other
than the flash memory (e.g., RAM) before
executing
Executing directly in user ROM or RAM
area possible
Areas which can be
rewritten
User ROM area User ROM area
However, blocks which contain a rewrite
control program are excluded(1)
Software command
restrictions
None • Program and block erase commands
Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be executed
Modes after program or
erase
Read status register mode Read array mode
Modes after read status
register
Read status register mode Do not execute this command
CPU status during auto-
write and auto-erase
Operating Hold state (I/O ports hold state before the
command is executed)
Flash memory status
detection
• Read bits FMR00, FMR06, and FMR07
in the FMR0 register by a program
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Read bits FMR00, FMR06, and FMR07 in
the FMR0 register by a program
Conditions for transition to
erase-suspend
Set bits FMR40 and FMR41 in the FMR4
register to 1 by a program.
The FMR40 bit in the FMR4 register is set
to 1 and the interrupt request of the
enabled maskable interrupt is generated
Conditions for transitions to
program-suspend
Set bits FMR40 and FMR42 in the FMR4
register to 1 by a program.
The FMR40 bit in the FMR4 register is set
to 1 and the interrupt request of the
enabled maskable interrupt is generated
CPU clock 5 MHz or below No restriction (on clock frequency to be
used)
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 495 of 580
REJ09B0324-0200
20.4.1 EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
During auto-erasure, set the FMR40 bit to 1 (erase-s uspend enabled) an d the FMR41 bit to 1 (request erase -
suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the
user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts).
To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the
FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read
enabled) before accessing the use r ROM area. The auto-pro gram operation can be restarted by settin g the
FMR42 bit to 0 (program restarts).
20.4.2 EW1 Mode
The MCU is switched to EW1 mode by settin g the FMR11 bit to 1 (EW1 mode) after settin g the FMR01 bit to
1 (CPU rewrite mode enabled).
The FMR0 register can be used to determine wh en program and erase operations complete. Do not execute
commands that use the read status register in EW1 mode.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is
acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically se t to 1 ( requests erase-suspend) and the
auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt
process completes, the auto-erase op erati on restarts by settin g the FMR41 bit to 0 (erasure restarts)
To enable the program-suspend function during auto-programming, execute the program command after setting
the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is
acknowledged.
When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program -suspend) and
the auto-program operation suspends. When the auto-pr ogram operatio n does not comp lete (FMR00 bit is 0)
after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0
(programming restarts).
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 496 of 580
REJ09B0324-0200
Figure 20.5 shows the FMR0 Register, Figure 20.6 shows the FMR1 Register and Figure 20.7 shows the FMR4
Register.
20.4.2.1 FMR00 Bit
This bit indicates the operating status of the flash memory. The bits value is 0 during prog ramming, erasure
(including suspend periods), or erase-suspend mode; otherwise, it is 1.
20.4.2.2 FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
20.4.2.3 FMR02 Bit
Rewriting of blocks 0 to 3 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of blocks 2 and 3 are enabled, if the FMR02 bit is set to 1 (rewrite enabled). Rewriting of blocks 0
and 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite enabled).
20.4.2.4 FMSTP Bit
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
•When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
•To provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock mode (XIN clock stops).
Figure 20.11 shows the handling to provide lower consumption in high-speed on-chip oscillator mode, low-
speed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops). Handle
according to this flowchart. Note that when going to stop or wait mode while the CPU rewrite mode is disabled,
the FMR0 register does not need to be se t becaus e the power for the flash memory is automatically turned off
and is turned back on again after returning from stop or wait mode.
20.4.2.5 FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program
error occurs; otherwise, it is set to 0. For details, refer to the description in 20.4.5 Full Status Check.
20.4.2.6 FMR07 Bit
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error
occurs; otherwise, it is set to 0. Refer to 20.4.5 Full Status Check for details.
20.4.2.7 FMR11 Bit
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
20.4.2.8 FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
20.4.2.9 FMR16 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1
accepts program and block erase commands.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 497 of 580
REJ09B0324-0200
20.4.2.10 FMR40 Bit
The suspend function is enabled by setting the FMR40 bit to 1 (enable).
20.4.2.11 FMR41 Bit
In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41
bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is
generated in EW1 mode, and then the MCU enters erase-suspend mode.
Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.
20.4.2.12 FMR42 Bit
In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The
FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled
interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode.
Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.
20.4.2.13 FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit
remains set to 1 (erase execution in progress) during erase-suspend operation.
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
20.4.2.14 FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44
bit remains set to 1 (program execution in progress) during program-suspend operation.
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
20.4.2.15 FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) d uring auto -prog ram or auto- erase execution and set to 1 (reading
enabled) in suspend mode. Do not access the fl ash memory while this bit is set to 0.
20.4.2.16 FMR47 Bit
Power consumption wh en reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in
low-speed clock mode (XIN clock stops) and low-speed on-chip oscillator mode (XIN clock stops).
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 498 of 580
REJ09B0324-0200
Figure 20.5 FMR0 Register
Flash Memory Control Register 0
Symbol Address After Reset
FMR0 01B7h 00000001b
Bit Symbol Bit Name Function RW
RY /BY
_
__
status flag
NOTES:
1.
2.
3.
4.
5.
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
FMR07
b3 b2 b1 b0
0 : Disables rew rite
1 : Enables rew rite
Flash memory stop bit(3, 5) 0 : Enables flash memory operation
1 : Stops flash memory
(enters low -pow er consumption state
and flash memory is reset)
FMR01
Blocks 0 to 3 rew rite enable bit(2, 6)
0 : Busy (w riting or erasing in progress)
1 : Ready
CPU rew rite mode select bit(1) 0 : CPU rew rite mode disabled
1 : CPU rew rite mode enabled
00
b7 b6 b5 b4
Reserved bits Set to 0.
RW
FMR02 RW
RW
—
(b5-b4)
FMR00
FMSTP
RW
RO
RO
RO
This bit is set to 0 by executing the clear status command.
This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0,
w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er
consumption state nor is it reset.
FMR06
To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
Set this bit by a program transferred to the RAM.
Program status flag(4) 0 : Completed successfully
1 : Terminated by error
Erase status flag(4) 0 : Completed successfully
1 : Terminated by error
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 499 of 580
REJ09B0324-0200
Figure 20.6 FMR1 Register
Flash Memory Control Register 1
Symbol Address After Reset
FMR1 01B5h 1000000Xb
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
b3 b2
Set to 0.
0
b1 b0
FMR11
—
(b4-b2)
10
b7 b6 b5 b4
RW
FMR15
—
(b0)
Reserved bits
When read, the content is undef ined.
EW1 mode select bit(1, 2) 0 : EW0 mode
1 : EW1 mode
Block 0 rew rite disable bit(2,3) 0 : Enables rew rite
1 : Disables rew rite
When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it f irst to 1.
To set this bit to 1, set it to 1.
—
(b7)
0
RW
RW
RW
RO
RW
Reserved bit
0 : Enables rew rite
1 : Disables rew rite
FMR16 Block 1 rew rite disable bit(2,3)
To set this bit to 1, set it to 1 immediately after setting it f irst to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
Reserved bit Set to 1.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 500 of 580
REJ09B0324-0200
Figure 20.7 FMR4 Register
Flash Memory Control Register 4
Symbol Address After Reset
FMR4 01B3h 01000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er consumption read mode.
In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
Program command flag 0 : Program not executed
1 : Program execution in progress RO
The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled
until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the
above.)
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming
w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.
FMR47
Read status flag
RW
Low -pow er consumption read
mode enable bit (1, 4, 5)
0 : Disable
1 : Enable
FMR46
Program-suspend request bit(3) 0 : Program restart
1 : Program-suspend request RW
FMR43 Erase command flag 0 : Erase not executed
1 : Erase execution in progress RO
RW
RW
Erase-suspend function
enable bit(1)
0 : Disables reading
1 : Enables reading
Reserved bit
0 : Disable
1 : Enable
Erase-suspend request bit(2) 0 : Erase restart
1 : Erase-suspend request
RO
RO
b7 b6 b5 b4
—
(b5)
0
FMR40
FMR42
FMR44
To set this bit to 1, set it to 1 immediately af ter setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing
an erase command and completing the erase. (This bit is set to 0 during periods other than above.)
In EW0 mode, it can be set to 0 or 1 by a program.
In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase
operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).
b3 b2
Set to 0.
b1 b0
FMR41
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 501 of 580
REJ09B0324-0200
Figure 20.8 shows the Timing of Suspend Operation.
Figure 20.8 Timing of Suspend Operation
FMR00 bit in
FMR0 register
FMR46 bit in
FMR4 register
FMR44 bit in
FMR4 register
FMR43 bit in
FMR4 register
1
0
1
0
1
0
1
0
Erasure
starts
Erasure
suspends
Programming
starts
Programming
suspends
Programming
restarts
Programming
ends
During erasure During programming During programming
Erasure
restarts
Erasure
ends
During erasure
Check that the
FMR43 bit is set to 1
(during erase
execution), and that
the erase-operation
has not ended.
Check that the
FMR44 bit is set to 1
(during program
execution), and that
the program has not
ended.
Check the status,
and that the
programming ends
normally.
Check the status,
and that the
erasure ends
normally.
Remains 0 during suspend
Remains 1 during suspend
NOTE:
1. If program-suspend is entered during erase-suspend, always restart programming.
The above figure shows an example of the use of program-suspend during programming following erase-suspend.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 502 of 580
REJ09B0324-0200
Figure 20.9 shows How to Set and Exit EW0 Mode. Figure 20.10 shows How to Set and Exit EW1 Mode.
Figure 20.9 How to Set and Exit EW0 Mode
Figure 20.10 How to Set and Exit EW1 Mode
Set registers(1) CM0 and CM1
Transfer a rewrite control program which uses CPU
rewrite mode to the RAM.
Jump to the rewrite control program which has been
transferred to the RAM.
(The subsequent process is executed by the rewrite
control program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)(2)
Execute the read array command(3)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to a specified address in the flash memory
Rewrite control program
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewrite mode after executing the read array command.
EW0 Mode Operating Procedure
Write 0 to the FMR01 bit before writing 1 (CPU
rewrite mode enabled)(1)
Write 0 to the FMR11 bit before writing 1 (EW1
mode)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
NOTE:
1.To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.
Do not generate an interrupt between writing 0 and 1.
EW1 Mode Operating Procedure
Program in ROM
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 503 of 580
REJ09B0324-0200
Figure 20.11 Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode,
Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode
(XIN Clock Stops)
Transfer a high-speed on-chip oscillator mode, low-
speed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program to
the RAM.
Jump to the high-speed on-chip oscillator mode, low-
speed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program
which has been transferred to the RAM.
(The subsequent processing is executed by the
program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)
Switch the clock source for the CPU clock.
Turn XIN off
Process in high-speed on-chip oscillator
mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock
mode (XIN clock stops)
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to a specified address in the flash memory
High-speed on-chip oscillator mode,
low-speed on-chip oscillator mode
(XIN clock stops), and low-speed
clock mode (XIN clock stops)
program
NOTES:
1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the
FMSTP bit to 1.
2. Before switching to a different clock source for the CPU, make sure
the designated clock is stable.
3. Insert a 30 µs wait time in a program. Do not access to the flash
memory during this wait time.
Write 1 to the FMSTP bit (flash memory stops.
low power consumption mode)(1)
Wait until the flash memory circuit stabilizes
(30 µs)(3)
Write 0 to the FMSTP bit
(flash memory operation)
Turn XIN clock on → wait until oscillation
stabilizes → switch the clock source for CPU
clock(2)
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 504 of 580
REJ09B0324-0200
20.4.3 Software Commands
The software commands are described below. Read or write commands and data in 8-bit units.
SRD: Status register data (D7 to D0)
WA: Write address (ensure the address specified in the first bus cycle is the same address as the write
address specified in the second bus cycle.)
WD: Write data (8 bits)
BA: Given block address
×: Any specified address in the user ROM area
20.4.3.1 Read Array Command
The read array command reads the flash memory.
The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since the MCU remains in read array mode until another command is written, the contents of multiple
addresses can be read continuously.
In addition, the MCU enters read array mode after a reset.
20.4.3.2 Read Status Register Command
The read status register command is used to read the status register.
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 20.4.4
Status Registers). When reading the status register, specify an address in the user ROM area.
Do not execute this command in EW1 mode.
The MCU remains in read status register mode until the next read array command is written.
20.4.3.3 Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written in the first bus cycle, bits FMR0 6 to FMR07 in the FMR0 register and SR4 to SR5 in the
status register are set to 0.
Table 20.4 Software Commands
Command
First Bus Cycle Second Bus Cycle
Mode Address Data
(D7 to D0) Mode Address Data
(D7 to D0)
Read array Write × FFh
Read status register Write × 70h Read × SRD
Clear status register Write × 50h
Program Write WA 40h Write WA WD
Block erase Write × 20h Write BA D0h
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 505 of 580
REJ09B0324-0200
20.4.3.4 Program Command
The program command writes data to the flash memory in 1-byte units.
By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program
operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the
same address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 r egister can be used to determine whether auto- programming has completed.
When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when auto-
programming completes. When suspend function enabled, t he FMR44 bit is set to 1 du ring auto-pro gramming
and set to 0 when auto-programmi ng com pletes.
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been
finished (refer to 20.4.5 Full Status Check).
Do not write additions to the already programmed addresses.
When the FMR02 bit in the FMR0 regi st er is set to 0 (rewriting disab led), program commands targeting blocks
0 to 3 are not acknowledged. When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1
register is set to 1 (rewriting disabled), p rogram command s targeting block 0 are not acknowl edged. When the
FMR16 bit is set to 1 (rewriting disabled), program commands targeting block 1 are not acknowledged.
Figure 20.12 shows the Program Command (When Suspend Function Disabled). Figure 20.13 show s the
Program Command (When Su sp end Function Enabled).
In EW1 mode, do not execute this command for any address which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts
and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register
mode until the next read array command is written. The status register can be read to dete rmine the r esult of
auto-programming after auto-programming has completed.
Figure 20.12 Program Command (When Suspend Function Disabled)
Start
Write the command code 40h to
the write address
Write data to the write address
FMR00 = 1?
Full status check
Program completed
No
Yes
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 506 of 580
REJ09B0324-0200
Figure 20.13 Program Command (When Suspend Function Enabled)
Start
Write the command code 40h
to the write address
Write data to the write address
FMR44 = 0 ?
Full status check
Program completed
No
Yes
EW0 Mode
FMR40 = 1
Start
Write the command code 40h
Write data to the write address
FMR44 = 0 ?
Full status check
Program completed
No
Yes
EW1 Mode
FMR40 = 1
Maskable interrupt (2)
REIT
Access flash memory
FMR42 = 0
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.
Maskable interrupt(1)
FMR46 = 1 ?
REIT
Yes
FMR42 = 1(4)
FMR42 = 0
Access flash memory
FMR44 = 1 ?
Yes
No
Access flash memory
No
I = 1 (enable interrupt)
I = 1 (enable interrupt)(3)
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 507 of 580
REJ09B0324-0200
20.4.3.5 Block Erase
When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus
cycle, an auto-erase operation (erase and verify) of th e specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has
completed (refer to 20.4.5 Full Status Check).
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), the block erase commands targeting
blocks 0 to 3 are n ot acknowledged . When the FMR02 bit is set to 1 (rewriting enabled) and the FMR15 b it in
the FMR1 register is set to 1 (rewriting disabled), the block erase commands targeting block 0 are not
acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase commands targeting block 1
are not acknowledged.
Do not use the block erase command during program-suspend.
Figure 20.14 shows the Block Erase Command (When Erase-Suspend Functio n Disabled). Figure 20.15 shows
the Block Erase Command (When Erase-Suspend Function Enabled).
In EW1 mode, do not execute this command for any address to which a rewrite control pro gram is allocated .
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to
1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read
array command is written.
Figure 20.14 Block Erase Command (When Erase-Suspend Function Disabled)
Start
Write the command code 20h
Write D0h to a given block
address
FMR00 = 1?
Full status check
Block erase completed
No
Yes
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 508 of 580
REJ09B0324-0200
Figure 20.15 Block Erase Command (When Erase-Suspend Function Enabled)
Start
Write the command code 20h
Write D0h to any block
address
FMR00 = 1 ?
Full status check
Block erase completed
No
Yes
EW0 Mode
FMR40 = 1
Start
Write the command code 20h
Write D0h to any block
address
FMR00 = 1 ?
Full status check
Block erase completed
No
Yes
EW1 Mode
I = 1 (enable interrupt)
Maskable interrupt (2)
REIT
Access flash memory
FMR41 = 0
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1.
Maskable interrupt(1)
FMR46 = 1 ?
REIT
Yes
FMR41 = 1(4)
FMR41 = 0
Access flash memory
FMR43 = 1 ?
Yes
No
Access flash memory
No
I = 1 (enable interrupt)(3)
FMR40 = 1
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 509 of 580
REJ09B0324-0200
20.4.4 Status Registers
The status register indicates the operating status of the flash memory and whether an erase or program operation
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and
FMR07 in the FMR0 register.
Table 20.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:
•When a given address in the user ROM area is read after writing the read status register command
•When a given address in the user ROM area is read after executing program or block erase command but
before executing the read array command.
20.4.4.1 Sequencer Status (Bits SR7 and FMR00)
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during auto-
programming and auto-erasure, and is set to 1 (ready) at the same time the operation comp let e s.
20.4.4.2 Erase Status (Bits SR5 and FMR07)
Refer to 20.4.5 Full Status Check.
20.4.4.3 Program Status (Bits SR4 and FMR06)
Refer to 20.4.5 Full Status Check.
D0 to D7:Indicate the data bus which is read when the read status register command is executed.
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot
be accepted.
Table 20.5 Status Register Bits
Status Register
Bit
FMR0 Register
Bit Status Name Description Value After
Reset
01
SR0 (D0) −Reserved −−−
SR1 (D1) −Reserved −−−
SR2 (D2) −Reserved −−−
SR3 (D3) −Reserved −−−
SR4 (D4) FMR06 Program status Completed
normally
Error 0
SR5 (D5) FMR07 Erase status Completed
normally
Error 0
SR6 (D6) −Reserved −−−
SR7 (D7) FMR00 Sequencer
status
Busy Ready 1
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 510 of 580
REJ09B0324-0200
20.4.5 Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Table 20.6 lists the Errors and FMR0 Register Status. Figure 20.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
NOTE:
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.
At the same time, the command code written in the first bus cycle is disabled.
Table 20.6 Errors and FMR0 Regi ster Status
FRM0 Register (Status
Register) Status Error Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1 1 Command
sequence
error
• When a command is not written correctly
• When invalid data other than that which can be written
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)(1)
• When the program command or block erase command
is executed while rewriting is disabled by the FMR02 bit
in the FMR0 register, or the FMR15 or FMR16 bit in the
FMR1 register.
• When an address not allocated in flash memory is input
during erase command input
• When attempting to erase the block for which rewriting
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write to a block for which rewriting
is disabled during write command input.
1 0 Erase error • When the block erase command is executed but auto-
erasure does not complete correctly
0 1 Program error • When the program command is executed but not auto-
programming does not complete.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 511 of 580
REJ09B0324-0200
Figure 20.16 Full Status Check and Handling Procedure for Individual Errors
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block
erase command is executed.
Full status check
FMR06 = 1
and
FMR07 = 1?
FMR07 = 1?
FMR06 = 1?
Full status check completed
No
Yes
Yes
No
Yes
No
Command sequence error
Erase error
Program error
Command sequence error
Execute the clear status register command
(set these status flags to 0)
Check if command is properly input
Re-execute the command
Erase error
Execute the clear status register command
(set these status flags to 0)
Erase command
re-execution times ≤ 3 times?
Re-execute block erase command
Program error
Execute the clear status register
command
(set these status flags to 0)
Specify the other address besides the
write address where the error occurs for
the program address(1)
Re-execute program command
Block targeting for erasure
cannot be used
No
Yes
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 512 of 580
REJ09B0324-0200
20.5 Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of Standard serial I/O modes:
•Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
•Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
•Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3.
Refer t o Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator.
Contact the manufacturer of your serial programmer for details. Refer to the user ’s manual of your serial
programmer for instructions on how to use it.
Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 20.8 lists the Pin Functions
(Flash Memory Standard Serial I/O Mode 3), and Figure 20.17 shows Pin Connections for Standard Serial I/O
Mode 3.
After processing the pins sh own in Table 20.8 and rew rit ing the flash memory using t he programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
20.5.1 ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match (refer to 20.3 Functions to Prevent Rewriting of Flash Memory).
Table 20.7 Pin Functions (Flash Memory S tandard Serial I/O Mode 2)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
VREF Reference voltage input I Reference voltage input pin to A/D converter and D/A
converter.
RESET Reset input I Reset input pin.
P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins.
P4_7/XOUT P4_7 input/clock output I/O
P4_3/XCIN P4_3 input/clock input I Connect crystal oscillator between pins XCIN and
XCOUT.
P4_4/XCOUT P4_4 input/clock output I/O
P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open.
P1_0 to P1_7 Input port P1 I
P2_0 to P2_7 Input port P2 I
P3_0 to P3_7 Input port P3 I
P4_5 Input port P4 I
P5_0 to P5_4 Input port P5 I
P6_0 to P6_5 Input port P6 I
P8_0 to P8_6 Input port P8 I
P6_6 TXD output O Serial data output pin.
P6_7 RXD input I Serial data input pin.
MODE MODE I Input “L” level signal.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 513 of 580
REJ09B0324-0200
Table 20.8 Pin Functions (Flash Memory S tandard Serial I/O Mode 3)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
VREF Reference voltage input I Reference voltage input pin to A/D converter and D/A
converter.
RESET Reset input I Reset input pin.
P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins when connecting
external oscillator. Apply “H” and “L” or leave the pin
open when using as input port.
P4_7/XOUT P4_7 input/clock output I/O
P4_3/XCIN P4_3 input/clock input I Connect crystal oscillator between pins XCIN and
XCOUT when connecting external oscillator. Apply “H”
and “L” or leave the pin open when using as a port.
P4_4/XCOUT P4_4 input/clock output I/O
P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open.
P1_0 to P1_7 Input port P1 I
P2_0 to P2_7 Input port P2 I
P3_0 to P3_7 Input port P3 I
P4_5 Input port P4 I
P5_0 to P5_4 Input port P5 I
P6_0 to P6_7 Input port P6 I
P8_0 to P8_6 Input port P8 I
MODE MODE I/O Serial data I/O pin. Connect to the flash programmer.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 514 of 580
REJ09B0324-0200
Figure 20.17 Pin Connections for Standard Serial I/O Mode 3
Connect oscillator circuit(1)
Package: PLQP0064KB-A
PLQP0064GA-A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R8C/2A Group,
R8C/2B Group
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCC
MODE VSS
Mode setting
Signal Value
MODE
RESET
Voltage from programmer
VSS → VCC NOTE:
1. It is not necessary to connect an oscillating circuit
when operating with the on-chip oscillator clock.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 515 of 580
REJ09B0324-0200
20.5.1.1 Example of Circuit Application in Standard Serial I/O Mode
Figure 20.18 shows an example of Pin Processing in Standard Serial I/O Mode 2 and Figure 20.19 shows an
example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the
programmer, refer to the manual of your serial programmer for details.
Figure 20.18 Pin Processing in Standard Serial I/O Mod e 2
Figure 20.19 Pin Processing in Standard Serial I/O Mod e 3
NOTES:
1. In this example, modes are switched between single-chip mode and
standard serial I/O mode by controlling the MODE input with a switch.
2. Connecting the oscillation is necessary. Set the main clock frequency 1
MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example
with M16C Flash Starter (M3A-0806).
MCU
TXD
RXD
Data Output
Data Input
MODE
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit.
MCU
MODE
RESET
User reset signal
MODE I/O
Reset input
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 516 of 580
REJ09B0324-0200
20.6 Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user ’s m anual of the parallel
programmer for details on how to use it.
ROM areas shown in Figures 20.1 and 20.2 can be rewritten in parallel I/O mode.
20.6.1 ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to the 20.3
Functions to Prevent Rewriting of Flash Memory.)
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 517 of 580
REJ09B0324-0200
20.7 Notes on Flash Memory
20.7.1 CPU Rewrite Mode
20.7.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
20.7.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
20.7.1.3 Interrupts
Table 20.9 lists the EW0 Mode Interrupt s and Table 20.10 lists the EW1 Mode Int errupts.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Table 20.9 EW0 Mode Interrupts
Mode Status
When Maskable
Interrupt Request is
Acknowledged
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
EW0 During auto-erasure Any interrupt can be used
by allocating a vector in
RAM
Once an interrupt request is acknowledged,
auto-programming or auto-erasure is
forcibly stopped immediately and the flash
memory is reset. Interrupt handling starts
after the fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it completes
normally.
Since the watchdog timer does not stop
during the command operation, interrupt
requests may be generated. Reset the
watchdog timer regularly.
Auto-programming
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 518 of 580
REJ09B0324-0200
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Table 20.10 EW1 Mode Interrupts
Mode Status When Maskable Interrupt
Request is Acknowledged
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
EW1 During auto-erasure
(erase-suspend
function enabled)
Auto-erasure is suspended after
td(SR-SUS) and interrupt
handling is executed. Auto-
erasure can be restarted by
setting the FMR41 bit in the
FMR4 register to 0 (erase restart)
after interrupt handling
completes.
Once an interrupt request is
acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt handling starts after the
fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly
using the erase-suspend function.
During auto-erasure
(erase-suspend
function disabled)
Auto-erasure has priority and the
interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-erasure
completes.
During auto-
programming
(program suspend
function enabled)
Auto-programming is suspended
after td(SR-SUS) and interrupt
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
During auto-
programming
(program suspend
function disabled)
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
R8C/2A Group, R8C/2B Group 20. Flash Memory
Rev.2.00 Nov 26, 2007 Page 519 of 580
REJ09B0324-0200
20.7.1.4 How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
20.7.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
20.7.1.6 Program
Do not write additions to the already programmed address.
20.7.1.7 Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
20.7.1.8 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 520 of 580
REJ09B0324-0200
21. Electrical Characteristics
Table 21.1 Absolute Maximum Ratings
Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage -0.3 to 6.5 V
VIInput voltage -0.3 to VCC + 0.3 V
VOOutput voltage -0.3 to VCC + 0.3 V
PdPower dissipation Topr = 25°C700mW
Topr Operating ambient temperature -20 to 85 (N version) /
-40 to 85 (D version)
°C
Tstg Storage temperature -65 to 150 °C
The electrical ch aracteristics of N ver sion (Topr = –20°C to 85°C) and D version (Topr = –40°C to 85°C) are
listed below.
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr =
–20°C to 105°C).
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 521 of 580
REJ09B0324-0200
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Figure 21.1 Ports P0 to P6, P8 Timing Measurement Circuit
Table 21.2 Recommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.2 −5.5 V
VSS/AVSS Supply voltage −0−V
VIH Input “H” voltage 0.8 VCC −VCC V
VIL Input “L” voltage 0 −0.2 VCC V
IOH(sum) Peak sum output
“H” current
Sum of all pins IOH(peak) −−−240 mA
IOH(sum) Average sum
output “H” current
Sum of all pins IOH(avg) −−−120 mA
IOH(peak) Peak output “H”
current
Except P2_0 to P2_7 −−-10 mA
P2_0 to P2_7 −−-40 mA
IOH(avg) Average output
“H” current
Except P2_0 to P2_7 −−-5 mA
P2_0 to P2_7 −−-20 mA
IOL(sum) Peak sum output
“L” current
Sum of all pins IOL(peak) −−240 mA
IOL(sum) Average sum
output “L” current
Sum of all pins IOL(avg) −−120 mA
IOL(peak) Peak output “L”
current
Except P2_0 to P2_7 −−10 mA
P2_0 to P2_7 −−40 mA
IOL(avg) Average output
“L” current
Except P2_0 to P2_7 −−5mA
P2_0 to P2_7 −−20 mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
2.2 V ≤ VCC < 2.7 V 0 −5MHz
f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz
−System clock OCD2 = 0
XlN clock selected
3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
2.2 V ≤ VCC < 2.7 V 0 −5MHz
OCD2 = 1
On-chip oscillator clock
selected
FRA01 = 0
Low-speed on-chip
oscillator clock selected
−125 −kHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
−−20 MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
−−10 MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
−−5MHz
P0
P1
P2
P3
P4
P5
P6
P8
30pF
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 522 of 580
REJ09B0324-0200
NOTES:
1. VCC/AVCC = Vref = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
NOTES:
1. VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF
not connected), IVref flows into the D/A converters.
Table 21.3 A/D Converter Characteristics(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution Vref = AVCC −−10 Bit
−Absolute
accuracy
10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±3 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±5 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±2 LSB
10-bit mode φAD = 5 MHz, Vref = AVCC = 2.2 V −−±5 LSB
8-bit mode φAD = 5 MHz, Vref = AVCC = 2.2 V −−±2 LSB
Rladder Resistor ladder Vref = AVCC 10 −40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 −−µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 −−µs
Vref Reference voltage 2.2 −AVCC V
VIA Analog input voltage(2) 0−AVCC V
−A/D operating
clock frequency
Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 −10 MHz
With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 −10 MHz
Without sample and hold Vref = AVCC = 2.2 to 5.5 V 0.25 −5MHz
With sample and hold Vref = AVCC = 2.2 to 5.5 V 1 −5MHz
Table 21.4 D/A Converter Characteristics(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution −−8Bit
−Absolute accuracy −−1.0 %
tsu Setup time −−3µs
ROOutput resistor 4 10 20 kΩ
IVref Reference power input current (NOTE 2) −−1.5 mA
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 523 of 580
REJ09B0324-0200
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 21.5 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) R8C/2A Group 100(3) −−times
R8C/2B Group 1,000(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
td(SR-SUS) Time delay from suspend request until
suspend
−−97+CPU clock
× 6 cycles
µs
−Interval from erase start/restart until
following suspend request
650 −−µs
−Interval from program start/restart until
following suspend request
0−−ns
−Time from suspend until program/erase
restart
−−3+CPU clock
× 4 cycles
µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(7) Ambient temperature = 55°C20 −−year
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 524 of 580
REJ09B0324-0200
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 21.6 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 10,000(3) −−times
−Byte program time
(program/erase endurance ≤ 1,000 times)
−50 400 µs
−Byte program time
(program/erase endurance > 1,000 times)
−65 −µs
−Block erase time
(program/erase endurance ≤ 1,000 times)
−0.2 9 s
−Block erase time
(program/erase endurance > 1,000 times)
−0.3 −s
td(SR-SUS) Time delay from suspend request until
suspend
−−97+CPU clock
× 6 cycles
µs
−Interval from erase start/restart until
following suspend request
650 −−µs
−Interval from program start/restart until
following suspend request
0−−ns
−Time from suspend until program/erase
restart
−−3+CPU clock
× 4 cycles
µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature -20(8) −85 °C
−Data hold time(9) Ambient temperature = 55 °C20 −−year
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 525 of 580
REJ09B0324-0200
Figure 21.2 Time delay until Suspend
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 21.7 Voltage Detection 0 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet0 Voltage detection level 2.2 2.3 2.4 V
−Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V −0.9 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(2)
−−300 µs
Vccmin MCU operating voltage minimum value 2.2 −−V
Table 21.8 Voltage Detection 1 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Voltage detection level 2.70 2.85 3.00 V
−Voltage monitor 1 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3)
−−100 µs
Table 21.9 Voltage Detection 2 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Voltage detection level 3.3 3.6 3.9 V
−Voltage monitor 2 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3)
−−100 µs
FMR46
Suspend request
(maskable interrupt request)
Fixed time
td(SR-SUS)
Clock-dependent
time Access restart
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 526 of 580
REJ09B0324-0200
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
Figure 21.3 Power-on Reset Circuit Electrical Characteristics
Table 21.10 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) −−0.1 V
Vpor2 Power-on reset or voltage monitor 0 reset valid
voltage
0−Vdet0 V
trth External power VCC rise gradient(2) 20 −−mV/msec
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
Vdet0(3)
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
2.2V
External
Power VCC
trth
trth
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 527 of 580
REJ09B0324-0200
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the correction value in the FRA6 register is written to the FRA1 register.
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 21.11 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency
temperature • supply voltage dependence
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(2)
39.2 40 40.8 MHz
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(2)
39.0 40 41.0 MHz
VCC = 2.2 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(3)
35.2 40 44.8 MHz
VCC = 2.2 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(3)
34.0 40 46.0 MHz
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register
VCC = 5.0 V, Topr = 25°C−36.864 −MHz
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
−3% −3% %
−Value in FRA1 register after reset 08h −F7h −
−Oscillation frequency adjustment unit of high-
speed on-chip oscillator
Adjust FRA1 register
(value after reset) to -1
−+0.3 −MHz
−Oscillation stability time VCC = 5.0 V, Topr = 25°C−10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−550 −µA
Table 21.12 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
−Oscillation stability time VCC = 5.0 V, Topr = 25°C−10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA
Table 21.13 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2)
1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 528 of 580
REJ09B0324-0200
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Table 21.14 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 −−
tCYC(2)
tHI SSCK clock “H” width 0.4 −0.6 tSUCYC
tLO SSCK clock “L” width 0.4 −0.6 tSUCYC
tRISE SSCK clock rising
time
Master −− 1tCYC(2)
Slave −− 1µs
tFALL SSCK clock falling
time
Master −− 1tCYC(2)
Slave −− 1µs
tSU SSO, SSI data input setup time 100 −− ns
tHSSO, SSI data input hold time 1 −−
tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 −− ns
tLAG SCS hold time Slave 1tCYC + 50 −− ns
tOD SSO, SSI data output delay time −− 1tCYC(2)
tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V −−1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V −−1.5tCYC + 200 ns
tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V −−1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V −−1.5tCYC + 200 ns
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 529 of 580
REJ09B0324-0200
Figure 21.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 0
CPHS, CPOS: Bits in SSMR register
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 530 of 580
REJ09B0324-0200
Figure 21.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
VIH or VOH
VIH or VOH
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 0
tOD
tLEAD
tSA
tLAG
tOR
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
tOD
tLEAD
tSA
tLAG
tOR
CPHS, CPOS: Bits in SSMR register
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 532 of 580
REJ09B0324-0200
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Figure 21.7 I/O Timing of I2C bus Interface
Table 21.15 Timing Requirements of I2C bus Interface (1)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) −−ns
tSCLH SCL input “H” width 3tCYC + 300(2) −−ns
tSCLL SCL input “L” width 5tCYC + 500(2) −−ns
tsf SCL, SDA input fall time −−300 ns
tSP SCL, SDA input spike pulse rejection time −−
1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) −−ns
tSTAH Start condition input hold time 3tCYC(2) −−ns
tSTAS Retransmit start condition input setup time 3tCYC(2) −−ns
tSTOP Stop condition input setup time 3tCYC(2) −−ns
tSDAS Data input setup time 1tCYC + 20(2) −−ns
tSDAH Data input hold time 0 −−ns
SDA
tSTAH
tSCLL
tBUF
VIH
VIL
tSCLH
SCL
tsr
tsf
tSDAH
tSCL
tSTAS
tSP tSTOP
tSDAS
P(2) S(1) Sr(3) P(2)
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 533 of 580
REJ09B0324-0200
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Table 21.16 Electrical Characteristics (1) [VCC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7,
XOUT
IOH = -5 mA VCC − 2.0 −VCC V
IOH = -200 µAVCC − 0.5 −VCC V
P2_0 to P2_7 Drive capacity HIGH IOH = -20 mA VCC − 2.0 −VCC V
Drive capacity LOW IOH = -5 mA VCC − 2.0 −VCC V
XOUT Drive capacity HIGH IOH = -1 mA VCC − 2.0 −VCC V
Drive capacity LOW IOH = -500 µAVCC − 2.0 −VCC V
VOL Output “L” voltage Except P2_0 to P2_7,
XOUT
IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
P2_0 to P2_7 Drive capacity HIGH IOL = 20 mA −−2.0 V
Drive capacity LOW IOL = 5 mA −−2.0 V
XOUT Drive capacity HIGH IOL = 1 mA −−2.0 V
Drive capacity LOW IOL = 500 µA−−2.0 V
VT+-VT- Hysteresis INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
0.1 0.5 −V
RESET 0.1 1.0 −V
IIH Input “H” current VI = 5 V −−5.0 µA
IIL Input “L” current VI = 0 V −−-5.0 µA
RPULLUP Pull-up resistance VI = 0 V 30 50 167 kΩ
RfXIN Feedback
resistance
XIN −1.0 −MΩ
RfXCIN Feedback
resistance
XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 534 of 580
REJ09B0324-0200
Table 21.17 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply
current
(V
CC
= 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
clock mode
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−12 20 mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−10 16 mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−7−mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−5.5 −mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4.5 −mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−3−mA
High-speed
on-chip
oscillator mode
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−612mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
Low-speed
on-chip
oscillator mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−150 400 µA
Low-speed
clock mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−150 400 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−35 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−30 90 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−18 55 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−3.5 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.3 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.7 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.7 −µA
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 535 of 580
REJ09B0324-0200
Timing Requirements
(Unless Otherwise Specified: V CC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Figure 21.8 XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Figure 21.9 TRAIO Input and INT1 Input Timing Diagram when VCC = 5 V
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
Figure 21.10 TRFI Input Timing Diagram when VCC = 5 V
Table 21.18 X I N Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 50 −ns
tWH(XIN) XIN input “H” width 25 −ns
tWL(XIN) XIN input “L” width 25 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 21.19 TRAIO Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 −ns
tWH(TRAIO) TRAIO input “H” width 40 −ns
tWL(TRAIO) TRAIO input “L” width 40 −ns
Table 21.20 T RFI Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRFI) TRFI input cycle time 400(1) −ns
tWH(TRFI) TRFI input “H” width 200(2) −ns
tWL(TRFI) TRFI input “L” width 200(2) −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 5 V
TRAIO input
VCC = 5 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
tWH(TRFI)
tc(TRFI)
tWL(TRFI)
TRFI input
VCC = 5 V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 536 of 580
REJ09B0324-0200
i = 0 to 2
Figure 21.11 Serial Interface Timing Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 21.12 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Table 21.21 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 200 −ns
tW(CKH) CLKi input “H” width 100 −ns
tW(CKL) CLKi input “L” width 100 −ns
td(C-Q) TXDi output delay time −50 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 50 −ns
th(C-D) RXDi input hold time 90 −ns
Table 21.22 External Interrupt INTi (i = 0, 2, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 250(1) −ns
tW(INL) INT0 input “L” width 250(2) −ns
tW(CKH)
tC(CK)
tW(CKL)
th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
i = 0 to 2
VCC = 5 V
INTi input
tW(INL)
tW(INH)
i = 0, 2, 3
VCC = 5 V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 537 of 580
REJ09B0324-0200
NOTE:
1. VCC =2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Table 21.23 Electrical Characteristics (3) [VCC = 3 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7,
XOUT
IOH = -1 mA VCC − 0.5 −VCC V
P2_0 to P2_7 Drive capacity
HIGH
IOH = -5 mA VCC − 0.5 −VCC V
Drive capacity
LOW
IOH = -1 mA VCC − 0.5 −VCC V
XOUT Drive capacity
HIGH
IOH = -0.1 mA VCC − 0.5 −VCC V
Drive capacity
LOW
IOH = -50 µAVCC − 0.5 −VCC V
VOL Output “L” voltage Except P2_0 to P2_7,
XOUT
IOL = 1 mA −−0.5 V
P2_0 to P2_7 Drive capacity
HIGH
IOL = 5 mA −−0.5 V
Drive capacity
LOW
IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH
IOL = 0.1 mA −−0.5 V
Drive capacity
LOW
IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
0.1 0.3 −V
RESET 0.1 0.4 −V
IIH Input “H” current VI = 3 V −−4.0 µA
IIL Input “L” current VI = 0 V −−-4.0 µA
RPULLUP Pull-up resistance VI = 0 V 66 160 500 kΩ
RfXIN Feedback resistance XIN −3.0 −MΩ
RfXCIN Feedback resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 538 of 580
REJ09B0324-0200
Table 21.24 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 −mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 11 mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.2 −mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−145 400 µA
Low-speed
clock mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−145 400 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−30 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−28 85 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−17 50 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−3.3 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.1 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.65 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.65 −µA
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 539 of 580
REJ09B0324-0200
Timing requirements
(Unless Otherwise Specified: V CC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Figure 21.13 XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 21.14 TRAIO Input and INT1 Input Timing Diagram when VCC = 3 V
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
Figure 21.15 TRFI Input Timing Diagram when VCC = 3 V
Table 21.25 X I N Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 100 −ns
tWH(XIN) XIN input “H” width 40 −ns
tWL(XIN) XIN input “L” width 40 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 21.26 TRAIO Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 300 −ns
tWH(TRAIO) TRAIO input “H” width 120 −ns
tWL(TRAIO) TRAIO input “L” width 120 −ns
Table 21.27 T RFI Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRFI) TRFI input cycle time 1200(1) −ns
tWH(TRFI) TRFI input “H” width 600(2) −ns
tWL(TRFI) TRFI input “L” width 600(2) −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 3 V
TRAIO input
VCC = 3 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
TRFI input
tWH(TRFI)
tc(TRFI)
tWL(TRFI)
VCC = 3 V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 540 of 580
REJ09B0324-0200
i = 0 to 2
Figure 21.16 Serial Interface Timing Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 21.17 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Table 21.28 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 300 −ns
tW(CKH) CLKi input “H” width 150 −ns
tW(CKL) CLKi Input “L” width 150 −ns
td(C-Q) TXDi output delay time −80 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 70 −ns
th(C-D) RXDi input hold time 90 −ns
Table 21.29 External Interrupt INTi (i = 0, 2, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 380(1) −ns
tW(INL) INT0 input “L” width 380(2) −ns
tW(CKH)
tC(CK)
tW(CKL)
th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 3 V
i = 0 to 2
INTi input
tW(INL)
tW(INH)
VCC = 3 V
i = 0, 2, 3
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 541 of 580
REJ09B0324-0200
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Table 21.30 Electrical Characteristics (5) [VCC = 2.2 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7,
XOUT
IOH = -1 mA VCC - 0.5 −VCC V
P2_0 to P2_7 Drive capacity
HIGH
IOH = -2 mA VCC - 0.5 −VCC V
Drive capacity
LOW
IOH = -1 mA VCC - 0.5 −VCC V
XOUT Drive capacity
HIGH
IOH = -0.1 mA VCC - 0.5 −VCC V
Drive capacity
LOW
IOH = -50 µAVCC - 0.5 −VCC V
VOL Output “L” voltage Except P2_0 to P2_7,
XOUT
IOL = 1 mA −−0.5 V
P2_0 to P2_7 Drive capacity
HIGH
IOL = 2 mA −−0.5 V
Drive capacity
LOW
IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH
IOL = 0.1 mA −−0.5 V
Drive capacity
LOW
IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
0.05 0.3 −V
RESET 0.05 0.15 −V
IIH Input “H” current VI = 2.2 V −−4.0 µA
IIL Input “L” current VI = 0 V −−-4.0 µA
RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ
RfXIN Feedback resistance XIN −5−MΩ
RfXCIN Feedback resistance XCIN −35 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 542 of 580
REJ09B0324-0200
Table 21.31 Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−2.5 −mA
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−4−mA
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.7 −mA
Low-speed on-
chip oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−110 300 µA
Low-speed
clock mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−125 350 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−27 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−20 60 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−12 40 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.8 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−1.9 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.6 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.60 −µA
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 543 of 580
REJ09B0324-0200
Timing requirements
(Unless Otherwise Specified: V CC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Figure 21.18 XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Figure 21.19 TRAIO Input and INT1 Input Timing Diagram when VCC = 2.2 V
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
Figure 21.20 TRFI Input Timing Diagram when VCC = 2.2 V
Table 21.32 X I N Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 200 −ns
tWH(XIN) XIN input “H” width 90 −ns
tWL(XIN) XIN input “L” width 90 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 21.33 TRAIO Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time TBD −ns
tWH(TRAIO) TRAIO input “H” width TBD −ns
tWL(TRAIO) TRAIO input “L” width TBD −ns
Table 21.34 T RFI Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRFI) TRFI input cycle time 2000(1) −ns
tWH(TRFI) TRFI input “H” width 1000(2) −ns
tWL(TRFI) TRFI input “L” width 1000(2) −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 2.2 V
TRAIO input
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
VCC = 2.2 V
TRFI input
tWH(TRFI)
tc(TRFI)
tWL(TRFI)
VCC = 2.2 V
R8C/2A Group, R8C/2B Group 21. Electrical Characteristics
Rev.2.00 Nov 26, 2007 Page 544 of 580
REJ09B0324-0200
i = 0 to 2
Figure 21.21 Serial Interface Timing Diagram when VCC = 2.2 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 21.22 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Table 21.35 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 800 −ns
tW(CKH) CLKi input “H” width 400 −ns
tW(CKL) CLKi input “L” width 400 −ns
td(C-Q) TXDi output delay time −200 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 150 −ns
th(C-D) RXDi input hold time 90 −ns
Table 21.36 External Interrupt INTi (i = 0, 2, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 1000(1) −ns
tW(INL) INT0 input “L” width 1000(2) −ns
tW(CKH)
tC(CK)
tW(CKL)
th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 2.2 V
i = 0 to 2
INTi input
tW(INL)
tW(INH)
VCC = 2.2 V
i = 0, 2, 3
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 545 of 580
REJ09B0324-0200
22. Usage Notes
22.1 Notes on Clock Generation Circuit
22.1.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR 1,FMR0 ; CPU rewrite mode disabled
BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
22.1.2 Wait Mode
When entering wait m ode, set the FMR01 bit in the FMR0 regist er to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WA IT instruction
BCLR 1,FMR0 ; CPU rewrite mode disabled
FSET I ; Enable interrupt
WAIT ; Wait mode
NOP
NOP
NOP
NOP
22.1.3 Oscillation S top Detection Function
Since the oscillation stop detectio n function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
22.1.4 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 546 of 580
REJ09B0324-0200
22.2 Notes on Interrupts
22.2.1 Reading Address 00000h
Do not read address 0000 0h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
22.2.2 SP Setting
Set any value in the SP before an interrupt is acknowl edged. The SP i s set to 000 0h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
22.2.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is ne cessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, re fer to Table 21.22 (V CC = 5V), Table 21.29 (VCC = 3V), Table 21.36 (VCC = 2.2V) External
Interrupt INTi (i = 0, 2, 3) Input and Table 21.19 (VCC = 5V), Table 21.26 (VCC = 3V), Table 21.33 (VCC
= 2.2V) TRAIO Input, INT1 Input.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 547 of 580
REJ09B0324-0200
22.2.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involve s interrupt so urces, edge polarities, an d timing, set t he IR bit to 0 (no i nterrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 22.1 shows an Example of Procedure for Changing In terrup t Sources.
Figure 22.1 Example of Procedure for Changing Interrupt Sources
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated,
disable the peripheral function before changing the
interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled. If all maskable interrupts cannot
be disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Interrupt source change
Disable interrupts(2, 3)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Change interrupt source (including mode
of peripheral function)
Enable interrupts(2, 3)
Change completed
IR bit: The interrupt control register bit of an
interrupt whose source is changed.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 548 of 580
REJ09B0324-0200
22.2.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are gen erated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt req uested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR , BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the samp le programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 549 of 580
REJ09B0324-0200
22.3 Notes on Timers
22.3.1 Notes on Timer RA
•Timer RA stops counting after a reset. Set the values in th e timer RA and timer RA prescalers before the
count starts.
•Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
•In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR regi ster, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instru ction.
•When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
•The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
•When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
•The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with tim er RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (duri ng count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
•When the TRAPRE register is continuously wri tten during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
•When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 550 of 580
REJ09B0324-0200
22.3.2 Notes on Timer RB
•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer val ue may be updated duri ng the period when th ese two registers are bei ng
read.
•In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR
register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in
programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer
count value before the timer stops.
•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit.
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elap sed. If th e TOSSP bit is written to 1 d uring the peri od
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
22.3.2.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 551 of 580
REJ09B0324-0200
22.3.2.2 Programmable waveform generation mode
The following three workarounds should be performe d in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operat ion (TCSTF bit is set to 1 ), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 22.2 and 22.3.
The following shows the detailed workaround examp les.
•Workaround example (a):
As shown in Figure 22.2, writ e to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginni ng of period A.
Figure 22.2 Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
IR bit in
TRBIC register
Secondary period
(b)
Interrupt
sequence
Instruction in
interrupt routine
Interrupt request is
acknowledged
(a)
Interrupt request
is generated
Ensure suffici ent time
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 552 of 580
REJ09B0324-0200
•Workaround example (b):
As shown in Figure 22.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’ s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicat es the TRBO pin output value.
Figure 22.3 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
22.3.2.3 Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuousl y during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
•When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then the primary register immediately.
(ii) (iii)
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 553 of 580
REJ09B0324-0200
22.3.2.4 Programmable wait one-shot generation mode
The following three workarounds should be performe d in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 554 of 580
REJ09B0324-0200
22.3.3 Notes on Timer RC
22.3.3.1 TRC Register
•The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register
is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register
is set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
•Reading from the TRC register immediat ely after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example MOV.W #XXXXh, TRC ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.W TRC,DATA ;Read
22.3.3.2 TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions .
Program Example MOV.B #XXh, TRCSR ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.B TRCSR,DATA ;Read
22.3.3.3 Count Source Switching
•Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
•After switching the count source from fOCO40M to another clock, allow a min imu m of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
22.3.3.4 Input Capture Function
•The pulse width of the input capture sign al shoul d be three cycles or more of the timer RC operation clock
(refer to Table 14.12 Timer RC Operation Clock).
•The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
22.3.3.5 TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 555 of 580
REJ09B0324-0200
22.3.4 Notes on Timer RD
22.3.4.1 TRDSTR Register
•Set the TRDSTR register using the MOV instruction.
•When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
•Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is se to 0.
•To stop counting by a program, set t he TSTARTi bit after setting the CSELi bit to 1. Although the CSELi
bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 inst ruction), the count cannot be
stopped.
•Table 22.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Co unt Stops to use the TRDIOji (j
= A, B, C, or D) pin with the timer RD output.
22.3.4.2 TRDi Register (i = 0 or 1)
•When writing the valu e to th e TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting t he TRDi register to 0000h overla ps with the tim ing for writing the value to
the TRDi register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the
TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
•When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example MOV.W #XXXXh, TRD0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.W TRD0,DATA ;Reading
22.3.4.3 TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example MOV.B #XXh, TRDSR0 ;Writing
JMP.B L1 ;JMP.B
L1: MOV.B TRDSR0,DATA ;Reading
Table 22.1 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Count Stop TRDIOji Pin Output when Count Stops
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count
stops.
Hold the output level immediately before the
count stops.
When the CSELi bit is set to 0, the count stops at compare match of
registers TRDi and TRDGRAi.
Hold the output level after output changes by
compare match.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 556 of 580
REJ09B0324-0200
22.3.4.4 Count Source Switch
•Switch the count source after the count stops.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi regist er.
•When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO 40M.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi regist er.
(3) Wait 2 or more cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
22.3.4.5 Input Capture Function
•Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.26 Timer RD Operation Clocks).
•The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD
operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or
D) (no digital filter).
22.3.4.6 Reset Synchronous PWM Mode
•When reset synchronous PWM mode is used for moto r control, make sure OLS0 = OLS1.
•Set to reset synchronous PWM mode by the following pro cedure:
Change procedure
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
22.3.4.7 Complementary PWM Mode
•When complementary PWM mode is used for moto r control, make sure OLS0 = OLS1.
•Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
timing from the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Change procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
•Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values wri tten to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGR A1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 557 of 580
REJ09B0324-0200
•If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
Figure 22.4 Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Complementary PWM Mode
No change
IMFA bit in
TRDSR0 register
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Count value in TRD0
register
Setting value in
TRDGRA0
register m
m+1
Set to 0 by a program
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 11b
(transfer from the buffer register to the
general register at compare match of
between registers TRD0 and
TRDGRA0).
1
0
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 558 of 580
REJ09B0324-0200
•The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to
CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at
underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During
FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this
time, the OVF bit remains unchanged.
Figure 22.5 Operation when TRD1 Register Underflows in Complementary PWM Mode
No change
UDF bit in
TRDSR0 register
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Count value in TRD0
register
Set to 0 by a program
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 10b
(transfer from the buffer register to the
general register when the TRD1 register
underflows).
OVF bit in
TRDSR0 register
FFFFh
1
0
1
0
0
1
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 559 of 580
REJ09B0324-0200
•Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:
Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is
transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1
to CMD0.
Figure 22.6 Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
Complementary PWM Mode
0000h
TRDGRD0 register
TRDIOB0 output
n3
n2
m+1
n3
n2
n1
n2 n1
n3
n2 n2 n1n1TRDGRB0 register
Transfer
Transfer at
underflow of TRD1
register because of
n3 > m
Transfer at
underflow of TRD1
register because
of first setting to
n2 < m
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
Count value in TRD0
register
Count value in TRD1
register
Transfer with timing set by
bits CMD1 to CMD0
Transfer with timing set by
bits CMD1 to CMD0
Transfer Transfer Transfer
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 560 of 580
REJ09B0324-0200
When the value in the buffer register is set to 0000h:
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register , and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general regi ster. Af ter that, the valu e is transferred with the
timing selected by bits CMD1 to CMD0 .
Figure 22.7 Operation when Value in Buffer Register Is Set to 000 0h in Complementary PWM
Mode
22.3.4.8 Count Source fOCO40M
•The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
0000h
TRDGRD0 register
TRDIOB0 output
n1
m+1
n2
n1
0000h n1
0000h
n1 n1n2TRDGRB0 register
Transfer
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in TRDGRD0
register is set to
0000h.
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001h ≤ n1 < m
Transfer with timing
set by bits CMD1 to
CMD0
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
Count value in TRD0 register
Count value in TRD1 register
Transfer with timing
set by bits CMD1 to
CMD0
Transfer Transfer Transfer
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 561 of 580
REJ09B0324-0200
22.3.5 Notes on Timer RE
22.3.5.1 Starting and Stopping Count
Timer RE has the TSTART bit f or instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counti ng and the TCSTF bit is set to 1 ( count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTA RT bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
22.3.5.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
•Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
•Bits H12_H24, PM, and INT in TRECR1 register
•Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 22.8 shows a Setting Example in Real-Time Clock Mode.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 562 of 580
REJ09B0324-0200
Figure 22.8 Setting Example in Real-Time Clock Mode
Stop timer RE operation
TCSTF in
TRECR1 register = 0?
TSTART in TRECR1 register = 0
TRERST in TRECR1 register = 1
TRERST in TRECR1 register = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2 register
TSTART in TRECR1 register = 1
TCSTF in
TRECR1 register = 1?
TREIC register←00h
(disable timer RE interrupt)
Setting of TREIC register (IR bit←0,
select interrupt priority level)
Timer RE register
and control circuit reset
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Start timer RE operation
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 563 of 580
REJ09B0324-0200
22.3.5.3 Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated befo re another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
•Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
•Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
•Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms whil e the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
•Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TRE HR, and TREW K and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat unti l the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 564 of 580
REJ09B0324-0200
22.3.6 Notes on Timer RF
•Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W 0290H,R0 ; Read out timer RF
•In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 565 of 580
REJ09B0324-0200
22.4 Notes on Serial Interface
•When reading data from the UiRB (i = 0 to 2) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
•When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit un its.
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 566 of 580
REJ09B0324-0200
22.5 Notes on Clock Synchronous Serial Interface
22.5.1 Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
22.5.2 Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
22.5.2.1 Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
•Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
•Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
22.5.2.2 Master Receive Mode
Either of the following actions must be performed to use th e I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 568 of 580
REJ09B0324-0200
22.7 Notes on A/D Converter
•Write to each bit (other than ADST bit) in the ADCON0 register, each bit in the ADCON1 register, or the
SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
•After changing the A/D operatin g mode, select an analog input pin again.
•When using the one- sh ot mo de, ensu re that A/D conversion is completed before reading the AD0 register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
•When using the repeat mode 0, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion .
Do not select the fOCO-F for the φAD.
•If the ADST bit in the ADCON0 register is set to 0 (A/D conv ersion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD0 register.
•Connect 0.1 µF capacitor between the VREF pin and AVSS pin.
•Do not enter stop mode during A/D conversion.
•Do not enter wait mode when the CM02 bi t in the CM0 regi ster is set to 1 (peripheral function clock stops in
wait mode) during A/D conversi on.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 569 of 580
REJ09B0324-0200
22.8 Notes on Flash Memory
22.8.1 CPU Rewrite Mode
22.8.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
22.8.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
22.8.1.3 Interrupts
Table 22.2 lists the EW0 Mode Interrupts and Table 22.3 lists the EW1 Mode Interrupts.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Table 22.2 EW0 Mode Interrupts
Mode Status
When Maskable
Interrupt Request is
Acknowledged
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
EW0 During auto-erasure Any interrupt can be used
by allocating a vector in
RAM
Once an interrupt request is acknowledged,
auto-programming or auto-erasure is
forcibly stopped immediately and the flash
memory is reset. Interrupt handling starts
after the fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it completes
normally.
Since the watchdog timer does not stop
during the command operation, interrupt
requests may be generated. Reset the
watchdog timer regularly.
Auto-programming
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 570 of 580
REJ09B0324-0200
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Table 22.3 EW1 Mode Interrupts
Mode Status When Maskable Interrupt
Request is Acknowledged
When Watchdog Timer, Oscillation
Stop Detection, Voltage Monitor 1, or
Voltage Monitor 2 Interrupt Request is
Acknowledged
EW1 During auto-erasure
(erase-suspend
function enabled)
Auto-erasure is suspended after
td(SR-SUS) and interrupt
handling is executed. Auto-
erasure can be restarted by
setting the FMR41 bit in the
FMR4 register to 0 (erase restart)
after interrupt handling
completes.
Once an interrupt request is
acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt handling starts after the
fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly
using the erase-suspend function.
During auto-erasure
(erase-suspend
function disabled)
Auto-erasure has priority and the
interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-erasure
completes.
During auto-
programming
(program suspend
function enabled)
Auto-programming is suspended
after td(SR-SUS) and interrupt
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
During auto-
programming
(program suspend
function disabled)
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 571 of 580
REJ09B0324-0200
22.8.1.4 How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
22.8.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
22.8.1.6 Program
Do not write additions to the already programmed address.
22.8.1.7 Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
22.8.1.8 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
R8C/2A Group, R8C/2B Group 22. Usage Notes
Rev.2.00 Nov 26, 2007 Page 572 of 580
REJ09B0324-0200
22.9 Notes on Noise
22.9.1
Inserting a Byp ass Cap acitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
22.9.2 Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port relate d registers
may be changed.
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull- up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
R8C/2A Group, R8C/2B Group 23. Notes on On-Chip Debugger
Rev.2.00 Nov 26, 2007 Page 573 of 580
REJ09B0324-0200
23. Notes on On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/2A Group and R8C/2B Group take note
of the following.
(1) Do not access the related UART1 registers.
(2) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
(3) Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
(4) Do not use the BRK instruction in a user system.
(5) Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and usin g the on-chip debugger has so me special restrictions. Refer to the on-chip deb ugger manual for
details.
R8C/2A Group, R8C/2B Group 24. Notes on Emulator Debugger
Rev.2.00 Nov 26, 2007 Page 574 of 580
REJ09B0324-0200
24. Notes on Emulator Debugger
When using the emulator debugger to develop the R8C/2A Group and R8C/2B Group program and debug, pay the
following attention.
(1) Do not use the following flash memory areas because these areas are used for the emulator debugger.
When debugging of these areas, intensive evaluation on the real chip is required.
Target product: ROM capacity 128 MB product (Refer to Table 1.5 Product List for R8C/2A Group and
Table 1.6 Product List for R8C/2B Group)
Unusable area: Addresses 20000h to 23FFFh
Connecting and using the emulator debugger has some peculiar restrictions. Refer to each emulator debugger manual
for emulator debugger details.
R8C/2A Group, R8C/2B Group Appendix 1. Package Dimensions
Rev.2.00 Nov 26, 2007 Page 575 of 580
REJ09B0324-0200
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
Terminal cross section
b
1
c
1
b
p
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Index mark
*3
17
32
64
49
116
3348
F
*1
*2
x
y
b
p
H
E
E
H
D
D
Z
D
Z
E
Detail F
A
c
A
2
A
1
L
1
L
P-LQFP64-10x10-0.50 0.3g
MASS[Typ.]
64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A
RENESAS CodeJEITA Package Code Previous Code
1.0
0.125
0.18
1.25
1.25
0.08
0.20
0.145
0.09
0.250.200.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
10.110.0
9.9
D
10.110.0
9.9
E
1.4
A2
12.212.011.8
12.212.011.8
1.7
A
0.15
0.1
0.05
0.65
0.5
0.35
L
x
8°0°
c
0.5
e
0.08
y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
e
Terminal cross section
b1
c1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*3
116
17
32
33
48
49
64
F
*1
*2
x
y
Index mark
D
HD
E
H
E
ebp
ZD
Z
E
Detail F
c
A
A
2
A
1
L
L1
Previous CodeJEITA Package Code RENESAS Code
PLQP0064GA-A 64P6U-A
MASS[Typ.]
0.7gP-LQFP64-14x14-0.80
1.0
0.125
0.35
1.0
1.0
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
14.114.013.9
D
14.114.013.9
E
1.4
A2
16.216.015.8
16.216.015.8
1.7
A
0.20.1
0
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
R8C/2A Group, R8C/2B Group Appendix 1. Package Dimensions
Rev.2.00 Nov 26, 2007 Page 576 of 580
REJ09B0324-0200
0.15
v
0.20
w
Previous CodeJEITA Package Code RENESAS Code
PTLG0064JA-A 64F0G
MASS[Typ.]
0.07gP-TFLGA64-6x6-0.65
0.08
0.470.430.39
MaxNomMin
Dimension in Millimeters
Symbol
Reference
6.0
D
6.0
E
1.05
A
x
0.65
e
0.10
y
b
1
b0.31 0.35 0.39
B
w
S
wA
S
A
H
G
F
E
D
C
B
12345678
S
yS
AB
Index mark
SAB
v
x4
(Laser mark)
Index mark
D
E
A
b
1
b
e
e
R8C/2A Group, R8C/2B GroupAppendix 2. Connection Examples between Serial Writer and On-Chip Debugging
Rev.2.00 Nov 26, 2007 Page 577 of 580
REJ09B0324-0200
Appendix 2. Connection Examples between Serial Writer and On-Chip
Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2
shows a Connection Example with E8 Emulator (R0E000080KCE00).
Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806)
Appendix Figure 2.2 Connection Example with E8 Emulator (R0E000080KCE00)
NOTE:
1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock.
RXD 4
7 VSS
1 VCC
10
M16C Flash Starter
(M3A-0806)
RXD
TXD
VSS
VCC
TXD
RESET
MODE
Connect oscillation
circuit(1)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R8C/2A Group,
R8C/2B Group
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NOTE:
1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock.
MODE
4.7kΩ ±10%
E8 emulator
(R0E000080KCE00)
RESET
12
10
8
6
4
2
VSS
13
7 MODE
VCC
14
VSS
VCC
Connect oscillation
circuit(1)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R8C/2A Group,
R8C/2B Group
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
4.7kΩ or more
Open collector buffer
User logic
R8C/2A Group, R8C/2B Group Appendix 3. Example of Oscillation Evaluation Circuit
Rev.2.00 Nov 26, 2007 Page 578 of 580
REJ09B0324-0200
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
Appendix Figure 3.1 Example of Oscillation Evaluation Circuit
Connect
oscillation
circuit
NOTE:
1. After reset, the XIN and XCIN clocks stop.
Write a program to oscillate the XIN and XCIN clocks.
VSS
VCC
RESET
Connect
oscillation
circuit
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R8C/2A Group,
R8C/2B Group
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Rev.2.00 Nov 26, 2007 Page 579 of 580
REJ09B0324-0200
R8C/2A Group, R8C/2B Group Index
[ A ]
AD0 ..................................................................................... 474
ADCON0 ............................................................................. 475
ADCON1 ............................................................................. 476
ADCON2 ............................................................................. 474
ADIC .................................................................................... 127
AIER .................................................................................... 143
[ C ]
CAPIC ................................................................................. 127
CM0 ....................................................................................... 96
CM1 ....................................................................................... 97
CMP0IC ............................................................................... 127
CMP1IC ............................................................................... 127
CPSRF ................................................................................ 101
CSPR .................................................................................. 152
[ E ]
DA0 to DA1 ......................................................................... 488
DACON ............................................................................... 488
[ G ]
FMR0 .................................................................................. 498
FMR1 .................................................................................. 499
FMR4 .................................................................................. 500
FRA0 ..................................................................................... 99
FRA1 ..................................................................................... 99
FRA2 ................................................................................... 100
FRA6 ................................................................................... 100
FRA7 ................................................................................... 100
[ I ]
ICCR1 ................................................................................. 427
ICCR2 ................................................................................. 428
ICDRR ................................................................................. 433
ICDRS ................................................................................. 433
ICDRT ................................................................................. 432
ICIER ................................................................................... 430
ICMR ................................................................................... 429
ICSR .................................................................................... 431
IICIC .................................................................................... 128
INT0IC ................................................................................. 129
INT1IC ................................................................................. 129
INT2IC ................................................................................. 129
INT3IC ................................................................................. 129
INTEN ................................................................................. 137
INTF .................................................................................... 138
[ K ]
KIEN .................................................................................... 141
KUPIC ................................................................................. 127
[ M ]
LINCR ................................................................................. 459
LINCR2 ............................................................................... 459
LINST .................................................................................. 460
MSTCR ............... 198, 250, 265, 283, 297, 308, 323, 396, 426
[ O ]
OCD ...................................................................................... 98
OFS ....................................................................... 36, 152, 493
[ Q ]
P2DRR .................................................................................. 70
PDi (i = 0 to 6 and 8) ............................................................. 68
PM0 ....................................................................................... 90
PM1 ....................................................................................... 90
PMR ....................................................... 70, 136, 380, 403, 433
PRCR .................................................................................. 121
PUR0 ..................................................................................... 71
PUR1 ..................................................................................... 71
PUR2 ..................................................................................... 71
Pi (i = 0 to 6 and 8) ................................................................ 69
[ S ]
S0RIC .................................................................................. 127
S0TIC .................................................................................. 127
S1RIC .................................................................................. 127
S1TIC ................................................................................... 127
S2RIC .................................................................................. 127
S2TIC .................................................................................. 127
SAR ..................................................................................... 432
RMAD0 ................................................................................ 143
RMAD1 ................................................................................ 143
SSCRH ................................................................................ 397
SSCRL ................................................................................. 398
SSER ................................................................................... 400
SSMR .................................................................................. 399
SSMR2 ................................................................................ 402
SSRDR ................................................................................ 403
SSSR ................................................................................... 401
SSTDR ................................................................................ 403
SSUIC .................................................................................. 128
[ U ]
U0C0 to U2C0 ..................................................................... 378
U0C1 to U2C1 ..................................................................... 379
U0BRG to U2BRG ............................................................... 377
U0MR to U2MR ................................................................... 377
U0RB to U2RB .................................................................... 379
U0TB to U2TB ..................................................................... 378
U1SR ................................................................................... 380
TRA ..................................................................................... 160
TRACR ................................................................................ 159
TRAIC .................................................................................. 127
TRAIOC ....................................... 159, 161, 164, 166, 168, 171
TRAMR ................................................................................ 160
TRAPRE .............................................................................. 160
TRC ..................................................................................... 202
TRBCR ................................................................................ 175
TRCCR1 ...................................................... 199, 222, 226, 231
TRCCR2 .............................................................................. 203
TRCDF ................................................................................ 204
TRCGRA ............................................................................. 202
TRCGRB ............................................................................. 202
TRCGRC ............................................................................. 202
TRCGRD ............................................................................. 202
TRBIC .................................................................................. 127
TRCIC .................................................................................. 128
TRCIER ............................................................................... 200
TRBIOC ............................................... 176, 178, 182, 184, 189
TRCIOR0 ............................................................. 206, 215, 220
TRCIOR1 ............................................................. 206, 216, 221
TRBMR ................................................................................ 176
TRCMR ................................................................................ 198
TRBOCR ............................................................................. 175
TRCOER ............................................................................. 205
Index
Rev.2.00 Nov 26, 2007 Page 580 of 580
REJ09B0324-0200
R8C/2A Group, R8C/2B Group Index
TRBPR ................................................................................ 177
TRBPRE .............................................................................. 177
TRBSC ................................................................................ 177
TRCSR ................................................................................ 201
TRD0 ........................................... 259, 276, 291, 303, 316, 331
TRD0IC ............................................................................... 128
TRD1 ........................................................... 259, 276, 291, 316
TRD1IC ............................................................................... 128
TRDCR0 ...................................... 255, 271, 288, 301, 313, 329
TRDCR1 ...................................................... 255, 271, 288, 313
TRECR1 ...................................................................... 348, 355
TRECR2 ...................................................................... 349, 355
TRECSR ..................................................................... 350, 356
TRDDF0 .............................................................................. 254
TRDDF1 .............................................................................. 254
TRDFCR ..................................... 253, 268, 286, 299, 311, 326
TRDGRAi (i = 0 to 1) ................... 260, 276, 292, 304, 316, 332
TRDGRC1 ........................................................................... 316
TRDGRBi (i = 0 to 1) ................... 260, 276, 292, 304, 316, 332
TRDGRCi (i = 0 to 1) ........................... 260, 276, 292, 304, 332
TRDGRDi (i = 0 to 1) ................... 260, 276, 292, 304, 316, 332
TREIC ................................................................................. 127
TRDIER0 ..................................... 259, 275, 290, 303, 315, 331
TRDIER1 ..................................... 259, 275, 290, 303, 315, 331
TRDIORA0 .................................................................. 256, 272
TRDIORA1 .................................................................. 256, 272
TRDIORC0 .................................................................. 257, 273
TRDIORC1 .................................................................. 257, 273
TREHR ................................................................................ 347
TREMIN ...................................................................... 346, 354
TRDMR ....................................... 251, 266, 284, 298, 310, 325
TRDOCR ............................................................. 270, 288, 328
TRDOER1 ........................................... 269, 287, 300, 312, 327
TRDOER2 ........................................... 269, 287, 300, 312, 327
TRDPMR ............................................................. 252, 267, 285
TRDPOCR0 ........................................................................ 291
TRDPOCR1 ........................................................................ 291
TRESEC ...................................................................... 346, 354
TRDSR0 ...................................... 258, 274, 289, 302, 314, 330
TRDSR1 ...................................... 258, 274, 289, 302, 314, 330
TRDSTR ...................................... 251, 266, 284, 298, 309, 324
TREWK ............................................................................... 347
TRF ..................................................................................... 363
TRFCR0 .............................................................................. 364
TRFCR1 .............................................................................. 365
TRFIC .................................................................................. 127
TRFM0 ................................................................................ 363
TRFM1 ................................................................................ 363
TRFOUT .............................................................................. 365
[ W ]
VCA1 ..................................................................................... 45
VCA2 ............................................................................. 45, 101
WDC .................................................................................... 151
WDTR ................................................................................. 151
WDTS .................................................................................. 151
VW0C .................................................................................... 46
VW1C .................................................................................... 47
VW2C .................................................................................... 48
C - 1
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
Rev. Date Description
Page Summary
0.01 Jul 28, 2006 −First Edition issued
0.10 Sep 15, 2006 95 Figure 10.6 FRA1 register NOTE1 revised
110 Figure 10.14 revised
160 Table 14.5 revised
202 Figure 14.39 revised
254 Figure 14.80 revised
382 Figure 15.12 revised
428 Figure 16.33 revised
430 Figure 16.34, Figure 16.35 revised
432 Figure 16.36 revised
433 Figure 16.37 revised
461 Table 17.2 revised
496 18.6 revised
560 23 (2) revised, (5) deleted
1.00 Feb 09, 2007 All pages “Preliminary” deleted
3 Table 1.2 revised
5 Table 1.4 revised
6 Table 1.5 and Figure 1.1 revised
7 Table 1.6 and Figure 1.2 revised
17 Figure 3.1 revised
18 Figure 3.2 revised
19 Table 4.1;
• 0008h:
“Module Standby Control Register”
→
“Module Operation Enable Register” revised
• 000Ah: “00XXX000b” → “00h” revised
• 000Fh: “00011111b” → “00X11111b” revised
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6” added
23 Table 4.5;
0105h: “LIN Control Register 2” register name revised
36 5.2 and Figure 5.7 revised
42 Figure 6.5; VCA2 register NOTE6 revised
72 Table 7.17 and Table 7.19 revised
76 Table 7.29 and Table 7.31 revised
77 Table 7.35 revised
88 Table 9.1, Table 9.2 and Table 9.3 revised
89 Table 9.4 added
90 10 and Table 10.1 NOTE4 revised
91 Figure 10.1 revised
93 Figure 10.3 NOTE4 revised
96 Figure 10.6; FRA0 register NOTE2 revised
R8C/2A Group, R8C/2B Group Hardware Manual
REVISION HISTORY
C - 2
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
1.00 Feb 09, 2007 97 Figure 10.7; FRA2 register revised, FRA6 register added
98 Figure 10.9 NOTE6 revised
99 Figure 10.10 added
101 10.2.2 revised
106 10.5.1.2 and 10.5.1.4 revised
108 Table 10.3 revised
110 10.5.2.5 and Figure 10.14 revised
112 Figure 10.15 revised
117 10.7.1 and 10.7.2 revised
118 Figure 11.1 revised
121 12.1.3.1 revised
135 Figure 12.14 revised and Figure 12.15 added
136 Figure 12.16 NOTE1 revised
139 Table 12.6 revised
143 12.6.4 deleted
148 Figure 13.2; WDC register revised
180 Table 14.10 NOTE2 added
185 Table 14.11 NOTE2 added
192 Figure 14.25 revised
201 Table 14.15 revised
224 Table 14.23 revised
227 Figure 14.57 revised
244 Figure 14.67 revised
258 Table 14.40 revised
259 Figure 14.82 revised
260 Figure 14.83; TRDSTR register revised
271 Figure 14.95 revised
274 Figure 14.97 revised
276 Table 14.42 revised
277 Figure 14.99 revised
278 Figure 14.100; TRDSTR register revised
290 Table 14.44 revised
291 Figure 14.113 revised
292 Figure 14.114; TRDSTR register revised
302 Figure 14.124 revised
303 Figure 14.125 revised
316 Table 14.48 revised
317 Figure 14.137 revised
318 Figure 14.138 revised
Rev. Date Description
Page Summary
C - 3
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
1.00 Feb 09, 2007 331 14.4.12.1 and Table 14.51 revised
355 to
367
14.6; The following bit name is revised.
• TRFC00 → TSTART, TRFC01 → TCK0, TRFC02 → TCK1: Bits in
TRFCR0 register
• TRFC10 → TIPF0, TRFC11 → TIPF1, TRFC12 → CCLR, TRFC13 →
TMOD: Bits in TRFCR1 register
359 Figure 14.178 NOTE1 deleted
365 Figure 14.181 revised
367 14.6.3 revised
375 Table 15.1 NOTE2 revised
378 Figure 15.9 revised
381 Table 15.4 revised
384 Figure 15.12 revised
387 15.3 revised
390 Figure 16.2 MSTCR register added
395 Figure 16.7 NOTE2 revised
420 Figure 16.25 revised
421 Figure 16.26 NOTE7 added
423 Figure 16.28 NOTE3 revised
450 16.3.8.2 and 16.3.8.3 added
453 Figure 17.2; LINCR2 register revised
456 Figure 17.5 revised
460 Figure 17.9 revised
461 Figure 17.10 revised
462 17.4.3 and Figure 17.11 revised
463 17.4.4 added
469 Figure 18.3 NOTE4 revised
471 Table 18.2 revised
472 Figure 18.5 NOTE4 revised
475 Figure 18.7 NOTE4 revised
480 18.7 revised
483 Table 20.1 and Table 20.2 revised
484 20.2 and Figure 20.1 revised
485 Figure 20.2 revised
488 Table 20.3 NOTE1 revised
489 20.4.1 and 20.4.2; “td(SR-ES)” → “td(SR-SUS)” revised
490 20.4.2.3 and 20.4.2.4 revised
491 20.4.2.15 revised
492 Figure 20.5 revised
494 Figure 20.7 NOTE5 revised
Rev. Date Description
Page Summary
C - 4
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
1.00 Feb 09, 2007 496
Figure 20.9 “any area othe r than the flash memory”
→
“the RAM” revised
497 Figure 20.11;
“any area other than the flash memory”
→
“the RAM”,
“15 µs” → “30 µs”, and NOTES 1 and 3 revised
499 20.4.3.4 revised
500 Figure 20.13 revised
501 20.4.3.5 revised
502 Figure 20.15 revised
504 Table 20.6 “FRM00 Register” → “FRM0 Register” revised
506 Table 20.7 revised
514 Table 21.2 revised
515 Table 21.3 and Table 21.4; NOTE1 revised
520 Table 21.11 revised
527 Table 21.17 revised
529 Table 21.21 and Figure 21.11; “i = 0 to 2” revised
531 Table 21.24 revised
533 Table 21.28 revised, Figure 21.16 “i = 0 to 2” revised
535 Table 21.31 revised
536 Table 21.34 revised
537 Table 21.35 and Figure 21.21; “i = 0 to 2” revised
538 22.1.1 and 22.1.2 revised
539 22.2.4 deleted
545 22.3.4.1 and Ta ble 22. 1 re vise d
554 22.3.6 revised
555 22.4 revised
557 22 .5.2.2 and 22.5 .2 .3 added
559 22.7 revised
565 24. Notes on Emulator Debugger added
567 Appendix Figure 2.1 and Appendix Figure 2.2 revised
568 Appendix Figure 3.1 NOTE1 revised
2.00 Nov 26, 20 07 −“RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A 16 4A/E, TN-16C -A1 67A / E
All pages “PTLG0064JA-A (64F0G) package” added
2, 4 Table 1.1, Table 1.3 Clock: “Real-time clock (timer RE)” added
3, 5 Tab le 1.2 and Table 1.4;
• Operating Ambient Temperature: Y version added
• Package: 64 -p in F LG A add e d
NOTE1 added
6, 7 Tab le 1.5 and Figure 1.1 revised
8, 9 Tab le 1.6 and Figure 1.2 revised
11 Fig ur e 1. 4 “6 4- pin LQFP Packa ge ” ad de d
Rev. Date Description
Page Summary
C - 5
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
2.00 Nov 26 , 20 07 12 Fig ur e 1.5 added
20, 21 Figure 3. 1 an d Fig u re 3.2 revis ed
22 Table 4.1 002Ch: High-Sp eed On-C hip Oscillato r Control Register 7
added
25 Table 4.4 00F5h: After reset “00h” → “0 00 000 XXb ” re vise d
36 Fig ur e 5. 3 re vise d
36, 152,
493 Figure 5.4, Figure 13.3, Figure 20.4 OFS NOTE1 revised
37 5.1.1, 5.1.2 “Wait for 1/fOCO-S × 20.” → “Wait for 10 µs or more.”
38 Figure 5.5, Figure 5.6 revised
75 Table 7.17 Function: RXD0 inpu t NO TE1 adde d
79 Table 7.29 revised
85 Table 7.54 Function: Inpu t po rt NO TE1 added
Table 7.55 Fu nc tion : RXD2 inpu t NO TE1 adde d
86 Table 7.58 Function: RXD1 inpu t NO TE1 ad ded
94 Figure 10.1 “Clock prescaler” added
99 Figure 10.6 FRA1 revised
100 Figure 10.7 FRA2: NOTE2 deleted, FRA7 added
104 10.2.2 “The frequency correction .... to the FRA1 before use.” added
117 10.6.1 “To use the high-speed on-chip oscillator clock for the CPU clock
.... and then set bits OCD1 to OCD0 to 11b.” revised
136 12.2.1 “.... with the pulse output forced cutoff of timer RD and the INT1
pin is shared with the external trigger input pin of timer RA.”
→ “.... with the pulse output forced cutoff of timer RC and timer
RD, and the external trigger input of timer RB.”
147 Fig ure 12 .2 2 NO TE2 revised
156 Table 14.1 Timer RE: Count sources “• fC32” deleted
157 Table 14.2 Timer RC: “TRDIOA” → “TRCIOA”, “TRDIOB” → “TRCIOB”,
“TRDIOC” → “TRCIOC”, “TRDIO D” → “TRCIOD”
Timer RF: Input pin “TCIN” → “TRFI”
158 Figure 14.1 “TSTART” → “TCSTF”
162 Fig ure 14 .5 “Both bits TSTART ... are set to 0 (During count).”
→ “Both bits TSTART ... are set to 1 (During count).”
173 14.1.6 “• When the TRAPRE register is .... for each write interval.
• When the TRA register is .... for each write interval.” added
174 14.2 “The reload register and counter are allocated at the same
address” deleted
177 Figure 14.15 “Programmable one-shot mode” → “Programmable one-
shot generation mode”
180 Figure 14.17 “Both bits TSTART .... are set to 0 (During count).”
→ “Both bits TSTART .... are set to 1 (During count).”
Rev. Date Description
Page Summary
C - 6
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
2.00 Nov 26, 2007 183 Tab l e 14.1 0 Co un t sto p co nd itio ns :
“• When the TOSSP .... is set to 0 (one-shot stops).”
→ “• When the TOSSP .... is set to 1 (one-shot stops).”
191 14.2.5 NOTE TRBIOC added
191 to 194
14.2.5.1, 14.2.5.2, 14.2.5.3, 14.2.5.4 added
204 Figure 14.37 TRCIOR0: b3 revised, NOTE4 added
213 14.3.4 “The TRCGRA register can .... input-capture trigger input.” added
Table 14.1 7 re vise d
214 Figure 14.43 revised
215 Fig ur e 14.4 4 b3 rev i se d, NOTE3 added
218 Table 14.19 Select functions:
“or output level inverted” → “or toggle output”
220 Fig ure 14 .4 8 b3 rev ise d
223 Figure 14.51 “• The CCLR bit in the TRCCR1 register is set to 0 ....”
→ “• The CCLR bit in the TRCCR1 register is set to 1 ....”
269 Figure 14.88 TRDOER1 revised
274 Figure 14.93 revised
280 Figure 14.99 revised
289 Figure 14.107 revised
298 Figure 14.116 “TRD” → “TRD0”
302 Figure 14.120 revised
304 Figure 14.123 NOTE1 revised
309 Figure 14.127 b0, b1 revised
310 Figure 14.128 “TRD” → “TRD0”
314 Figure 14.132 revised
324 Figure 14.140 revised
330 Figure 14.146 revised
334 Figur e 14 .1 50 “TST P0 bit in TR DST R re gist er ” → “CSEL0 bit in
TRDSTR register”
350 Figure 14.164 b 0, b1: “Set to 0 0 in re al- time clock mod e.” → “Se t to 00 b
in real-time clock mode.”
359 Figure 14.173 revised
365 Figure 14.179 NOTE4 added
377 Figure 15.4 UARTi Transmit/Receive Mode Register revised
380 Figure 15.7 After Reset: “00h” → “000000 XXb ”, b1 -b 0 revis ed
388 Table 15.5 NOTE2 added
397 Figure 16.3 NOTE4 deleted
398 Figure 16.4 SOLP: “Cannot w rite to this.” → “The SOLP bit remains
unchanged even if 1 is written to it.”, NOTE4 deleted
399 Figure 16.5 NOTE2 deleted
Rev. Date Description
Page Summary
C - 7
REVISION HISTORY R8C/2A Group, R8C/2B Group Hardware Manual
2.00 Nov 26, 2007 400 Figure 16.6 NOTE1 deleted
401 Figure 16.7 NOTE7 revised
402 Figure 16.8 NOTE5 revised
403 Figure 16.9 SSTDR NOTE1 deleted, SSRDR NOTE2 deleted
417 Figure 16.19 revised
423 16 .2.8.1 deleted
427 Fig ur e 16 .26 NOTE6 de let ed
428 Fig ur e 16 .27 NOTE5 de let ed
429 Fig ur e 16 .28 NOTE7 de let ed
430 Fig ur e 16 .29 NOTE3 de let ed
431 Fig ur e 16 .30 NOTE7 de let ed
432 Figur e 16 .3 1 SAR, ICDRT NOTE1 delete d
433 Figure 16.31 ICDRR NOTE1 deleted
456 16 .3.8.1 deleted
457 Figure 17.1 revised
459 17.3 “• LIN Special Function Register (LINCR2)” → “• LIN Control
Register 2 (LINCR2)”
462, 463 Figure 17.5, Figure 17.6 revised
464 Figure 17.7 revised
466 Figure 17.9 revised
469 Figure 17.12 revised
484 Figure 18.11 revised
494 Table 20.3 Areas in which a rewrite co ntr ol pro gr am can be ex ec ute d :
EW1 Mode “Executing directly in use r ROM area is p ossible”
→ “Executing directly in user ROM or RAM area possible”
500 Figure 20.7 NOTE5 revised
502 Figure 20.9 NOTE2 “Write to the FMR01 bit in the RAM.” added
503 Figure 20.11 NOTE4 deleted
506, 508 Figure 20.13, Figu r e 20 .1 5 re vise d
520 Table 21.1 Pd: Rated Value “TBD” → “700” revised
521 Table 21.2 NOTE2 revised
527 Table 21.11 revised
562 Figure 22.8 revised
566 22.5.1.1, 22.5.2.1 deleted
577 Package Dimensions “PTLG0064JA-A (64F0G) package” added
578 Appendix Figure 2.1, Appendix Figure 2.2 revised
579 Appendix Figure 3.1 revised
Rev. Date Description
Page Summary
R8C/2A Group, R8C/2B Group Hardware Manual
Publication Date: Rev.0.01 Jul 28, 2006
Rev.2.00 Nov 26, 2007
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan
R8C/2A Group, R8C/2B Group
Hardware Manual
