ESD8351HT1G - ON SEMICONDUCTOR

August, 2018 − Rev. 10 1Publication Order Number:

ESD8351/D

ESD8351, SZESD8351

ESD Protection Diodes

Low Capacitance ESD Protection Diode

for High Speed Data Line

The ESD8351 Series ESD protection diodes are designed to protect

high speed data lines from ESD. Ultra−low capacitance and low ESD

clamping voltage make this device an ideal solution for protecting

voltage sensitive high speed data lines.

Features

•Low Capacitance (0.55 pF Max, I/O to GND)

•Protection for the Following IEC Standards:

IEC 61000−4−2 (Level 4)

ISO 10605

•Low ESD Clamping Voltage

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•USB 2.0

•eSATA

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Operating Junction Temperature Range TJ−55 to +125 °C

Storage Temperature Range Tstg −55 to +150 °C

Lead Solder Temperature −

Maximum (10 Seconds) TL260 °C

IEC 61000−4−2 Contact (ESD)

IEC 61000−4−2 Air (ESD)

ISO 10605 330 pF / 2 kW Contact

ESD

±15

±30

Maximum Peak Pulse Current

8/20 ms @ TA = 25°CIpp 5.0 A

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

See Application Note AND8308/D for further description of

survivability specs.

MARKING

DIAGRAMS

X3DFN2

CASE 152AF

PIN CONFIGURATION

AND SCHEMATIC

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X, XX = Specific Device Code

M = Date Code

Cathode 2

Anode

SOD−323

CASE 477

SOD−523

CASE 502

PIN 1

2AE

2AF

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

ESD8351, SZESD8351

www.onsemi.com

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

VRWM Working Peak Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

VHOLD Holding Reverse Voltage

IHOLD Holding Reverse Current

RDYN Dynamic Resistance

IPP Maximum Peak Pulse Current

VCClamping Voltage @ IPP

VC = VHOLD + (IPP * RDYN)

VCVRWMVHOLD

VBR

RDYN

IHOLD

−IPP

RDYN

IPP

VC = VHOLD + (IPP * RDYN)

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM I/O Pin to GND 3.3 V

Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 7.0 7.8 V

Reverse Leakage Current IRVRWM = 3.3 V, I/O Pin to GND 500 nA

Holding Reverse Voltage VHOLD I/O Pin to GND 1.15 V

Holding Reverse Current IHOLD I/O Pin to GND 20 mA

Clamping Voltage

TLP (Note 2)

See Figures 1 through 11

VCIPP = 8 A IEC 61000−4−2 Level 2 equivalent

(±4 kV Contact, ±4 kV Air) 6.5 V

IPP = 16 A IEC 61000−4−2 Level 4 equivalent

(±8 kV Contact, ±15 kV Air) 11.2

Clamping Voltage (Note 3) VCIPP = 5 A tp = 8 x 20 ms8.2 V

Dynamic Resistance RDYN Pin1 to Pin2

Pin2 to Pin1 0.62

0.59 W

Junction Capacitance CJVR = 0 V, f = 1 Mhz

VR = 0 V, f = 2.5 Ghz 0.37

0.35 0.55

0.45 pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. For test procedure see Figures 8 and 9 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

3. Non−repetitive current pulse at TA = 20°C, per IEC 61000−4−5 waveform.

ESD8351, SZESD8351

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Figure 1. CV Characteristics

C (pF)

VBias (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

CAPACITANCE (pF)

FREQUENCY

0.1

0.2

0.3

0.4

0.5

1.0

123 567 9

FREQUENCY (Hz)

−14

−12

−10

−8

−6

−4

−2

1E7 1E8 1E9 1E10

002 2016141246810

TLP CURRENT (A)

VC, VOLTAGE (V)

3E10

m1 m2

0.6

0.7

0.8

0.9

4810

EQUIVALENT VIEC (kV)

002 2016141246810

TLP CURRENT (A)

VC, VOLTAGE (V)

EQUIVALENT VIEC (kV)

Figure 2. Clamping Voltage vs Peak Pulse

Current ( tp = 8/20 ms)

Vpk (V)

Ipk (A)

1 1.5 2 3 3.5 4 5

2.5 4.5 5.5

Figure 3. RF Insertion Loss Figure 4. Capacitance over Frequency

Figure 5. Positive TLP I−V Curve Figure 6. Negative TLP I−V Curve

ESD8351, SZESD8351

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Latch−Up Considerations

ON Semiconductor’s 8000 series of ESD protection

devices utilize a snap−back, SCR type structure. By using

this technology, the potential for a latch−up condition was

taken into account by performing load line analysis of

common high speed serial interfaces. Example load lines for

latch−up free applications and applications with the

potential for latch−up are shown below with a generic IV

characteristic of a snapback, SCR type structured device

overlaid on each. In the latch−up free load line case, the IV

characteristic of the snapback protection device intersects

the load−line in one unique point (VOP, IOP). This is the only

stable operating point of the circuit and the system is

therefore latch−up free. In the non−latch up free load line

case, the IV characteristic of the snapback protection device

intersects the load−line in two points (VOPA, IOPA) and

(VOPB, IOPB). Therefore in this case, the potential for

latch−up exists if the system settles at (VOPB, IOPB) after a

transient. Because of this, ESD8351 Series should not be

used for HDMI applications – ESD8104 or ESD8040 have

been designed to be acceptable for HDMI applications

without latch−up. Please refer to Application Note

AND9116/D for a more in−depth explanation of latch−up

considerations using ESD8000 series devices.

Figure 7. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch−up

ESD8351 Potential Latch*up:

HDMI 1.4/1.3a TMDS

ESD8351 Latch*up free:

USB 2.0 LS/FS, USB 2.0 HS, USB 3.0 SS,

DisplayPort

ISSMAX

IOPB

IOPA

VOPB VOPA VDD

VOP VDD V

ISSMAX

IOP

Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH−UP FREE APPLICATIONS

Application VBR (min)

(V) IH (min)

(mA) VH (min)

(V) ON Semiconductor ESD8000 Series

Recommended PN

HDMI 1.4/1.3a TMDS 3.465 54.78 1.0 ESD8104, ESD8040

USB 2.0 LS/FS 3.301 1.76 1.0 ESD8004, ESD8351

USB 2.0 HS 0.482 N/A 1.0 ESD8004, ESD8351

USB 3.0 SS 2.800 N/A 1.0 ESD8004, ESD8006, ESD8351

DisplayPort 3.600 25.00 1.0 ESD8004, ESD8006, ESD8351

ESD8351, SZESD8351

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IEC 61000−4−2 Spec.

Level Test Volt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 W aveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 8. IEC61000−4−2 Spec

Figure 9. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD8351, SZESD8351

www.onsemi.com

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 10. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 11 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels.

Figure 10. Simplified Schematic of a Typical TLP

System

DUT

LS÷

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

ORDERING INFORMATION

Device Package Shipping†

ESD8351HT1G,

SZESD8351HT1G* SOD−323

(Pb−Free) 3000 / Tape & Reel

ESD8351XV2T1G,

SZESD8351XV2T1G* SOD−523

(Pb−Free)

3000 / Tape & Reel

ESD8351XV2T5G,

SZESD8351XV2T5G* 8000 / Tape & Reel

ESD8351MUT5G X3DFN2

(Pb−Free) 10000 / Tape & Reel

SZESD8351MUT5G* X3DFN2

(Pb−Free) 15000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP

Capable.

ESD8351, SZESD8351

www.onsemi.com

PACKAGE DIMENSIONS

X3DFN2, 0.62x0.32, 0.355P, (0201)

CASE 152AF

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

A B

BOTTOM VIEW

e2X

L22X

TOP VIEW

0.05 C

CSEATING

PLANE

SIDE VIEW

DIM MIN MAX

MILLIMETERS

A0.25 0.33

A1 −−− 0.05

b0.22 0.28

e0.355 BSC

L2 0.17 0.23

MOUNTING FOOTPRINT*

DIMENSIONS: MILLIMETERS

0.74

0.30

0.31

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

See Application Note AND8398/D for more mounting details

0.05 BC

RECOMMENDED

PIN 1

INDICATOR

(OPTIONAL)

D0.58 0.66

E0.28 0.36

ESD8351, SZESD8351

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PACKAGE DIMENSIONS

SOD−323

CASE 477−02

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. LEAD THICKNESS SPECIFIED PER L/F DRAWING

WITH SOLDER PLATING.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

5. DIMENSION L IS MEASURED FROM END OF RADIUS.

NOTE 3

12bE

CNOTE 5

DIM MIN NOM MAX

MILLIMETERS

A0.80 0.90 1.00

A1 0.00 0.05 0.10

A3 0.15 REF

b0.25 0.32 0.4

C0.089 0.12 0.177

D1.60 1.70 1.80

E1.15 1.25 1.35

0.08

2.30 2.50 2.70

0.031 0.035 0.040

0.000 0.002 0.004

0.006 REF

0.010 0.012 0.016

0.003 0.005 0.007

0.062 0.066 0.070

0.045 0.049 0.053

0.003

0.090 0.098 0.105

MIN NOM MAX

INCHES

1.60

0.063

0.63

0.025 0.83

0.033

2.85

0.112

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ESD8351, SZESD8351

www.onsemi.com

PACKAGE DIMENSIONS

SOD−523

CASE 502

ISSUE E

NOTES:

6. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

7. CONTROLLING DIMENSION: MILLIMETERS.

8. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.

MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

9. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-

TRUSIONS, OR GATE BURRS.

D−X−

−Y−

0.08 X Y

DIM MIN NOM MAX

MILLIMETERS

D1.10 1.20 1.30

E0.70 0.80 0.90

A0.50 0.60 0.70

b0.25 0.30 0.35

c0.07 0.14 0.20

L0.30 REF

H1.50 1.60 1.70

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

RECOMMENDED

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.48 0.40

1.80

DIMENSION: MILLIMETERS

PACKAGE

OUTLINE

L2 0.15 0.20 0.25

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