CY62126EV30 MoBL®
1-Mbit (64 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05486 Rev. *P Revised November 24, 2017
1-Mbit (64 K × 16) Static RAM
Features
■High speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
❐Automotive-A: –40 °C to +85 °C
❐Automotive-E: –40 °C to +125 °C
■Wide voltage range: 2.2 V to 3.6 V
■Pin compatible with CY62126DV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 4 A
■Ultra low active power
❐Typical active current: 1.3 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Offered in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
64K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A0
A1
A9
A10
BLE
Document Number: 38-05486 Rev. *P Page 2 of 18
CY62126EV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
Switching Characteristics ................................................ 7
Switching Waveforms ......................................................8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure .......................................................15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community .................................18
Technical Support ..................................................... 18
Document Number: 38-05486 Rev. *P Page 3 of 18
CY62126EV30 MoBL®
Pin Configuration
Figure 1. 48-ball VFBGA pinout (Top View) Figure 2. 44-pin TSOP II pinout (Top View) [1]
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
NC
NC
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
26
5
4
1
D
E
B
A
C
F
G
H
NC
NC
V
cc
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
NC
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2
(A)
f = 1 MHz f = fmax
Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max
CY62126EV30LL Industrial 2.2 3.0 3.6 45 1.3 2 11 16 1 4
CY62126EV30LL Automotive-A 2.2 3.0 3.6 45 1.3 2 11 16 1 4
CY62126EV30LL Automotive-E 2.2 3.0 3.6 55 1.3 4 11 35 1 30
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05486 Rev. *P Page 4 of 18
CY62126EV30 MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential [3, 4] .....–0.3 V to 3.6 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High Z state [3, 4] .............–0.3 V to 3.6 V (VCCmax + 0.3 V)
DC input voltage [3, 4]  0.3 V to 3.6 V (VCCmax + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current .................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC[5]
CY62126EV30LL Industrial /
Automotive-A –40 °C to +85 °C 2.2 V to
3.6 V
Automotive-E –40 °C to +125 °C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns (Industrial /
Automotive-A) 55 ns (Automotive-E) Unit
Min Typ[6] Max Min Typ[6] Max
VOH Output high voltage IOH = –0.1 mA 2.0 – – 2.0 – – V
IOH = –1.0 mA, VCC > 2.70 V 2.4 – – 2.4 – – V
VOL Output low voltage IOL = 0.1 mA – – 0.4 – 0.4 V
IOL = 2.1 mA, VCC > 2.70 V – – 0.4 – – 0.4 V
VIH Input high voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 1.8 – VCC + 0.3 V
VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 2.2 – VCC + 0.3 V
VIL Input low voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V
VCC = 2.7 V to 3.6 V –0.3 – 0.8 –0.3 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 –4 – +4 A
IOZ Output leakage current GND < VO < VCC, Output
Disabled
–1 – +1 –4 – +4 A
ICC VCC operating supply
current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
–11 16 –11 35 mA
f = 1 MHz – 1.3 2.0 – 1.3 4.0
ISB1[7] Automatic CE power
down current —CMOS
inputs
CE > VCC 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
–1 4 –1 35 A
ISB2 [7] Automatic CE power
down current —CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–1 4 –1 30 A
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 38-05486 Rev. *P Page 5 of 18
CY62126EV30 MoBL®
Capacitance
Parameter [8] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [8] Description Test Conditions 48-ball VFBGA
Package
44-pin TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still Air, soldered on a 4.25 × 1.125 inch,
two-layer printed circuit board
58.85 28.2 °C/W
JC Thermal resistance
(junction to case) 17.01 3.4 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT VTH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameters 2.2 V–2.7 V 2.7 V–3.6 V Unit
R1 16600 1103
R2 15400 1554
RTH 8000 645
VTH 1.2 1.75 V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05486 Rev. *P Page 6 of 18
CY62126EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [9] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR[10] Data retention current VCC = VDR,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
Industrial /
Automotive-A ––3
A
Automotive-E – – 30 A
tCDR[11] Chip deselect to data retention
time
0––ns
tR[12] Operation recovery time CY62126EV30LL-45 45 – – ns
CY62126EV30LL-55 55 – –
Data Retention Waveform
Figure 4. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s.
Document Number: 38-05486 Rev. *P Page 7 of 18
CY62126EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [13, 14] Description
45 ns (Industrial /
Automotive-A) 55 ns (Automotive-E) Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 –55 –ns
tAA Address to data valid –45 –55 ns
tOHA Data hold from address change 10 –10 –ns
tACE CE LOW to data valid –45 –55 ns
tDOE OE LOW to data valid –22 –25 ns
tLZOE OE LOW to Low Z [15] 5–5–ns
tHZOE OE HIGH to High Z [15, 16] –18 –20 ns
tLZCE CE LOW to Low Z [15] 10 –10 –ns
tHZCE CE HIGH to High Z [15, 16] –18 –20 ns
tPU CE LOW to power up 0–0–ns
tPD CE HIGH to power down –45 –55 ns
tDBE BHE / BLE LOW to data valid –22 –25 ns
tLZBE BHE / BLE LOW to Low Z [15] 5–5–ns
tHZBE BHE / BLE HIGH to High Z [15, 16] –18 –20 ns
Write Cycle [17, 18]
tWC Write cycle time 45 –55 –ns
tSCE CE LOW to write end 35 –40 –ns
tAW Address setup to write end 35 –40 –ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 –40 –ns
tBW BHE / BLE pulse width 35 –40 –ns
tSD Data setup to write end 25 –25 –ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to High Z [15, 16] –18 –20 ns
tLZWE WE HIGH to Low Z [15] 10 –10 –ns
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and 30-pF load capacitance.
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
18. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 38-05486 Rev. *P Page 8 of 18
CY62126EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address transition controlled) [19, 20]
Figure 6. Read Cycle No. 2 (OE controlled) [20, 21]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
19. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
20. WE is high for read cycle.
21. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05486 Rev. *P Page 9 of 18
CY62126EV30 MoBL®
Figure 7. Write Cycle No. 1 (WE controlled) [22, 23, 24]
Figure 8. Write Cycle No. 2 (CE controlled) [22, 23, 24]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 25
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 25
Notes
22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any
of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05486 Rev. *P Page 10 of 18
CY62126EV30 MoBL®
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW [26, 27]
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW) [26]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 28
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 28
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Notes
26. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state.
27. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05486 Rev. *P Page 11 of 18
CY62126EV30 MoBL®
Truth Table
CE[29] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/power down Standby (ISB)
L X X H H High Z Output disabled Active (ICC)
L H L L L Data out (I/O0–I/O15) Read Active (ICC)
LHLHLData out (I/O
0–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read Active (ICC)
L H H L L High Z Output disabled Active (ICC)
L H H H L High Z Output disabled Active (ICC)
L H H L H High Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write Active (ICC)
Note
29. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05486 Rev. *P Page 12 of 18
CY62126EV30 MoBL®
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
45 CY62126EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial
CY62126EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial
CY62126EV30LL-45ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A
55 CY62126EV30LL-55BVXE 51-85150 48-ball VFBGA (Pb-free) Automotive-E
CY62126EV30LL-55ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive-E
Contact your local Cypress sales representative for availability of other parts.
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
Voltage: V30 = 3 V Typical
Process Technology: E = 90 nm
Bus Width: 6 = × 16
Density: 2 = 1-Mbit
Family Code: 621= MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 26EV30 LL X X
-
Document Number: 38-05486 Rev. *P Page 13 of 18
CY62126EV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
Document Number: 38-05486 Rev. *P Page 14 of 18
CY62126EV30 MoBL®
Figure 12. 44-pin TSOP II Package Outline, 51-85087
Package Diagrams (continued)
51-85087 *E
Document Number: 38-05486 Rev. *P Page 15 of 18
CY62126EV30 MoBL®
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
RAM Random Access Memory
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mm millimeter
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
Document Number: 38-05486 Rev. *P Page 16 of 18
CY62126EV30 MoBL®
Document History Page
Document Title: CY62126EV30 MoBL®, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05486
Rev. ECN No. Submission
Date
Orig. of
Change Description of Change
** 202760 See ECN AJU New data sheet.
*A 300835 See ECN SYT Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA
Package and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins,
respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 ns
and 45 ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns
speed bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins
respectively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed
bins respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip
can be deselected by either disabling the chip enable signals or by disabling
both BHE and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then
tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B 461631 See ECN NXR Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for
f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz, ISB1, ISB2 (max) from
1A to 4 A, ISB1, ISB2 (Typ) from 0.5 A to 1 A, ICCDR (max) from 1.5 A to
3A, AC Test load Capacitance value from 50 pF to 30 pF, tLZOE from 3 to
5 ns, tLZCE from 6 to 10 ns, tHZCE from 22 to 18 ns, tLZBE from 6 to 5 ns, tPWE
from 30 to 35 ns, tSD from 22 to 25 ns, tLZWE from 6 to 10 ns, and updated the
Ordering Information table.
*C 925501 See ECN VKN Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
*D 1045260 See ECN VKN Added Automotive information
Updated Ordering Information table
*E 2631771 01/07/09 NXR / PYRS Changed CE condition from X to L in Truth table for Output Disable mode
Updated template
*F 2944332 06/04/2010 VKN Added Contents
Removed byte enable from footnote #2 in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
*G 2996166 07/29/2010 AJU Added CY62126EV30LL-45ZSXA part in Ordering Information.
Added Ordering Code Definitions.
Modified table footnote format.
*H 3113864 12/17/2010 PRAS Updated Figure 1 and Package Diagram, and fixed Typo in Figure 3.
Document Number: 38-05486 Rev. *P Page 17 of 18
CY62126EV30 MoBL®
*I 3270487 05/31/2011 RAME Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Electrical Characteristics.
Updated Data Retention Characteristics.
Added Acronyms and Units of Measure.
Updated to new template.
*J 4205722 11/29/2013 MEMJ Updated Features:
Added Automotive-A range information.
Updated Product Portfolio:
Added Automotive-A range information.
Updated Operating Range:
Segregated Automotive-A and Automotive-E ranges.
Updated Electrical Characteristics:
Added Automotive-A with Industrial for 45 ns speed bin.
Renamed Automotive as Automotive-E for 55 ns speed bin.
Updated Data Retention Characteristics:
Segregated Automotive-A and Automotive-E in conditions for ICCDR
parameter.
Updated Switching Characteristics:
Added Automotive-A with Industrial for 45 ns speed bin.
Renamed Automotive as Automotive-E for 55 ns speed bin.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Updated to new template.
*K 4211675 12/12/2013 MEMJ No technical updates.
Removed the border lines in Package Diagram specs.
*L 4410948 06/17/2014 VINI Updated Switching Characteristics:
Added Note 18 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 27 and referred the same note in Figure 9.
Completing Sunset Review.
*M 4576475 11/21/2014 VINI Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*N 4612072 01/05/2015 VINI Updated Maximum Ratings:
Referred Notes 3, 4 in “Supply voltage to ground potential”.
*O 4797476 06/15/2015 VINI Updated to new template.
Completing Sunset Review.
*P 5975641 11/24/2017 AESATMP9 Updated logo and Copyright.
Document History Page (continued)
Document Title: CY62126EV30 MoBL®, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05486
Rev. ECN No. Submission
Date
Orig. of
Change Description of Change
Document Number: 38-05486 Rev. *P Revised November 24, 2017 Page 18 of 18
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