Integrated Circuit Systems, Inc. ICS9176 Low Skew Output Buffer General Description The ICS9176 is designed specifically to support the tight timing requirements of high-performance microprocessors and chip sets. Because the jitter of the device is limited to +250ps, the 1C$9176 is ideal for clocking Pentium systems. The 10 high drive (40mA), low-skew (+250ps) outputs make the 1CS9176 a perfect fit for PCI clocking requirements. The 1CS9176 has 10 outputs synchronized in phase and fre- quency to an input clock. The internal phase locked loop (PLL) acts either as a LX clock multiplier or a 1/2X clock multiplier depending on the state of the input control pins TO and T1. With metal mask options, any type of ratio between the input clock and output clock can be achieved, including 2X. The PLL maintains the phase and frequency relationship be- tween the input clock and the outputs by externally feeding back FBOUT to FBIN. Any change in the input will be tracked by all 10 outputs. However, the change at the outputs will happen smoothly so no glitches will be present on any driven input. The PLL circuitry matches rising edges of the input clock and the output clock. Since the input to FBIN skew is guaran- teed to 500ps, the part acts as a zero delay buffer. The 1CS9176 has a total of eleven outputs. Of these, FROUT is dedicated as the feedback into the PLL and another, Q/2, has an output frequency half that of the remaining nine. These nine outputs can either be running at the same speed as the input, or at half the frequency of the input. With Q/2 as the feedback to FBIN, the nine Q outputs will be running at twice the input frequency in the normal divide-by-| mode. In this case, the output can go to 120 MHz with a 60 MHz input clock. The maximum rise and fall time of an output is Ins and each is TTL-compatible with a 40mA symmetric drive. The I1CS9176 is fabricated using CMOS technology which results in much lower power consumption and cost compared with the gallium arsenide based 1086E. The typical operating current for the ICS9176 is 60mA versus I115mA for the GAI086E. Features e 1C89176-01 is pin compatible with Triquint GA 1086 e =+500ps skew (max) between input and outputs @ =+250ps skew (max) between outputs $10 symmetric, TLL-compatible outputs 28-pin PLCC or 28-pin wide SOICsurtace mount package High drive, 40mA outputs Power-down option Output frequency range 20 MHz to 120 MHz Input frequency range 20 MHz to 100 MHz Ideal for PCI bus applications Selection Table | T =| To DESCRIPTION sid | 0 0 Power-down 0 | l | Test Mode (PLL Off CLK=outputs) | 0 Normal (PLL On) 1 | Divide by 2 Mode Block Diagram FBOUT at a2 a3 aa DIVIDE LOGIC Qs To as CONTROL LOGIC Q7 Q8 Qs Qle v1 Pentium is a trademark ot Intel Corporation ICS9176RevC 120195 D-55ICS9176 Pin Configuration z Qa a Pr gees GND ed Q8 = 2 27 Fm 6 nt Si ZES vbD as GND 1 5 24 F O05 ae O as NC =] 6 23 f= a4 GND GND (pin 1) NC 7 7 53 2 VDD FBOUT E a7 VDD 8 gH 2) Q3 CLK =} 9 q@ 20 Q2 arq a6 T1 =] 10 = 19 fF GND VDD o VDD FBIN = 11 18 PF VDD anesazrea voo + 13 16 = BOUT B CS FCS qr L414 15 F GND 28-Pin PLCC 28-Pin SOIC J-10 J-7 Pin Descriptions PINNUMBER | PINNAME TYPE DESCRIPTION . GND . . (GROUND. 2 Q8 Output Output clock &. 3 Q9 | Output. Output clock 9. 4 ; VDD : - Power supply (+5V). 5 (GND - GROUND. 6 NC / - (No Connect. 7 NC - {No Connect. \ 8 VDD ; - Power supply (+5V). | | 9 CLK : Input _Input for reference clock. . 10 TI ; Input _T1 selects normal operation, power-down, or test mode. tH _FBIN , Input ; FEEDBACK INPUT from output FBOUT. 12 TO i Input TO selects normal operation, power-down, or test mode. 13 VDD : - Power Supply (+5). \4 Qf Output Half-clock output. : IS GND - (GROUND. 16 FBOUT : Output (FEEDBACK OUTPUT to Input FBIN. 17 Ql Output Output clock I. I8 VDD ! - Power Supply (+5V). 19 GND - GROUND. , 20 'Q2 . Output Output elock 2. : 2I Q3 Output Output clock 3. ; 2 VDD . Power supply (+5). 23 Q4 / Output Output clock 4. | 24 QS Output Output clock 5. : 25 GND - GROUND. | 26 VDD | - Power Supply (+5). , | 27 Q6 : Output Output clock 6. | i 28 Q7 Output Output clock 7. D-56ICS9176 Timing Diagrams INPUT CLOCK Q1-Q9 eo! Lei fF Wie Timing in Divide by 1 Mode Db neraox + LI LI LI LI aot Li J L_J- e_| Wnt Timing in Divide by 2 Mode INPUT CLOCK oo ! LI LI LI LL i es Timing in Eliminate by Test Mode Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD. INPUT CLOCK | | | L__| L Q1-Q9 Q/2 Timing in Power-down Mode D-57ICS9176 Absolute Maximum Ratings VDD reterenced toGND ...000.00..0 000000205. IV Operating Temperature under bias... 2.2... OC to +70C Storage Temperature... 000.0000. ee ee -65C to +150C Voltage on I/O pins referenced o GND... 2.0.2... GND -0.5V to VDD +0.5V Power Dissipation. ......0000.0.. 0.000 eee eee 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability, Electrical Characteristics DC Characteristics | PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX | UNITS | Input Low Voltage . Vu. Yopesv , - - . 0.8 , Vv | Input High Voltage VIH | Wpp=SV 2.0 | - - Vv Input Current li VIN=OV, 5V -5 : - | 5 | HA : Output Low Voltage VoL _@loL=l4mA | - 0.25 : 0.4 Vv | Output Low Current lon. @Vo1=0.8V 33 ; 42 - mA 1 Output High Voltage! Vou | @lon=-38mA 2.4 - | - Vv i Output High Current! = oH | @VH=2.0V ; - | -59 | -41 , mA Supply Current. Ipb Unloaded outputs, : - 55 75 mA - _ Normal Mode @ 66.6 MHz : | Supply Current, Ipp-PD ITI, To=0, 0 - | 2.0 10.0 mA | | Power-down Mode : : | Note: 1. Guaranteed by design and characterization. Not subject to [00% test. D-58ICS9176 AC Characteristics | PARAMETER | SYMBOL | TESTCONDITIONS | MIN + TYP. | MAX ~ UNITS | pS OREAeS | pee MeL EN EEE a ae Input Clock Pulse Width! | CLKw |VDD=45V.feLk=l00MHz | 2500 | | Ss Output Rise time, tr I5pF load - i 0.7 | ns 0.8t020VE Cb eee Pe, - _ Rise time, [| t, |1SpF toad po 15 2 ns 20% 10.80% Vop! | ao coef nef a Output Fall time, tf i 15pF load - 0.7 1 ns 2.0V to 0.8V! Joe . _ Fall time, tr 15pF load - 1.2 2 ns {80% 10.20% Vopt | a _ a . . ae Output Duty cycle! | ch ISpPload,Note3 5 | AST Jiter, Vsigmat Tw - 60 - ___Ps Jitter, absolute! Tabs ee +100 | 2500 ops Unput Frequency | ee 100 MHz | Output Frequency fo For outputs >100 MHz, 20 - 120 MHz (Qoutputsy) | __|use Q/2 as feedback. i So FBIN to IN skew! tskewl Note 2, 4. Input rise time -500 250 0) ps Skew between any 2 out- tskew2 Note 2, 4. -250 ' 50 250 ps [puts at same frequency) fn ; De Joo ene Skew between any 1 out- tskew3 | Note 2, 4 -3 +0.1 3 ns putand Q/21 ot - a _ | _ | Notes: 1. Guaranteed by design and characterization. Not subject ot 100% test. 2. All skew specifications are measured with a SOQ transmission line, load terminated with 50Q to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at |.4V on rising edges. Loading must be equal on outputs. D-59ICS9176 Applications FBOUT is normally connected to FBIN to facilitate input to output skew control. However, there is no requirement that the external feedback connection be a direct hardwire from an output pin to the FBIN pin. As long as the signal at FBIN is derived directly from the FBOUT pin and maintains its fre- quency, additional delays can be accommodated. The clock phase of the outputs (rising edge) will be adjusted so that the phase of FBIN and the input clock will be the same. See Figure | for an example. FBIN 66 MHz +2 33 MHz 66 MHz| |CS9176 Figure 1 In Figure |, the propagation delay through the divide-by-2 circuit is eliminated. The internal phase-locked loop will adjust the output clock on the 1CS9176 to ensure zero phase delay between the FBIN and CLK signals, as a result, the rising edge at the output of the divide by two circuit will be aligned with the rising edge of the 66 MHz input clock. This type of configuration can be used to eliminate propagation delay as long as the signal at FBIJN is continuous and is not gated or conditional. Ordering Information 1CS9176Q-01 or ICS9176M-01 Example: ICS XXXX M -PPP ] Q=PLCC; M=SOIC Jo _. Prefix ICS, AV=Standard Device The [CS9176 is also ideal for clocking multi-processor sys- tems. The 10 outputs can be used to synchronize the operation of CPU cache and memory banks operating at different speeds. Figure 2 depicts a 2-CPU system in which processors and associated peripherals are operating at 66 MHz. Each of the nine outputs operating at 66 MHz are fully utilized to drive the appropriate CPU, cache and memory control logic. The 33 MHz output is used to synchronize the operation of the slower memory bank to the restart of the system. FBOUT ai Q2 Q3 Q4 Qs Q6 Q7 Qs ag SYSTEM CLOCK MEMORY CONTROL GND VDO SLOW MEMORY CONTROL LOGIC Figure 2 { | _---- Pattern Number (2 or 3 digit number for parts with ROM code patterns) ~~ Package Type Device Type (consists of 3 or 4 digit numbers) D-60