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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
LMV3xx-N/-Q1 Single, Dual, and Quad General Purpose, Low-Voltage, Rail-to-Rail Output
Operational Amplifiers
1
1 Features
1• (For V+=5VandV−= 0 V, Unless Otherwise
Specified)
• LMV321-N, LMV358-N, and LMV324-N are
available in Automotive AEC-Q100 Grade 1 and 3
versions
• Ensured 2.7-V and 5-V Performance
• No Crossover Distortion
• Industrial Temperature Range −40°C to +125°C
• Gain-Bandwidth Product 1 MHz
• Low Supply Current
• LMV321-N 130 μA
• LMV358-N 210 μA
• LMV324-N 410 μA
• Rail-to-Rail Output Swing At 10 kΩV+−10 mV &
V−+ 65 mV
• VCM Range −0.2 V to V+−0.8 V
2 Applications
• Active Filters
• General Purpose Low Voltage Applications
• General Purpose Portable Devices
3 Description
The LMV358-N and LMV324-N are low-voltage (2.7 V
to 5.5 V) versions of the dual and quad commodity op
amps LM358 and LM324 (5 V to 30 V). The LMV321-
N is the single channel version. The LMV321-N,
LMV358-N, and LMV324-N are the most cost-
effective solutions for applications where low-voltage
operation, space efficiency, and low price are
important. They offer specifications that meet or
exceed the familiar LM358 and LM324. The LMV321-
N, LMV358-N, and LMV324-N have rail-to-rail output
swing capability and the input common-mode voltage
range includes ground. They all exhibit excellent
speed to power ratio, achieving 1 MHz of bandwidth
and 1-V/µs slew rate with low supply current.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMV321-N SOT-23 (5) 2.90 mm x 1.60 mm
SC70 (5) 2.00 mm x 1.25 mm
LMV321-N-Q1 SOT-23 (5) 2.90 mm x 1.60 mm
LMV324-N SOIC (14) 8.65 mm x 3.91 mm
TSSOP (14) 5.00 mm x 4.40 mm
LMV324-N-Q1 SOIC (14) 8.65 mm x 3.91 mm
TSSOP (14) 5.00 mm x 4.40 mm
LMV358-N SOIC (8) 4.90 mm x 3.91 mm
VSSOP (8) 3.00 mm x 3.00 mm
LMV358-N-Q1 SOIC (8) 4.90 mm x 3.91 mm
VSSOP (8) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Gain and Phase vs. Capacitive Load Output Voltage Swing vs. Supply Voltage
2
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description (Continued)........................................ 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings - Commercial....................................... 4
7.3 ESD Ratings - Automotive........................................ 4
7.4 Recommended Operating Conditions....................... 4
7.5 Thermal Information.................................................. 5
7.6 2.7-V DC Electrical Characteristics........................... 5
7.7 2.7-V AC Electrical Characteristics........................... 5
7.8 5-V DC Electrical Characteristics.............................. 6
7.9 5-V AC Electrical Characteristics.............................. 7
7.10 Typical Characteristics............................................ 8
8 Detailed Description............................................ 16
8.1 Overview................................................................. 16
8.2 Functional Block Diagram....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 19
9 Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Applications ................................................ 20
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 Device and Documentation Support................. 34
12.1 Related Links ........................................................ 34
12.2 Trademarks........................................................... 34
12.3 Electrostatic Discharge Caution............................ 34
12.4 Glossary................................................................ 34
13 Mechanical, Packaging, and Orderable
Information........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (February 2013) to Revision J Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision H (February 2013) to Revision I Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 32
3
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
5 Description (Continued)
The LMV321-N is available in the space saving 5-Pin SC70, which is approximately half the size of the 5-Pin
SOT23. The small package saves space on PC boards and enables the design of small portable electronic
devices. It also allows the designer to place the device closer to the signal source to reduce noise pickup and
increase signal integrity.
The chips are built with Texas Instruments's advanced submicron silicon-gate BiCMOS process. The LMV321-
N/LMV358-N/LMV324-N have bipolar input and output stages for improved noise performance and higher output
current drive.
6 Pin Configuration and Functions
DBV and DCK Package
5-Pin SC70, SOT-23
Top View
D and DGK Package
8-Pin SOIC, VSSOP
Top View
D and PW Package
14-Pin SOIC, TSSOP
Top View
Pin Functions
PIN
TYPE DESCRIPTION
NAME
LMV321-N,
LMV321-N-Q1,
LMV321-N-Q3
DVB, DCK
LMV358-N,
LMV358-N-Q1,
LMV358-N-Q3
D, DGK
LMV324-N,
LMV324-N-Q1,
LMV324-N-Q3
D, PW
+IN 1 - - I Noninverting input
IN A+ - 3 3 I Noninverting input, channel A
IN B+ - 5 5 I Noninverting input, channel B
IN C+ - - 10 I Noninverting input, channel C
IN D+ - - 12 I Noninverting input, channel D
-IN 3 - - I Inverting input
IN A- - 2 2 I Inverting input, channel A
IN B- - 6 6 I Inverting input, channel B
IN C- - - 9 I Inverting input, channel C
IN D- - - 13 I Inverting input, channel D
OUTPUT 4 - - O Output
OUT A - 1 1 O Output, channel A
OUT B - 7 7 O Output, channel B
OUT C - - 8 O Output , channel C
OUT D - - 14 O Output, channel D
V+ 5 8 4 P Positive (highest) power supply
V- 2 4 11 P Negative (lowest) power supply
4
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the
test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and
specifications.
(3) Shorting output to V+will adversely affect reliability.
(4) Shorting output to V-will adversely affect reliability.
(5) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PC Board.
7 Specifications
7.1 Absolute Maximum Ratings
See (1)(2).MIN MAX UNIT
Differential Input Voltage ±Supply Voltage V
Input Voltage −0.3 +Supply Voltage V
Supply Voltage (V+–V −) 5.5 V
Output Short Circuit to V + (3)
Output Short Circuit to V −(4)
Soldering Information: Infrared or Convection (30 sec) 260 °C
Junction Temperature(5) 150 °C
Storage temperature Tstg −65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings - Commercial VALUE UNIT
LMV358-N, and LMV324-N in all packages
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Machine model ±100
LMV321-N in all packages
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±900 V
Machine model ±100
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings - Automotive VALUE UNIT
LMV358-N-Q1, LMV324-N-Q1, LMV358-N-Q3 and LMV324-N-Q3 in all packages
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Machine model ±100
LM321-N-Q1 and LM321-N-Q3 in all packages
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±900 V
Machine model ±100
(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PC Board.
7.4 Recommended Operating Conditions MIN MAX UNIT
Supply Voltage 2.7 5.5 V
Temperature Range (1): LMV321-N, LMV358-N, LMV324-N –40 125 °C
Temperature Range (1): LMV321-N-Q1, LMV358-N-Q1, LMV324-N-Q1 –40 125 °C
Temperature Range (1): LMV321-N-Q3, LMV358-N-Q3, LMV324-N-Q3 –40 85 °C
5
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Thermal Information
THERMAL METRIC(1)
LMV321-N,
LMV321-N-Q1,
LMV321-N-Q3
LMV321-N LMV324-N,
LMV324-N-Q1,
LMV324-N-Q3
LMV358-N,
LMV358-N-Q1,
LMV358-N-Q3 UNIT
DBV DCK D PW D DGK
5 PINS 14 PINS 8 PINS
RθJA Junction-to-ambient thermal
resistance 265 478 145 155 190 235 °C/W
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
7.6 2.7-V DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ= 25°C, V+= 2.7 V, V−= 0 V, VCM = 1.0 V, VO= V+/2 and RL> 1 MΩ.
TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage 1.7 7 mV
TCVOS Input Offset Voltage Average Drift 5 µV/°C
IBInput Bias Current 11 250 nA
IOS Input Offset Current 5 50 nA
CMRR Common Mode Rejection Ratio 0 V ≤VCM ≤1.7 V 50 63 dB
PSRR Power Supply Rejection Ratio 2.7 V ≤V+≤5 V
VO= 1V 50 60 dB
VCM Input Common-Mode Voltage
Range For CMRR ≥50 dB 0 −0.2 V
1.9 1.7 V
VOOutput Swing RL= 10 kΩto 1.35 V V+−100 V+−10 mV
60 180 mV
ISSupply Current Single 80 170 µA
Dual
Both amplifiers 140 340 µA
Quad
All four amplifiers 260 680 µA
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
7.7 2.7-V AC Electrical Characteristics
Unless otherwise specified, all limits specified for T J= 25°C, V+= 2.7 V, V−= 0 V, VCM = 1.0 V, VO= V+/2 and RL> 1 MΩ.
TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
GBWP Gain-Bandwidth Product CL= 200 pF 1 MHz
ΦmPhase Margin 60 Deg
GmGain Margin 10 dB
enInput-Referred Voltage Noise f = 1 kHz 46
inInput-Referred Current Noise f = 1 kHz 0.17
6
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) RLis connected to V-. The output voltage is 0.5 V ≤VO≤4.5 V.
7.8 5-V DC Electrical Characteristics
Unless otherwise specified, all limits specified for T J= 25°C, V+= 5 V, V−= 0 V, VCM = 2.0 V, VO= V+/2 and R L> 1 MΩ.
TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage 1.7 7 mV
Over Temperature 9
TCVOS Input Offset Voltage Average Drift 5 µV/°C
IBInput Bias Current 15 250 nA
Over Temperature 500
IOS Input Offset Current 5 50 nA
Over Temperature 150
CMRR Common Mode Rejection Ratio 0 V ≤VCM ≤4 V 50 65 dB
PSRR Power Supply Rejection Ratio 2.7 V ≤V+≤5 V
VO= 1V, VCM = 1 V 50 60 dB
VCM Input Common-Mode Voltage
Range For CMRR ≥50 dB 0 −0.2 V
4.2 4 V
AVLarge Signal Voltage Gain (3) RL= 2 kΩ15 100 V/mV
RL= 2 kΩ, Over Temperature 10
VOOutput Swing RL= 2 kΩto 2.5 V V+−300 V+−40
mV
RL= 2 kΩto 2.5 V, Over Temperature V+−400
RL= 2 kΩto 2.5 V 120 300
RL= 2 kΩto 2.5 V, Over Temperature 400
RL= 10 kΩto 2.5 V V+−100 V+−10
RL= 10 kΩto 2.5 V, Over Temperature V+−200
RL= 2 kΩto 2.5 V 65 180
RL= 2 kΩto 2.5 V, 125°C 280
IOOutput Short Circuit Current Sourcing, VO= 0 V 5 60 mA
Sinking, VO= 5 V 10 160
ISSupply Current Single 130 250
µA
Single, Over Temperature 350
Dual (both amps) 210 440
Dual (both amps), Over Temperature 615
Quad (all four amps) 410 830
Quad (all four amps), Over
Temperature 1160
7
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Connected as voltage follower with 3-V step input. Number specified is the slower of the positive and negative slew rates.
7.9 5-V AC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5 V, V−= 0 V, VCM = 2.0 V, VO= V+/2 and R L> 1 MΩ.
TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SR Slew Rate (3) 1 V/µs
GBWP Gain-Bandwidth Product CL= 200 pF 1 MHz
ΦmPhase Margin 60 Deg
GmGain Margin 10 dB
enInput-Referred Voltage Noise f = 1 kHz 39
inInput-Referred Current Noise f = 1 kHz 0.21
8
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
7.10 Typical Characteristics
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 1. Supply Current vs. Supply Voltage (LMV321-N) Figure 2. Input Current vs. Temperature
Figure 3. Sourcing Current vs. Output Voltage Figure 4. Sourcing Current vs. Output Voltage
Figure 5. Sinking Current vs. Output Voltage Figure 6. Sinking Current vs. Output Voltage
9
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 7. Output Voltage Swing vs. Supply Voltage Figure 8. Input Voltage Noise vs. Frequency
Figure 9. Input Current Noise vs. Frequency Figure 10. Input Current Noise vs. Frequency
Figure 11. Crosstalk Rejection vs. Frequency Figure 12. PSRR vs. Frequency
10
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 13. CMRR vs. Frequency Figure 14. CMRR vs. Input Common Mode Voltage
Figure 15. CMRR vs. Input Common Mode Voltage Figure 16. ΔVOS vs. CMR
Figure 17. ΔVOS vs. CMR Figure 18. Input Voltage vs. Output Voltage
11
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 19. Input Voltage vs. Output Voltage Figure 20. Open Loop Frequency Response
Figure 21. Open Loop Frequency Response Figure 22. Open Loop Frequency Response vs. Temperature
Figure 23. Gain and Phase vs. Capacitive Load Figure 24. Gain and Phase vs. Capacitive Load
12
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 25. Slew Rate vs. Supply Voltage Figure 26. Non-Inverting Large Signal Pulse Response
Figure 27. Non-Inverting Large Signal Pulse Response Figure 28. Non-Inverting Large Signal Pulse Response
Figure 29. Non-Inverting Small Signal Pulse Response Figure 30. Non-Inverting Small Signal Pulse Response
13
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 31. Non-Inverting Small Signal Pulse Response Figure 32. Inverting Large Signal Pulse Response
Figure 33. Inverting Large Signal Pulse Response Figure 34. Inverting Large Signal Pulse Response
Figure 35. Inverting Small Signal Pulse Response Figure 36. Inverting Small Signal Pulse Response
14
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 37. Inverting Small Signal Pulse Response Figure 38. Stability vs. Capacitive Load
Figure 39. Stability vs. Capacitive Load Figure 40. Stability vs. Capacitive Load
Figure 41. Stability vs. Capacitive Load Figure 42. THD vs. Frequency
15
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
www.ti.com
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation FeedbackCopyright © 2000–2014, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, VS= 5 V, single supply, TA= 25°C.
Figure 43. Open Loop Output Impedance vs. Frequency Figure 44. Short Circuit Current vs. Temperature (Sinking)
Figure 45. Short Circuit Current vs. Temperature (Sourcing)
16
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The LMV358-N/LMV324-N are low voltage (2.7 V to 5.5 V) versions of the dual and quad commodity op amps
LM358/LM324 (5 V to 30 V). The LMV321-N is the single channel version. The LMV321-N/LMV358-N/LMV324-N
are the most cost effective solutions for applications where low voltage operation, space efficiency, and low price
are important. They offer specifications that meet or exceed the familiar LM358/LM324. The LMV321-N/LMV358-
N/LMV324-N have rail-to-rail output swing capability and the input common-mode voltage range includes ground.
They all exhibit excellent speed to power ratio, achieving 1 MHz of bandwidth and 1-V/µs slew rate with low
supply current.
8.1.1 Benefits of the LMV321-N/LMV358-N/LMV324-N
8.1.1.1 Size
The small footprints of the LMV321-N/LMV358-N/LMV324-N packages save space on printed circuit boards, and
enable the design of smaller electronic products, such as cellular phones, pagers, or other portable systems. The
low profile of the LMV321-N/LMV358-N/LMV324-N make them possible to use in PCMCIA type III cards.
8.1.1.2 Signal Integrity
Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier
package, the LMV321-N/LMV358-N/LMV324-N can be placed closer to the signal source, reducing noise pickup
and increasing signal integrity.
8.1.1.3 Simplified Board Layout
These products help you to avoid using long PC traces in your PC board layout. This means that no additional
components, such as capacitors and resistors, are needed to filter out the unwanted signals due to the
interference between the long PC traces.
8.1.1.4 Low Supply Current
These devices will help you to maximize battery life. They are ideal for battery powered systems.
8.1.1.5 Low Supply Voltage
Texas Instruments provides ensured performance at 2.7 V and 5 V. These specifications ensure operation
throughout the battery lifetime.
8.1.1.6 Rail-to-Rail Output
Rail-to-rail output swing provides maximum possible dynamic range at the output. This is particularly important
when operating on low supply voltages.
8.1.1.7 Input Includes Ground
Allows direct sensing near GND in single supply operation.
Protection should be provided to prevent the input voltages from going negative more than −0.3V (at 25°C). An
input clamp diode with a resistor to the IC input terminal can be used.
8.1.1.8 Ease of Use and Crossover Distortion
The LMV321-N/LMV358-N/LMV324-N offer specifications similar to the familiar LM324-N. In addition, the new
LMV321-N/LMV358-N/LMV324-N effectively eliminate the output crossover distortion. The scope photos in
Figure 46 and Figure 47 compare the output swing of the LMV324-N and the LM324-N in a voltage follower
configuration, with VS= ± 2.5V and RL(= 2 kΩ) connected to GND. It is apparent that the crossover distortion
has been eliminated in the new LMV324-N.
_
+
OUT
V+
V–
IN –
IN +
Copyright © 2016,
Texas Instruments Incorporated
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,
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,
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,
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,
LMV324-N-Q1
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Overview (continued)
Figure 46. Output Swing of LMV324 Figure 47. Output Swing of LM324
8.2 Functional Block Diagram
Figure 48. Each Amplifier
8.3 Feature Description
8.3.1 Capacitive Load Tolerance
The LMV321-N/LMV358-N/LMV324-N can directly drive 200 pF in unity-gain without oscillation. The unity-gain
follower is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase
margin of amplifiers. The combination of the amplifier's output impedance and the capacitive load induces phase
lag. This results in either an underdamped pulse response or oscillation. To drive a heavier capacitive load, the
circuit in Figure 49 can be used.
Figure 49. Indirectly Driving a Capacitive Load Using Resistive Isolation
In Figure 49 , the isolation resistor RISO and the load capacitor CLform a pole to increase stability by adding more
phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO
resistor value, the more stable VOUT will be. Figure 50 is an output waveform of Figure 49 using 620Ωfor RISO
and 510 pF for CL..
18
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Feature Description (continued)
Figure 50. Pulse Response of the LMV324 Circuit in Figure 49
The circuit in Figure 51 is an improvement to the one in Figure 49 because it provides DC accuracy as well as
AC stability. If there were a load resistor in Figure 49, the output would be voltage divided by RISO and the load
resistor. Instead, in Figure 51, RFprovides the DC accuracy by using feed-forward techniques to connect VIN to
RL. Caution is needed in choosing the value of RFdue to the input bias current of theLMV321-N/LMV358-
N/LMV324-N. CFand RISO serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop. Increased capacitive drive is possible by increasing the value of CF. This in turn will slow
down the pulse response.
Figure 51. Indirectly Driving A Capacitive Load with DC Accuracy
8.3.2 Input Bias Current Cancellation
The LMV321-N/LMV358-N/LMV324-N family has a bipolar input stage. The typical input bias current of LMV321-
N/LMV358-N/LMV324-N is 15 nA with 5V supply. Thus a 100 kΩinput resistor will cause 1.5 mV of error voltage.
By balancing the resistor values at both inverting and non-inverting inputs, the error caused by the amplifier's
input bias current will be reduced. The circuit in Figure 52 shows how to cancel the error caused by input bias
current.
19
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,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Feature Description (continued)
Figure 52. Cancelling the Error Caused by Input Bias Current
8.4 Device Functional Modes
The LMV321-N/LMV321-N-Q1/LMV358-N/LMV358-N-Q1/LMV324-N/LMV324-N-Q1 are powered on when the
supply is connected. They can be operated as a single supply or a dual supply operational amplifier depending
on the application.
20
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMV32x-N family of amplifiers is specified for operation from 2.7 V to 5 V (±1.35 V to ±2.5 V). Many of the
specifications apply from –40°C to 125°C. They provide ground-sensing inputs as well as rail-to-rail output swing.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
the Typical Characteristics.
9.2 Typical Applications
9.2.1 Simple Low-Pass Active Filter
A simple active low-pass filter is shown in Figure 53.
Figure 53. Simple Low-Pass Active Filter
9.2.1.1 Design Requirements
The simple single pole active lowpass filter shown in Figure 53 will pass low frequencies and attenuate
frequencies above corner frequency (fc) at a roll-off rate of 20dB/Decade.
9.2.1.2 Detailed Design Procedure
The values of R1, R2, R3 and C1 are selected using the formulas in Figure 54. The low-frequency gain (ω→0)
is defined by −R3/R1. This allows low-frequency gains other than unity to be obtained. The filter has a −20
dB/decade roll-off after its corner frequency fc. R2should be chosen equal to the parallel combination of R1and
R3to minimize errors due to bias current. The frequency response of the filter is shown in Figure 55.
Figure 54. Simple Low-Pass Active Filter Equations
21
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,
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Typical Applications (continued)
9.2.1.3 Application Curves
Figure 55. Frequency Response of Simple Low-Pass Active Filter
Note that the single-op-amp active filters are used in the applications that require low quality factor, Q( ≤10), low
frequency (≤5 kHz), and low gain (≤10), or a small value for the product of gain times Q (≤100). The op amp
should have an open loop voltage gain at the highest frequency of interest at least 50 times larger than the gain
of the filter at this frequency. In addition, the selected op amp should have a slew rate that meets the following
requirement:
Slew Rate ≥0.5 × (ωHVOPP) × 10−6V/µsec (1)
where ωHis the highest frequency of interest, and VOPP is the output peak-to-peak voltage.
9.2.2 Difference Amplifier
The difference amplifier allows the subtraction of two voltages or, as a special case, the cancellation of a signal
common to two inputs. It is useful as a computational amplifier, in making a differential to single-ended
conversion or in rejecting a common mode signal.
Figure 56. Difference Amplifier
9.2.3 Instrumentation Circuits
The input impedance of the previous difference amplifier is set by the resistors R1, R2, R3, and R4. To eliminate
the problems of low input impedance, one way is to use a voltage follower ahead of each input as shown in the
following two instrumentation amplifiers.
22
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
9.2.3.1 Three-Op-Amp Instrumentation Amplifier
The quad LMV324 can be used to build a three-op-amp instrumentation amplifier as shown in Figure 57.
Figure 57. Three-Op-Amp Instrumentation Amplifier
The first stage of this instrumentation amplifier is a differential-input, differential-output amplifier, with two voltage
followers. These two voltage followers assure that the input impedance is over 100 MΩ. The gain of this
instrumentation amplifier is set by the ratio of R2/R1. R3should equal R1, and R4equal R2. Matching of R3to R1
and R4to R2affects the CMRR. For good CMRR over temperature, low drift resistors should be used. Making R4
slightly smaller than R2and adding a trim pot equal to twice the difference between R2and R4will allow the
CMRR to be adjusted for optimum performance.
9.2.3.2 Two-Op-Amp Instrumentation Amplifier
A two-op-amp instrumentation amplifier can also be used to make a high-input-impedance DC differential
amplifier (Figure 58). As in the three-op-amp circuit, this instrumentation amplifier requires precise resistor
matching for good CMRR. R4should equal R1and, R3should equal R2.
Figure 58. Two-Op-Amp Instrumentation Amplifier
23
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,
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,
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LMV358-N-Q1
,
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,
LMV324-N-Q1
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Typical Applications (continued)
9.2.3.3 Single-Supply Inverting Amplifier
There may be cases where the input signal going into the amplifier is negative. Because the amplifier is
operating in single supply voltage, a voltage divider using R3and R4is implemented to bias the amplifier so the
input signal is within the input common-mode voltage range of the amplifier. The capacitor C1is placed between
the inverting input and resistor R1to block the DC signal going into the AC signal source, VIN. The values of R1
and C1affect the cutoff frequency, fc = 1/2πR1C1.
As a result, the output signal is centered around mid-supply (if the voltage divider provides V+/2 at the non-
inverting input). The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system.
Figure 59. Single-Supply Inverting Amplifier
9.2.4 Sallen-Key 2nd-Order Active Low-Pass Filter
The Sallen-Key 2nd-order active low-pass filter is illustrated in Figure 60. The DC gain of the filter is expressed
as
(2)
Its transfer function is
(3)
Figure 60. Sallen-Key 2nd-Order Active Low-Pass Filter
24
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
9.2.4.1 Detailed Design Procedure
The following paragraphs explain how to select values for R1, R2, R3, R4, C1, and C 2for given filter requirements,
such as ALP, Q, and fc.
The standard form for a 2nd-order low pass filter is
(4)
where
Q: Pole Quality Factor
ωC: Corner Frequency
A comparison between Equation 3 and Equation 4 yields
(5)
(6)
To reduce the required calculations in filter design, it is convenient to introduce normalization into the
components and design parameters. To normalize, let ωC=ωn= 1 rad/s, and C1= C2= Cn= 1F, and substitute
these values into Equation 5 and Equation 6. From Equation 5, we obtain
(7)
From Equation 6, we obtain
(8)
For minimum DC offset, V+= V−, the resistor values at both inverting and non-inverting inputs should be equal,
which means
(9)
From Equation 2 and Equation 9, we obtain
(10)
(11)
The values of C1and C2are normally close to or equal to
(12)
As a design example:
Require: ALP =2,Q=1,fc=1kHz
Start by selecting C1and C2. Choose a standard value that is close to
(13)
(14)
25
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
From Equation 7,Equation 8,Equation 10, and Equation 11,
R1= 1Ω(15)
R2= 1Ω(16)
R3= 4Ω(17)
R4= 4Ω(18)
The above resistor values are normalized values with ωn= 1 rad/s and C1= C2= Cn= 1F. To scale the
normalized cutoff frequency and resistances to the real values, two scaling factors are introduced, frequency
scaling factor (kf) and impedance scaling factor (km).
(19)
Scaled values:
R2= R1= 15.9 kΩ(20)
R3= R4= 63.6 kΩ(21)
C1= C2= 0.01 µF (22)
An adjustment to the scaling may be made in order to have realistic values for resistors and capacitors. The
actual value used for each component is shown in the circuit.
9.2.5 2nd-Order High Pass Filter
A 2nd-order high pass filter can be built by simply interchanging those frequency selective components (R1, R2,
C1, C2) in the Sallen-Key 2nd-order active low pass filter. As shown in Figure 61, resistors become capacitors,
and capacitors become resistors. The resulted high pass filter has the same corner frequency and the same
maximum gain as the previous 2nd-order low pass filter if the same components are chosen.
Figure 61. Sallen-Key 2nd-Order Active High-Pass Filter
9.2.6 State Variable Filter
A state variable filter requires three op amps. One convenient way to build state variable filters is with a quad op
amp, such as the LMV324 (Figure 62).
26
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
This circuit can simultaneously represent a low-pass filter, high-pass filter, and bandpass filter at three different
outputs. The equations for these functions are listed below. It is also called "Bi-Quad" active filter as it can
produce a transfer function which is quadratic in both numerator and denominator.
Figure 62. State Variable Active Filter
(23)
where for all three filters,
(24)
(25)
9.2.6.1 Detailed Design Procedure
Assume the system design requires a bandpass filter with f O= 1 kHz and Q = 50. What needs to be calculated
are capacitor and resistor values.
First choose convenient values for C1, R1and R2:
C1= 1200 pF (26)
27
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,
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,
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LMV358-N-Q1
,
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,
LMV324-N-Q1
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Typical Applications (continued)
2R2= R1= 30 kΩ(27)
Then from Equation 24,
(28)
From Equation 25,
(29)
From the above calculated values, the midband gain is H0= R3/R2= 100 (40 dB). The nearest 5% standard
values have been added to Figure 62.
9.2.7 Pulse Generators and Oscillators
A pulse generator is shown in Figure 63. Two diodes have been used to separate the charge and discharge
paths to capacitor C.
Figure 63. Pulse Generator
When the output voltage VOis first at its high, VOH, the capacitor C is charged toward VOH through R2. The
voltage across C rises exponentially with a time constant τ= R2C, and this voltage is applied to the inverting
input of the op amp. Meanwhile, the voltage at the non-inverting input is set at the positive threshold voltage
(VTH+) of the generator. The capacitor voltage continually increases until it reaches VTH+, at which point the
output of the generator will switch to its low, VOL which 0V is in this case. The voltage at the non-inverting input is
switched to the negative threshold voltage (VTH−) of the generator. The capacitor then starts to discharge toward
VOL exponentially through R1, with a time constant τ= R1C. When the capacitor voltage reaches VTH−, the output
of the pulse generator switches to VOH. The capacitor starts to charge, and the cycle repeats itself.
28
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
Figure 64. Waveforms of the Circuit in Figure 16
As shown in the waveforms in Figure 64, the pulse width (T1) is set by R2, C and VOH, and the time between
pulses (T2) is set by R1, C and VOL. This pulse generator can be made to have different frequencies and pulse
width by selecting different capacitor value and resistor values.
Figure 65 shows another pulse generator, with separate charge and discharge paths. The capacitor is charged
through R1and is discharged through R2.
29
LMV321-N
,
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,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
Figure 65. Pulse Generator
Figure 66 is a squarewave generator with the same path for charging and discharging the capacitor.
Figure 66. Squarewave Generator
9.2.8 Current Source and Sink
The LMV321-N/LMV358-N/LMV324-N can be used in feedback loops which regulate the current in external PNP
transistors to provide current sources or in external NPN transistors to provide current sinks.
9.2.8.1 Fixed Current Source
A multiple fixed current source is shown in Figure 67. A voltage (VREF = 2V) is established across resistor R3by
the voltage divider (R3and R4). Negative feedback is used to cause the voltage drop across R1to be equal to
VREF. This controls the emitter current of transistor Q1and if we neglect the base current of Q1and Q2,
essentially this same current is available out of the collector of Q1.
Large input resistors can be used to reduce current loss and a Darlington connection can be used to reduce
errors due to the βof Q1.
The resistor, R2, can be used to scale the collector current of Q2either above or below the 1 mA reference value.
30
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
Figure 67. Fixed Current Source
9.2.8.2 High Compliance Current Sink
A current sink circuit is shown in Figure 68. The circuit requires only one resistor (RE) and supplies an output
current which is directly proportional to this resistor value.
Figure 68. High Compliance Current Sink
31
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,
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,
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Typical Applications (continued)
9.2.9 Power Amplifier
A power amplifier is illustrated in Figure 69. This circuit can provide a higher output current because a transistor
follower is added to the output of the op amp.
Figure 69. Power Amplifier
9.2.10 LED Driver
The LMV321-N/LMV358-N/LMV324-N can be used to drive an LED as shown in Figure 70.
Figure 70. LED Driver
9.2.11 Comparator With Hysteresis
The LMV321-N/LMV358-N/LMV324-N can be used as a low power comparator. Figure 71 shows a comparator
with hysteresis. The hysteresis is determined by the ratio of the two resistors.
VTH+ = VREF/(1+R 1/R2)+VOH/(1+R2/R1) (30)
VTH−= VREF/(1+R 1/R2)+VOL/(1+R2/R1) (31)
VH= (VOH−VOL)/(1+R 2/R1) (32)
where
VTH+: Positive Threshold Voltage
VTH−: Negative Threshold Voltage
VOH: Output Voltage at High
VOL: Output Voltage at Low
VH: Hysteresis Voltage
Since LMV321-N/LMV358-N/LMV324-N have rail-to-rail output, the (VOH−VOL) is equal to VS, which is the supply
voltage.
VH= VS/(1+R2/R1) (33)
32
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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Typical Applications (continued)
The differential voltage at the input of the op amp should not exceed the specified absolute maximum ratings.
For real comparators that are much faster, we recommend you use Texas Instruments's
LMV331/LMV93/LMV339, which are single, dual and quad general purpose comparators for low voltage
operation.
Figure 71. Comparator with Hysteresis
10 Power Supply Recommendations
The LMV3xx-N is specified for operation from 2.7 V to 5.5 V; many specifications apply from –40°C to 125°C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
the Typical Characteristics.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques,SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
33
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,
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,
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LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
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11.2 Layout Example
Figure 72. Operational Amplifier Board Layout for Noninverting Configuration
34
LMV321-N
,
LMV321-N-Q1
,
LMV358-N
LMV358-N-Q1
,
LMV324-N
,
LMV324-N-Q1
SNOS012J –AUGUST 2000–REVISED DECEMBER 2014
www.ti.com
Product Folder Links: LMV321-N LMV321-N-Q1 LMV358-N LMV358-N-Q1 LMV324-N LMV324-N-Q1
Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
LMV321-N Click here Click here Click here Click here Click here
LMV321-N-Q1 Click here Click here Click here Click here Click here
LMV358-N Click here Click here Click here Click here Click here
LMV358-N-Q1 Click here Click here Click here Click here Click here
LMV324-N Click here Click here Click here Click here Click here
LMV324-N-Q1 Click here Click here Click here Click here Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Dec-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV321M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 A13
LMV321M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A13
LMV321M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A13
LMV321M7 NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 125 A12
LMV321M7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A12
LMV321M7X NRND SC70 DCK 5 3000 TBD Call TI Call TI -40 to 125 A12
LMV321M7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A12
LMV321Q1M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AYA
LMV321Q1M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AYA
LMV321Q3M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AZA
LMV321Q3M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AZA
LMV324M NRND SOIC D 14 55 TBD Call TI Call TI -40 to 125 LMV324M
LMV324M/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV324M
LMV324MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LMV324
MT
LMV324MTX NRND TSSOP PW 14 2500 TBD Call TI Call TI -40 to 125 LMV324
MT
LMV324MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LMV324
MT
LMV324MX NRND SOIC D 14 2500 TBD Call TI Call TI -40 to 125 LMV324M
LMV324MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV324M
LMV324Q1MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV324Q1
MA
PACKAGE OPTION ADDENDUM
www.ti.com 19-Dec-2017
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV324Q1MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV324Q1
MA
LMV324Q1MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV324
Q1MT
LMV324Q1MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV324
Q1MT
LMV324Q3MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMV324Q3
MA
LMV324Q3MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMV324Q3
MA
LMV324Q3MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMV324
Q3MT
LMV324Q3MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMV324
Q3MT
LMV358M NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LMV
358M
LMV358M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV
358M
LMV358MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 V358
LMV358MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 V358
LMV358MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 V358
LMV358MX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 LMV
358M
LMV358MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV
358M
LMV358Q1MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV35
8Q1MA
LMV358Q1MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV35
8Q1MA
LMV358Q1MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AFAA
LMV358Q1MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AFAA
PACKAGE OPTION ADDENDUM
www.ti.com 19-Dec-2017
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV358Q3MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMV35
8Q3MA
LMV358Q3MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMV35
8Q3MA
LMV358Q3MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AHAA
LMV358Q3MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AHAA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Dec-2017
Addendum-Page 4
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV321-N, LMV321-N-Q1, LMV324-N, LMV324-N-Q1, LMV358-N, LMV358-N-Q1 :
•Catalog: LMV321-N, LMV324-N, LMV358-N
•Automotive: LMV321-N-Q1, LMV324-N-Q1, LMV358-N-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV321M5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321M7 SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV321M7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV321M7X SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV321M7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV321Q1M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321Q1M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321Q3M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321Q3M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV324MTX TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LMV324MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LMV324MX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMV324MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMV324Q1MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMV324Q1MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LMV324Q3MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jun-2018
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV324Q3MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LMV358MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMV358MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMV358Q1MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMV358Q1MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358Q1MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358Q3MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMV358Q3MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358Q3MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV321M5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV321M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV321M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV321M7 SC70 DCK 5 1000 210.0 185.0 35.0
LMV321M7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jun-2018
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV321M7X SC70 DCK 5 3000 210.0 185.0 35.0
LMV321M7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV321Q1M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV321Q1M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV321Q3M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV321Q3M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV324MTX TSSOP PW 14 2500 367.0 367.0 35.0
LMV324MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LMV324MX SOIC D 14 2500 367.0 367.0 35.0
LMV324MX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMV324Q1MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMV324Q1MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LMV324Q3MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMV324Q3MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LMV358MM VSSOP DGK 8 1000 210.0 185.0 35.0
LMV358MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV358MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMV358MX SOIC D 8 2500 367.0 367.0 35.0
LMV358MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMV358Q1MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMV358Q1MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV358Q1MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMV358Q3MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMV358Q3MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV358Q3MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jun-2018
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
IMPORTANT NOTICE
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TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
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other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
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INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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