DS92LV010A
Bus LVDS 3.3/5.0V Single Transceiver
General Description
The DS92LV010Ais one in a series of transceivers designed
specifically for the high speed, low power proprietary bus
backplane interfaces. The device operates from a single
3.3V or 5.0V power supply and includes one differential line
driver and one receiver. To minimize bus loading the driver
outputs and receiver inputs are internally connected. The
logic interface provides maximum flexibility as 4 separate
lines are provided (DIN, DE, RE, and ROUT). The device
also features flow through which allows easy PCB routing for
short stubs between the bus pins and the connector. The
driver has 10 mA drive capability, allowing it to drive heavily
loaded backplanes, with impedance as low as 27 Ohms.
The driver translates between TTL levels (single-ended) to
Low Voltage Differential Signaling levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is ±100mV over a ±1V common
mode range and translates the low voltage differential levels
to standard (CMOS/TTL) levels.
Features
nBus LVDS Signaling (BLVDS)
nDesigned for Double Termination Applications
nBalanced Output Impedance
nLite Bus Loading 5pF typical
nGlitch free power up/down (Driver disabled)
n3.3V or 5.0V Operation
n±1V Common Mode Range
n±100mV Receiver Sensitivity
nHigh Signaling Rate Capability (above 100 Mbps)
nLow Power CMOS design
nProduct offered in 8 lead SOIC package
nIndustrial Temperature Range Operation
Connection Diagram
Block Diagram
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS100052-1
Order Number DS92LV010ATM
See NS Package Number M08A
DS100052-2
May 1998
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
© 1998 National Semiconductor Corporation DS100052 www.national.com
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) 6.0V
Enable Input Voltage (DE,
RE) −0.3V to (V
CC
+
0.3V)
Driver Input Voltage (DIN) −0.3V to (V
CC
+
0.3V)
Receiver Output Voltage
(R
OUT
)−0.3V to (V
CC
+
0.3V)
Bus Pin Voltage (DO/RI±) −0.3V to + 3.9V
Driver Short Circuit
Current Continuous
ESD (HBM 1.5 kΩ, 100
pF) >2.0 kV
Maximum Package Power Dissipation at 25˚C
SOIC 1025 mW
Derate SOIC Package 8.2 mW/˚C
Storage Temperature
Range −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) 260˚C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (V
CC
), or 3.0 3.6 V
Supply Voltage (V
CC
) 4.5 5.5 V
Receiver Input Voltage 0.0 2.9 V
Operating Free Air
Temperature −40 +85 ˚C
DC Electrical Characteristics (Notes 2, 3)
T
A
= −40˚C to +85˚C unless otherwise noted, V
CC
= 3.3V ±0.3V
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD
Output Differential
Voltage R
L
=27Ω,
Figure 1
DO+/RI+,
DO−/RI− 140 250 360 mV
∆V
OD
V
OD
Magnitude Change 330mV
V
OS
Offset Voltage 1 1.25 1.65 V
∆V
OS
Offset Magnitude
Change 550mV
I
OSD
Output Short Circuit
Current V
O
= 0V, DE = V
CC
−12 −20 mA
V
OH
Voltage Output High V
ID
= +100 mV I
OH
= −400 µA R
OUT
2.8 3 V
Inputs Open 2.8 3 V
Inputs Shorted 2.8 3 V
Inputs Terminated,
R
L
=27Ω2.8 3 V
V
OL
Voltage Output Low I
OL
= 2.0 mA, V
ID
= −100 mV 0.1 0.4 V
I
OS
Output Short Circuit
Current V
OUT
= 0V, V
ID
= +100 mV −5 −35 −85 mA
V
TH
Input Threshold High DE = 0V DO+/RI+,
DO−/RI− +100 mV
V
TL
Input Threshold Low −100 mV
I
IN
Input Current DE = 0V, V
IN
= +2.4V, or 0V −20 ±1 +20 µA
V
CC
= 0V, V
IN
= +2.4V, or 0V −20 ±1 +20 µA
V
IH
Minimum Input High
Voltage DIN, DE,
RE 2.0 V
CC
V
V
IL
Maximum Input Low
Voltage GND 0.8 V
I
IH
Input High Current V
IN
=V
CC
or 2.4V ±1±10 µA
I
IL
Input Low Current V
IN
= GND or 0.4V ±1±10 µA
V
CL
Input Diode Clamp
Voltage I
CLAMP
= −18 mA −1.5 −0.8 V
I
CCD
Power Supply Current DE = RE = V
CC
,R
L
=27ΩV
CC
13 20 mA
I
CCR
DE=RE=0V 58mA
I
CCZ
DE = 0V, RE = V
CC
3 7.5 mA
I
CC
DE=V
CC
,RE=0V,R
L
=27Ω16 22 mA
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DC Electrical Characteristics (Notes 2, 3) (Continued)
T
A
= −40˚C to +85˚C unless otherwise noted, V
CC
= 3.3V ±0.3V
Symbol Parameter Conditions Pin Min Typ Max Units
C
output
Capacitance @BUS
Pins DO+/RI+,
DO−/RI− 5pF
DC Electrical Characteristics (Notes 2, 3)
T
A
= −40˚C to +85˚C unless otherwise noted, V
CC
= 5.0V ±0.5V
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD
Output Differential
Voltage R
L
=27Ω,
Figure 1
DO+/RI+,
DO−/RI− 145 270 390 mV
∆V
OD
V
OD
Magnitude Change 330mV
V
OS
Offset Voltage 1 1.35 1.65 V
∆V
OS
Offset Magnitude
Change 550mV
I
OSD
Output Short Circuit
Current V
O
= 0V, DE = V
CC
−12 −20 mA
V
OH
Voltage Output High V
ID
= +100 mV I
OH
= −400 µA R
OUT
4.3 5.0 V
Inputs Open 4.3 5.0 V
Inputs Shorted 4.3 5.0 V
Inputs
Terminated, R
L
=27Ω4.3 5.0 V
V
OL
Voltage Output Low I
OL
= 2.0 mA, V
ID
= −100 mV 0.1 0.4 V
I
OS
Output Short Circuit
Current V
OUT
= 0V, V
ID
= +100 mV −35 −90 −130 mA
V
TH
Input Threshold High DE = 0V DO+/RI+,
DO−/RI− +100 mV
V
TL
Input Threshold Low −100 mV
I
IN
Input Current DE = 0V, V
IN
= +2.4V, or 0V −20 ±1 +20 µA
V
CC
= 0V, V
IN
= +2.4V, or 0V −20 ±1 +20 µA
V
IH
Minimum Input High
Voltage DIN,
DE,
RE
2.0 V
CC
V
V
IL
Maximum Input Low
Voltage GND 0.8 V
I
IH
Input High Current V
IN
=V
CC
or 2.4V ±1±10 µA
I
IL
Input Low Current V
IN
= GND or 0.4V ±1±10 µA
V
CL
Input Diode Clamp
Voltage I
CLAMP
= −18 mA −1.5 −0.8 V
I
CCD
Power Supply Current DE = RE = V
CC
,R
L
=27ΩV
CC
17 25 mA
I
CCR
DE=RE=0V 610mA
I
CCZ
DE = 0V, RE = V
CC
38mA
I
CC
DE=V
CC
,RE=0V,R
L
=27Ω20 25 mA
C
output
Capacitance @BUS
Pins DO+/RI+,
DO−/RI− 5pF
Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except VOD,V
ID,V
TH and
VTL unless otherwise specified.
Note 3: All typicals are given for VCC = +3.3V or 5.0 V and TA= +25˚C, unless otherwise stated.
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) >2.0 kV EAT (0Ω, 200 pF) >300V.
Note 5: CLincludes probe and fixture capacitance.
Note 6: Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω,tr,tf≤6.0ns (0%–100%) on control pins and ≤1.0ns for RI inputs.
Note 7: The DS92LV010A is a current mode device and only function with datasheet specification when a resistive load is applied between the driver outputs.
Note 8: For receiver TRI-STATE®delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ.
www.national.com3
AC Electrical Characteristics (Note 6)
T
A
= −40˚C to +85˚C, V
CC
= 3.3V ±0.3V
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to
Low R
L
=27Ω,
Figures 2, 3
C
L
=10pF 1.0 3.0 5.0 ns
t
PLHD
Differential Prop. Delay Low to
High 1.0 2.8 5.0 ns
t
SKD
Differential SKEW |t
PHLD
-t
PLHD
| 0.2 1.0 ns
t
TLH
Transition Time Low to High 0.3 2.0 ns
t
THL
Transition Time High to Low 0.3 2.0 ns
t
PHZ
Disable Time High to Z R
L
=27Ω,
Figures 4, 5
C
L
=10pF 0.5 4.5 9.0 ns
t
PLZ
Disable Time Low to Z 0.5 5.0 10.0 ns
t
PZH
Enable Time Z to High 2.0 5.0 7.0 ns
t
PZL
Enable Time Z to Low 1.0 4.5 9.0 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to
Low
Figures 6, 7
C
L
=10pF 2.5 5.0 12.0 ns
t
PLHD
Differential Prop. Delay Low to
High 2.5 5.5 10.0 ns
t
SKD
Differential SKEW |t
PHLD
-t
PLHD
| 0.5 2.0 ns
t
r
Rise Time 1.5 4.0 ns
t
f
Fall Time 1.5 4.0 ns
t
PHZ
Disable Time High to Z R
L
= 500Ω,
Figures 8, 9
C
L
= 10 pF (Note 8) 2.0 4.0 6.0 ns
t
PLZ
Disable Time Low to Z 2.0 5.0 7.0 ns
t
PZH
Enable Time Z to High 2.0 7.0 13.0 ns
t
PZL
Enable Time Z to Low 2.0 6.0 10.0 ns
AC Electrical Characteristics (Note 6)
T
A
= −40˚C to +85˚C, V
CC
= 5.0V ±0.5V
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to
Low R
L
=27Ω,
Figures 2, 3
C
L
=10pF 0.5 2.7 4.5 ns
t
PLHD
Differential Prop. Delay Low to
High 0.5 2.5 4.5 ns
t
SKD
Differential SKEW |t
PHLD
-t
PLHD
| 0.2 1.0 ns
t
TLH
Transition Time Low to High 0.3 2.0 ns
t
THL
Transition Time High to Low 0.3 2.0 ns
t
PHZ
Disable Time High to Z R
L
=27Ω,
Figures 4, 5
C
L
=10pF 0.5 3.0 7.0 ns
t
PLZ
Disable Time Low to Z 0.5 5.0 10.0 ns
t
PZH
Enable Time Z to High 2.0 4.0 7.0 ns
t
PZL
Enable Time Z to Low 1.0 4.0 9.0 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to
Low
Figures 6, 7
C
L
=10pF 2.5 5.0 12.0 ns
t
PLHD
Differential Prop. Delay Low to
High 2.5 4.6 10.0 ns
t
SKD
Differential SKEW |t
PHLD
-t
PLHD
| 0.4 2.0 ns
t
r
Rise Time 1.2 2.5 ns
t
f
Fall Time 1.2 2.5 ns
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AC Electrical Characteristics (Note 6) (Continued)
T
A
= −40˚C to +85˚C, V
CC
= 5.0V ±0.5V
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHZ
Disable Time High to Z R
L
= 500Ω,
Figures 8, 9
C
L
= 10 pF (Note 8) 2.0 4.0 6.0 ns
t
PLZ
Disable Time Low to Z 2.0 4.0 6.0 ns
t
PZH
Enable Time Z to High 2.0 5.0 9.0 ns
t
PZL
Enable Time Z to Low 2.0 5.0 7.0 ns
Test Circuits and Timing Waveforms
DS100052-3
FIGURE 1. Differential Driver DC Test Circuit
DS100052-4
FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit
DS100052-5
FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms
www.national.com5
Test Circuits and Timing Waveforms (Continued)
DS100052-6
FIGURE 4. Driver TRI-STATE Delay Test Circuit
DS100052-7
FIGURE 5. Driver TRI-STATE Delay Waveforms
DS100052-8
FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit
DS100052-9
FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms
www.national.com 6
Test Circuits and Timing Waveforms (Continued)
Typical Bus Application Configurations
Application Information
There are a few common practices which should be implied
when designing PCB for BLVDS signaling. Recommended
practices are:
•Use at least 4 layer PCB board (BLVDS signals, ground,
power and TTL signals).
•Keep drivers and receivers as close to the (BLVDS port
side) connector as possible.
DS100052-10
FIGURE 8. Receiver TRI-STATE Delay Test Circuit
DS100052-11
FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
DS100052-12
Bi-Directional Half-Duplex Point-to-Point Applications
DS100052-13
Multi-Point Bus Applications
www.national.com7
Application Information (Continued)
•Bypass each BLVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-
layer ceramic (MLC) surface mount capacitors (0.1 µF,
and 0.01 µF in parallel should be used between each V
CC
and ground. The capacitors should be as close as pos-
sible to the V
CC
pin.
•Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
•Leave unused LVDS receiver inputs open (floating)
TABLE 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
TRI-STATE MODE L H
LOOP BACK MODE H L
TABLE 2. Transmitter Mode
INPUTS OUTPUTS
DE DI DO+ DO−
HL LH
HH H L
H2
>
&
>
0.8 X X
LX ZZ
L = Low state
H = High state
TABLE 3. Receiver Mode
INPUTS OUTPUT
RE (RI+)-(RI−)
LL(
<
−100 mV) L
LH(
>
+100 mV) H
L 100 mV >&>−100 mV X
HXZ
X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
TABLE 4. Device Pin Description
Pin Name Pin # Input/Output Description
DIN 2 I TTL Driver Input
DO±/RI±6, 7 I/O LVDS Driver Outputs/LVDS Receiver Inputs
R
OUT
3 O TTL Receiver Output
RE 5 I Receiver Enable TTL Input (Active Low)
DE 1 I Driver Enable TTL Input (Active High)
GND 4 NA Ground
V
CC
8 NA Power Supply
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9
Physical Dimensions inches (millimeters) unless otherwise noted
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tems which, (a) are intended for surgical implant into
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Order Number DS92LV010ATM
See NS Package Number M08A
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
