1
LTC1864L/LTC1865L
sn18645L 18645Lfs
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
µPower, 3V, 16-Bit, 150ksps
1- and 2-Channel ADCs in MSOP
Single 3V Supply, 150ksps, 16-Bit Sampling ADC
Supply Current vs Sampling Frequency
The LTC
®
1864L/LTC1865L are 16-bit A/D converters that
are offered in MSOP and SO-8 packages and operate on a
single 3V supply. At 150ksps, the supply current is only
450µA. The supply current drops at lower speeds because
the LTC1864L/LTC1865L automatically power down
between conversions. These 16-bit switched capacitor
successive approximation ADCs include sample-and-holds.
The LTC1864L has a differential analog input with an
external reference pin. The LTC1865L offers a software-
selectable 2-channel MUX and an external reference pin on
the MSOP version.
The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
These ADCs can be used in ratiometric applications or
with external references. The high impedance analog
inputs and the ability to operate with reduced spans down
to 1V full scale allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
■
16-Bit 150ksps ADCs in MSOP Package
■
Single 3V Supply
■
Low Supply Current: 450µA (Typ)
■
Auto Shutdown Reduces Supply Current
to 10µA at 1ksps
■
True Differential Inputs
■
1-Channel (LTC1864L) or 2-Channel (LTC1865L)
Versions
■
SPI/MICROWIRE
TM
Compatible Serial I/O
■
16-Bit Upgrade to 12-Bit LTC1285/LTC1288
■
Pin Compatible with 12-Bit LTC1860L/LTC1861L
■
No Minimum Data Transfer Rate
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
High Speed Data Acquisition
■
Portable or Compact Instrumentation
■
Low Power Battery-Operated Instrumentation
■
Isolated and/or Remote Data Acquisition
1
2
3
4
8
7
6
5
V
REF
IN
+
IN
–
GND
V
CC
SCK
SDO
CONV
LTC1864L
1864 TA01
ANALOG INPUT
0V TO 3V
3V
1µF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
MICROWIRE is a trademark of National Semiconductor Corporation.
SAMPLING FREQUENCY (kHz)
0.1
SUPPLY CURRENT (µA)
1
10
100
1000
0.01 1 10 1000
1864L/65L TA02
0.1 100
CONV LOW = 2µs
TA = 25°C
VCC = 2.7V
2
LTC1864L/LTC1865L
sn18645L 18645Lfs
Operating Temperature Range
LTC1864LC/LTC1865LC/
LTC1864LAC/LTC1865LAC .................... 0°C to 70°C
LTC1864LI/LTC1865LI/
LTC1864LAI/LTC1865LAI ................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Supply Voltage (V
CC
) ................................................. 7V
Ground Voltage Difference
AGND, DGND LTC1865L MSOP Package ......... ±0.3V
Analog Input ............... (GND – 0.3V) to (V
CC
+ 0.3V)
Digital Input ................................ (GND – 0.3V) to 7V
Digital Output .............. (GND – 0.3V) to (V
CC
+ 0.3V)
Power Dissipation.............................................. 400mW
(Notes 1, 2)
ORDER PART
NUMBER
MS8 PART MARKING MS PART MARKING
LTJ4
LTC1865LCMS
LTC1865LIMS
LTC1865LACMS
LTC1865LAIMS
ORDER PART
NUMBER
LTC1864LCMS8
LTC1864LIMS8
LTC1864LACMS8
LTC1864LAIMS8
LTC7
T
JMAX
= 150°C, θ
JA
= 210°C/W
T
JMAX
= 150°C, θ
JA
= 210°C/W
1
2
3
4
V
REF
IN
+
IN¯
GND
8
7
6
5
V
CC
SCK
SDO
CONV
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ORDER PART
NUMBER
S8 PART MARKING
S8 PART MARKING
1864L
1864LI
LTC1864LCS8
LTC1864LIS8
LTC1864LACS8
LTC1864LAIS8
ORDER PART
NUMBER
T
JMAX
= 150°C, θ
JA
= 175°C/W
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
V
REF
IN
+
IN
–
GND
V
CC
SCK
SDO
CONV
1864LA
864LAI
1865L
1865LI
LTC1865LCS8
LTC1865LIS8
LTC1865LACS8
LTC1865LAIS8
1865LA
865LAI
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
CONV
CH0
CH1
GND
V
CC
SCK
SDO
SDI
T
JMAX
= 150°C, θ
JA
= 175°C/W
1
2
3
4
5
CONV
CH0
CH1
AGND
DGND
10
9
8
7
6
V
REF
V
CC
SCK
SDO
SDI
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
● LTC1864L/LTC1865L LTC1864LA/LTC1865LA
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution ●16 16 Bits
No Missing Codes Resolution ●14 15 Bits
INL (Note 3) ●±8±6 LSB
Transition Noise 2 2 LSB
RMS
Gain Error ●±20 ±20 mV
CO VERTER A D ULTIPLEXER CHARACTERISTICS
U
WU
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
3
LTC1864L/LTC1865L
sn18645L 18645Lfs
LTC1864L/LTC1865L
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 82 dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio 1kHz Input Signal 82 dB
THD Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal 92 dB
Full Power Bandwidth 10 MHz
Full Linear Bandwidth S/(N + D) ≥ 75dB 20 kHz
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Offset Error ●±2±5±2±5mV
Input Differential Voltage V
IN
= IN
+
– IN
–
●0V
REF
0V
REF
V
Range
Absolute Input Range IN
+
Input – 0.05 V
CC
+ 0.05 – 0.05 V
CC
+ 0.05 V
IN
–
Input – 0.05 V
CC
/2 – 0.05 V
CC
/2 V
V
REF
Input Range LTC1864L SO-8 and MSOP, LTC1865L MSOP 1 V
CC
1V
CC
V
Analog Input Leakage Current (Note 4) ●±1±1µA
C
IN
Input Capacitance In Sample Mode 12 12 pF
During Conversion 5 5 pF
DY A IC ACCURACY
U
W
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
U
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
CO VERTER A D ULTIPLEXER CHARACTERISTICS
U
WU
TA = 25°C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise noted.
LTC1864L/LTC1865L
SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
CC
= 3.3V ●1.9 V
V
IL
Low Level Input Voltage V
CC
= 2.7V ●0.45 V
I
IH
High Level Input Current V
IN
= V
CC
●2.5 µA
I
IL
Low Level Input Current V
IN
= 0V ●–2.5 µA
V
OH
High Level Output Voltage V
CC
= 2.7V, I
O
= 10µA●2.3 2.6 V
V
CC
= 2.7V, I
O
= 360µA●2.1 2.45 V
V
OL
Low Level Output Voltage V
CC
= 2.7V, I
O
= 400µA●0.3 V
I
OZ
Hi-Z Output Leakage CONV = V
CC
●±3µA
I
SOURCE
Output Source Current V
OUT
= 0V –6.5 mA
I
SINK
Output Sink Current V
OUT
= V
CC
6.5 mA
I
REF
Reference Current (LTC1864L SO-8 and CONV = V
CC
●0.001 3 µA
MSOP, LTC1865L MSOP) f
SMPL
= f
SMPL(MAX)
●0.01 0.1 mA
I
CC
Supply Current CONV = V
CC
After Conversion ●0.5 10 µA
f
SMPL
= f
SMPL(MAX)
●0.45 1.0 mA
P
D
Power Dissipation f
SMPL
= f
SMPL(MAX)
1.22 mW
LTC1864L/LTC1865L LTC1864LA/LTC1865LA
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
4
LTC1864L/LTC1865L
sn18645L 18645Lfs
LTC1864L/LTC1865L
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage 2.7 3.6 V
f
SCK
Clock Frequency ●DC 8 MHz
t
CYC
Total Cycle Time 16 • SCK + t
CONV
µs
t
SMPL
Analog Input Sampling Time (Note 5) LTC1864L 16 SCK
LTC1865L 14 SCK
t
suCONV
Setup Time CONV↓ Before First SCK↑60 ns
(See Figure 1)
t
hDI
Hold Time SDI After SCK↑LTC1865L 30 ns
t
suDI
Setup Time SDI Stable Before SCK↑LTC1865L 30 ns
t
WHCLK
SCK High Time f
SCK
= f
SCK(MAX)
45% 1/f
SCK
t
WLCLK
SCK Low Time f
SCK
= f
SCK(MAX)
45% 1/f
SCK
t
WHCONV
CONV High Time Between Data t
CONV
µs
Transfer Cycles
t
WLCONV
CONV Low Time During Data Transfer 16 SCK
t
hCONV
Hold Time CONV Low After Last SCK↑26 ns
LTC1864L/LTC1865L
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
CONV
Conversion Time (See Figure 1) ●3.7 4.66 µs
f
SMPL(MAX)
Maximum Sampling Frequency ●150 kHz
t
dDO
Delay Time, SCK↓ to SDO Data Valid C
LOAD
= 20pF 45 55 ns
●60 ns
t
dis
Delay Time, CONV↑ to SDO Hi-Z ●55 120 ns
t
en
Delay Time, CONV↓ to SDO Enabled C
LOAD
= 20pF ●35 120 ns
t
hDO
Time Output Data Remains C
LOAD
= 20pF ●515 ns
Valid After SCK↓
t
r
SDO Rise Time C
LOAD
= 20pF 25 ns
t
f
SDO Fall Time C
LOAD
= 20pF 12 ns
RECO E DED OPERATI G CO DITIO S
UUUUWW
TI I G CHARACTERISTICS
UW
The ● denotes specifications which apply over the
full operating temperature range, otherwise specifications are TA = 25°C.
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating
Conditions, unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Assumes f
SCK
= f
SCK(MAX)
In the case of the LTC1864L SCK does
not have to be clocked during this time if the SDO data word is not
desired. In the case of the LTC1865L a minimum of 2 clocks are required
on the SCK input after CONV falls to configure the MUX during this time.
5
LTC1864L/LTC1865L
sn18645L 18645Lfs
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Supply Current vs Sampling
Frequency Supply Current vs Temperature Sleep Current vs Temperature
Reference Current vs
Sampling Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
Typical INL Curve Typical DNL Curve
Analog Input Leakage Current vs
Temperature
SAMPLING FREQUENCY (kHz)
0.1
SUPPLY CURRENT (µA)
1
10
100
1000
0.01 1 10 1000
1864L/65L G01 1864L/65L G02 1864L/65L G03
0.1 100
CONV LOW = 2µs
TA = 25°C
VCC = 2.7V
TEMPERATURE (°C)
–50
SUPPLY CURRENT (µA)
600
500
400
300
200
100
0
25 75
–25 0 50 100 125
fS = 150kHz
VCC = 2.7V
VREF = 2.5V
TEMPERATURE (°C)
–50
SHUTDOWN CURRENT (µA)
20
15
10
5
0
25 75
–25 0 50 100 125
fS = 150kHz
VCC = 2.7V
VREF = 2.5V
SAMPLING FREQUENCY (kHz)
0
REFERENCE CURRENT (µA)
25 50 75 100
1864L/65L G04
125
10
9
8
7
6
5
4
3
2
1
0
150
CONV LOW = 2µs
TA = 25°C
VCC = 2.7V
VREF = 2.5V
TEMPERATURE (°C)
–50
REFERENCE CURRENT (µA)
25
20
15
10
5
0
25 75
1864L/65L G05
–25 0 50 100 125
fS = 150kHz
VCC = 2.7V
VREF = 2.5V
REFERENCE VOLTAGE (V)
0
REFERENCE CURRENT (µA)
0.5 1.0 2.01.5 3.02.5
1864L/65L G06
3.5
25
20
15
10
5
0
4.0
fS = 150kHz
TA = 25°C
VCC = 3.6V
TEMPERATURE (°C)
–50
ANALOG INPUT LEAKAGE (nA)
100
75
50
25
0
25 75
1864L/65L G09
–25 0 50 100 125
CONV = 0V
VCC = 2.7V
VREF = 2.5V
CODE
0
INL ERROR (LSBs)
0
2
65536
1865 G02
–2
–4 16384 32768 49152
4VCC = 2.7V
VREF = 2.5V
fS = 150kHz
CODE
0
DNL ERROR (LSBs)
0
1
65536
1865 G03
–1
–2 16384 32768 49152
2VCC = 2.7V
VREF = 2.5V
fS = 150kHz
6
LTC1864L/LTC1865L
sn18645L 18645Lfs
REFERENCE VOLTAGE (V)
0
CHANGE IN OFFSET (LSB)
4
1864L/65L G10
123
20
15
10
5
0
–5
–10
–15
–20
f
S
= 150kHz
T
A
= 25°C
V
CC
= 3.6V
REFERENCE VOLTAGE (V)
0
GHANGE IN GAIN ERROR (LSB)
4
1864L/65L G12
123
f
S
= 150kHz
T
A
= 25°C
V
CC
= 3.6V
TEMPERATURE (°C)
–50 25 75
1864L/65L G11
–25 0 50 100 125
CHANGE IN OFFSET (LSB)
5
4
3
2
1
0
–1
–2
–3
–4
–5
5
4
3
2
1
0
–1
–2
–3
–4
–5
V
CC
= 2.7V
V
REF
= 2.5V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
TEMPERATURE (°C)
–50 25 75
1864L/65L G13 1864L/65L G14
–25 0 50 100 125
CHANGE IN GAIN ERROR (LSB)
5
4
3
2
1
0
–1
–2
–3
–4
–5
THD (dB)
1864L/65L G15
INPUT FREQUENCY (kHz)
1
SINAD (dB)
100
90
80
70
60
50
40
30
20
10
010 100
1864L/65L G16
INPUT FREQUENCY (kHz)
1 10 100
1864L/65L G17
SFDR (dB)
100
90
80
70
60
50
40
30
20
10
0
INPUT FREQUENCY (kHz)
110100
1864L/65L G18
30 31 33 35 37 39 41 4332 34 36 38 40 42 44
FREQUENCY
1200
1000
800
600
400
200
0
CODE
V
CC
= 2.7V
V
REF
= 2.5V
f
S
= 125kHz
T
A
= 25°C
V
CC
= 3V
V
IN
= 0dB
V
REF
= 3V
f
S
= 125kHz
T
A
= 25°C
V
CC
= 3V
V
IN
= 0dB
V
REF
= 3V
f
S
= 125kHz
T
A
= 25°C
V
CC
= 3V
V
IN
= 0dB
V
REF
= 3V
SNR
SINAD
0752 45 20 00
169
407
1040
648
152
291
576
689
INPUT FREQUENCY (kHz)
0
AMPLITUDE (dB)
60
5101520253540505565
30 45
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
f
S
= 125kHz
T
A
= 25°C
V
CC
= 3V
V
IN
= 0.946045kHz
V
REF
= 3V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SINAD vs Input Frequency THD vs Input Frequency SFDR vs Input Frequency
Change in Offset vs
Reference Voltage Change in Offset vs Temperature
Change in Gain Error vs
Reference Voltage
Change in Gain Error vs
Temperature
Histogram of 4096 Conversions
of a DC Input Voltage 4096 Point FFT Nonaveraged
7
LTC1864L/LTC1865L
sn18645L 18645Lfs
V
REF
(Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN
+
, IN
–
(Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK (Pin 7): Shift Clock Input. This clock synchronizes the
serial data transfer.
V
CC
(Pin 8):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
UU
U
PI FU CTIO S
LTC1865L (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D configuration
word is shifted into this input.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
LTC1865L (SO-8 Package)
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes the
serial data transfer.
V
CC
(Pin 9):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
V
REF
(Pin 10): Reference Input. The reference input de-
fines the span of the A/D converter and must be kept free
of noise with respect to AGND.
SDI (Pin 5):
Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes the
serial data transfer.
V
CC
(Pin 8):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. V
REF
is tied internally to this pin.
LTC1864L
8
LTC1864L/LTC1865L
sn18645L 18645Lfs
Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
Voltage Waveforms for SDO Delay Times, tdDO and thDO
Voltage Waveforms for ten
SDO
3k
20pF
TEST POINT
V
CC
t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
1864 TC01
SCK
SDO
VIL
tdDO
thDO
VOH
VOL
1864 TC02
1864 TC03
CONV
SDO
ten
SDO
t
r
t
f
1864 TC04
V
OH
V
OL
TEST CIRCUITS
Voltage Waveforms for tdis
SDO
WAVEFORM 1
(SEE NOTE 1)
VIH
tdis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1864 TC05
FUNCTIONAL BLOCK DIAGRA
UU
W
1864/65 BD
16-BIT
SAMPLING
ADC
BIAS AND
SHUTDOWN
CONVERT
CLK
SERIAL
PORT
16 BITS
IN
+
(CH0)
IN
–
(CH1)
VCC
VREF
SDO
GND
CONV (SDI) SCK
PIN NAMES IN
PARENTHESES
REFER TO LTC1865L
DATA OUT
DATA IN
+
–
9
LTC1864L/LTC1865L
sn18645L 18645Lfs
LTC1864L OPERATION
Operating Sequence
The LTC1864L conversion cycle begins with the rising
edge of CONV. After a period equal to t
CONV
, the conver-
sion is finished. If CONV is left high after this time, the
LTC1864L goes into sleep mode drawing only leakage
current. On the falling edge of CONV, the LTC1864L goes
into sample mode and SDO is enabled. SCK synchronizes
the data transfer with each bit being transmitted from SDO
on the falling SCK edge. The receiving system should
capture the data from SDO on the rising edge of SCK. After
completing the data transfer, if further SCK clocks are
applied with CONV low, SDO will output zeros indefinitely.
See Figure 1.
Analog Inputs
The LTC1864L has a unipolar differential analog input. The
converter will measure the voltage between the “IN
+
” and
“IN
–
” inputs. A zero code will occur when IN
+
minus IN
–
equals zero. Full scale occurs when IN
+
minus IN
–
equals
V
REF
minus 1LSB. See Figure 2. Both the “IN
+
” and
“IN
–
” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN
–
”
is grounded and V
REF
is tied to V
CC
, a rail-to-rail input span
will result on “IN
+
” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864L
defines the full-scale range of the A/D converter. The
LTC1864L can operate with reference voltages from V
CC
to
1V.
CONV
tCONV
SCK
SDO
16151413121110987654321
B15 B14 B12 B10 B8 B6 B4 B2 B0* Hi-Z
1854 F01
Hi-Z
B13 B11 B9 B7 B5 B3 B1
SLEEP MODE
tSMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
DON'T CARE
1
2
3
4
8
7
6
5
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
LTC1864L
1864 F03
VIN = 0V TO VCC
VCC
1µF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
Figure 1. LTC1864L Operating Sequence
Figure 3. LTC1864L with Rail-to-Rail Input SpanFigure 2. LTC1864L Transfer Curve
0V
1LSB
V
REF
– 2LSB
V
REF
– 1LSB
V
REF
V
IN
*
*V
IN
= IN
+
– IN
–
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1864 F02
APPLICATIO S I FOR ATIO
WUUU
10
LTC1864L/LTC1865L
sn18645L 18645Lfs
LTC1865L OPERATION
Operating Sequence
The LTC1865L conversion cycle begins with the rising
edge of CONV. After a period equal to t
CONV
, the conver-
sion is finished. If CONV is left high after this time, the
LTC1865L goes into sleep mode drawing only leakage
current. The LTC1865L’s 2-bit data word is clocked into
the SDI input on the rising edge of SCK after CONV goes
low. Additional inputs on the SDI pin are then ignored until
the next CONV cycle. The shift clock (SCK) synchronizes
the data transfer with each bit being transmitted on the
falling SCK edge and captured on the rising SCK edge in
both transmitting and receiving systems. The data is
transmitted and received simultaneously (full duplex).
After completing the data transfer, if further SCK clocks
are applied with CONV low, SDO will output zeros indefi-
nitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the
“+” and “–” signs in the selected row of Table 1. In
CONV
SDI
SCK
16151413121110987654321
SDO B15 B14 B12 B10 B8 B6 B4 B2 B0* Hi-Z
B13 B11 B9 B7 B5 B3 B1
S/D O/S DON’T CAREDON’T CARE
t
CONV
1864 F04
SLEEP MODE
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Hi-Z
t
SMPL
DON'T CARE
Figure 4. LTC1865L Operating Sequence
APPLICATIO S I FOR ATIO
WUUU
MUX ADDRESS
Table 1. Multiplexer Channel Selection
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
1864 TBL1
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
single-ended mode, all input channels are measured with
respect to GND. A zero code will occur when the “+” input
minus the “–” input equals zero. Full scale occurs when
the “+” input minus the “–” input equals VREF minus
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1865L SO-8 package is
internally tied to V
CC
. The span of the A/D converter is
therefore equal to V
CC
. The voltage on the reference input
of the LTC1865L MSOP package defines the span of the
A/D converter. The LTC1865L MSOP package can operate
with reference voltages from 1V to V
CC
.
11
LTC1864L/LTC1865L
sn18645L 18645Lfs
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864L/LTC1865L should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluate the device. To achieve the optimum performance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1865L MSOP package and GND for the
LTC1864L and LTC1865L SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Bypassing
For good performance, the V
CC
and V
REF
pins must be free
of noise and ripple. Any changes in the V
CC
/V
REF
voltage
with respect to ground during the conversion cycle can
induce errors or noise in the output code. Bypass the V
CC
and V
REF
pins directly to the analog ground plane with a
minimum of 1µF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864L/
LTC1865L have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200Ω or high
speed op amps are used (e.g., the LT
®
1211, LT1469,
LT1807, LT1810, LT1630, LT1226 or LT1215). But if large
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conver-
sion begins.
APPLICATIO S I FOR ATIO
WUUU
0V
1LSB
V
CC
– 2LSB
V
CC
– 1LSB
V
CC
V
IN
*
*V
IN
= (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1864 F05
Figure 5. LTC1865L Transfer Curve
12
LTC1864L/LTC1865L
sn18645L 18645Lfs
APPLICATIO S I FOR ATIO
WUUU
LTC1864L Evaluation Circuit Schematic
U12B
74AC109
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
JP8
246
135
JP9
246
135
2
3
4
1
5
6
7
8
10
9
8
3.3V
DIG
3.3V
DIG
3.3V
DIG
3.3V
DIG
3.3V
DIG
15V
–15V
3.3V
DIG
3.3V
DIG
3.3V
AN
3.3V
DIG
3.3V
DIG
3.3V
DIG
C16
0.1µF
C23
0.1µF
C5
0.1µF
C6
0.1µF
C24
0.1µF
C18
0.1µF
C17
0.1µF
3.3V
DIG
3.3V
DIG
3.3V
DIG
C13
0.1µF
C12
10µF
6.3V
1206
C14
0.1µF
U12A
74AC109
U10
LTC1799
RESET
CLK
P0
P1
P2
P3
ENP
GND
V
CC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U6
74HC163AD
J
K
CLK
CLR
PRE
Q
Q
GND
V
CC
1
2
3
5
4
V
+
GND
SET DIV
14
13
12
15
11
J
K
CLK
CLR
PRE
Q
Q
GND
V
CC
16 16
U9B
74AC00
U9A
74AC00
U13B
74AC32
RESET
CLK
P0
P1
P2
P3
ENP
GND
V
CC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U7
74HC163AD
R10
10k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
J4
3201S40G1
QB
QC
QD
QE
QF
QG
QH
GND
V
CC
QA
A
OENB
LCLK
SCLK
RESET
SQH
RN1
330
QB
QC
QD
QE
QF
QG
QH
GND
V
CC
QA
A
OENB
LCLK
SCLK
RESET
SQH
R9
51Ω
C8
470pF
1205
C9
100pF
1206
C7
100pF
1206
C20
0.1µF
C1
0.1µF
C4
0.1µF
C21
47pF
C22
47pF
C10
0.1µF
3.3V
DIG
C15
0.1µF
3.3V
DIG
C19
0.1µF
C2
1µF
10V
0805
C3
10µF
6.3V
1206
–IN
JP3
BUF
JP2
JP1
+IN
R1
100Ω
1206
R3
2Ω
R2
100Ω
V
IN
V
OUT
GND
U1
LT1460DCS8-2.5
V
IN
V
OUT
GND
R4
2Ω
15V
15V
IN
+
IN
+
AGND
IN
–
IN
–
V
REF
+IN
–IN
GND
V
CC
SCLK
D
OUT
CONV
U8A
74AC14
U8B
74AC14
U8E
74AC14
U8D
74AC14 U8F
74AC14
OUT
15V 3.3V
AN
U4
74HC595ADT
U5
74HC595ADT
U9C
74AC00
U9D
74AC00
U13A
74AC32
U13D
74AC32
U13C
74AC32
ANALOG GROUND PLANE
CLK
JP6
CLK JP7
EXTCK
JP4
CONV
J1
J2
E1
E8
E9
U2
OPT
U3
LTC1864LAIMS8
1
2
3
4
8
7
6
5
R6
402Ω
1%
R5
402Ω
1%
1
2
3
4
8
7
6
5
2
3
3
3
3
1
2
2
1
6
7
21
2
3
3
3
2
1
2
1
4
4
61
2
3
CONV
DGND
DGND
DOUT
CLKOUT
CLKIN
ENABLE
DATA
U8C
74AC14
E2
E3
E7
E6
E4
E5
J3
NOTES: UNLESS OTHERWISE SPECIFIED
INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2;
ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
1864/65 AI1
R7
20k
LT1121-3.3
CKIN
CKIN
EXT
INT
EXT
INT
R8
1M
P0
P0
P1
P1
P2
P2
P3
P3
1
IN
+
IN
–
BUF
ON OFF
GND
EN
JP5
3
2
1
GND EXT
5632
5632
5632
13
LTC1864L/LTC1865L
sn18645L 18645Lfs
APPLICATIO S I FOR ATIO
WUUU
Component Side Silk Screen for LTC1864L Evaluation Circuit
Component Side Showing Traces
(Note Wider Traces on Analog Side)
Bottom Side Showing Traces
(Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds Supply Layer with 5V Digital Supply and Analog Ground Repeated
14
LTC1864L/LTC1865L
sn18645L 18645Lfs
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
MSOP (MS8) 0802
0.53 ± 0.015
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.077)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.13 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.15
(1.93 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
0.52
(.206)
REF
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
U
PACKAGE DESCRIPTIO
15
LTC1864L/LTC1865L
sn18645L 18645Lfs
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
MSOP (MS) 0802
0.53 ± 0.01
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.13 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.15
(1.93 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
16
LTC1864L/LTC1865L
sn18645L 18645Lfs
LT/TP 0403 2K • PRINTED IN USA
RELATED PARTS
© LINEAR TECHNOLOGY CORPORATION 2001
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
U
TYPICAL APPLICATIO
Tiny 2-Chip Data Acquisition System
–
+
LTC6910-1
0.1µF
1µF
1µF
3V 3V
AGND
3
8
41
2765
VIN
GAIN
CONTROL
ADC
CONTROL
499Ω
270pF
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
LTC1864L
LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN
RANGE TO THE LTC1864L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY
1864L/65L TA03
PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION
12-Bit Serial I/O ADCs
LTC1860L/LTC1861L 150ksps 1.22mW Pin Compatible with LTC1864L/LTC1865L
LTC1860/LTC1861 250ksps 4.25mW Pin Compatible with LTC1864/LTC1865
14-Bit Serial I/O ADCs
LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V
LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V or ±5V
16-Bit Serial I/O ADCs
LTC1609 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V
LTC1864/LTC1865 250ksps 4.25mW MSOP, SO-8, 1- and 2-Channel, 5V Supply
References
LT1460 Micropower Precision Series Reference Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23
LT1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT-23
Op Amps
LT1468/LT1469 Single/Dual 90MHz, 16-Bit Accurate Op Amps 22V/µs Slew Rate, 75µV/125µV Offset
LT1806/LT1807 Single/Dual 325MHz Low Noise Op Amps 140V/µs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
LT1809/LT1810 Single/Dual 180MHz Low Distortion Op Amps 350V/µs Slew Rate, – 90dBc Distortion at 5MHz
