AK8136A Low Power Multiclock Generator with VCXO AK8136A Features Description The AK8136A is a member of AKM's low power multi clock generator family designed for a feature rich DTV or STB, requiring a range of system clocks with high performance. The AK8136A generates different frequency clocks from a 27MHz crystal oscillator and provides them to up to four outputs configured by register-setting. The on-chip VCXO accepts a voltage control input to allow the output clocks to vary by 150 ppm for synchronizing to the external clock system. Both circuitries of VCXO and PLL in AK8136A are derived from AKM's long-term-experienced clock device technology, and enable clock output to perform low jitter and to operate with very low current consumption. The AK8136A is available in a 20-pin SSOP package. 27MHz Crystal Input One 27MHz-Reference Output 2 wire serial register interface Selectable Clock out Frequencies: - 148.352, 148.5MHz - 100.71, 108MHz - 22.5792, 24.576, 33.8688, 36.864MHz - 27.0MHz Built-in VCXO - Pull Range: 150ppm (typ.) Low Jitter Performance - Period Jitter: 150 psec (Typ.) at CLK2,CLK3,CLK4 - TIE HDMI 1.3a compliant 100 psec (Max) at CLK1p,CLK1n - Long term jitter 160 psec (Typ.) at REFOUT Low Current Consumption: 32 mA (Typ.) at 3.3V Supply Voltage: 3.0 - 3.6V Operating Temperature Range: -20 to +85 Package: 20-pin SSOP (Lead free, Halogen free) Applications * Set-Top-Boxes VDD XI XO Voltage Controlled Crystal Oscillator PLL1 CLK1p CLK1n PLL2 VIN CLK2 CLK3 PLL3 Full PD CLK4 REFOUT SDA SCL Control Register VREF GND AK8136A Multi Clock Generator MS1108-E-03 February-10 -1- AK8136A Pin Descriptions Package: 20-Pin SSOP(Top View) XI 1 20 GND3 2 19 VDD3 VIN 3 18 REFOUT GND4 4 17 VDDI CLK2 5 16 SCL VDD2 6 15 SDA GND2 7 14 CLK1n CLK3 8 13 CLK1p CLK4 9 12 VDD1 VREF 10 11 GND1 Pin No. Pin Name XO Pin Type Description 1 XI AIN Crystal connection, Connect to 27.000MHz crystal 2 GND3 PWR 3 VIN AIN 4 GND4 PWR 5 CLK2 DO 6 VDD2 PWR Power Supply 2 7 GND2 PWR Ground 2 8 CLK3 DO 9 CLK4 DO 10 VREF AO 11 GND1 PWR Ground 1 12 VDD1 PWR Power Supply 1 13 CLK1p DO Clock output 1, these are differential pair. See register description 14 CLK1n DO In full power down or disable, these pins are "L". 15 SDA DI/DO 16 SCL DI 17 VDDI PWR 18 REFOUT DO 19 VDD3 PWR 20 XO AO Ground 3 VCXO Control Voltage Input Ground 4 Clock output 2, See register description. In full power down or disable, this pin is "L". Clock output 3, See register description In full power down or disable, this pin is "L". Clock output 4, Copy of CLK3 See register description In full power down or disable, this pin is "L". VREF Pin Connect 1uF capacitor. Hi-Z in full power down state. Serial data input and output pin. Open drain. Serial interface clock input. Power supply for serial interface. 1.8V or 3.3V can be used. Reference Clock Output of VCXO based on 27.000MHz Crystal In full power down or disable, this pin is "L". Power Supply 3 Crystal connection, Connect to 27.000MHz crystal Ordering Information Part Number Marking Shipping Packaging Package Temperature Range AK8136A 8136A Tape and Reel 20-pin SSOP -20 to 85 February-10 MS1108-E-03 -2- AK8136A Absolute Maximum Rating Over operating free-air temperature range unless otherwise noted Items (1) Symbol Supply voltage Ratings Unit V VDD/VDDI -0.3 to 4.6 Input voltage Vin VSS-0.3 to VDD+0.3 V Input current (any pins except supplies) IIN 10 mA Tstg -55 to 130 C Storage temperature Note (1) Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. ESD Sensitive Device This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. Recommended Operation Conditions Parameter Symbol Conditions Min Typ Max Unit -20 85 C (1) VDDI Pin: VDDI 1.7 3.6 V (2) Supply voltage 2 VDD Pin: VDD1,VDD2,VDD3 3.0 3.6 V Output Load Condition CL1 Operating temperature Supply voltage 1 Output Load Capacitance Ta 3.3 Pin: CLK1p,CLK1n See Figure 1 Cp1 Pin: CLK2,CLK3,CLK4 15 pF Cp2 Pin: REFOUT 25 pF Note: (1) A decoupling capacitor for power supply line should be installed close to VDDI pin. (2)Power to VDD1, VDD2, VDD3 requires to be supplied from a single source. supply line should be installed close to each VDD pin. MS1108-E-03 A decoupling capacitor for power February-10 -3- AK8136A DC Characteristics VDD: over 3.0 to 3.6V,VDDI:over 1.7 to 3.6V, Ta: -20 to +85, 27MHz Crystal, unless otherwise noted Parameter Conditions Symbol High Level Input Voltage VIH Pin: SDA,SCL Low Level Input Voltage VIL Pin: SDA,SCL Input Current 1 IL 1 Pin: SDA,SCL Input Current 2 IL 2 Pin: VIN High Level Output Voltage VOH Low level Output Voltage VOL Pin: CLK2-4, REFOUT IOH=-4mA VREF Current Consumption 1 IDD1 Pin:VREF Cvref=1F MAX 0.7VDDI Unit V 0.3VDDI V -10 +10 A -3 +3 A 0.8VDD V IOL=+4mA Ta=25,3.3V VREF Voltage TYP Pin: CLK2-4, REFOUT Pin:CLK1p,CLK1n Output impedance MIN 0.2VDD V 14 20 26 0.72 0.8 0.88 V No load Clock out selection by note(1) VDD/VDDI=3.3V, Ta=25 32 mA 46 mA On load(2) Current Consumption 2 IDD2 Clock out selection by note(1) VDD/VDDI=3.3V, Ta=25 Current Consumption 3 IDDPD FULL_PD="H" VDD/VDDI=3.3V, Ta=25 0 150 A (1) CLK1p/1n:148.5MHz, CLK2=108MHz,CLK3/4=36.864MHz,REFOUT=27.0MHz (2) CLK1p/1n: Figure1, CLK2-4: Cp1=15pF, REFOUT:Cp2=25pF February-10 MS1108-E-03 -4- AK8136A AC Characteristics (Clock signals) VDD: over 3.0 to 3.6V, VDDI over 1.7 to 3.6V,Ta: over -20 to +85, 27MHz Crystal, unless otherwise noted Parameter Symbol Conditions MIN TYP MAX Unit Crystal Clock Frequency Fosc Pin:XI,XO 27.0000 MHz Output Clock Accuracy Faccuracy Pin:CLK2 100.71MHz Relative to 27.0MHz 106.25 ppm PRvcxo VIN at over 0 to VDD V 150 ppm GVCXO VIN range at 1.5V1.0V ppm/V Jit_period Pin:REFOUT ,CLK2-4 150 150 (6) Jit_tie Pin:CLK1 VCXO Pullable Range (1) VCXO Gain Period Jitter (5) Time Interval Error Long Term Jitter (6) (7) Jit_long (2) (3) (4) ps 100 Pin:REFOUT 1000 cycle delay (4) Pin: CLK1p,n Figure.3 (3) CLK2-4 (2) Pin: REFOUT Output Clock Duty Cycle DtyCyc Output Clock Slew Rate Slew_rise_fall Pin:CLK1p,n (4) Figure.3 Slew rate matching Slew_ver Pin:CLK1p,n (4) Figure.2 ps 160 45 50 40 50 2.5 ps 55 % 60 % 8.0 V/ns 20 % 550 mV Differential output swing V_swing Pin:CLK1p,n (4) Figure.3 300 Crossing point voltage V_cross Pin:CLK1p,n (4) Figure.2 300 Variation of Vcrs V_cross_delta Pin:CLK1p,n (4) Figure.2 140 mV Maximum output voltage V_max Pin:CLK1p,n (4) Figure.2 1.15 V Pin:CLK1p,n (4) Figure.2 3.0 ns Minimum output voltage V_min Output Clock Rise Time T_rise Output Clock Fall Time Output enable/disable Time T_fall (8) T_en_dis Power-up Time 1 (9) T_put1 Power-up Time 2 (10) T_put2 Pin: CLK2-4 Pin: CLK2-4 -0.3 (3) Pin: REFOUT mV (2 ) (3) (2 ) Pin: REFOUT Pin: REFOUT,CLK1p,n CLK2-4 Pin: REFOUT,CLK1p,n CLK2-4 Pin: REFOUT,CLK1p,n CLK2-4 V 1.0 2.5 5.0 ns 1.0 3.0 ns 2.5 5.0 ns 500 ns 4 ms 150 ms (1) Pullable range depends on crystal characteristics, on-chip load capacitance, and stray capacity of PCB. Typ. 150ppm is applied to AKM's authorized test condition. Please contact us when you plan the use of other crystal unit. (2) Measured with load capacitance of 25pF (3) Measured with load capacitance of 15pF (4) Measured with load condition shown in Figure.1 (5) 3 in 10000 sampling or more (6) 16ms accumulate with higher than 10GSa/s, under HDMI Compliant test Ver1.3a condition. (7) 3 in 10000 sampling or more (8) Refer to Figure.7 on Clock enable and disable sequence. (9) Time to settle output into 0.1% of specified frequency from FULL_PD is "L". Power Down sequence". Refer to Figure.6 on "Full (10) Refer to Figure.5 on "Power on Reset sequence". MS1108-E-03 February-10 -5- AK8136A 3.3V <5inch T-Line Z=50 30+/-5% Rs Measure point PLL 2pF Core T-Line Z=50 Vref 2pF Figure.1 CLK1 Load condition V_max=1.15V CLK1p V_cross_max=550mV V_cross V_cross_min=300mV CLK1n V_min=-0.3V CLK1p V_cross_delta_max=140mV V_cross_delta CLK1n CLK1n Slew_rise SE(Avg) +75mV Slew_fall SE(Avg) +75mV V_cross(Avg) -75mV -75mV CLK1p Figure.2 Single ended (SE) measurement waveforms February-10 MS1108-E-03 -6- AK8136A Period -DtyCyc 0.0V CLK1_diff +DtyCyc Slew_fall Slew_rise +150mV 0.0V V_swing 0.0V -150mV CLK1_diff Figure.3 Differential (DIFF) measurement waveforms MS1108-E-03 February-10 -7- AK8136A AC Characteristics (Serial interface VDD: over 3.0 to 3.6V, VDDI over 1.7 to 3.6V,Ta: over -20 to +85 , 27MHz Crystal, unless otherwise noted Parameter Symbol Conditions MIN MAX Unit 400 kHz SCL clock frequency fSCL SCL Clock Low Period tLOW 1.3 s SCL Clock High Period tHIGH 0.6 s Pulse width of spikes which must be suppressed tI 50 ns tAA 0.3 s tBUF 1.3 s Start Condition Hold Time tHD.STA 0.6 s Start Condition Setup Time (for a Repeated Start condition) tSU.STA 0.6 ms Data in Hold Time tHD.DAT 0 s Data in Setup Time tSU.DAT 100 ns SLC Low to SDA Data Out Bus free time between a STOP and START condition SDA and SCL Rise Time tR 0.3 s SDA and SCL Fall Time tF 0.3 s Stop Condition Setup Time tSU.STO Bus Line Load s 0.6 200 Cb tF pF tR SCL (IN) tSU.STA tLOW tHIGH tHD.DAT tHD.STA tSU.STO tSU.DAT SDA (IN) tAA tDH tBUF SDA (OUT) Figure.4 Serial Interface Timing February-10 MS1108-E-03 -8- AK8136A Function Description Power On Reset sequence AK8136A has the POR(Power On Reset) circuit. In power up, the POR works and the register is set to the initial value and all clock output becomes enable without glitch. Note1) The assumption power start time to reach 90 % of VDD is within 20 ms. Note2) The first register setting should be done after the 150 ms elapse after the power on. VDD1/2/3 VDD*0.9 POR (Internal signal) SCL/SDA Register setting available CLK1p/CLK2-4/REFOUT CLK1n Max:20ms Min:150ms Figure.5 Recommend Power Up Sequence MS1108-E-03 February-10 -9- AK8136A Serial interface Read/Write performance of serial interface is expressed below. The device address #1 of AK8136A is fixed as "1010". The device address #2 is "110". Device address of AK8136A 1 0 1 0 Device Adress#1 1 1 R:1 W:0 0 R/W Device Adress#2 Byte wtire operation Byte write operation is described below. Data must be sent after sending 8 bits address and receiving ACK. Byte write SDA 1 0 1 0 1 1 0 0 S T A R T Device Address -1 Device R A Address / C W K -2 Address (MSB First) Data (MSB First) A C K A S C T K O P Page write operation Page write operation is described below. Only lower 4 bits of address are valid. Upper 4 bits are fixed as "1111". Therefore the address which is written after "1111 1111" becomes "1111 1110". Page write 1 0 1 0 1 1 0 0 SDA S T A R T Device Address -1 Device R A Address / C W K -2 Address (MSB First) A C K Data A C K (Address) Data (Address+1) A C K A C K Data (Address+n) A S C T K O P Current address read Current address read operation is described below. The data that is read by this operation is obtained as "last accessed address + 1". Therefore, It is consequent to return "1111 1110" after accessing the address "1111 1111". Current address read SDA 1 0 1 0 1 1 01 S T A R T Device Address -1 Device R A Address / C W K -2 Data (MSB First) N O A C K S T O P February-10 MS1108-E-03 - 10 - AK8136A Random read Random read operation is described below. It is necessary to operate "dummy write" before sending read command. Dummy write is to send the address to read. Random read SDA 1 0 1 0 1 1 0 0 S T A R T Device Address -1 Device R A Address / C W K -2 1 0 1 0 1 1 0 1 Address (MSB First) A S C T K A R T Device Address -1 Device R A Address / C W K -2 Data (MSB First) N O A C K S T O P Dummy Write Sequential read Sequential read operation is described below. It is possible to read next address sequentially by sending ACK instead of stop condition. Sequential read SDA 1 1 0 1 Device R A Address / C W K -2 Data (MSB First) (Address) A C K Data (MSB First) (Address+1) A C K A C K Data (MSB First) (Address+n) N O A C K S T O P Change data Change data operation is described below. It is available when SCL is Low. Change data SCL SDA DATA STABLE DATA CHANGE Start / Stop timing Start / Stop timing is described below. The sequence is started when SDA goes from high to low during SCL is high. The sequence is stopped when SDA goes from low to high during SCL is high. Start / Stop timing SCL SDA START STOP MS1108-E-03 February-10 - 11 - AK8136A Register description The AK8136A generates a range of low-jitter and hi-accuracy clock frequencies with three built-in PLLs and provides to up to five assigned outputs. A frequency selection at assigned output pin and power down control is configured by register-setting. Register Map Address D7 D6 D5 D4 D3 D2 D1 D0 FULL_PD - - - CLK3S[1] CLK3S[0] CLK2S CLK1S 0 - - - 1 1 0 0 CLK4_DIS CLK3_DIS CLK2_DIS CLK1_DIS REF_DIS 0 0 0 0 0 Note FF Default FE Default Register definition FULL_PD (Address FF:D7) Power Down Control 0 Device Active (PLL ON) Enable VCXO, VREF and PLLs 1 Full Power Down Disable VCXO, VREF and PLLs (default) Full Power Down sequence The full power down setting is done by following sequence. 1) Change CLKn_DIS(n=1,2,3,4) and REF_DIS to "1" . 2) Change FULL_PD to "1" from "0". The output transfers to the disabled state without glitch. The full power down state is released by following sequence. 1) Changing FULL_PD to "0" from "1" . 2) After more than 4 ms elapse, change CLKn_DIS and REF_DIS The output transfers to the enable state without glitch. "0" to "1". CLKn_DIS, REF_DIS FULL_PD CLK1p/CLK2-4/REFOUT >4ms CLK1n Figure.6 Full Down sequence February-10 MS1108-E-03 - 12 - AK8136A CLK3S[1:0] (Address FF:D3,D2) CLK3&4 Output frequency selection CLK2S 00 22.5792MHz 01 24.576MHz 10 33.8688MHz 11 36.864MHz (default) (Address FF:D1) CLK2 Output frequency selection CLK1S 0 108MHz. 1 100.71MHz (default) (Address FF:D0) CLK1 Output frequency selection 0 148.5MHz/1.001 1 148.5MHz (default) CLK4_DIS (Address FE:D7) CLK4 Output Disable 0 Enable (CLK4 Active) 1 Disable(CLK4="L") (default) CLK3_DIS (Address FE:D6) CLK3 Output Disable 0 Enable (CLK3 Active) 1 Disable(CLK3="L") (default) CLK2_DIS (Address FE:D5) CLK2 Output Disable 0 Enable (CLK2 Active) 1 Disable(CLK2="L") (default) CLK1_DIS (Address FE:D4) CLK1 Output Disable 0 Enable (CLK1 Active) 1 Disable(CLK1p,CLK1n="L" ) MS1108-E-03 (default) February-10 - 13 - AK8136A REF_DIS (Address FE:D3) REFOUT Output Disable 0 Enable (REFOUT Active) 1 Disable(REFOUT="L") (default) Clock Enable and Disable sequence The enabling and disabling of the clock output are executed without glitch within 500 ns from the rising edge of SCL during the acknowledge operation after the corresponding byte date reception. SCL SDA Disable ACK < 500ns CLKn REFOUT SCL SDA Enable ACK < 500ns CLKn REFOUT Figure.7 Output Enable and Disable sequence February-10 MS1108-E-03 - 14 - AK8136A Voltage Controlled Crystal Oscillator (VCXO) The AK8136A has a voltage controlled crystal oscillator (VCXO), featuring fine frequency tuning for 27MHz of primary clock frequency by external DC voltage control. This tuning enables output clock frequency to synchronize the external clock system. VIN (Pin3) accepts DC voltage control from a processor or a system controller, and pulls the primary frequency of crystal to higher or lower. This pulling range is determined by crystal characteristic, on-chip load capacitor, and stray capacitance of PCB. The AK8136A is designed to range 150ppm of primary frequency in AKM's authorized condition, and the typical pulling profile is shown in Figure 8. For details about the condition and other specific crystal application case, refer the AK8136A application note. 27MHz VCXO Characteristics KDS DSX530GA 200 150 100 50 0 0 0 .5 1 1.5 2 2.5 3 3 .5 -50 -100 -150 -200 Figure 8: Typical VCXO Pulling Profile MS1108-E-03 February-10 - 15 - AK8136A KDS DSX530GA Item MIN TYP MAX 27.000 Unit Remark MHz CL=10.0pF Nominal frequency f0 Equivalent resistance R1 Shunt capacitance C0 3.0 pF Motional capacitance C1 11.4 fF Motional inductance L1 3.0 mH 50 Drive Level 10 300 uW Spurious No spurious within 3fo13kHz With in f0500kHz the attenuation of the spurious response should be more than 3dB. L1 R1 C1 Crystal unit C0 Load capacitance CL CL Figure.9 Equivalent parameter and load February-10 MS1108-E-03 - 16 - AK8136A +0.10 -0.05 0.500.20 Package Information +0.30 -0.10 0.15 6.5 11 4.400.20 6.400.30 20 1 10 0.10 M 010 0.220.10 0.65 0.45MAX S 1.150.10 0.10 0.100.10 S * Marking 20 11 b 8136A XXXXX AKM c a: b: c: d #1 Pin Index Part number Date code (5 digits) (1) Product Family Logo d a 10 1 * RoHS Compliance All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in "lead-free" packages* are fully compliant with RoHS. (*) RoHS compliant products from AKM are identified with "Pb free" letter indication on product label posted on the anti-shield bag and boxes. MS1108-E-03 February-10 - 17 - AK8136A IMPORTANT NOTICE l These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. l AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. l Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. l AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. l It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Asahi Kasei EMD Corporation has changed its company name to Asahi Kasei Microdevices Corporation (AKM) effective 1st April 2009. It is noted the documents according to this product, which was released before the date of 1st April 2009, shall include the old company name as Asahi Kasei EMD Corporation (AKEMD). These documents will be continuously valid by interpreting the old company name to the new one as Asahi Kasei Microdevices Corporation (AKM). Further information of this company name change, contact AKM's sales person or AKM's authorized distributor. February-10 MS1108-E-03 - 18 -