Supertex inc. MD1711 High Speed, Integrated Ultrasound Driver IC Features General Description Drives two ultrasound transducer channels Generates 5-level waveform Drives 12 high voltage MOSFETs 2.0A source and sink peak current Up to 20MHz output frequency 12V/ns slew rate 3ns matched delay times Second harmonic is less than -40dB Two separate gate drive voltages 1.8 to 3.3V CMOS logic interface The Supertex MD1711 is an IC for a two-channel, 5-level, high voltage and high speed transmitter driver. It is designed for medical ultrasound imaging applications, but can also be used for metal flaw detection, Non-Destructive Testing (NDT), and for driving piezoelectric transducers. The MD1711 is a two-channel logic controller circuit with low impedance MOSFET gate drivers. There are two sets of control logic inputs, one for channel A and one for channel B. Each channel consists of three pairs of MOSFET gate drivers. These drivers are designed to match the drive requirements of the Supertex TC6320. The MD1711 drives six TC6320s. Each pair consists of an N-channel and a P-channel MOSFET. They are designed to have the same impedance and can provide peak currents of over 2.0 amps. Applications Medical ultrasound imaging Piezoelectric transducer drivers Non-Destructive Testing (NDT) Metal flaw detection Sonar transmitter Typical Application Circuit +10V +5.0V 0.22F +10V 0.22F +10V -10V 0.22F 0.22F 40 FB 6 0.1F EN SEL POSA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2A / NEG2A ClampA +3.3V 36 33 35 DVDD2 DVDD2 DGND DVDD1 DVSS AVDD1 0.22F 42 43 45 31 +100V DVDD1 DVDD1 30 DGND DGND VPP1 1F DVDD2 OUTPA1 47 39 Control Logic & Level Translator 13 1 2 10nF DVDD2 OUTNA1 37 10nF VNN1 -100V +50V 3 4 46 41 DVDD1 (1/2 of I/O) 0.1F 48 OUTPA2 MD1711 VLL VPP2 1F DVDD1 5 1F 10nF OUTNA2 34 10nF VNN2 AVSS -50V 0.1F 1F Transducer 0V 0.1F 14 15 AVSS SUB OUTPA3 AVSS 44 VSS DVDD1 OUTNA3 32 -10V DGND AGND 7 0 DVDD1 18 DVSS DVDD2 DVDD1 DGND DVDD2 19 16 21 28 26 0.22F +10V Supertex inc. 0V 25 TC6320 0 -10V +10V +5.0V 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com MD1711 Pin Configurations Ordering Information Package Options Device MD1711 1 48-Lead QFN 48-Lead LQFP 7.00x7.00mm body 1.60mm height (max) 0.50mm pitch 7.00x7.00mm body 1.00mm height (max) 0.50mm pitch MD1711FG-G MD1711K6-G 48 48 1 -G indicates package is RoHS compliant (`Green') 48-Lead LQFP (FG) (top view) 48-Lead QFN (K6) (top view) Package Marking Top Marking YYWW Absolute Maximum Ratings MD1711FG LLLLLLLLL Parameter Value VLL logic supply voltage -0.5V to +5.5V AVDD1, DVDD1, positive gate drive supply -0.5V to +15V DVDD2, positive gate drive supply -0.5V to +15V AVSS, DVSS, negative gate drive supply -15V to +0.5V Thermal resistance (JA): Bottom Marking CCCCCCCC AAA Maximum junction temperature 48-Lead LQFP (FG) MD1711K6 LLLLLLLLL YYWW AAA CCC +125C Storage temperature -65C to 150C Power dissipation 1.2W *May be part of top marking Package may or may not include the following marks: Si or 50C/W 29C/W 48-Lead LQFP* 48-Lead QFN* YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging Package may or may not include the following marks: Si or 48-Lead QFN (K6) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * 1.0oz 4-layer 3x4" PCB Operating Supply Voltages and Currents (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25C) Sym Parameter Min Typ Max Logic supply +1.8 +3.3 +5.0 V --- AVDD1 Positive drive bias supply +8.0 +10.0 +12.6 V --- DVDD1 Positive gate drive supply +4.75 - +12.60 V --- DVDD2 Positive gate drive supply +4.75 - +12.60 V --- -12.0 -10.0 -8.0 V --- VLL AVSS, DVSS Negative gate drive and bias supply Supertex inc. Units Conditions 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 MD1711 Operating Supply Voltages and Currents (cont.) (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25C) Sym Parameter Min Typ Max IVLL Logic supply current - 2.0 - IAVDD1 Positive bias current - 5.0 - Negative drive and bias supply current - 20 - IDVDD1 Positive drive current 1 - 55 - IDVDD2 Positive drive current 2 - 13 IAVDD1Q VAVDD1 quiescent current - IAVSSQ VAVSS quiescent current IDVDD1Q IDVDD2Q IAVSS & IDVSS IVLLQ Units Conditions mA All channels on at 5.0Mhz, no load - mA All channels on at 5.0Mhz, DVDD2 = 5.0, no load 2.0 - mA - 0.75 - mA VDVDD1 quiescent current - - 10 A VDVDD2 quiescent current - - 10 A Logic supply current - 1.0 - mA EN = low, All inputs low or high. DC Electrical Characteristics (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70C) P-Channel Gate Driver Outputs Sym Parameter Min Typ Max RSINK Output sink resistance - - 6.0 ISINK = 100mA RSOURCE Output source resistance - - 6.0 ISOURCE = 100mA ISINK Peak output sink current - 2.0 - A --- Peak output source current - 2.0 - A --- Min Typ Max ISOURCE Units Conditions N-Channel Gate Driver Outputs Sym Parameter RSINK Output sink resistance - - 10 ISINK = 100mA RSOURCE Output source resistance - - 10 ISOURCE = 100mA ISINK Peak output sink current - 1.5 - A --- Peak output source current - 1.5 - A --- Min Typ Max ISOURCE Units Conditions Logic Inputs Sym Parameter Units Conditions VIH Input logic high voltage 0.8VLL - VLL V --- VIL Input logic low voltage 0 - 0.2VLL V --- IIH Input logic high current - - 1.0 A --- IIL Input logic low current -1.0 - - A --- Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 MD1711 AC Electrical Characteristics (Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70C) Sym Parameter Min Typ Max Units Conditions fOUT Output frequency range - - 20 MHz tPH Propagation delay when output is from low to high - 19 - ns No load, See timing diagram tPL Propagation delay when output is from high to low - 19 - ns No load, See timing diagram tr Output rise time - 8.0 - ns 1000pF load, see timing diagram tf Output fall time - 8.0 - ns 1000pF load, see timing diagram tDM Delay time matching - - 3.0 ns No load, from device to device tDLAY Output jitter - 30 - ps Standard deviation of tD samples (1k) Output slew rate - 12 - V/ns 2nd harmonic distortion - -40 - dB SR HD2 --- Measured at TC6320 output with 100 load Power-Up Sequence Step Connection Description 1 AVSS , DVSS Negative gate drive supply and substrate bias 2 VLL, AVDD1, DVDD1 & DVDD2 Logic supply, positive gate drive supply and bias Test Circuit for Channel A 1/2 of MD1711 3x TC6320 DVDD2 OUT-PA1 +10V AV DD1 10nF +100V VPP1 GPA1 HVOUTPA1 +10V DVDD1 DVDD2 +10VDVDD2 OUT-NA1 10nF GNA1 +3.3V VLL VNN1 POSA/POS1A HVEN1A/POS2A HVEN2A/NEG2A RLOAD 100 HVOUTNA1 -100V EN NEGA/NEG1A HVOUTA Channel A Control Logic and Level Translation DVDD1 OUT-PA2 10nF +50V VPP2 GPA2 HVOUTPA2 DVDD1 OUT-NA2 CLAMPA 10nF GNA2 HVOUTNA2 -50V SEL VNN2 AGND VPP3 DGND AVSS DVSS -10V OUT-PA3 GPA3 HVOUTPA3 DVSS DVDD1 OUT-NA3 GNA3 HVOUTNA3 VNN3 Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 MD1711 Truth Table for Channels A and B (For SEL = L) Logic Control Inputs VPP1 to VNN1 Output VPP2 to VNN2 Output VPP3 to VNN3 Output SEL EN HVEN1/ POS2 HVEN2/ NEG2 Clamp POS/ POS1 NEG/ NEG1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 0 0 OFF OFF 0 1 1 0 0 0 1 OFF ON 0 1 1 0 0 1 0 ON OFF 0 1 1 0 0 1 1 OFF OFF 0 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 X X X X X Supertex inc. HVOUTP1 HVOUTN1 HVOUTP2 OFF HVOUTN2 OFF OFF HVOUTP3 HVOUTN3 ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF ON OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 MD1711 Truth Table for Channels A and B (For SEL = H) Logic Control Inputs VPP1 to VNN1 Output VPP2 to VNN2 Output VPP3 to VNN3 Output SEL EN Clamp HVEN1/ POS2 HVEN2/ NEG2 POS/ POS1 NEG/ NEG1 HVOUTP1 HVOUTN1 1 1 0 0 0 0 0 OFF OFF 1 1 0 0 0 0 1 OFF ON 1 1 0 0 0 1 0 ON OFF 1 1 0 0 0 1 1 ON ON 1 1 0 0 1 0 0 OFF OFF 1 1 0 0 1 0 1 OFF ON 1 1 0 0 1 1 0 ON OFF 1 1 0 0 1 1 1 ON ON 1 1 0 1 0 0 0 OFF OFF 1 1 0 1 0 0 1 OFF ON 1 1 0 1 0 1 0 ON OFF 1 1 0 1 0 1 1 ON ON 1 1 0 1 1 0 0 OFF OFF 1 1 0 1 1 0 1 OFF ON 1 1 0 1 1 1 0 ON OFF 1 1 0 1 1 1 1 ON ON 1 1 1 0 0 0 0 OFF OFF 1 1 1 0 0 0 1 OFF ON 1 1 1 0 0 1 0 ON OFF 1 1 1 0 0 1 1 ON ON 1 1 1 0 1 0 0 OFF OFF 1 1 1 0 1 0 1 OFF ON 1 1 1 0 1 1 0 ON OFF 1 1 1 0 1 1 1 ON ON 1 1 1 1 0 0 0 OFF OFF 1 1 1 1 0 0 1 OFF ON 1 1 1 1 0 1 0 ON OFF 1 1 1 1 0 1 1 ON ON 1 1 1 1 1 0 0 OFF OFF 1 1 1 1 1 0 1 OFF ON 1 1 1 1 1 1 0 ON OFF 1 1 1 1 1 1 1 ON ON 1 0 X X X X X OFF OFF Supertex inc. HVOUTP2 HVOUTN2 HVOUTP3 OFF OFF OFF OFF ON OFF ON OFF OFF ON ON OFF OFF OFF ON OFF ON ON ON OFF ON ON ON ON OFF OFF OFF 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 6 HVOUTN3 MD1711 Timing Diagram VLL HVEN1A/POS2A 0V VLL HVEN2A/NEG2A 0V VLL POSA/POS1A 0V VLL NEGA/NEG1A 0V VPP1 fOUT VPP2 HVOUTA 0V VNN2 VNN1 tr1, rise time from 0.9VNN1 to 0.9VPP1 tf1, fall time from 0.9VPP1 to 0.9VNN1 tr2, rise time from 0.9VNN2 to 0.9VPP2 tf2, fall time from 0.9VPP2 to 0.9VNN2 3.3V 50% IN 0V 50% tPH tPL 10V 90% 90% OUT 0V Supertex inc. 10% 10% tr t 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 7 MD1711 Block Diagram +100V 1.0F DV DD 2 10nF DVDD1 DV DD 2 DVDD2 10nF -100V AVDD1 1.0F +100V DV DD 1 Piezoelectric Transducer A 1.0F 10nF DV DD 1 POSA/POS1A 10nF NEGA/NEG1A -100V 1.0F HVEN1A/POS2A HVEN2A/NEG2A CLAMPA VSS DV DD 1 VLL SEL EN Control Logic and Level Translate +100V 1.0F DV DD 2 10nF DV DD 2 POSB/POS1B 10nF -100V NEGB/NEG1B 1.0F HVEN1B/POS2B HVEN2B/NEG2B +100V DV DD 1 1.0F CLAMP Piezoelectric Transducer B 10nF DV DD 1 10nF -100V 1.0F AVSS DVSS AGND DGND VSS DV DD 1 MD1711 Supertex inc. TC6320 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 8 MD1711 Pin Description (48-Lead LQFP & 48-Lead QFN) Pin # Name Description 1 POSA / POS1A Logic input control for channel A. When SEL = L, the pin is POSA. When SEL = H, the pin is POS1A. 2 NEGA / NEG1A Logic input control for channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin is NEG1A. 3 HVEN1A / POS2A Logic input control for channel A. When SE L= L, the pin is HVEN1A. When SEL = H, the pin is POS2A. 4 HVEN2A / NEG2A Logic input control for channel A. When SEL = L, the pin is HVEN2A. When SEL = H, the pin is NEG2A. 5 CLAMPA Used with SEL = H. Logic input control for OUT-PA3 and OUT-NA3. Connect to ground when SEL = L. 6 AVDD1 Supplies analog circuitry portion of the gate driver. Should be at the same potential as DVDD1. 7 AGND Analog Ground. 8 CLAMPB Used with SEL = H. Logic input control for OUT-PB3 and OUT-NB3. Connect to ground when SEL = L. 9 HVEN2B / NEG2B Logic input control for channel B. When SEL = L, the pin is HVEN2B. When SEL = H, the pin is NEG2B. 10 HVEN1B / POS2B Logic input control for channel B. When SEL = L, the pin is HVEN1B. When SEL = H, the pin is POS2B. 11 NEGB / NEG1B Logic input control for channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin is NEG1B. 12 POSB / POS1B Logic input control for channel B. When SEL = L, the pin is POSB. When SEL = H, the pin is POS1B. 13 SEL Logic input select. See truth tables for SEL = L and SEL = H. AVSS Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected to the IC substrate. They are required to connect to the most negative potential of voltage supplies. 16 DVSS Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and the main Output stage. Should be at the same potential as AVSS. 17 OUT-PB3 18 DGND Digital Ground. 19 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3. Should be at the same potential as AVDD1. 20 Out-PB2 21 DVDD2 22 Out-PB1 23 N/C 24 Out-NB1 25 DVDD2 14 15 Output P-Channel gate driver for channel B. Output P-Channel gate driver for channel B. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different potential than DVDD1. Output P-Channel gate driver for channel B. No connect. Output N-Channel gate driver for channel B. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different potential than DVDD1. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 9 MD1711 Pin # Name Description 26 DGND Digital Ground. 27 Out-NB2 28 DVDD1 29 Out-NB3 30 DGND Digital Ground. 31 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3. Should be at the same potential as AVDD1. 32 OUT-NA3 33 DVDD1 34 Out-NA2 35 DGND Digital Ground. 36 DVDD2 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different potential than DVDD1. 37 Out-NA1 38 N/C 39 Out-PA1 40 DVDD2 41 OUT-PA2 42 DVDD1 Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3. Should be at the same potential as AVDD1. 43 DGND Digital Ground. 44 Out-PA3 45 DVSS 46 VLL Logic supply voltage. 47 EN Logic input enable control. When EN = L, all P-channel output drivers are high and all Nchannel output drivers are low. 48 AVSS Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected to the IC substrate. They are required to connect to the most negative potential of voltage supplies. Center Pad AVSS For the QFN package, the center pad is at AVSS potential. It should be externally connected to AVSS. Output N-Channel gate driver for channel B Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3. Should be at the same potential as AVDD1. Output N-Channel gate driver for channel B Output N-Channel gate drivers for channel A. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3. Should be at the same potential as AVDD1. Output N-Channel gate drivers for channel A. Output N-Channel gate drivers for channel A. No connect. Output P-Channel gate drivers for channel A Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different potential than DVDD1. Output P-Channel gate drivers for channel A Output P-Channel gate drivers for channel A Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and the main output stage. Should be at the same potential as AVSS. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 10 MD1711 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) 48 1 e b Top View A A2 L Seating Plane L1 Side View A1 Gauge Plane L2 View B Seating Plane View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* - - 1.40 0.22 9.00 7.00 9.00 7.00 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 11 L2 0.25 BSC 0O 3.5O 7O MD1711 48-Lead QFN Package Outline (K6) 7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 48 48 Note 1 (Index Area D/2 x E/2) 1 1 Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 A3 A A1 L Seating Plane L1 Note 2 View B Side View Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.18 6.85* 1.25 6.85* 1.25 0.25 7.00 - 7.00 - 0.30 7.15* 5.45 7.15* 5.45 0.50 BSC L L1 0.00 0O 0.40 - - 0.50 0.15 14O 0.30 JEDEC Registration MO-220, Variation VKKD-6, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-48QFNK67X7P050, Version C041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. (c)2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-MD1711 D011612 12 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com