Supertex inc. MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Features
►Drives two ultrasound transducer channels
►Generates 5-level waveform
►Drives 12 high voltage MOSFETs
►±2.0A source and sink peak current
►Up to 20MHz output frequency
►12V/ns slew rate
►±3ns matched delay times
►Second harmonic is less than -40dB
►Two separate gate drive voltages
►1.8 to 3.3V CMOS logic interface
Applications
►Medical ultrasound imaging
►Piezoelectric transducer drivers
►Non-Destructive Testing (NDT)
►Metal aw detection
►Sonar transmitter
General Description
The Supertex MD1711 is an IC for a two-channel, 5-level,
high voltage and high speed transmitter driver. It is designed
for medical ultrasound imaging applications, but can also be
used for metal aw detection, Non-Destructive Testing (NDT),
and for driving piezoelectric transducers.
The MD1711 is a two-channel logic controller circuit with
low impedance MOSFET gate drivers. There are two sets of
control logic inputs, one for channel A and one for channel B.
Each channel consists of three pairs of MOSFET gate drivers.
These drivers are designed to match the drive requirements of
the Supertex TC6320. The MD1711 drives six TC6320s. Each
pair consists of an N-channel and a P-channel MOSFET. They
are designed to have the same impedance and can provide
peak currents of over 2.0 amps.
Typical Application Circuit
High Speed, Integrated Ultrasound Driver IC
VNN1
TC6320
+100V
-100V
+50V
-50V
0V
0V
30
32
34
44
39
41
37
DV
DD
2
V
SS
DVSS
-10V
DVDD1DVDD2
16
19 21
+10V
VLL
+3.3V
AVSS
48
14
15
AVSS
SEL
POSA / POS1A
EN
DGND
AGND
0
MD1711
(1/2 of I/O)
SUB
718
AVSS
33
36
28 25
31
DGND
35
40 42
43
DVSS
45
FB
AVDD1
6
0
46
47
13
1
2
3
4
5
OUTPA1
OUTNA1
OUTPA2
OUTNA2
OUTPA3
OUTNA3
DGND
DGND
+5.0V
DVDD1
+10V
DVDD2
+5.0V
+10V
+10V
26
DGND
+10V
-10V
-10V
DVDD2
DVDD1
DVDD1
Transducer
0.22µF
Control Logic
& Level
Translator
NEGA / NEG1A
HVEN1A / POS2A
HVEN2A / NEG2A
ClampA
0.1µF
0.1µF
0.1µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.1µF
10nF
10nF
10nF
10nF
1µF
1µF
1µF
1µF
VNN2
VPP2
VPP1
DV
DD
2
DV
DD
1
DV
DD
1
DV
DD
1
DVDD2DVDD1
2
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
Device
Package Options
48-Lead LQFP
7.00x7.00mm body
1.60mm height (max)
0.50mm pitch
48-Lead QFN
7.00x7.00mm body
1.00mm height (max)
0.50mm pitch
MD1711 MD1711FG-G MD1711K6-G
Absolute Maximum Ratings
Parameter Value
VLL logic supply voltage -0.5V to +5.5V
AVDD1, DVDD1, positive gate drive supply -0.5V to +15V
DVDD2, positive gate drive supply -0.5V to +15V
AVSS, DVSS, negative gate drive supply -15V to +0.5V
Thermal resistance (θJA):
48-Lead LQFP*
48-Lead QFN*
50°C/W
29°C/W
Maximum junction temperature +125C
Storage temperature -65°C to 150°C
Power dissipation 1.2W
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
* 1.0oz 4-layer 3x4” PCB
-G indicates package is RoHS compliant (‘Green’)
Pin Congurations
Package Marking
48-Lead LQFP (FG)
48-Lead LQFP (FG)
(top view)
1
48
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
MD1711FG
LLLLLLLLL
CCCCCCCC
AAA
48-Lead QFN (K6)
(top view)
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
MD1711K6
LLLLLLLLL
YYWW
AAA CCC
48-Lead QFN (K6)
1
48
Operating Supply Voltages and Currents
(Over operating conditions unless otherwise specied, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
VLL Logic supply +1.8 +3.3 +5.0 V ---
AVDD1 Positive drive bias supply +8.0 +10.0 +12.6 V ---
DVDD1 Positive gate drive supply +4.75 - +12.60 V ---
DVDD2 Positive gate drive supply +4.75 - +12.60 V ---
AVSS, DVSS Negative gate drive and bias supply -12.0 -10.0 -8.0 V ---
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
3
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
DC Electrical Characteristics
(Over operating conditions unless otherwise specied, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70°C)
P-Channel Gate Driver Outputs
Sym Parameter Min Typ Max Units Conditions
RSINK Output sink resistance - - 6.0 ΩISINK = 100mA
RSOURCE Output source resistance - - 6.0 ΩISOURCE = 100mA
ISINK Peak output sink current - 2.0 -A ---
ISOURCE Peak output source current - 2.0 - A ---
N-Channel Gate Driver Outputs
Sym Parameter Min Typ Max Units Conditions
RSINK Output sink resistance - - 10 ΩISINK = 100mA
RSOURCE Output source resistance - - 10 ΩISOURCE = 100mA
ISINK Peak output sink current - 1.5 - A ---
ISOURCE Peak output source current - 1.5 - A ---
Logic Inputs
Sym Parameter Min Typ Max Units Conditions
VIH Input logic high voltage 0.8VLL - VLL V ---
VIL Input logic low voltage 0 - 0.2VLL V ---
IIH Input logic high current - - 1.0 µA ---
IIL Input logic low current -1.0 - - µA ---
Operating Supply Voltages and Currents (cont.)
(Over operating conditions unless otherwise specied, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25°C)
Sym Parameter Min Typ Max Units Conditions
IVLL Logic supply current - 2.0 -
mA All channels on at 5.0Mhz,
no load
IAVDD1 Positive bias current - 5.0 -
IAVSS & IDVSS Negative drive and bias supply current - 20 -
IDVDD1 Positive drive current 1 - 55 -
IDVDD2 Positive drive current 2 - 13 - mA All channels on at 5.0Mhz,
DVDD2 = 5.0, no load
IAVDD1Q VAVDD1 quiescent current - 2.0 - mA
EN = low, All inputs low or
high.
IAVSSQ VAVSS quiescent current - 0.75 - mA
IDVDD1Q VDVDD1 quiescent current - - 10 µA
IDVDD2Q VDVDD2 quiescent current - - 10 µA
IVLLQ Logic supply current - 1.0 - mA
4
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
AC Electrical Characteristics
(Over operating conditions unless otherwise specied, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70°C)
Sym Parameter Min Typ Max Units Conditions
fOUT Output frequency range - - 20 MHz ---
tPH
Propagation delay when
output is from low to high - 19 - ns No load, See timing diagram
tPL
Propagation delay when
output is from high to low - 19 - ns No load, See timing diagram
trOutput rise time - 8.0 - ns 1000pF load, see timing diagram
tfOutput fall time - 8.0 - ns 1000pF load, see timing diagram
ΔtDM Delay time matching - - ±3.0 ns No load, from device to device
ΔtDLAY Output jitter - 30 - ps Standard deviation of tD samples (1k)
SR Output slew rate - 12 - V/ns Measured at TC6320 output
with 100Ω load
HD2 2nd harmonic distortion - -40 - dB
Power-Up Sequence
Step Connection Description
1AVSS , DVSS Negative gate drive supply and substrate bias
2 VLL, AVDD1, DVDD1 & DVDD2 Logic supply, positive gate drive supply and bias
Test Circuit for Channel A
DVDD2
POSA/POS1A
NEGA/NEG1A
HVEN1A/POS2A
HVEN2A/NEG2A
AGND
DGND
GPA1
HVOUTPA1
OUT-NA3
RLOAD
100
HVOUTA
10nF
10nF
AVSS
CLAMPA
DVSS
SEL
EN
+10V AV DD1
+10V DVDD1
+10VDVDD2
+3.3V VLL
-10V
+100V
-100V
+50V
-50V
1/2 of MD1711 3x TC6320
Channel A
Control
Logic and
Level
Translation
DVDD2
DVDD1
DVDD1
DVDD1
DVSS
VPP1
VPP2
VNN1
VNN2
OUT-PA3
OUT-NA2
OUT-PA2
OUT-NA1
OUT-PA1
10nF
10nF
HVOUTNA1
HVOUTPA2
HVOUTNA2
HVOUTPA3
HVOUTNA3
GNA1
GPA2
GNA2
GPA3
GNA3
VPP3
VNN3
5
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Truth Table for Channels A and B (For SEL = L)
Logic Control Inputs VPP1 to VNN1 Output VPP2 to VNN2 Output VPP3 to VNN3 Output
SEL EN HVEN1/
POS2
HVEN2/
NEG2 Clamp POS/
POS1
NEG/
NEG1 HVOUTP1 HVOUTN1 HVOUTP2 HVOUTN2 HVOUTP3 HVOUTN3
0100000
OFF OFF
ON ON
0 1 0 0 0 0 1 ON ON
0 1 0 0 0 1 0 ON ON
0 1 0 0 0 1 1 OFF OFF
0100100
OFF OFF OFF
0100101
0100110
0100111
0101000
OFF
OFF OFF ON ON
0 1 0 1 0 0 1 OFF ON OFF OFF
0 1 0 1 0 1 0 ON OFF OFF OFF
0 1 0 1 0 1 1 OFF OFF OFF OFF
0101100
OFF OFF OFF
0101101
0101110
0101111
0 1 1 0 0 0 0 OFF OFF
OFF
ON ON
0 1 1 0 0 0 1 OFF ON OFF OFF
0 1 1 0 0 1 0 ON OFF OFF OFF
0 1 1 0 0 1 1 OFF OFF OFF OFF
0110100
OFF OFF OFF
0110101
0110110
0110111
0111000
OFF OFF OFF
0111001
0111010
0111011
0111100
OFF OFF OFF
0111101
0111110
0111111
0 0 X X X X X OFF OFF OFF
6
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Truth Table for Channels A and B (For SEL = H)
Logic Control Inputs VPP1 to VNN1 Output VPP2 to VNN2 Output VPP3 to VNN3 Output
SEL EN Clamp HVEN1/
POS2
HVEN2/
NEG2
POS/
POS1
NEG/
NEG1 HVOUTP1 HVOUTN1 HVOUTP2 HVOUTN2 HVOUTP3 HVOUTN3
1 1 0 0 0 0 0 OFF OFF
OFF OFF OFF
1 1 0 0 0 0 1 OFF ON
1 1 0 0 0 1 0 ON OFF
1 1 0 0 0 1 1 ON ON
1 1 0 0 1 0 0 OFF OFF
OFF ON OFF
1 1 0 0 1 0 1 OFF ON
1 1 0 0 1 1 0 ON OFF
1 1 0 0 1 1 1 ON ON
1 1 0 1 0 0 0 OFF OFF
ON OFF OFF
1 1 0 1 0 0 1 OFF ON
1 1 0 1 0 1 0 ON OFF
1 1 0 1 0 1 1 ON ON
1 1 0 1 1 0 0 OFF OFF
ON ON OFF
1 1 0 1 1 0 1 OFF ON
1 1 0 1 1 1 0 ON OFF
1 1 0 1 1 1 1 ON ON
1 1 1 0 0 0 0 OFF OFF
OFF OFF ON
1 1 1 0 0 0 1 OFF ON
1 1 1 0 0 1 0 ON OFF
1 1 1 0 0 1 1 ON ON
1 1 1 0 1 0 0 OFF OFF
OFF ON ON
1 1 1 0 1 0 1 OFF ON
1 1 1 0 1 1 0 ON OFF
1 1 1 0 1 1 1 ON ON
1 1 1 1 0 0 0 OFF OFF
ON OFF ON
1 1 1 1 0 0 1 OFF ON
1 1 1 1 0 1 0 ON OFF
1 1 1 1 0 1 1 ON ON
1 1 1 1 1 0 0 OFF OFF
ON ON ON
1 1 1 1 1 0 1 OFF ON
1 1 1 1 1 1 0 ON OFF
1 1 1 1 1 1 1 ON ON
1 0 X X X X X OFF OFF OFF OFF OFF
7
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Timing Diagram
POSA/POS1A
NEGA/NEG1A
0V
VLL
HVEN2A/NEG2A
VPP1
VNN1
VPP2
VNN2
HVOUTA
tr1, rise time from
0.9VNN1 to 0.9VPP1
fOUT
0V
3.3V
IN
tPH
10%
90%
50%
0V
10V
50%
OUT
tPL
tr
90%
10%
t
tf1, fall time from
0.9VPP1 to 0.9VNN1
tr2, rise time from
0.9VNN2 to 0.9VPP2
tf2, fall time from
0.9VPP2 to 0.9VNN2
VLL
VLL
VLL
0V
0V
0V
0V
HVEN1A/POS2A
8
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Block Diagram
10nF
10nF
+
100
V
1.0µF
DVDD1
10nF
10nF
10nF
10nF
10nF
10nF
TC
63
2
0
DVDD2
AVDD1
VLL
SEL
EN
AVSS
DVSS
AGND
DGND
POSA/POS1A
CLAMPA
NEGA/NEG1A
HVEN1A/POS2A
HVEN2A/NEG2A
POSB/POS1B
CLAMP
NEGB/NEG1B
HVEN1B/POS2B
HVEN2B/NEG2B
DV
DD
1
V
SS
Piezoelectric
Transducer A
Control
Logic
and
Level
Translate
MD1711
-100V
1.0µF
+100V
1.0µF
-100V
1.0µF
+100V
1.0µF
-100V
1.0µF
+100V
1.0µF
-100V
1.0µF
DV
DD
1
DV
DD
1
DV
DD
2
DV
DD
2
DV
DD
1
DV
DD
1
V
SS
DV
DD
1
DV
DD
2
DV
DD
2
Piezoelectric
Transducer B
9
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin Description (48-Lead LQFP & 48-Lead QFN)
Pin # Name Description
1 POSA / POS1A Logic input control for channel A. When SEL = L, the pin is POSA. When SEL = H, the pin
is POS1A.
2 NEGA / NEG1A Logic input control for channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin
is NEG1A.
3 HVEN1A / POS2A Logic input control for channel A. When SE L= L, the pin is HVEN1A. When SEL = H, the
pin is POS2A.
4 HVEN2A / NEG2A Logic input control for channel A. When SEL = L, the pin is HVEN2A. When SEL = H, the
pin is NEG2A.
5 CLAMPA Used with SEL = H. Logic input control for OUT-PA3 and OUT-NA3. Connect to ground when
SEL = L.
6AVDD1Supplies analog circuitry portion of the gate driver. Should be at the same potential as
DVDD1.
7 AGND Analog Ground.
8 CLAMPB Used with SEL = H. Logic input control for OUT-PB3 and OUT-NB3. Connect to ground when
SEL = L.
9 HVEN2B / NEG2B Logic input control for channel B. When SEL = L, the pin is HVEN2B. When SEL = H, the
pin is NEG2B.
10 HVEN1B / POS2B Logic input control for channel B. When SEL = L, the pin is HVEN1B. When SEL = H, the
pin is POS2B.
11 NEGB / NEG1B Logic input control for channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin
is NEG1B.
12 POSB / POS1B Logic input control for channel B. When SEL = L, the pin is POSB. When SEL = H, the pin
is POS1B.
13 SEL Logic input select. See truth tables for SEL = L and SEL = H.
14
AVSS
Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected
to the IC substrate. They are required to connect to the most negative potential of voltage
supplies.
15
16 DVSS Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and
the main Output stage. Should be at the same potential as AVSS.
17 OUT-PB3 Output P-Channel gate driver for channel B.
18 DGND Digital Ground.
19 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3.
Should be at the same potential as AVDD1.
20 OUT-PB2 Output P-Channel gate driver for channel B.
21 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different po-
tential than DVDD1.
22 OUT-PB1 Output P-Channel gate driver for channel B.
23 N/C No connect.
24 OUT-NB1 Output N-Channel gate driver for channel B.
25 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different po-
tential than DVDD1.
10
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin # Name Description
26 DGND Digital Ground.
27 OUT-NB2 Output N-Channel gate driver for channel B
28 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3.
Should be at the same potential as AVDD1.
29 OUT-NB3 Output N-Channel gate driver for channel B
30 DGND Digital Ground.
31 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3.
Should be at the same potential as AVDD1.
32 OUT-NA3 Output N-Channel gate drivers for channel A.
33 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3.
Should be at the same potential as AVDD1.
34 OUT-NA2 Output N-Channel gate drivers for channel A.
35 DGND Digital Ground.
36 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different po-
tential than DVDD1.
37 OUT-NA1 Output N-Channel gate drivers for channel A.
38 N/C No connect.
39 OUT-PA1 Output P-Channel gate drivers for channel A
40 DVDD2
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different po-
tential than DVDD1.
41 OUT-PA2 Output P-Channel gate drivers for channel A
42 DVDD1
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3.
Should be at the same potential as AVDD1.
43 DGND Digital Ground.
44 OUT-PA3 Output P-Channel gate drivers for channel A
45 DVSS Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and
the main output stage. Should be at the same potential as AVSS.
46 VLL Logic supply voltage.
47 EN Logic input enable control. When EN = L, all P-channel output drivers are high and all N-
channel output drivers are low.
48 AVSS
Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected
to the IC substrate. They are required to connect to the most negative potential of voltage
supplies.
Center
Pad AVSS For the QFN package, the center pad is at AVSS potential. It should be externally connected
to AVSS.
11
MD1711
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
Dimension
(mm)
MIN 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80*
0.50
BSC
0.45
1.00
REF
0.25
BSC
0O
NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5O
MAX 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-48LQFPFG Version, D041309.
1
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
D
D1
E
E1
b e
Side View
A2
A
A1
Note 1
(Index Area
D1/4 x E1/4)
48
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
12
MD1711
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-MD1711
D011612
48-Lead QFN Package Outline (K6)
7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch
Symbol A A1 A3 b D D2 E E2 e L L1 θ
Dimension
(mm)
MIN 0.80 0.00 0.20
REF
0.18 6.85* 1.25 6.85* 1.25 0.50
BSC
0.30†0.00 0O
NOM 0.90 0.02 0.25 7.00 - 7.00 - 0.40†- -
MAX 1.00 0.05 0.30 7.15* 5.45 7.15* 5.45 0.50†0.15 14O
JEDEC Registration MO-220, Variation VKKD-6, Issue K, June 2006.
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc.#: DSPD-48QFNK67X7P050, Version C041009.
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Seating
Plane
Top View
Side View
Bottom View
A
A1
D
E
D2
b
E2
A3
L
L1
View B
View B
1
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
48
1
48
θ
