Preliminary I/||CATALYST SEMICONDUCTOR CAT28F010/CAT28F010I 1 Megabit CMOS FLASH MEMORY FEATURES @ Fast Read Access Time: 120/150/200 ns m Low Power CMOS Dissipation: Active: 30 mA max (CMOS/TTL levels) Standby: 1 mA max (TTL levels) ~Standby: 100 .A max (CMOS levels) m High Speed Programming: ~10 US per byte 2 Sec Typ Chip Program @ 12.0V + 5% Programming and Erase Voltage @ Stop Timer for Program/Erase On-Chip Address and Data Latches m JEDEC Standard Pinouts: ~32 pin DIP -32 pin PLCC ~32 pin TSOP (8 x 14; 8 x 20) mw 10,000 Program/Erase Cycles m@ 10 Year Data Retention @ Electronic Signature DESCRIPTION The CAT28F010/CAT28F 0101 is a high speed 128K x 8 bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-sys- tem or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 1 second. It is pin and Read timing compatible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algo- rithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the /O bus and address bus during the write operation. The CAT28F010/CAT28F010I is manufactured using Catalysts advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32 pin plastic DIP, 32 pin PLCC or 32 pin TSOP packages. BLOCK DIAGRAM VOg-VO7 VO BUFFERS | ERASE VOLTAGE 7% SWITCH WE ] COMMAND PROGRAM VOLTAGE | | == DATA | [SENSE >| REGISTER [> SWITCH CE,OE LOGIC [i atcH| | amp 4 CE OE 3 | Y-GATING & | Y-DECODER a AoAt6 TY oD 1,048,576 BIT w MEMORY [* a X-DECODER ARRAY << VOLTAGE VERIFY $108 FHD Foz SWITCH | TD 5108 1992 by Catalyst Semiconductor, Inc. 8-37 Characteristics subject to change without noticeCAT28F010/CAT28F0101! Preliminary PIN CONFIGURATION PIN FUNCTIONS DIP Package PLCC Package Pin Name Type Function Vpp Cet 32 [Veco f zz = oe 8 Ao~A16 Input Address Inputs for Aig OQ 2 31 [WE nooooon memory addressing AisL} 3 30 FI NIC 4 3 2 1 323130 VOo-V/O7 V0 Data Input/Output Ayo 4 29 [1 Ay4 CJ A14 , A7O)5 28 DL Ayg Aig CE Input Chip Enable As) 6S 27 Fi Ag PI Ag OE input | Output Enable As Cl] 7 26 [FD Ag i] Ag ; Agt)s = =28 PAny rT An E Input | Write Enable A309 24 (7 OE POE Vec Voltage Supply Aol] 10 23 FAO V] Ato A;O) 1 622 [CE | CE Vss Ground Ag C4 12 21 1 07 1] v/O7 Vpp Program/Erase Oo9C4 13 20 1 106 Voltage Supply WO, 14 19 (Ws WOo( 15 18 [104 VssO] 16) #17 F103 5108 FHD Fot TSOP Package (Standard Pinout) Ay, C1 32 fr OE Ag C2 31 3 Ato Ag [13 30 Fr CE Ay3 44 29 FA 1/07 Aig COS 28 FI 1/06 NC cr6 27 FA 1/05 WE (7 26 FO 1/04 Voc 448 25 3 1/03 Vpp [9 24 FS Vss Aig 410 23 FO 1/2 Atsg CO 11 22 Pr I/O; Ay2 14 12 21 FT l/09 A7 413 20 LH Ag Ag 414 19 3 Ay As (415 18 FC Ap Ag 716 17 FT Ag TSOP Package (Reverse Pinout) OE co 32 FS Ay Aigo (O42 31 FO Ag CE cy3 30 Fr Ag VO7 cry 4 29 FO Ay3 Og HO5 28 FC A14 Os cr6 27 A NC O04 O7 26 Fr WE O03 COs 250779 Vcc Vss o9 24 17 Vpp Op (410 23 A Aig VO, CH 22 FC Ais VWOp (W112 21 Ft Ayo Ap 413 203 Az A, 4114 19 FE Ag Ap 4 15 18 FT As Ag (1416 17 FO Ag 5108 FHD F14 8-38Preliminary ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .......0.0..00000. 55C to +95C Storage Temperature .......0..0.000cc 65C to +150C Voltage on Any Pin with Respect to Ground 0.00... -2.0V to +Vcc + 2.0V Voltage on Pin Ag with Respect to Ground 00.00. 2.0V to +13.5V Vee with Respect to Ground during ProgranV/Erase ooo... -2.0V to +14.0V Vcc with Respect to Ground ooo. -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) oo. ccc eee 1.0W Lead Soldering Temperature (10 secs) Output Short Circuit Current) ooo. 100 mA RELIABILITY CHARACTERISTICS CAT28F010/CAT28F0101 *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Symbol Parameter Min. Max. Units Test Method Nenp) Endurance 1K, 10K Cycles/Byte | MIL-STD-883, Test Method 1033 Toa) Data Retention 10 Years MIL-STD-883, Test Method 1008 Vzap() ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH@M4) Latch-Up 100 mA JEDEC Standard 17 CAPACITANCE Ta = 25C, f = 1.0 MHz Limits Symbol Test Min Max. Units Conditions Cin) Input Pin Capacitance 6 pF Vin = OV Cout) Output Pin Capacitance 10 pF Vout = OV Cypp) Vpp Supply Capacitance 25 pF Vpp = 0V Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Vec +0.5V, which may overshoot to Vec + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to Voc +1V. 8-39CAT28F010/CAT28F010I Preliminary D.C. OPERATING CHARACTERISTICS CAT28F010 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT28F010I Ta = 40C to +85C, Vcc = +5V +10%, unless otherwise specified. Limits Symbol Parameter Min. Max. Unit Test Conditions lu Input Leakage Current +1.0 BA Vin = Vcc or Vss Vec = 5.5V, OE = Vin ILo Output Leakage Current +10 pA Vout = Vcc or Vss, Voc = 5.5V, OE = Vin Isp Vcc Standby Current CMOS 100 pA CE = Vcc +0.5V, Vec = 5.5V Isp2 Vec Standby Current TTL 1.0 mA CE = Vin, Voc = 5.5V lect Vcc Active Read Current 30 mA Voc = 5.5V, CE =ViuL, lout = OmA, f = 6 MHz loca) | Vec Programming Current 15 mA Vec = 55V, Programming in Progress Icca) | Vcc Erase Current 15 mA Voc = 5.5V, Erasure in Progress Icca) | Voc Prog./Erase Verify Current 15 mA Vpp = VppH, Program or Erase Verify in Progress lpps Vpp Standby Current +10 pA Vpp = Vee Ipp4 Vpp Read Current 200 pA Vpp = VpPH Ipp23) | Vep Programming Current 30 mA Vpp = VepH, Programming in Progress Ipp3) Vpp Erase Current 30 mA Vec = 5.5V, Erasure in Progress Ippa@} | Vpp Prog./Erase Verify Current 5.0 mA Vpp = Vee, Program or Erase Verify in Progress Vit input Low Level TTL -0.5 0.8 Vv Vitc Input Low Level CMOS -0.5 0.8 Vv VoL Output Low Level 0.45 V lo. = 5.8mA, Vcc = 4.5V Vin Input High Level TTL 2.0 Vect+0.5 Vv Vic Input High Level CMOS 0.7 Vec Vect+0.5 Vv VoH Output High Level TTL 2.4 Vv loH = -2.5mA, Vcc = 4.5V VoHi Output High Level CMOS 0.85 Vcc Vv lon = -2.5mA, Vcc = 4.5V Vone Output High Level CMOS Vec-0.4 Vv lon = -400nA, Vcc = 4.5V Vip Ag Signature Voltage 11.4 13.0 Vv Ag = Vip lip Ag Signature Current 200 pA Ag = Vip Vio Vcc Erase/Prog. Lockout Voltage 2.5 Vv Note: (3) This parameter is tested initially and after a design or process change that affects the parameter.Preliminary CAT28F010/CAT28F010I SUPPLY CHARACTERISTICS Limits Symbol Parameter Min Max. Unit Vec Vec Supply Voltage 45 5.5 Vv VppL Vpp During Read Operations 0 6.5 Vv VPPH Vpp During Read/Erase/Program 11.4 12.6 Vv A.C. CHARACTERISTICS, Read Operation CAT28F010 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT28F010I Ta =40C to +85C, Voc = +5V +10%, unless otherwise specified. 28F010-12 28F010-15 28F010-20 28F010I-12 28F010I-15 28F010I-20 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max.| Unit tre Read Cycie Time 120 150 200 ns tce CE Access Time 120 150 200 ns tacc Address Access Time 120 150 200 ns toe OE Access Time 50 55 60 ns toH Output Hold from Address OE/CE Change 0 0 ns toLz) | OE to Output in Low-Z ns tLzV9) CE to Output in Low-Z 0 ns tor) OE High to Output High-Z 30 35 40 ns teHaz5) | CE High to Output High-Z 55 55 55 ns twua.) Write Recovery Time Before Read 6 6 6 ys Figure 1. A.C. Testing Input/Output Waveform(6)(7)(8) 24V 2.0V INPUT PULSE LEVELS 08V 0.45V REFERENCE POINTS 5108 FHO FO3 Cy INCLUDES JIG CAPACITANCE Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER OUT TEST CL = 100 pF Note: ~ (3) This parameter is tested initially and after a design or process change that affects the parameter. (5) (6) Input Rise and Fall Times (10% to 90%) < 10 ns. (7) Input Pulse Levels = 0.45V and 2.4V. (8) Input and Output Timing Reference = 0.8V and 2.0V. (9) Output floating (High-Z) is defined as the state where the extemal data line is no longer driven by the output buffer. Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. $108 FHD Fo4 8-41CAT28F010/CAT28F010I Preliminary A.C. CHARACTERISTICS, Program/Erase Operation CAT28F010 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT28F0101 Ta = 40C to +85C, Voc = +5V +10%, unless otherwise specified. 28F010-12 28F010-15 28F010-20 28F0101-12 28F010I-15 28F010I-20 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit twc Write Cycle Time 120 150 200 ns tas Address Setup Time 0 0 0 ns taH Address Hold Time 60 60 75 ns tos Data Setup Time 50 50 50 ns tbH Data Hold Time 10 10 10 ns tcs CE Setup Time 0 0 ) ns tou CE Hold Time 0 0 0 ns twp WE Pulse Width 60 60 60 ns tweH WE High Pulse Width 20 20 20 ns twewHil!) Program Pulse Width 10 10 10 us twewn2l?) Erase Pulse Width 9.5 9.5 9.5 ms twPGL Write Recovery Time Before Read 6 6 6 ys t@HWL Read Recovery Time Before Write 0 0 0 ps tVPEL Vpp Setup Time to CE 100 100 100 ns ERASE AND PROGRAMMING PERFORMANCE(9) 28F010-12 28F010-15 28F010-20 28F0101-12 28F0101-15 28F010!-20 Parameter Min. | Typ. | Max. | Min. | Typ. | Max. } Min. | Typ. | Max.; Unit Chip Erase Time(!2)(14) 1.0 10 1.0 10 1.0 30 sec Chip Program Time2)(13) 2 12.5 2 12.5 2 12.5 sec Note: (10) Please refer to Supply characteristics for the value of Vppy and Vpp,. The Vpp supply can be either hardwired or switched. If Vpp is switched, Vpp_ can be ground, less than Vcc + 2.0V or a no connect with a resistor tied to ground. (11) Program and Erase operations are controlled by intemal stop timers. (12) Typicals are not guaranteed, but based on characterization data. Data taken at 25C, 12.0V Vpp. (13) Minimum byte programming time (excluding system overhead) is 16 ps (10 ps program + 6 1s write recovery), while maximum is 400 j1s/ byte (16 ys x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algonthm since most bytes program significantly faster than the worst case byte. (14) Excludes 00H Programming prior to Erasure. 8-42Preliminary CAT28F010/CAT28F010! FUNCTION TABLE(!5) Pins Mode CE OE WE Vep vo Notes Read Vit Vit Vin VpPL Dout Output Disable Vit Vin Vin x High-Z Standby Vin Xx X VPPL High-Z Signature (MFG) Vit Vit Vin X 31H Ao = Vit, Ag = 12V Signature (Device) Vit Vit Vin Xx B4H Ao = Vit, Ag = 12V Program/Erase ViL ViH Vit VpPH Din See Command Table Write Cycle Vit Vi Vit VpPH Din During Write Cycle Read Cycle Vit Vit Vin VpPH Dout During Write Cycle WRITE COMMAND TABLE Commands are written into the command register in one or two write cycles. The command register can be altered only when Vpp is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch addresses and data required for programming and erase operations. Pins First Bus Cycle Second Bus Cycle Mode Operation Address Din Operation Address Din Dout Set Read Write x 00H Read Any Dout Read Sig. (MFG) Write Xx 90H Read 00 31H Read Sig. (Device) Write x 90H Read 01 B4H Erase Write X 20H Write X 20H Erase Verify Write X AOH Read Xx Dour Program Write X 40H Write Ain Din Program Verify Write Xx COH Read xX Dout Reset Write xX FFH Write x FFH Note: (15) Logic Levels: X = Logic Do not care (Vin, Vit, VppL. VepH) 8-43CAT28F010/CAT28F0101 READ OPERATIONS Read Mode A Read operation is performed with both CE and OE low and with WE high. Vep can be either high or low, however, if Vep is high, the Set READ command has to be sent before reading data (see Write Operations). The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 17 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin Ag or by sending an instruction to the command register (see Write Operations). Preliminary The conventional mode is entered as a regular READ mode by driving the CE and OE pins low (with WE high), and applying the required high voltage on address pin Ag while all other address lines are held at Vi. A Read cycle from address OOOOH retrieves the binary code for the IC manufacturer on outputs |/Oo to l/O7: CATALYST Code = 00110001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs |/Oo to I/O7. 28F010/28F010I Code = 1011 0100 (B4H) Standby Mode With CE at a logic-high level, the CAT28F010/ CAT28F0101 is placed ina standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance state. Figure 3. A.C. Timing for Read Operation POWER UP STANDBY DEVICE AND ADDRESS SELECTION ADDRESSES DATA (I/O) ADDRESS STABLE tavay (RC) 'eLox oLz) (tz) tavav (acc) OUPUTS ENABLED DATA VALID STANDBY POWER DOWN 'gHaz (pF) grav oe) 'ELav (Ice) HIGH-Z OUTPUT VALID 5108 FHD FOSPreliminary CAT28F010/CAT28F010! WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Mode The device can be put into a standard READ mode by initiating a write cycle with OOH on the data bus. The subsequent read cycles will be performed similar to a standard EPROM or E2PROM Read. Signature Mode An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register while keeping Vep high. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. CATALYST Code = 00110001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/Op to I/O7. 28F010/28F0101 Code = 1011 0100 (B4H) Figure 4. A.C. Timing for Erase Operation Voc POWER-UP SETUP ERASE ERASE ERASING ERASE VERIFY ERASE V, POWER-DOWN/ & STANDBY COMMAND COMMAND COMMAND VERIFICATION STANDBY VY VV VV ARR RR ADDRESSES XOXOXXXXXOY OOK RROD h+ two two t+ twe e 'RC 4 tas mhe-mi tay CE (E) / HH be Ics >| 'cH > CH cs i _ SS OE (G) / | 1 'GHWL-P{ Hetos + 'WHWH2 > tWPHl<+> so y We) / / a | Wem <> we wel he>ltDH >|'DH tH tpsie tos tps toLZ + HIGH-Z # DATAIN DATAIN 4 DATAIN DATA(VO) z20H Po oo0H { =AOH t VALID Lz DATA OUT ce 5.0V, Vec \ ov PEL Vv Vpp PPH \ VPPL 5108 FHD F11 8-45CAT28F010/CAT28F0101 Preliminary Erase Mode During the first Write cycle, the command 20H is written into the command register. In order to commence the erase operation, the identical command of 20H has to be written again into the register. This two-step process ensures against accidental erasure of the memory con- tents. The final erase cycle will be stopped at the rising edge of WE, at which time the Erase Verify command (AOH) is sent to the command register. During this cycle, the address to be verified is sent to the address bus and latched when WE goes high. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum erase timing speci- fication. Refer to AC Characteristics (Program/Erase) for specific timing parameters. TIMING PARAMETER SYMBOLS Standard JEDEC Standard JEDEC tas tavwe {iz tELax taH tWLAXx toe tatav tce teLav toLz teLax tcH tWHEH tac tavayv tcs TELWL twc tavav toF taHaz twp tWLWH {DH twHDx twPH tWHWL tos tovWH 8-46Preliminary CAT28F010/CAT28F010I Figure 5. Chip Erase Algorithm(1) START ERASURE Bue yay] COMMAND COMMENTS OPERATION APPLY Vppy Vpp RAMPS TO Vppy (OR Vpp HARDWIRED) = 1 aL ALL BYTES SHALL BE PROGRAMMED TO 00 BYTES TO 00H STANDBY BEFORE AN ERASE | OPERATION INITIALIZE ADDRESS INITIALIZE ADDRESS INITIALIZE PLSCNT =0 PLSCNT = PULSE COUNT : ACTUAL ERASE WRITE ERASE WRITE ERASE NEEDS 10ms PULSE, SETUP COMMAND DATA. 20H WAITE ERASE COMMAND WRITE ERASE DATA = 20H TIME OUT toms WAIT = Vv WRITE ERASE WRITE ERASE see tA on ERIFY VERIFY COMMAND VERIFY | crops ERASE OPERATION TIME OUT 6s WAIT INCREMENT | ADDRESS READ DATA READ READ BYTE TO FROM DEVICE VERIFY ERASURE NO INC PLSCNT STANDBY COMPARE OUTPUT TO FF 00 ? INCREMENT PULSE COUNT YES LAST ADDRESS? DATA=00H MOOMMANDS WRITE READ RESETS THE REGISTER | FOR READ OPERATION Vpp RAMPS TO V PP PPL APPLY Vpp,_ APPLY Vpp.. STANOBY (OR Vpp HARDWIRED) ERASE ERROR $108 FHD F10 ERASURE COMPLETED L Note: (16) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. 8-47CAT28F010/CAT28F0101 Preliminary Erase-Verify Mode The Erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. Programming Mode The programming operation ts initiated using the pro- gramming algorithm of Figure 7. During the first write cycle, the command 40H is written into the command register. During the second write cycle, the address of the memory location to be programmed is latched on the falling edge of WE, while the data is latched on the rising edge of WE. The program operation terminates with the next rising edge of WE. An integrated stop timer allows for automatic timing control over this operation, eliminat- ing the need for a maximum program timing specifica- tion. Refer to AC Characteristics (Program/Erase) for specific timing parameters. Figure 6. A.C. Timing for Programming Operation Vec POWER-UP SETUP PROGRAM LATCH ADDRESS & STANDBY COMMAND & DATA ADDRESSES XM PROGRAMMIN PROGRAM PROGRAM = Vcc POWER-DOWN/ VERIFY VERIFICATION STANDBY G COMMAND EI te tywo+1 twe tas bert taH - CE (E) / Nf VL #t tos >| tem 'EHOZ 'cH >| \ OE (G) / | / \ 'GHWL-P +i} cs WHWH1 >i'WHGL->) hee 'OF 'WPH _. r \ f 7 y 5% WE (W) / / \ /\ NY ff LL Lined twp WP }-> oe > het > |'DH DH tos} tos bem tose toLz>| HIGH-Z "1 DATAWO) of DATAIN b4 DATAIN ton | VALID Lz DATA OUT CE 5.0V Voc / \ ov VPEL Vv \ Vpp pray VPPL 106 FAO FO7 8-48Preliminary Program-Verify Mode A Program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Program- CAT28F010/CAT28F010I verify operation is initiated by writing COH into the command register. An intemal reference generates the necessary high voltages so that the user does not need to modify Vcc. Refer to AC Characteristics (Program/ Erase) for specific timing parameters. TIMING PARAMETER SYMBOLS Standard JEDEC Standard JEDEC tas tavwe tLz teLax taH tWLAX toe tarav tceE teLav toiz taLax tcH tWHEH tre tavav tcs tELWL twe tavav tor taHaz twe tWLWH tDH tWHDXx twPH tWHWL tos tovwH 8-49CAT28F010/CAT28F010I Preliminary Figure 7. Programming Algorithm('6) START BUS PROGRAMMING OPERATION | COMMAND COMMENTS APPLY VppH STANDBY Vpp RAMPS TO VppH (OR Vpp HARDWIRED) INITIALIZE ADDRESS INITIALIZE ADDRESS PLSCNT =0 INITIALIZE PULSE COUNT PLSCNT = PULSE COUNT WRITE SETUP 1ST WRITE WRITE PROG. COMMAND CYCLE SETUP DATA = 40H WRITE PROG. CMD 2ND WRITE ADDR AND DATA CYCLE. | PROGRAM | VALID ADDRESS AND DATA TIME OUT 10ps WAIT WRITE PROGRAM 1ST WRITE | PROGRAM VERIFY COMMAND CYCLE VERIFY DATA = COH TIME OUT 6s WAIT READ DATA READ READ BYTE TO VERIFY FROM DEVICE PROGRAMMING NO VERIFY INC COMPARE DATA OUTPUT DATA? ae STANDBY TO DATA EXPECTED YES INCREMENT LAST ADDRESS ADDRESS? DATA=00H WRITE READ 1STWRITE | pea~D | SETSTHE REGISTERFOR COMMAND CYCLE READ OPERATION APPLY Vpp,. APPLY Vpp,_ STANDBY Vpp RAMPS TO Vppi (OR Vpp HARDWIRED) PROGRAMMING PROGRAM COMPLETED ERROR Note: (16) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. $108 FHD Foe 8-50Preliminary CAT28F010/CAT28F010I Abort/Reset An Abort/Reset command is available to allow the user reset operation can interrupt at any time in a program or to safely abort an erase or program sequence. Two erase operation and the device is reset to the Read consecutive program cycles with FFH on the data bus Mode. will abort an erase or a program operation. The abort/ Figure 8. Alternate A.C. Timing for Program Operation Voc POWER-UP SETUP PROGRAM LATCH ADDRESS PROGRAM PROGRAM = Voc POWER-DOWN/ & STANDBY COMMAND & DATA VERIFY VERIFICATION STANDBY PROGRAMMING COMMAND }e to p<1 two tAVEL > 'ELAX | tWLEL >| be teHWH le 'WLEL ee EHWH be! tEHOZ tEHWH > _.WLEL a ke aes vy y OE (G) / NK VI \ tGHEL >{ 'EHEH EHGL > bey toe tEHEL > : q p-4, y OF y cE) =f \ / YA yf KN YT \. 'ELEH > mH tELEH tELEH +> toe > hem EDX | ke teEHDx a+ >| EHDX >| befox tDVEH/+> le tOVEH tbvEH oLz HIGH-Z DATA IN f 1 _DATAIN DATA (I/O) L cao pk CDATAIN =COH 4 4 _ tz VAI DATA OUT ce > OV Veco YL ov >| VPEL Vpp VPPH J \ VPPL $18 FHD FCG 8-51CAT28F010/CAT28F010I Pretiminary POWER UP/DOWN PROTECTION The CAT28F010/CAT28F010I offers protection against inadvertent programming during Vep and Vcc power transitions. When powering up the device there is no power-on sequencing necessary. In other words, Vpp and Vcc may power up in any order. Additionally Vpp may be hardwired to VppH independent of the state of Vcc and any power up/down cycling. The internal com- mand register of the CAT28F010/CAT28F0101I is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1uF ceramic capacitor between Vcc and Vss and Vpp and Vss. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. TIMING PARAMETER SYMBOLS Standard JEDEC two tavav toLz teLax tiz teLax tce teLav {DE teLav tor tGHaz 8-52Preliminary CAT28F010/CAT28F010I ALTERNATE CE-CONTROLLED WRITES 28F010-12 28F010-15 28F010-20 28F0101-12 28F0101-15 28F0101-20 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit tavav Write Cycle Time 120 150 200 ns tAVEL Address Setup Time 0 0 0 ns tELAx Address Hold Time 80 80 95 ns tDVEH Data Setup Time 50 50 50 ns teHDx Data Hold Time 10 10 10 ns tEHGL Write Recovery Time Before Read 6 6 6 Us tGHEL Read Recovery Time Before Write 0 0 0 Ls tWLeL WE Setup Time Before CE 0 ) 0 ns teEHWH Write Enable Hold Time 0 0 0 ns teLeH Write Pulse Width 70 70 80 ns tEHEL Write Pulse Width High 20 20 20 ns {vPEL Vpp Setup Time to CE Low 1.0 1.0 1.0 us