MC10H131P - ON Semiconductor

 Semiconductor Components Industries, LLC, 2003

October, 2003 − Rev. 8 1Publication Order Number:

AN1568/D

Interfacing Between LVDS

and ECL

Prepared by: Paul Lee

Logic Applications Engineer

ON Semiconductor

Introduction

Recent growth in high−speed data transmission between

high−speed ICs demand more bandwidth than ever before

while still maintaining high performance, low power

consumption and good noise immunity. Emitter Coupled

Logic (ECL) recognized the challenge and provided high

performance and good noise immune devices. ECL

migrated toward low voltages to reduce the power

consumption and to keep up with current technology trends

by offering 3.3 V and 2.5 V Low Voltage ECL (LVECL)

devices.

LVDS (Low Voltage Differential Signaling) technology

also addresses the needs of current high performance

applications. LVDS as specified in ANSI/TIA/EIA−644 by

Data Transmission Interface committee TR30.2 and IEEE

1596.3 SCI−LVDS by IEEE Scalable Coherent Interface

standard (SCI) is a high speed, low power interface that is a

solution in many application areas. LVDS provides an

output swing of 250 mV to 400 mV with a DC of fset of 1.2 V.

External resistor components are required for

board−to−board data transfer or clock distribution.

LVECL and LVDS are both differential voltage signals,

but with different output amplitude and offset. The purpose

of this documentation is to show the interfacing between

LVECL and LVDS. In addition, it gives interface

recommendations t o and from 5.0 V supplied PECL devices

and negative supplied ECL or NECL

ECL levels

Today’s applications typically use ECL devices in the

PECL mode. PECL (Positive ECL) is nothing more than

supplying any ECL device with a positive power supply

(VCC = +5.0 V, VEE = 0 V). In addition, ECL uses differential

data transmission technology, which results in better noise

immunity. Since the common mode noise is coupled onto the

differential interconnect, it will be seen as a common mode

modulation and will be rejected.

With the trend towards low voltage systems, a new

generation of ECL circuitry has been developed. The Low

Voltage NECL (LVNECL) devices work using negative

–3.3 V or –2.5 V power supply, or more popular positive

power supplies, VCC = +3.3 V or +2.5 V and VEE = GND as

LVPECL. LVECL maintains 750 mV output swing with a

0.9 V o f fset from VCC, which makes them ideal as peripheral

components.

The temperature compensated (100EL, 100LVEL,

100EP, 100LVEP) output DC levels for the different supply

levels are shown in Table 1. ECL outputs are designed as an

open emitter, requiring a DC path to a more negative supply

than VOL. (see AND8020 for ECL Termination

information).

ECL standard DC input levels are also relative to VCC.

Many devices are available with Voltage Input HIGH

Common Mode Range (VIHCMR). These differential inputs

allow processing signals with small VINPPMIN (down to

200 mV, 150 mV or even 50 mV signal levels) within an

appropriate offset range. The VIHCMR ranges of ECL

devices are listed in each respective data sheets.

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Table 1. MC100EXXX/MC100ELXXX/LVELXXX/EPXXX/LVEPXXX (TA = 0°C to +85°C)

Symbol Parameter 2.5 V LVPECL

(Note 1) 3.3 V LVPECL

(Note 1) 5.0 V PECL

(Note 1) NECL Unit

VCC Positive Supply Voltage +2.5 +3.3 +5 GND V

VEE Negative Supply Voltage GND GND GND −5.2, −4.5, −3.3 or −2.5 V

VOH Maximum Output HIGH Level 1.680 2.480 4.180 −0.820 V

VOH Typical Output HIGH Level 1.555 2.355 4.055 −0.945 V

VOH Minimum Output HIGH Level 1.430 2.230 3.930 −1.070 V

VOL Maximum Output LOW Level 0.880 1.680 3.380 −1.620 V

VOL Typical Output LOW Level 0.755 1.555 3.255 −1.745 V

VOL Minimum Output LOW Level 0.630 1.430 3.130 −1.870 V

1. All levels vary 1:1 with VCC and loaded with 50  to VCC − 2.0 V.

LVDS Levels

As the name indicates, the LVDS main attribute is the low

voltage amplitude levels compared to other data

transmission standards, as shown in Figure 1. The LVDS

specification states 250 mV to 400 mV output swing for

driver/transmitter (VOUTPP). The low voltage swing levels

result in low power consumption while maintaining high

performance levels required by most users. In addition,

LVDS uses differential data transmission technology

equivalent to ECL. Furthermore, LVDS technology is not

dependent on specific power supply levels like ECL

technology. This signifies an easy migration path to lower

supply voltages such as 3.3 V, 2.5 V, or lower voltages while

still maintaining the same signaling levels and high

performance. ON Semiconductor currently provides a 2.5 V

1:5 dual differential LVDS Clock Driver/Receiver

(MC100EP210S).

Figure 1. Comparison of Output Voltage Levels

Standards (Figure not to Scale)

PECL

3.3 V LVPECL

NECL/LVNECL

LVDS

2.5 V LVPECL 3.3 V LVTTL/LVCMOS

SIGNAL VOLTAGE

LVDS require a 100 load resistor between the

differential outputs to generate the Differential Output

Voltage (VOD) with a maximum current of 2.5 mA flowing

through the load resistor. This load resistor will terminate the

50  controlled characteristic impedance line, which

prevent reflections and reduces unwanted electromagnetic

emission (Figure 2).

Figure 2. LVDS Output Definition

LVDS

Z = 50 

Z = 50 100 

LVDS receivers require 200 mV minimum input swing

within the input voltage range of 0 V to 2.4 V and can tolerate

a minimum of 1.0 V ground shift between the driver’s

ground and the receiver’s ground, since LVDS receivers

have a typical driver offset voltage of 1.2 V. The common

mode range of the LVDS receiver is 0.2 V to 2.2 V, and the

recommended LVDS receiver input voltage range is from

0 V to 2.4 V. Common mode range of LVDS is similar to the

theory of Voltage Input HIGH Common Mode Range

(VIHCMR) of ECL devices.

Currently more LVDS standards are being developed as

LVDS technology gains in popularity.

BLVDS

Bus LVDS (BLVDS) was developed for multipoint

applications. This standard is ta r geted at heavily loaded back

planes, which reduces the impedance of the transmission

line by 50% or more. By providing increased drive current,

the double termination seen by the driver will be

compensated.

M−LVDS

TIA TR30.2 standards group is developing another

multipoint LVDS application called Multipoint LVDS

(M−LVDS). The maximum data rate is 500 Mbps.

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GLVDS and SLVS

Ground referenced LVDS (GLVDS) is similar to LVDS

except the driver output voltage offset is nearer to ground.

The advantage of GLVDS is the use of very low power

supply voltages (0.5 V).

Similar standard to GLVDS is SLVS (Scalable

Low−Voltage Signaling for 400 mV) by JEDEC. The

interface is terminated to ground with 400mV swing and a

minimum supply voltage of 0.8 V.

LVDM

LVDM is designed for double 100 −terminated

applications. The driver’s output current is two times the

standard LVDS, thus producing LVDS characteristic levels.

Interfacing

Common mode range inputs are capable of processing

signals with 150 mV to 400 mV amplitude. The ECL input

processes signals up to 1.0 V amplitude. The DC voltage

levels should be within the voltage input HIGH common

mode range (VIHCMR).

To interface between these two voltage levels, capacitive

coupling can be used. Only clock or coded signals should be

capacitively coupled. A capacitive coupling of NRZ signals

will cause problems, which can require a passive or active

interfacing.

Table 2. LVDS LEVELS

LVDS

Specification BLVDS

Specification M−LVDS

Specification GLVDS

Specification LVDM

Specification

Symbol Parameter Min Max Min Max Min Max Min Max Min Max Unit Condition

Transmitter

VPP Output Differen-

tial Voltage 250 400 240 500 480 650 150 500 247 454 mV

VOS Output Offset

Voltage 1125 1275 1225 1375 300 2100 75 250 1.125 mV

RLLoad Resistor 100 27 50 50 Internal To Rx 50 

IOD Output Differen-

tial Current 2.5 4.5 9 17 9 13 Adjustable 6 mA

Receiver

Input Voltage

Range 0 2400 0 2400 −1000 3800 −500 1000 0 2400 MV Vgpd < 950 mV

(Note 2)

Differential HIGH

Input Threshold +100 +100 +50 +100 +100 mV Vgpd < 950 mV

(Note 2)

Differential LOW

Input Threshold −100 −100 −50 −100 −100 mV Vgpd < 950 mV

(Note 2)

2. Vgpd is the voltage of Ground Potential Delta across or between boards.

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Capacitive Coupling LVDS to ECL

Capacitive Coupling LVDS to ECL Using V BB

Several ECL devices provide an externally accessible

VBB (VBB ≈ V

CC –1.3V) reference voltage. This ECL

reference voltage can be used for differential capacitive

coupling. The 10 nF capacitor can be used to decouple V BB

to GND. (Figure 3)

Figure 3. Capacitive Coupling LVDS to ECL

Using VBB

LVDS

Z = 50 

Z = 50 100 ECL

1 k1 k

VBB

10 nF

10 pF

Capacitive Coupling LVDS to ECL with External

Biasing

If VBB reference voltage is not available, equivalent DC

voltage can be generated using a resistor divider network.

The resistor values depend on VCC and VEE voltages

(Table 3). Stability is enhanced during null signal conditions

if a 50 mV differential voltage is maintained between the

divider networks. (Figure 4)

Table 3. Examples:

VCC = GND VEE = −5.0 V R1 = 1.2 kR2 = 3.4 k

VCC = GND VEE = −3.3 V R1 = 680 R2 = 1.0 k

VCC = GND VEE = −2.5 V R1 = 100 R2 = 90 

Figure 4. Capacitive Coupling LVDS to ECL with

External Biasing

LVDS

Z = 50 

Z = 50 100 ECL

R2R2

10 pF

VCC

VEE

In the layout for both interfaces, the resistors and the

capacitors should be located as close as possible to the ECL

input to insure reduced reflection and increased signal

integrity.

Capacitive Coupling ECL to LVDS

The ECL output requires a DC current path to VEE;

therefore, the pulldown termination resistors, RT, are

connected to VEE. The Thevenin resistor pair represent the

termination of the transmission line Z = R1 || R2 and

generates an appropriate DC offset level of 1.2 V. (Figure 5)

Figure 5. Capacitive Coupling ECL to LVDS

Z = 50 

ECL

130 

10 pF

130 

3.3 V

VEE

80 

LVDS

An example of capacitive coupled LVPECL

(ECLinPS Plus Device) to LVDS is shown below.

(Figure 6)

Figure 6. Capacitive Coupling LVPECL to LVDS

43 

LVPECL

237 

3.9 k

3.3 V

2 k

LVDS

3.3 V2.5 V or 3.3 V

43 

10 pF

Capacitive Coupling ECL to LVDS Using VOS

Reference Voltage

Some LVDS devices supply external offset reference

voltage (VOS), which can be used for capacitive coupling.

When the transmission line is very short, a parallel

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termination should be used and placed as close as possible

to the coupling capacitors. (Figure 7)

Figure 7. Capacitive Coupling ECL to LVDS Using

VOS Reference Voltage

Z = 50 

ECL

1 k

100 k

VOS=

1.2 V

10 pF

3.3 V

50 

VTT

LVDS

Direct Interfacing

Interfacing from 2.5 V LVPECL to LVDS

Provided that the LVDS receiver can tolerate large input

voltage peak to peak amplitude, 2.5 V LVPECL can be

directly interfaced to LVDS receiver using proper ECL

termination. 2.5 V LVPECL will be able to drive LVDS

receiver with and without internal 100  termination

resistor. (See Figures 8, 9 and 10).

Figure 8. Interfacing 2.5 V LVPECL to LVDS with

External 100  Termination Resistor

100 

LVPECL

2.5 V VCC

RTRT

LVDS

Figure 9. Interfacing 2.5 V LVPECL to LVDS with

Internal 100  Termination Resistor

100 

LVPECL

2.5 V VCC

RTRT

LVDS

Figure 10. PSPICE Simulation Levels of 2.5V LVPECL

to LVDS Interface with Example Resistor Values

1.50 V

0.78 V

720 mV LVDS

Input

2.5 V LVPECL

Output

Where RT = 75 

Furthermore, sreies termination can be used to reduce the

amplitude of the signal as described in AND8020

application note, by placing RS resistor between the driver

and the transmission line. (See Figures 11, 12 and 13).

Figure 11. Interfacing 2.5 V LVPECL to LVDS with

Series RS and External 100  Termination Resistor

100 

LVPECL

2.5 V VCC

RTRT

LVDS

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Figure 12. Interfacing 2.5 V LVPECL to LVDS with

Series RS and Internal 100  Termination Resistor

100 

LVPECL

2.5 V VCC

RTRT

LVDS

Figure 13. PSPICE Simulation Levels of 2.5V LVPECL

to LVDS Interface with Series RS Resistor

1.30 V

0.87 V

430 mV LVDS

Input

2.5 V LVPECL

Output

Where RT = 75 

RS = 43 

Interfacing from 3.3 V LVPECL to LVDS

Since the output levels VOH and VOL of 3.3 V LVPECL

are more positive than the input range of LVDS receiver,

special interface is required. (See Figures 14 and 15).

Furthermore, the open emitter design of the ECL output

structure need proper termination, which can be

incorporated with the resistor divider network to generate a

proper LVDS DC levels (eq. 1).

R1R2RT(eq. 1)

The resistor divider network will divide the output

common mode voltage of LVPECL (VCM(LVPECL)) to

input common mode voltage of LVDS (VCM(LVDS)).

R1R2VCM(LVDS)

VCM(LVPECL) (eq. 2)

Where:

RT = Termination Resistor

VCM(LVPECL) = Common Mode Voltage

VCM(LVDS) = Common Mode Voltage

3.3 V LVPECL will be able to drive LVDS receiver with

and without internal 100  termination resistor. The above

equations may give non−standard resistor values and when

choosing resistors off the shelf, to avoid cutoff condition

under worst−case scenario.

Figure 14. Interfacing 3.3 V LVPECL to LVDS

LVPECL

LVDS

3.3 V

VCC

R1 R1

R2R2

ZOZO

ZO100 

Figure 15. Interfacing LVPECL to LVDS with Internal

100  Termination Resistor

LVPECL

LVDS

3.3 V

VCC

R1 R1

R2R2

100 

ZOZO

Examples:

For 50  controlled impedance, the resistor values for

3.3V LVPECL converted to LVDS voltage levels are as

follows:

R1 = 55 

R2 = 95 

RT = 150 

VCM(LVPECL) = 1.9 V

VCM(LVDS) = 1.2 V

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Figure 16. PSPICE Simulated Voltage Levels of

3.3 V LVPECL to LVDS Interface with Example

Resistor Values

1.07 V

1.39 V

2.37 V

1.52 V

850 mV

320 mV

LVDS3.3 V LVPECL

VCM(LVPECL)

VCM(LVDS)

Interfacing from LVDS to LVPECL

The input common mode range of the low voltage ECL

line receivers are wide enough to process LVDS signals.

(Figure 17)

Figure 17. Interfacing LVDS to LVPECL

LVDS

Z = 50 

Z = 50 100 LVPECL

3.3 V 2.5 V or 3.3 V

This direct interface is possible for all ECL devices with

sufficiently low minimum differential input HIGH common

mode range inputs. A differentially operated receiver’s

VIHCMR minimum must be 1.2 V or less (see device data

sheet).

Table 4. LVDS Input Compatible Devices

EP14 LVEP210S LVEL37 EL56

EP809 LVE222 LVEL39 EL91

LVEP11 LVEL05 LVEL40 SG11

LVEP14 LVEL11 LVEL51 SG14

LVEP16 LVEL13 LVEL56 SG16

LVEP17 LVEL14 LVEL92 SG16M

LVEP34 LVEL16 EL13 SG16VS

LVEP56 LVEL17 EL14 SG53A

LVEP91 LVEL29 EL17 SG72A

LVEP111 LVEL32 EL29 SG86A

LVEP210 LVEL33 EL39 SG111

Interfacing from PECL to LVDS

Since the output levels VOH and VOL of 5 V PECL are

more positive than the input range of LVDS receiver, special

interface i s required. (See Figure 18). Furthermore, the open

emitter design of the ECL output structure need proper

termination, which can be incorporated with the resistor

divider network to generate a proper LVDS DC levels (eq.

3).

R1R2RT(eq. 3)

The resistor divider network will divide the output

common mode voltage of PECL (VCM(PECL)) to input

common mode voltage of LVDS (VCM(LVDS)).

R1R2VCM(LVDS)

VCM(PECL) (eq. 4)

Where:

RT = Termination Resistor

VCM(PECL) = Common Mode Voltage

VCM(LVDS) = Common Mode Voltage

The above equations may give non—standard resistor

values and when choosing resistors off the shelf, to avoid

cutoff condition under worst−case scenario.

Figure 18. Interfacing 5 V PECL to LVDS

PECL

LVDS

5 V

VCC

R1 R1

R2R2

ZOZO

Examples:

For 5 0  controlled impedance, the resistor values for 5V

PECL converted to LVDS voltage levels are as follows:

R1 = 134 

R2 = 66 

RT = 200 

VCM(PECL) = 3.65 V

VCM(LVDS) = 1.2 V

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Figure 19. PSPICE Simulated Voltage Levels of

5 V PECL to LVDS Interface with Example Resistor

Values

1.07 V

1.34 V

4.05 V

3.25 V

800 mV

270 mV

LVDS5 V PECL

VCM(PECL)

VCM(LVDS)

Interfacing from +3.3 V LVDS to +5.0 V PECL

To translate LVDS signals to PECL a differential ECL

device with extended common mode range inputs (See

Table 4) can be used to process and translate LVDS signals

when supplied with 5.0 V  5% supply voltage.

(See Figure 20)

Figure 20. Interfacing LVDS to PECL

5 V

LVDS

Z = 50 

Z = 50 100 PECL

3.3 V

RTRT

Interfacing Between NECL to LVDS

ON Semiconductor has developed level translators to

interface between the different voltage levels. The

MC100EP90 translates from negative supplied ECL to

LVPECL. The interface from LVPECL to LVDS inputs is

described above. (Figure 21)

Figure 21. Interfacing from NECL to LVDS

NECL MC100EL90

MC100EP90

LVPECL

Interface

LVPECL to

LVDS LVDS

3.3 V

LVPECL

−3.3 V, −4.5 V

or −5.2 V

−3.3 V, −4.5 V

or −5.2 V

GND

RTRT

To interface from LVDS to negative supplied ECL the

common mode range (VIHCMR) of the MC100LVEL91 for

–3.3 V supply and the MC100EL91 for –4.5 V/–5.2 V

supply is wide enough to process LVDS signals.

(See Figure 22)

If VCC = +5 V  5% supply and a VEE = –5.2 V ± 5%

supply is available the MC10E1651 can be used.

3.3 V

Figure 22. Interfacing from LVDS to NECL

LVDS

Z = 50 

Z = 50 100 LVEL91

LVEP91

3.3 V

LVEL91: −3.3 V,

EL91: −4.5 V, −5.2 V

NECL

GND

RTRT

−3.3 V, −4.5 V, or −5.2 V

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Notes

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