12-Bit, 400 MSPS A/D Converter AD12400 FUNCTIONAL BLOCK DIAGRAM FEATURES DATA READY A AD12400 ADC A CLK DISTRIBUTION DA0-DA11 POSTPROCESSING AIN ADC B APPLICATIONS Communications test equipment Radar and satellite subsystems Phased array antennas--digital beam Multichannel, multimode receivers Secure communications Wireless and wired broadband communications Wideband carrier frequency systems CLOCK DISTRIBUTION DIVIDE BY 2 ENC DB0-DB11 DATA READY B ENC 03735-0-001 400 MSPS sample rate SNR of 63 dBFS @128 MHz SFDR of 70 dBFS @128 MHz VSWR of 1:1.5 Wideband ac-coupled input signal conditioning Enhanced spurious-free dynamic range Single-ended or differential encode signal LVDS output levels Twos complement output data Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD12400 is a 12-bit analog-to-digital converter (ADC) with a transformer-coupled analog input and digital postprocessing for enhanced SFDR. The product operates at a 400 MSPS conversion rate with outstanding dynamic performance in wideband carrier systems. 1. Guaranteed sample rate of 400 MSPS. 2. Input signal conditioning with optimized dynamic performance to 180 MHz. 3. Additional performance options available; contact factory. The AD12400 requires 3.8 V analog, 3.3 V digital, and 1.5 V digital supplies, and provides a flexible encode signal that can be differential or single-ended. No external reference is required. 4. Proprietary Advanced Filter Bank (AFBTM) digital postprocessing from V Corp Technologies, Inc. The AD12400 package style is an enclosed 2.9" x 2.6" x 0.6" module. Performance is rated over a 0C to 60C case temperature range. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005 Analog Devices, Inc. All rights reserved. AD12400 TABLE OF CONTENTS Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 13 Time-Interleaving ADCs........................................................... 13 Analog Input ............................................................................... 13 Clock Input.................................................................................. 13 Digital Outputs ........................................................................... 14 Power Supplies............................................................................ 14 Start-Up and RESET .................................................................. 14 LEAD/LAG ................................................................................. 14 Thermal Considerations............................................................ 14 Package Integrity/Mounting Guidelines ................................. 15 AD12400 Evaluation Kit ........................................................... 16 Layout Guidelines........................................................................... 21 PCB Interface .............................................................................. 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 6/05--Rev. 0 to Rev. A Changes to Table 2............................................................................ 4 Changes to Figure 3.......................................................................... 6 Changes to Table 5............................................................................ 6 Renamed Definition of Specifications Section to Terminology Section ........................................................................ 9 Changes to LEAD/LAG Section ................................................... 14 Changes to Ordering Guide .......................................................... 22 11/03--Revision 0: Initial Version Rev. A | Page 2 of 24 AD12400 SPECIFICATIONS DC SPECIFICATIONS VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0C TCASE 60C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error @ 10 MHz Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Gain Error ANALOG INPUT (AIN) Full-Scale Input Voltage Range Frequency Range Flatness (10 MHz to 180 MHz) Input VSWR (50 ) (10 MHz to 180 MHz) Analog Input Bandwidth POWER SUPPLY 1 Supply Voltage VA VC VD Supply Current IVA (VA = 3.8 V) IVC (VC = 3.3 V) IVD (VD = 1.5 V) Total Power Dissipation ENCODE INPUTS 2 Differential Inputs (ENC, ENC) Input Voltage Range Input Resistance Input Capacitance Common-Mode Voltage Single-Ended Inputs (ENC) Input Voltage Input Resistance LOGIC INPUTS (RESET) 3 Logic 1 Voltage Logic 0 Voltage Source IIH Source IIL LOGIC OUTPUTS (DRA, DRB, Output Bits) 4 Differential Output Voltage Output Drive Current Output Common-Mode Voltage Start-Up Time Case Temp Test Level Min Full Full Full 60C 60C IV I I V V 60C V 60C Full Full 60C V IV IV V 60C V Full Full Full IV IV IV Full Full Full Full I I I I Full 60C 60C 60C IV V V V 0.4 Full 60C IV V 0.4 Full Full 60C 60C IV IV V V 2.0 Full Full Full Full IV IV IV IV 247 -4 1.125 AD12400JWS Typ 12 Max Min Guaranteed -12 -10 AD12400KWS Typ Max 12 Unit Bits Guaranteed +12 +10 -12 -10 0.3 0.5 0.3 0.5 LSB %FS LSB LSB 0.02 0.02 %/C 3.2 10 0.5 1.5 3.2 180 1 10 0.5 1.5 450 3.6 3.2 1.475 180 1 450 3.8 3.4 1.575 0.95 400 1.4 7.0 +12 +10 3.6 3.2 1.475 1.11 500 2.0 8.5 0.95 400 1.4 7.0 MHz 3.8 3.4 1.575 V V V 1.11 500 2.0 8.5 A mA A W 0.4 100 4 3 2 50 V pF V 100 4 3 2.5 0.4 2 50 2.5 2.0 0.8 0.8 10 1 10 1 454 +4 1.375 600 1 Tested using input frequency of 70 MHz. See Figure 17 for VD current vs. input frequency. All ac specifications tested by driving ENC single-ended. Refer to Table 5 for logic convention on all logic inputs. 4 Digital output logic levels: VC = 3.3 V, CLOAD = 8 pF. 3.3 V LVDS, R1 = 100 . 2 3 Rev. A | Page 3 of 24 247 -4 1.125 454 +4 1.375 600 V p-p MHz dB V p-p V V A mA mV mA V ms AD12400 AC SPECIFICATIONS 1 VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0C TCASE 60C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE 2 SNR Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz SINAD 3 Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz Spurious-Free Dynamic Range3 Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz Image Spur 4 Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz Offset Spur4 Analog Input @ -1.0 dBFS Two-Tone IMD 5 F1, F2 @ -6 dBFS SWITCHING SPECIFICATIONS Conversion Rate 6 Encode Pulse Width High (tEH)1 Encode Pulse Width Low (tEL)1 DIGITAL OUTPUT PARAMETERS Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DR Propagation Delay (tEDR) Data to DR Skew (tEDR - tPD) Pipeline Latency 7 Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) AD12400JWS Min Typ Max AD12400KWS Min Typ Max Case Temp Test Level Full Full Full Full I I I I 62 61.5 60 60 64.4 64 63.5 62.5 62 61.5 60 60 64.4 64 63.5 62.5 dBFS dBFS dBFS dBFS Full Full Full Full I I I I 61 60.5 59 57 64 64 62.5 61 61 60.5 59 57 64 64 62.5 61 dBFS dBFS dBFS dBFS Full Full Full Full I I I I 69 69 67 62 80 84 76 71 69 69 67 62 80 84 76 71 dBFS dBFS dBFS dBFS Full Full Full Full I I I I 60 60 56 54 75 72 70 70 62 62 62 62 75 72 70 70 dBFS dBFS dBFS dBFS 60C V 65 65 dBFS 60C V -75 -75 dBc Full 60C 60C IV V V 396 400 1.25 1.25 404 396 400 1.25 1.25 404 MSPS ns ns Full 60C 60C 60C 60C 60C Full 60C 60C IV V V V V V IV 1.9 2.4 1.20 1 1 3.88 2.68 74 1.6 0.4 3.1 1.9 2.4 1.20 1 1 3.88 2.68 74 1.6 0.4 3.1 ns ns ns ns ns ns Cycles ns ps rms IV V 1 Unit All ac specifications tested with a single-ended, 2.0 V p-p encode. Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz. Not including image spur. 4 The image spur is at fs/2 - AIN; the offset spur is at fs/2. 5 F1 = 70 MHz, F2 = 73 MHz. 6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design for encode 400 MSPS 1%. 7 Pipeline latency is exactly 74 cycles. 2 3 Rev. A | Page 4 of 24 AD12400 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter VA to AGND VC to DGND VD to DGND Analog Input Voltage Analog Input Power Encode Input Voltage Encode Input Power Logic Inputs and Outputs to DGND Storage Temperature Range, Ambient Operating Temperature Value 5V 4V 1.65 V 6 V (dc) 18 dBm (ac) 6 V (dc) 12 dBm (ac) 5V -65C to +150C 0C to 60C ESD CAUTION EXPLANATION OF TEST LEVELS Level I II III IV V VI Description 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. Rev. A | Page 5 of 24 ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. AD12400 Table 4. Output Coding (Twos Complement) AIN (V) +1.6 . . . 0 -0.000781 . . -1.6 Table 5. Option Pin List with Necessary Associated Circuitry Digital Output 0111 1111 1111 . . . 0000 0000 0000 1111 1111 1111 . . 1000 0000 0000 Active High or Low Low Low Pin Name RESET LEAD/LAG Logic Level Type LVTTL LVTTL Associated Circuitry Within Part 3.74 k Pull-Up Default Level High High 3.3V 100 ENC 3.3V 100 100 PECL DRIVER 03735-0-003 ENC 100 Figure 2. Encode Equivalent Circuit N-1 N N+1 N+2 N+3 tEL tEH 1/fS ENC 400MHZ 74 CLOCK CYCLES N - 74 DATA OUT A 1 N N - 73 N+2 N+4 N+6 N+8 DRA DRA 1 N+1 DATA OUT B N+3 N+5 N+7 DRB DRB NOTES 1. DATA LOST DUE TO ASSERTION OF LEAD/LAG. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID. 2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS THE 50% POINT AND APPLY THE SAME TIMING INFORMATION. 3. THE LEAD/LAG PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES. THE LEAD/LAG PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12400. IF APPLIED ASYNCHRONOUSLY, LEAD/LAG MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION. THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE LEAD/LAG PIN IS SET HIGH AGAIN. DRA AND DRB RESUME ON THE NEXT VALID DRA AFTER LEAD/LAG IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS PIN TO 3.3V THROUGH A 3.74k RESISTOR. Figure 3. Timing Diagram tPD ENC ENC DATA OUT DR DR tV Figure 4. Highlighted Timing Diagram Rev. A | Page 6 of 24 03735-0-002 LEAD LAG 03735-0-004 Code 4095 . . . 2048 2047 . . 0 AD12400 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 119 ENC ENC TOP VIEW VA VA VA VA AGND AGND DNC DNC DNC DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND AGND JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821 PIN 79 2-56 STUDS 4x END VIEW SAMTEC CONNECTOR QTE-060-01-L-D-A-K-TR BOARD ENC ENC PIN 39 AIN BOTTOM VIEW LEFT SIDE VIEW 1INTEGRAL GROUND PLANE CONNECTIONS. NOTES 1. FOR MATING HALF, USE SAMTEC, INC. SECTION A = DGND, PINS 121-124. PART NO. QSE-60-01-L-D-A-K. SECTION B = DGND, PINS 125-128. SECTION C = AGND, PINS 129-132. PIN 1 DNC LEAD/LAG DA1+ DA1- DA3+ DA3- DA5+ DA5- DA7+ DA7- DA9+ DA9- DA11+ DA11- DNC DNC VD VD VD VD DB1+ DB1- DB3+ DB3- DB5+ DB5- DB7+ DB7- DB9+ DB9- DB11+ DB11- DNC DNC DNC DNC DNC RESET VC VC 1 VA VA VA VA AGND AGND DNC DNC DNC DNC DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND PIN 120 DRA DRA DA0+ DA0- DA2+ DA2- DA4+ DA4- DA6+ DA6- DA8+ DA8- DA10+ DA10- DNC PASS VD VD VD VD PIN 80 DB0+ DB0- DB2+ DB2- DB4+ DB4- DB6+ DB6- DB8+ DB8- DB10+ DB10- DNC DNC DRB DRB DNC DNC VC VC PIN 40 C 1 B 1 A PIN 2 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 to 4 5 Mnemonic VC RESET 6 to 9, 11, 13 to 16, 49, 51, 52, 79, 96 to 108 10 12 17 18 DNC Description Digital Supply, 3.3 V. LVTTL. 0 = device reset. Minimum width = 200 ns. Device resumes operation after 600 ms maximum. Do Not Connect. DRB DRB DB11- DB10- Channel B Data Ready. Complement output. Channel B Data Ready. True output. Channel B Data Bit 11. Complement output bit. Channel B Data Bit 10. Complement output bit. Rev. A | Page 7 of 24 03735-0-005 PIN 1 AIN AD12400 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 to 48 50 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 to 95, 109 to 112, 129 to 132 1 113 to 120 121 to 1281 1 Mnemonic DB11+ DB10+ DB9- DB8- DB9+ DB8+ DB7- DB6- DB7+ DB6+ DB5- DB4- DB5+ DB4+ DB3- DB2- DB3+ DB2+ DB1- DB0- DB1+ DB0+ VD PASS DA11- DA10- DA11+ DA10+ DA9- DA8- DA9+ DA8+ DA7- DA6- DA7+ DA6+ DA5- DA4- DA5+ DA4+ DA3- DA2- DA3+ DA2+ DA1- DA0- DA1+ DA0+ LEAD/LAG DRA DRA AGND Description Channel B Data Bit 11. True output bit. Channel B Data Bit 10. True output bit. Channel B Data Bit 9. Complement output bit. Channel B Data Bit 8. Complement output bit. Channel B Data Bit 9. True output bit. Channel B Data Bit 8. True output bit. Channel B Data Bit 7. Complement output bit. Channel B Data Bit 6. Complement output bit. Channel B Data Bit 7. True output bit. Channel B Data Bit 6. True output bit. Channel B Data Bit 5. Complement output bit. Channel B Data Bit 4. Complement output bit. Channel B Data Bit 5. True output bit. Channel B Data Bit 4. True output bit. Channel B Data Bit 3. Complement output bit. Channel B Data Bit 2. Complement output bit. Channel B Data Bit 3. True output bit. Channel B Data Bit 2. True output bit. Channel B Data Bit 1. Complement output bit. Channel B Data Bit 0. Complement output bit. DB0 is LSB. Channel B Data Bit 1. True output bit. Channel B Data Bit 0. True output bit. DB0 is LSB. Digital Supply, 1.5 V. LVTTL. Factory use only. (DNC). Channel A Data Bit 11. Complement output bit. Channel A Data Bit 10. Complement output bit. Channel A Data Bit 11. True output bit. Channel A Data Bit 10. True output bit. Channel A Data Bit 9. Complement output bit. Channel A Data Bit 8. Complement output bit. Channel A Data Bit 9. True output bit. Channel A Data Bit 8. True output bit. Channel A Data Bit 7. Complement output bit. Channel A Data Bit 6. Complement output bit. Channel A Data Bit 7. True output bit. Channel A Data Bit 6. True output bit. Channel A Data Bit 5. Complement output bit. Channel A Data Bit 4. Complement output bit. Channel A Data Bit 5. True output bit. Channel A Data Bit 4. True output bit. Channel A Data Bit 3. Complement output bit. Channel A Data Bit 2. Complement output bit. Channel A Data Bit 3. True output bit. Channel A Data Bit 2. True output bit. Channel A Data Bit 1. Complement output bit. Channel A Data Bit 0. Complement output bit. DA0 is LSB. Channel A Data Bit 1. True output bit. Channel A Data Bit 0. True output bit. DA0 is LSB. Typically DNC. See the LEAD/LAG section. Channel A Data Ready. Complement output. Channel A Data Ready. True output. Analog Ground. VA DGND Analog Supply, 3.8 V. Digital Ground. Internal ground plane connections: Section A = DGND, Pins 121 to 124; Section B = DGND, Pins 125 to 128; Section C = AGND, Pins 129 to 132. Rev. A | Page 8 of 24 AD12400 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Analog Input VSWR (50 ) The voltage standing wave ratio (VSWR) is a ratio of the transmitted and reflected signals. The VSWR can be related to input impedance = (ZL - ZS)/(ZL + ZS) Full-Scale Input Power Expressed in dBm. Computed using the following equation: POWERFull-Scale = 10 log ((V2Full-Scalerms)/(|ZINPUT| x 0.001)) Full-Scale Input Voltage Range The maximum peak-to-peak input signal magnitude that results in a full-scale response, 0 dBFS on a single-tone input signal case. Any magnitude increase from this value results in an overrange condition. Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBFS. where: Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBFS. ZL = actual load impedance. ZS = reference impedance. VSWR = (1 - ||)/(1 +||) Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Distortion, Image Spur The ratio of the rms signal amplitude to the rms signal amplitude of the image spur, reported in dBFS. The image spur, a result of gain and phase errors between two time-interleaved conversion channels, is located at fs/2 - fAIN. Distortion, Offset Spur The ratio of the rms signal amplitude to the rms signal amplitude of the offset spur, reported in dBFS. The offset spur, a result of offset errors between two time-interleaved conversion channels, is located at fs/2. Minimum Conversion Rate The minimum ENCODE rate at which the image spur calibration degrades no more than 1 dB (when the image spur is 70 dB). Offset Error The dc offset imposed on the input signal by the ADC, reported in LSB (codes). Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE (or zero crossing of a single-ended ENCODE). Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation ENOB = Maximum Conversion Rate The maximum ENCODE rate at which the image spur calibration degrades no more than 1 dB (when the image spur is 70 dB). SNRMEASURED - 1.76 dB 6.02 Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time the ENCODE pulse should be left in low state. Pipeline Latency The number of clock cycles the output data lags the corresponding clock cycle. Power Supply Rejection Ratio (PSRR) The ratio of power supply voltage change to the resulting ADC output voltage change. Rev. A | Page 9 of 24 AD12400 Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc and image spur. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, except the image spur. The peak spurious component may or may not be an harmonic. It can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full-scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It can be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full-scale). Total Noise Calculated as - SignaldBFS ( FSdBm - SNRdBc ) 10 VNOISE = Z x 0.001 x 10 where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value of the particular input level. Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Rev. A | Page 10 of 24 AD12400 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 SNR = 63.3dB SFDR = 75dBc SINAD = 62.9dB IMAGE SPUR = 80.5dBc -10 -20 -30 -30 -40 -40 -50 -50 dB -60 X N -120 40 60 80 100 120 140 160 180 -120 0 200 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 Figure 9. FFT: fS = 400 MSPS, AIN = 180.123 MHz @ -1.0 dBFS; X = Image Spur, N - Interleaved Offset Spur Figure 6. FFT: fS = 400 MSPS, AIN = 10.123 MHz @ -1.0 dBFS; X = Image Spur, N - Interleaved Offset Spur 0 0 SNR = 63.1dB SFDR = 78.7dBc SINAD = 62.7dB IMAGE SPUR = 78.8dBc -50 -60 -60 2 X 3N 5 6 -80 4 -90 -90 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 N -100 03735-0-007 -100 X2 X1 03735-0-010 -80 F2 - F1 -70 -70 F2 + F1 -40 -50 dB -30 -40 2F1 + F2 2F2 + F1 -20 -30 2F1 - F2 -20 SFDR = 76.3dBc -10 2F2 - F1 -10 -110 -120 0 200 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 Figure 10. Two-Tone Intermodulation Distortion (25.1 MHz and 28.1 MHz; fS = 400 MSPS); X = Image Spur, N - Interleaved Offset Spur Figure 7. FFT: fS = 400 MSPS, AIN = 65.123 MHz @ -1.0 dBFS; X = Image Spur, N - Interleaved Offset Spur 0 0 SNR = 62.5dB SFDR = 69.9dBc SINAD = 61.1dB IMAGE SPUR = 73.4dBc -10 -20 SFDR = 77.3dBc -10 -20 -30 -30 -40 -40 -50 -50 -80 N 6 4 -90 5 -100 03735-0-008 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 N 03735-0-011 -90 -100 X2 X1 2F2 + F1 2F1 + F2 -80 -60 -70 2 X F2 + F1 3 -70 2F1 - F2 dB -60 F2 - F1 dB 6 -110 FREQUENCY (MHz) dB 5 -100 03735-0-006 -110 20 4 -90 -100 0 N -80 4 5 6 2 3 2 X -70 3 -80 -90 -60 03735-0-009 -70 2F2 - F1 dB -20 SNR = 61.6dB SFDR = 69.0dBc SINAD = 60.0dB IMAGE SPUR = 70.4dBc -10 -110 -120 200 0 Figure 8. FFT: fS = 400 MSPS, AIN = 128.123 MHz @ -1.0 dBFS; X = Image Spur, N - Interleaved Offset Spur 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 Figure 11. Two-Tone Intermodulation Distortion (70.1 MHz and 73.1 MHz; fS = 400 MSPS); X = Image Spur, N - Interleaved Offset Spur Rev. A | Page 11 of 24 200 AD12400 95 0 SFDR = 70dBc IMAGE SPUR -10 90 -20 -30 HARMONICS (dBc) 85 MAGNITUDE (dB) -40 -80 2F2 - F1 2F1 - F2 -70 F1 + F2 F2 - F1 X2 X1 -60 2F1 + F2 2F2 + F1 -50 SECOND HARMONIC 80 75 THIRD HARMONIC 70 -90 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 60 200 03735-0-014 65 03735-0-036 -100 0 40 60 80 100 120 140 160 180 ANALOG INPUT FREQUENCY (MHz) Figure 12. Two-Tone Intermodulation Distortion (178.1 MHz and 182.1 MHz; fs = 400 MSPS), SFDR = 70 dBc; X = Image Spur, N - Interleaved Offset Spur Figure 15. Harmonics vs. Analog Input Frequency 0.5 64.6 0.4 64.4 0.3 64.2 0.2 64.0 SNR (dBFS) GAIN (dB) 20 0.1 0 -0.1 63.8 63.6 63.4 -0.2 03735-0-012 -0.4 -0.5 10.7 35.0 59.3 03735-0-015 63.2 -0.3 63.0 62.8 0 83.6 107.9 132.2 156.5 180.8 205.1 229.4 20 40 60 80 100 120 140 160 180 ANALOG INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. SNR vs. Analog Input Frequency Figure 13. Interleaved Gain Flatness 2.2 100 THIRD HARMONIC 2.1 95 VD SUPPLY CURRENT (A) 2.0 IMAGE SPUR 85 SECOND HARMONIC 80 75 70 60 0 10 20 30 40 50 ANALOG INPUT LEVEL (dB) 60 1.8 1.7 1.6 1.5 1.4 1.3 1.2 03735-0-013 65 1.9 03735-0-016 DISTORTION (dBFS) 90 1.1 1.0 0 70 20 40 60 80 100 120 140 160 180 INPUT FREQUENCY (MHz) Figure 14. Second/Third Harmonics and Image Spur vs. Analog Input Level; fS = 400 MSPS, AIN = 70 MHz Rev. A | Page 12 of 24 Figure 17. VD Supply Current vs. AIN Frequency 200 AD12400 THEORY OF OPERATION The AD12400 uses two high speed, 12-bit ADCs in a timeinterleaved configuration to double the sample rate, while maintaining a high level of dynamic range performance. The digital output of each ADC channel is calibrated using a proprietary digital postprocessing technique, Advanced Filter Bank (AFB). AFB is implemented using a state-of-the-art field programmable gate array (FPGA) and provides a wide bandwidth and wide temperature match for any gain, phase, and clock timing errors between each ADC channel. When two ADCs are time-interleaved, gain and/or phase mismatches between each channel produce an image spur at fs/2 - fAIN and an offset spur as shown in Figure 18. These mismatches can be the result of any combination of device tolerance, temperature, and frequency deviations. -20 IMAGE SPUR -40 X dB OFFSET SPUR -60 N -70 2 CLOCK INPUT 6 4 5 03735-0-017 -100 -110 -120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) . Figure 18. Image Spur due to Mismatches Between Two Interleaved ADCs (No AFB Digital Postprocessing) Figure 19 shows the performance of a similar converter with on-board AFB postprocessing implemented. The -44 dBFS image spur has been reduced to -77 dBFS and, as a result, the dynamic range of this time-interleaved ADC is no longer limited by the channel matching. 0 1 -10 -20 -30 The AD12400 requires a 400 MSPS encode that is divided by 2 and distributed to each ADC channel, 180 out of phase from each other. Internal ac coupling and bias networks provide the framework for flexible clock input requirements that include single-ended sine wave, single-ended PECL, and differential PECL. While the AD12400 is tested and calibrated using a single-ended sine wave, properly designed PECL circuits that provide fast slew rates (>1 V/ns) and minimize ringing result in comparable dynamic range performance. Aperture jitter and harmonic content are two major factors to consider when designing the input clock circuit for the AD12400. The relationship between aperture jitter and SNR can be characterized using the following equation. The equation assumes a full-scale, single-tone input signal. SNR = -40 -50 -60 2 2 1 1 + 2 2 x VNOISErms - 20log (20 x f A x 0 t JRMS )2 + x N + 1.5 2 2N IMAGE SPUR 3 -70 X OFFSET SPUR 2 -80 -90 5 6 4 N where: -100 03735-0-018 dB Image Spur (dBc) -40 -54 -62 -70 3 -80 -90 Aperture Delay Error (ps) 15 2.7 1.1 0.5 The AD12400 analog input is ac-coupled using a proprietary transformer front-end circuit that provides 1 dB of gain flatness over the first Nyquist zone and a -3 dB bandwidth of 450 MHz. This front-end circuit provides a VSWR of 1.5 (50 ) over the first Nyquist zone, and the typical full-scale input is 3.2 V p-p. The Mini-Circuits(R) HELA-10 amplifier module can be used to drive the input at these power levels. 1 -50 Gain Error (%) 1 0.25 0.2 0.025 ANALOG INPUT 0 -30 Table 7. Image Spur vs. Channel Mismatch For a more detailed description of time-interleaving in ADCs and a design example using the AD12400, refer to "Advanced Digital Post-Processing Techniques Enhance Performance in Time Interleaved ADC Systems," published in the August, 2003 edition of Analog Dialogue. This article can be found at http://www.analog.com/analogDialogue. TIME-INTERLEAVING ADCS -10 The relationship between image spur and channel mismatches is captured in Table 7 for specific conditions. -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 Figure 19. AD12400 with AFB Digital Postprocessing 200 fA = input frequency. tJRMS = aperture jitter. N = ADC resolution (bits). = ADCDNL (LSB). VNOISE = ADC input noise (LSBrms). Rev. A | Page 13 of 24 AD12400 Figure 20 displays the application of this relationship to a fullscale, single-tone input signal on the AD12400, where the DNL was assumed to be 0.4 LSB, and the input noise was assumed to be 0.8 LSBrms. The vertical marker at 0.4 ps displays the SNR at the jitter level present in the AD12400 evaluation system, including the jitter associated with the AD12400 itself. 65 AIN = 10MHz 64 AIN = 65MHz 63 SNR (dB) 62 AIN = 128MHz START-UP AND RESET 61 60 59 03735-0-037 AIN = 180MHz 58 57 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 APERTURE JITTER (ps rms) 0.8 0.9 While this product has been designed to provide good PSRR performance, system designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed ADC systems. Switching power supplies typically produces both conducted and radiated energy that result in common-/differential-mode EMI currents. Any system that requires 12-bit performance has very little room for errors associated with power supply EMI. For example, a system goal of 74 dB dynamic range performance on the AD12400 requires noise currents that are less than 4.5 A and noise voltages of less than 225 V in the analog input path. 1.0 Figure 20. SNR vs. Aperture Jitter In addition to jitter, the harmonic content of the single-ended sine wave clock sources must be controlled. The clock source used in the test and calibration process has an harmonic performance that is better than 60 dBc. Also, when using PECL or other square-wave clock sources, unstable behavior, such as overshoot and ringing, can affect phase matching and degrade the image spur performance. DIGITAL OUTPUTS The AD12400's FPGA configuration is stored in the on-board EPROM and loaded into the FPGA when power is applied to the device. The RESET pin (active low) allows the user to reload the FPGA in case of a low digital supply voltage condition or a power supply glitch. Pulling the RESET pin low pulls the data ready and output bits high until the FPGA is reloaded. The RESET pin should remain low for a minimum of 200 ns. On the rising edge of the reset pulse, the AD12400 starts loading the configuration into the FPGA. The reload process requires a maximum of 600 ms to complete. Valid signals on the data ready pins indicate the reset process is complete. Also, system designers must be aware of the thermal conditions of the AD12400 at startup. If large thermal imbalances are present, the AD12400 may require additional time to stabilize before providing specified image spur performance. LEAD/LAG The AD12400's digital postprocessing circuit provides two parallel, 12-bit, 200 MSPS data output buses. By providing two output busses that operate at one half the conversion rate, the AD12400 eliminates the need for large, expensive, high power demultiplexing circuits. The output data format is twos complement, maintaining the standard set by other high speed ADCs, such as the AD9430 and AD6645. Data-ready signals are provided for facilitating proper timing in the data capture circuit. The digital postprocessing circuit can be configured to provide alternate data output formats. The LEAD/LAG pin is used to synchronize the collection of data into external buffer memories. The LEAD/LAG pin can be applied synchronously or asynchronously to the AD12400. If applied asynchronously, LEAD/LAG must be held low for a minimum of 5 ns to ensure correct operation. The function shuts off DRA and DRB until the LEAD/LAG pin is set high again. DRA and DRB resumes on the next valid DRA after LEAD/LAG is released. If this feature is not required, tie this pin to 3.3 V through a 3.74 k. THERMAL CONSIDERATIONS POWER SUPPLIES The AD12400 requires three different supply voltages: a 1.5 V supply for the digital postprocessing circuit, a 3.3 V supply to facilitate digital I/O through the system, and a 3.8 V supply for the analog conversion and clock distribution circuits. The AD12400 incorporates two key features that result in solid PSRR performance. First, on-board linear regulators are used to provide an extra level of power supply rejection for the analog circuits. The linear regulator used to supply the ADCs provides an additional 60 dB of rejection at 100 kHz. Second, in order to address higher frequency noise (where the linear regulators' rejection degrades), the AD12400 incorporates high quality ceramic decoupling capacitors. The module is rated to operate over a case temperature of 0C to 60C. To maintain the tight channel matching and reliability of the AD12400, care must be taken to assure that proper thermal and mechanical considerations have been made and addressed to ensure case temperature is kept within this range. Each application requires evaluation of the thermal management as applicable to the system design. This section provides information that should be used in the evaluation of the AD12400's thermal management for each specific use. Rev. A | Page 14 of 24 AD12400 130 In addition to the radiation of heat into its environment, the AD12400 module enables flow of heat through the mounting studs and standoffs as they contact the motherboard. As described in the Package Integrity/Mounting Guidelines section, the module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32-inch ounces. Using a thermal grease at the standoffs results in better thermal coupling between the board and module. Depending on the ambient conditions, airflow can be necessary to ensure the components in the module do not exceed their maximum operating temperature. For reliability, the most sensitive component has a maximum junction temperature rating of 125C. 120 TEMPERATURE (C) 100 90 80 70 CASE 60 50 AMBIENT 03735-0-019 40 30 20 NO AIRFLOW 100 LFM 300 LFM AIRFLOW CONDITION Figure 21 and Figure 22 provide a basic guideline for two key thermal management decisions: the use of thermal interface material between the module bottom cover/mother board and airflow. Figure 21 characterizes the typical thermal profile of an AD12400 that is not using thermal interface material. Figure 22 provides the same information for a configuration that uses gap-filling thermal interface material (in this case, Thermagon T-flexTM 600 series, 0.040" thickness was used). One can see from these profiles that the maximum die temperature is reduced by approximately 2C when thermal interface material is used. Figure 21 and Figure 22 also provide a guideline for determining the airflow requirements for given ambient conditions. For example, a goal of 120C die temperature in a 40C ambient environment without the use of thermal interface material requires an airflow of 100 LFM. From a channel-matching perspective, the most important consideration is external thermal influences. It is possible for thermal imbalances in the end application to adversely affect the dynamic performance. Due to the temperature dependence of the image spur, substantial deviation from the factory calibration conditions can have a detrimental effect. Unbalanced thermal influences can cause gradients across the module, and performance degradation may result. Examples of unbalanced thermal influences may include large heat dissipating elements near one side of the AD12400, or obstructed airflow that does not flow uniformly across the module. The thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2C. TYPICAL JUNCTION 110 Figure 21. Typical Temperature vs. Airflow with No Module/Board Interface Material (Normalized to 60C Module Case Temperature) 130 120 TYPICAL JUNCTION 110 TEMPERATURE (C) 100 90 80 70 CASE 60 50 AMBIENT 03735-0-020 40 30 20 NO AIRFLOW 100 LFM 300 LFM AIRFLOW CONDITION Figure 22. Typical Temperature vs. Airflow with T-flex Module/Board Interface Material (Normalized to 60C Module Case Temperature Ambient) PACKAGE INTEGRITY/MOUNTING GUIDELINES The AD12400 is a printed circuit board (PCB)-based module designed to provide mechanical stability and support the intricate channel-to-channel matching necessary to achieve high dynamic range performance. The module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32-inch ounces. The SMA edge connectors (AIN and ENC/ENC) are surface mounted to the board in order to achieve minimum height of the module. When attaching and routing the cables, one must ensure they are stress-relieved and do not apply stress to the SMA connector/board. The presence of stress on the cables may degrade electrical performance and mechanical integrity of the module. In addition to the routing precautions, the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the AD12400's SMA connectors. The torque should never exceed 5-inch pounds. Rev. A | Page 15 of 24 AD12400 Any disturbances to the AD12400 structure, including removing the covers or mounting screws, invalidates the calibration and results in degraded performance. Refer to the Outline Dimensions section for mounting stud dimensions. Refer also to Figure 37 for PCB interface locations. Mounting stud length typically accommodates a PCB thickness of 0.093". Consult the factory if board thickness requirements exceed this dimension. AD12400 EVALUATION KIT The AD12400/KIT offers an easy way to evaluate the AD12400. The AD12400/KIT includes the AD12400KWS mounted on an adapter card, the AD12400 evaluation board, the power supply cables, a 225 MHz buffer memory FIFO board, and the Dual Analyzer software. The user must supply a clock source, an analog input source, a 1.5 V power supply, a 3.3 V power supply, a 5 V power supply, and a 3.8 V power supply. The clock source and analog input source connect directly to the AD12400KWS. The power supply cables (included) and a parallel port cable (not included) connect to the evaluation board. Data Outputs The AD12400KWS digital outputs are available at the 80-pin connector, P2, on the evaluation board. The AD12400/KIT comes with a buffer memory FIFO board connected to P2 that provides the interface to the parallel port of a PC. The Dual Analyzer software is compatible with Windows(R) 95, Windows 98, Windows 2000, and Windows NT(R). The buffer memory FIFO board can be removed, and an external logic analyzer, or other data acquisition module, can be connected to this connector, if required. Adapter Card The AD12400KWS is attached to an adapter card that interfaces to the evaluation board through a 120-pin connector, P1, which is on the top side of the evaluation board. Digital Postprocessing Control Power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). The AD12400 has a two-pin jumper labeled AFB that allows the user to enable/disable the digital postprocessing. The digital postprocessing is active when the AFB jumper is applied. When the jumper is removed, the FPGA is set to a passthrough mode, which demonstrates to the user the performance of the AD12400 without the digital postprocessing. Table 8. Power Connector RESET Power Connector VA 3.8 V VC 3.3 V VD 1.5 V1 VB 5.0 V 1 Analog Supply for the ADC (950 mA typ) Digital supply for the ADC outputs (200 mA typ) Digital supply for the FPGA (2.5 A max, 1.4 A typ) Digital supply for the buffer memory board (400 mA typ) The power supply cable has an approximately 100 mV drop. The VD supply current is dependent on the analog input frequency. Refer to Figure 17. Analog Input The analog input source connects directly to an SMA on the AD12400KWS. Encode The single-ended or differential encode signal connects directly to SMA connector(s) on the AD12400KWS. A single-ended sine wave at 10 dBm connected to the encode SMA is recommended. A low jitter clock source is recommended (<0.5 ps) to properly evaluate the AD12400. The AD12400KWS's FPGA configuration is stored in an EEPROM and loaded into the FPGA when power is applied to the AD12400. The RESET switch, SW1 (active low), allows the user to reload the FPGA in case of a low voltage condition or a power supply glitch. Depressing the RESET switch pulls the data ready and output bits high. The RESET switch should remain low for a minimum of 200 ns. On the rising edge of the RESET pulse, the AD12400 starts loading the configuration into the on-module FPGA. The reload process requires a maximum of 600 ms to complete. Valid signals on the data-ready pins indicate the reset process is complete. The AD12400 is not compatible with the HSC-ADC-EVALDC/SC hardware or software. Table 9. Evaluation Board Bill of Materials (BOM) Item No. 1 2 3 4 5 6 7 8 9 Quantity 2 2 1 1 1 1 3 1 1 REF-DES C3, C5 C4, C6 R9 AFB P2 SW1 J2, J3, J4 P1 PCB Device Capacitors Capacitors Resistor 2-Pin Header/Jumper 80-Pin Dual Connector Assemble Switch Push Button SPST 4-Pin Header Power Connecters 60-Pin Dual-Socket Assembly AD12400 Interface Bd GS08054 Rev. A | Page 16 of 24 Package 603 805 603 Pin Strip Surface Mount 6 MM Pin Strip Surface Mount PCB Value 0.1 F, 25 V 10 F, 6.3 V 4.02 k, 1% Molex/GC/Weldon Post Header AMP Panasonic Wieland SAMTEC AD12400 3.3VC R8 4.02k SPARE1 SPARE1 AFB PASS 3.3VC SPARE2 SPARE2 R9 4.02k E14 E18 H/L_GAIN H/L_GAIN 3.3VC R10 4.02k NYQ NYQ R11 4.02k 3.3VC DITHER OTHER E12 E13 JP2 JP3 DGND 1 DGND +VA SELECT D 5V 5V C4 10F 1 2 2 3 3 1 JP4 E17 E1 DGND DGND 1 RESET AGND DIGITAL J3 3.3VD SELECT D C3 0.1F 4 4 5V 1.5VD 3.8V ANALOG J2 3.3VC 3.3VD C6 10F C5 0.1F 2 2 3 4 3 EVQ-PAC85R DGND DGND DGND 4 E22 DGND Figure 23. Evaluation Board Rev. A | Page 17 of 24 1.5V SENSE 03735-0-021 3.3VC DIGITAL J4 AD12400 AD12400 P1:A 3.3VC RESET DNC DNC DNC DNC DNC DB11 DB11 DB9 DB9 DB7 DB7 DB5 DB5 DB3 DB3 DB1 DB1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 121 GND 123 GND P2:C 2 3.3VC 4 6 DNC 8 10 DRB 12 14 DNC 16 DNC 18 20 DB10 22 24 DB8 26 28 DB6 30 32 DB4 34 36 DB2 38 40 DB0 122 GND 124 GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DRA DRA DNC DRB DA11 DA11 DA10 DB10 DA10 DA9 DB8 DA9 DA8 DB6 DA8 DB4 DA7 DA7 DA6 DB2 DA6 DB0 DA5 DA5 QSE-60-01-L-D-A-K DNC DA11 DA9 DA7 DA5 DA3 DA1 DNC 41 43 45 47 49 DNC 51 53 DA11 55 57 DA9 59 61 DA7 63 65 DA5 67 69 DA3 71 73 DA1 75 77 LEAD/LAG 79 125 GND 127 GND DGND QSE-60-01-L-D-A-K DB10 DB10 DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DA4 DGND DA3 DA3 DA2 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 126 GND 128 GND DB11 DB11 AMP104655-9 P2:D P1:B 1.5VD DRB DRB AMP104655-9 DA4 DGND P2:A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DA2 1.5VD DA1 DA1 DA0 DA0 PASS DNC DA10 DA10 DA8 DA8 OR DA6 OR DA6 DA4 DA4 AMP104655-9 DA2 P2:B 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 OR OR AMP104655-9 DA2 DGND DA0 DGND DA0 DRA DRA DGND P1:C DNC DNC DNC DNC DNC AGND +VA AGND GND 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 130 GND 132 GND QSE-60-01-L-D-A-K AGND DNC WP 3.3VC DNC DNC DNC E2 E19 AGND +VA 03735-0-022 AGND 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 129 131 AGND Figure 24. Evaluation Board Rev. A | Page 18 of 24 03735-0-023 03735-0-026 AD12400 Figure 25. Power Plane 1 Figure 26. Power Plane 2 03735-0-027 03735-0-024 Figure 28. Second Ground Plane 03735-0-025 03735-0-028 Figure 29. Top Side Copper Figure 27. First Ground Plane Figure 30. Bottom Side Copper Rev. A | Page 19 of 24 03735-0-032 03735-0-029 AD12400 03735-0-030 Figure 32. Top Silkscreen 03735-0-033 Figure 34. Evaluation Adapter Board--Top Silkscreen Figure 31. Top Mask Figure 33. Bottom Silkscreen 03735-0-034 03735-0-031 Figure 35. Evaluation Adapter Board--Analog and Digital Layers Figure 36. Evaluation Adapter Board--Bottom Silkscreen Rev. A | Page 20 of 24 AD12400 LAYOUT GUIDELINES The AD12400 requires a different approach to traditional high speed ADC system layouts. While the AD12400's internal PCB isolates digital and analog grounds, these planes are tied together through the product's aluminum case structure. Therefore, the decision of isolating the analog and digital grounds on the system PCB has additional factors to consider. For example, if the AD12400 is attached with conductive thermal interface material to the system PCB, there is essentially no benefit to keeping the analog and digital ground planes separate. If neither thermal interface material nor nonconductive interface material is used, system architects must consider the ground loop that is created if analog and digital planes are tied together directly under the AD12400. This EMI-based decision must be considered on a case-by-case basis and is largely dependent on the other sources of EMI in the system. One critical consideration is that a 12-bit performance requirement (-74 dBc) requires keeping conducted EMI currents (referenced to the input of the AD12400) below 4.5 A. All the characterization and testing of the AD12400 is performed using a system that isolated these ground planes. PCB INTERFACE Figure 37 provides the mounting hole footprint for assembling the AD12400 to the second-level assembly. The diagram is referenced to the center of the mating QTE connector. Refer to the QTE/QSE series connector documentation at www.samtec.com for the SMT footprint of the mating connector. The top view of the second-level assembly footprint provides a diagram of the second-level assembly locating tab locations for mating the SAMTEC QTE-060-01-L-A-K-TR terminal strip on the AD12400KWS to a QSE-060-01-L-A-K-TR socket on the second-level assembly. The diagram is referenced to the center of the QTE terminal strip on the AD12400KWS and the mounting holds for the screws, which holds the AD12400KWS to the second-level assembly board. The relationship of these locating tabs is based on information provided by SAMTEC (connector supplier) and should be verified with SAMTEC by the customer. Mating and unmating forces--the knifing or peeling action of applying force to one end or one side--must be avoided to prevent damage to the connector and guidepost. If thermal interface material is used in the final system design, the following layout factors need to be considered: open solder mask on the area that contacts the interface material and the thickness of the ground plane. While this should be analyzed in each specific system design, the use of solder mask may negate any advantage achieved by using the thermal interface material, and its use should be carefully considered. The ground plane thickness does not have a major impact on the thermal performance, but if design margin is slight, additional thickness can yield incremental improvements. 1.184 [30.0673] 1.025 [26.0164] 2x 0, 0 DATUM = CENTER OF CONNECTOR .000 [.0000] R.0470[R1.19] 6x 1.025 [26.0164] 2x Figure 37. Top View of Interface PCB Assembly Rev. A | Page 21 of 24 03735-0-035 0.000 [.0000] 0.105 [2.6670] 2x 0.396 [10.0456] 2x 2.159 [54.8258] 2x 1.184 [30.0673] AD12400 OUTLINE DIMENSIONS 3.190 TYP BOARD 2.890 MAX PIN 1 AIN 2.060 2.040 2.590 MAX 2.328 TYP ENC ENC 0.856 TYP 0.267 TYP TOP VIEW 0.256 TYP SIDE VIEW JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821 0.600 MAX 0.700 MAX 2-56 STUDS 4x 0.200 TYP 0.175 TYP SAMTEC CONNECTOR QTE-060-01-L-D-A-K-TR 2.060 2.040 0.270 2x 0.505 TYP 2x 1.773 1.753 BOTTOM VIEW Figure 38. Outline Dimensions Dimensions shown in inches Tolerances: 0.xxx = 5 mils ORDERING GUIDE Model AD12400KWS AD12400JWS AD12400/KIT Temperature Range 0C to 60C (Case) 0C to 60C (Case) Package Description 2.9" x 2.6" x 0.6" Module 2.9" x 2.6" x 0.6" Module Evaluation Kit Rev. A | Page 22 of 24 AD12400 NOTES Rev. A | Page 23 of 24 AD12400 NOTES (c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03735-0-6/05(A) Rev. A | Page 24 of 24