12-Bit, 400 MSPS A/D Converter
AD12400
Rev. A
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS sample rate
SNR of 63 dBFS @128 MHz
SFDR of 70 dBFS @128 MHz
VSWR of 1:1.5
Wideband ac-coupled input signal conditioning
Enhanced spurious-free dynamic range
Single-ended or differential encode signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas—digital beam
Multichannel, multimode receivers
Secure communications
Wireless and wired broadband communications
Wideband carrier frequency systems
GENERAL DESCRIPTION
The AD12400 is a 12-bit analog-to-digital converter (ADC)
with a transformer-coupled analog input and digital post-
processing for enhanced SFDR. The product operates at a 400
MSPS conversion rate with outstanding dynamic performance
in wideband carrier systems.
The AD12400 requires 3.8 V analog, 3.3 V digital, and 1.5 V
digital supplies, and provides a flexible encode signal that can
be differential or single-ended. No external reference is
required.
The AD12400 package style is an enclosed 2.9" × 2.6" × 0.6"
module. Performance is rated over a 0°C to 60°C case
temperature range.
FUNCTIONAL BLOCK DIAGRAM
03735-0-001
ADC
A
DATA
READY
A
DATA
READY
B
DA0–DA11
DB0–DB11
CLK DISTRIBUTION
AD12400
POST-
PROCESSING
ADC
B
AIN
CLOCK DISTRIBUTION
DIVIDE BY 2
ENC ENC
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 400 MSPS.
2. Input signal conditioning with optimized dynamic
performance to 180 MHz.
3. Additional performance options available; contact factory.
4. Proprietary Advanced Filter Bank (AFB™) digital
postprocessing from V Corp Technologies, Inc.
AD12400
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels........................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 7
Terminolog y ...................................................................................... 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 13
Time-Interleaving ADCs ........................................................... 13
Analog Input ............................................................................... 13
Clock Input.................................................................................. 13
Digital Outputs........................................................................... 14
Power Supplies............................................................................ 14
Start-Up and RESET .................................................................. 14
LEAD/LAG ................................................................................. 14
Thermal Considerations............................................................ 14
Package Integrity/Mounting Guidelines ................................. 15
AD12400 Evaluation Kit ........................................................... 16
Layout Guidelines........................................................................... 21
PCB Interface .............................................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Table 2............................................................................ 4
Changes to Figure 3.......................................................................... 6
Changes to Table 5............................................................................ 6
Renamed Definition of Specifications Section to
Terminology Section ........................................................................ 9
Changes to LEAD/LAG Section ................................................... 14
Changes to Ordering Guide .......................................................... 22
11/03—Revision 0: Initial Version
AD12400
Rev. A | Page 3 of 24
SPECIFICATIONS
DC SPECIFICATIONS
VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 1.
AD12400JWS AD12400KWS
Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits
ACCURACY
No Missing Codes Full IV Guaranteed Guaranteed
Offset Error Full I −12 +12 −12 +12 LSB
Gain Error @ 10 MHz Full I −10 +10 −10 +10 %FS
Differential Nonlinearity (DNL) 60°C V 0.3 0.3 LSB
Integral Nonlinearity (INL) 60°C V 0.5 0.5 LSB
TEMPERATURE DRIFT
Gain Error 60°C V 0.02 0.02 %/°C
ANALOG INPUT (AIN)
Full-Scale Input Voltage Range 60°C V 3.2 3.2 V p-p
Frequency Range Full IV 10 180 10 180 MHz
Flatness (10 MHz to 180 MHz) Full IV 0.5 1 0.5 1 dB
Input VSWR (50 Ω)
(10 MHz to 180 MHz)
60°C V 1.5 1.5
Analog Input Bandwidth 60°C V 450 450 MHz
POWER SUPPLY1
Supply Voltage
VA Full IV 3.6 3.8 3.6 3.8 V
VC Full IV 3.2 3.4 3.2 3.4 V
VD Full IV 1.475 1.575 1.475 1.575 V
Supply Current
IVA (VA = 3.8 V) Full I 0.95 1.11 0.95 1.11 A
IVC (VC = 3.3 V) Full I 400 500 400 500 mA
IVD (VD = 1.5 V) Full I 1.4 2.0 1.4 2.0 A
Total Power Dissipation Full I 7.0 8.5 7.0 8.5 W
ENCODE INPUTS2
Differential Inputs (ENC, ENC)
Input Voltage Range Full IV 0.4 0.4 V
Input Resistance 60°C V 100 100 Ω
Input Capacitance 60°C V 4 4 pF
Common-Mode Voltage 60°C V ±3 ±3 V
Single-Ended Inputs (ENC)
Input Voltage Full IV 0.4 2 2.5 0.4 2 2.5 V p-p
Input Resistance 60°C V 50 50 Ω
LOGIC INPUTS (RESET)3
Logic 1 Voltage Full IV 2.0 2.0 V
Logic 0 Voltage Full IV 0.8 0.8 V
Source IIH 60°C V 10 10 μA
Source IIL 60°C V 1 1 mA
LOGIC OUTPUTS
(DRA, DRB, Output Bits)4
Differential Output Voltage Full IV 247 454 247 454 mV
Output Drive Current Full IV −4 +4 −4 +4 mA
Output Common-Mode Voltage Full IV 1.125 1.375 1.125 1.375 V
Start-Up Time Full IV 600 600 ms
1 Tested using input frequency of 70 MHz. See Figure 17 for VD current vs. input frequency.
2 All ac specifications tested by driving ENC single-ended.
3 Refer to Table 5 for logic convention on all logic inputs.
4 Digital output logic levels: VC = 3.3 V, CLOAD = 8 pF. 3.3 V LVDS, R1 = 100 Ω.
AD12400
Rev. A | Page 4 of 24
AC SPECIFICATIONS1
VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 2.
AD12400JWS AD12400KWS
Parameter Case Temp Test Level Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE2
SNR
Analog Input 10 MHz Full I 62 64.4 62 64.4 dBFS
@ −1.0 dBFS 70 MHz Full I 61.5 64 61.5 64 dBFS
128 MHz Full I 60 63.5 60 63.5 dBFS
180 MHz Full I 60 62.5 60 62.5 dBFS
SINAD3
Analog Input 10 MHz Full I 61 64 61 64 dBFS
@ −1.0 dBFS 70 MHz Full I 60.5 64 60.5 64 dBFS
128 MHz Full I 59 62.5 59 62.5 dBFS
180 MHz Full I 57 61 57 61 dBFS
Spurious-Free Dynamic Range3
Analog Input 10 MHz Full I 69 80 69 80 dBFS
@ −1.0 dBFS 70 MHz Full I 69 84 69 84 dBFS
128 MHz Full I 67 76 67 76 dBFS
180 MHz Full I 62 71 62 71 dBFS
Image Spur4
Analog Input 10 MHz Full I 60 75 62 75 dBFS
@ −1.0 dBFS 70 MHz Full I 60 72 62 72 dBFS
128 MHz Full I 56 70 62 70 dBFS
180 MHz Full I 54 70 62 70 dBFS
Offset Spur4
Analog Input @ −1.0 dBFS 60°C V 65 65 dBFS
Two-Tone IMD5
F1, F2 @ −6 dBFS 60°C V −75 −75 dBc
SWITCHING SPECIFICATIONS
Conversion Rate6Full IV 396 400 404 396 400 404 MSPS
Encode Pulse Width High (tEH)160°C V 1.25 1.25 ns
Encode Pulse Width Low (tEL)1 60°C V 1.25 1.25 ns
DIGITAL OUTPUT PARAMETERS
Valid Time (tV) Full IV 1.9 2.4 3.1 1.9 2.4 3.1 ns
Propagation Delay (tPD) 60°C V 1.20 1.20 ns
Rise Time (tR) (20% to 80%) 60°C V 1 1 ns
Fall Time (tF) (20% to 80%) 60°C V 1 1 ns
DR Propagation Delay (tEDR) 60°C V 3.88 3.88 ns
Data to DR Skew (tEDR − tPD) 60°C V 2.68 2.68 ns
Pipeline Latency7Full IV 74 74 Cycles
Aperture Delay (tA) 60°C
IV 1.6 1.6 ns
Aperture Uncertainty (Jitter, tJ) 60°C V 0.4 0.4 ps rms
1 All ac specifications tested with a single-ended, 2.0 V p-p encode.
2 Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz.
3 Not including image spur.
4 The image spur is at fs/2 – AIN; the offset spur is at fs/2.
5 F1 = 70 MHz, F2 = 73 MHz.
6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 400 MSPS ±1%.
7 Pipeline latency is exactly 74 cycles.
AD12400
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Value
VA to AGND 5 V
VC to DGND 4 V
VD to DGND 1.65 V
Analog Input Voltage 6 V (dc)
Analog Input Power 18 dBm (ac)
Encode Input Voltage 6 V (dc)
Encode Input Power 12 dBm (ac)
Logic Inputs and Outputs to DGND 5 V
Storage Temperature Range, Ambient −65°C to +150°C
Operating Temperature 0°C to 60°C
EXPLANATION OF TEST LEVELS
Level Description
I 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature
extremes for military devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage may
occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
AD12400
Rev. A | Page 6 of 24
Table 4. Output Coding (Twos Complement)
Code AIN (V) Digital Output
4095 +1.6 0111 1111 1111
. . .
. . .
. . .
2048 0 0000 0000 0000
2047 −0.000781 1111 1111 1111
. . .
. . .
0 −1.6 1000 0000 0000
Table 5. Option Pin List with Necessary Associated Circuitry
Pin Name
Active
High or
Low
Logic
Level
Type
Default
Level
Associated
Circuitry
Within Part
RESET Low LVTTL High 3.74 kΩ Pull-Up
LEAD/LAG Low LVTTL High
03735-0-003
ENC 100Ω
100Ω
100Ω
100Ω
3.3V
3.3V PECL
DRIVER
ENC
Figure 2. Encode Equivalent Circuit
ENC
400MHZ
DRA
DRB
DRB
DRA
DATA OUT
B
LEAD LAG
DATA OUT A N – 74
N– 1
N – 73 N
N
N + 2
N + 1
N + 1 N + 2 N + 3
N + 3 N + 5 N + 7
N + 4 N + 6 N + 8
1/f
S
tEL
tEH
1
1
74 CLOCK CYCLES
03735-0-002
1. DATA LOST DUE TO ASSERTION OF LEAD/LAG. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID.
2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS
THE 50% POINT AND APPLY THE SAME TIMING INFORMATION.
3. THE LEAD/LAG PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES.
THE LEAD/LAG PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12400. IF APPLIED
ASYNCHRONOUSLY, LEAD/LAG MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION.
THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE LEAD/LAG PIN IS SET HIGH AGAIN. DRA AND DRB RESUME
ON THE NEXT VALID DRA AFTER LEAD/LAG IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS
PIN TO 3.3V THROUGH A 3.74kΩ RESISTOR.
NOTES
Figure 3. Timing Diagram
03735-0-004
t
PD
t
V
ENC
DATA OUT
DR
ENC
DR
Figure 4. Highlighted Timing Diagram
AD12400
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03735-0-005
SAMTEC CONNECTOR
QTE-060-01-L-D-A-K-TR
BOTTOM VIEW LEFT SIDE VIEW
AIN
ENC
BOARD
1
INTEGRAL GROUND PLANE CONNECTIONS.
SECTION A = DGND, PINS 121–124.
SECTION B = DGND, PINS 125–128.
SECTION C = AGND, PINS 129–132.
NOTES
1. FOR MATING HALF, USE SAMTEC, INC.
PART NO. QSE-60-01-L-D-A-K.
ENC
2-56 STUDS 4×
JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821
END VIEW
TOP VIEW
PIN 1
AIN
ENC
ENC
DB0+
DB0–
DB2+
DB2–
DB4+
DB4–
DB6+
DB6–
DB8+
DB8–
DB10+
DB10–
DNC
DNC
DRB
DRB
DNC
DNC
VC
VC
DB1+
DB1–
DB3+
DB3–
DB5+
DB5–
DB7+
DB7–
DB9+
DB9–
DB11+
DB11–
DNC
DNC
DNC
DNC
DNC
RESET
VC
VC
1
DRA
DRA
DA0+
DA0–
DA2+
DA2–
DA4+
DA4–
DA6+
DA6–
DA8+
DA8–
DA10+
DA10–
DNC
PASS
VD
VD
VD
VD
DNC
LEAD/LAG
DA1+
DA1–
DA3+
DA3–
DA5+
DA5–
DA7+
DA7–
DA9+
DA9–
DA11+
DA11–
DNC
DNC
VD
VD
VD
VD
PIN 120
PIN 2
PIN 40
A
B
C
PIN 1
PIN 119
1
VA
VA
VA
VA
AGND
AGND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VA
VA
VA
VA
AGND
AGND
DNC
DNC
DNC
DNC
DNC
DNC
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
1
PIN 80
PIN 79
PIN 39
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 VC Digital Supply, 3.3 V.
5 RESET LVTTL. 0 = device reset. Minimum width = 200 ns. Device resumes operation after 600 ms
maximum.
6 to 9, 11, 13 to 16, 49,
51, 52, 79, 96 to 108
DNC Do Not Connect.
10 DRB Channel B Data Ready. Complement output.
12 DRB Channel B Data Ready. True output.
17 DB11− Channel B Data Bit 11. Complement output bit.
18 DB10− Channel B Data Bit 10. Complement output bit.
AD12400
Rev. A | Page 8 of 24
Pin No. Mnemonic Description
19 DB11+ Channel B Data Bit 11. True output bit.
20 DB10+ Channel B Data Bit 10. True output bit.
21 DB9− Channel B Data Bit 9. Complement output bit.
22 DB8− Channel B Data Bit 8. Complement output bit.
23 DB9+ Channel B Data Bit 9. True output bit.
24 DB8+ Channel B Data Bit 8. True output bit.
25 DB7− Channel B Data Bit 7. Complement output bit.
26 DB6− Channel B Data Bit 6. Complement output bit.
27 DB7+ Channel B Data Bit 7. True output bit.
28 DB6+ Channel B Data Bit 6. True output bit.
29 DB5− Channel B Data Bit 5. Complement output bit.
30 DB4− Channel B Data Bit 4. Complement output bit.
31 DB5+ Channel B Data Bit 5. True output bit.
32 DB4+ Channel B Data Bit 4. True output bit.
33 DB3− Channel B Data Bit 3. Complement output bit.
34 DB2− Channel B Data Bit 2. Complement output bit.
35 DB3+ Channel B Data Bit 3. True output bit.
36 DB2+ Channel B Data Bit 2. True output bit.
37 DB1− Channel B Data Bit 1. Complement output bit.
38 DB0− Channel B Data Bit 0. Complement output bit. DB0 is LSB.
39 DB1+ Channel B Data Bit 1. True output bit.
40 DB0+ Channel B Data Bit 0. True output bit. DB0 is LSB.
41 to 48 VD Digital Supply, 1.5 V.
50 PASS LVTTL. Factory use only. (DNC).
53 DA11− Channel A Data Bit 11. Complement output bit.
54 DA10− Channel A Data Bit 10. Complement output bit.
55 DA11+ Channel A Data Bit 11. True output bit.
56 DA10+ Channel A Data Bit 10. True output bit.
57 DA9− Channel A Data Bit 9. Complement output bit.
58 DA8− Channel A Data Bit 8. Complement output bit.
59 DA9+ Channel A Data Bit 9. True output bit.
60 DA8+ Channel A Data Bit 8. True output bit.
61 DA7− Channel A Data Bit 7. Complement output bit.
62 DA6− Channel A Data Bit 6. Complement output bit.
63 DA7+ Channel A Data Bit 7. True output bit.
64 DA6+ Channel A Data Bit 6. True output bit.
65 DA5− Channel A Data Bit 5. Complement output bit.
66 DA4− Channel A Data Bit 4. Complement output bit.
67 DA5+ Channel A Data Bit 5. True output bit.
68 DA4+ Channel A Data Bit 4. True output bit.
69 DA3− Channel A Data Bit 3. Complement output bit.
70 DA2− Channel A Data Bit 2. Complement output bit.
71 DA3+ Channel A Data Bit 3. True output bit.
72 DA2+ Channel A Data Bit 2. True output bit.
73 DA1− Channel A Data Bit 1. Complement output bit.
74 DA0− Channel A Data Bit 0. Complement output bit. DA0 is LSB.
75 DA1+ Channel A Data Bit 1. True output bit.
76 DA0+ Channel A Data Bit 0. True output bit. DA0 is LSB.
77 LEAD/LAG Typically DNC. See the LEAD/LAG section.
78 DRA Channel A Data Ready. Complement output.
80 DRA Channel A Data Ready. True output.
81 to 95, 109 to 112,
129 to 1321
AGND Analog Ground.
113 to 120 VA Analog Supply, 3.8 V.
121 to 1281DGND Digital Ground.
1 Internal ground plane connections: Section A = DGND, Pins 121 to 124; Section B = DGND, Pins 125 to 128; Section C = AGND, Pins 129 to 132.
AD12400
Rev. A | Page 9 of 24
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Analog Input VSWR (50 Ω)
The voltage standing wave ratio (VSWR) is a ratio of the
transmitted and reflected signals. The VSWR can be related to
input impedance
Γ = (ZL − ZS)/(ZL + ZS)
where:
ZL = actual load impedance.
ZS = reference impedance.
VSWR = (1 − |Γ|)/(1 +|Γ|)
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Distortion, Image Spur
The ratio of the rms signal amplitude to the rms signal
amplitude of the image spur, reported in dBFS. The image spur,
a result of gain and phase errors between two time-interleaved
conversion channels, is located at fs/2 – fAIN.
Distortion, Offset Spur
The ratio of the rms signal amplitude to the rms signal
amplitude of the offset spur, reported in dBFS. The offset spur, a
result of offset errors between two time-interleaved conversion
channels, is located at fs/2.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
026
761
.
dB.SNR
ENOB MEASURED −
=
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time the ENCODE
pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time the
ENCODE pulse should be left in low state.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
POWERFull-Scale = 10 log ((V2Full-Scalerms)/(|ZINPUT| × 0.001))
Full-Scale Input Voltage Range
The maximum peak-to-peak input signal magnitude that results
in a full-scale response, 0 dBFS on a single-tone input signal
case. Any magnitude increase from this value results in an over-
range condition.
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBFS.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBFS.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Maximum Conversion Rate
The maximum ENCODE rate at which the image spur
calibration degrades no more than 1 dB (when the image
spur is 70 dB).
Minimum Conversion Rate
The minimum ENCODE rate at which the image spur
calibration degrades no more than 1 dB (when the image
spur is 70 dB).
Offset Error
The dc offset imposed on the input signal by the ADC, reported
in LSB (codes).
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE (or zero crossing of a single-ended ENCODE).
Pipeline Latency
The number of clock cycles the output data lags the correspond-
ing clock cycle.
Power Supply Rejection Ratio (PSRR)
The ratio of power supply voltage change to the resulting ADC
output voltage change.
AD12400
Rev. A | Page 10 of 24
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc and image spur.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, except the image spur. The
peak spurious component may or may not be an harmonic. It
can be reported in dBc (that is, degrades as signal level is
lowered) or dBFS (always related back to converter full-scale).
Tota l Nois e
Calculated as
)(
.ZV
dBFSdBcdBm SignalSNRFS
NOISE 10
100010
−−
××=
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value of the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale. This value includes both thermal and quantization
noise.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported in
dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It can be reported in dBc
(that is, degrades as signal level is lowered) or in dBFS (always
related back to converter full-scale).
AD12400
Rev. A | Page 11 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
03735-0-006
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 20 40 60 80 100 120 140 160 180 200
SNR = 63.3dB
SFDR = 75dBc
SINAD = 62.9dB
IMAGE SPUR = 80.5dBc
2
3
456
XN
FREQUENCY (MHz)
dB
Figure 6. FFT: fS = 400 MSPS, AIN = 10.123 MHz @ –1.0 dBFS;
X = Image Spur, N – Interleaved Offset Spur
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03735-0-007
0 20 40 60 80 100 120 140 160 180 200
SNR = 63.1dB
SFDR = 78.7dBc
SINAD = 62.7dB
IMAGE SPUR = 78.8dBc
23
4
5
6
FREQUENCY (MHz)
dB
N
X
Figure 7. FFT: fS = 400 MSPS, AIN = 65.123 MHz @ –1.0 dBFS;
X = Image Spur, N – Interleaved Offset Spur
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03735-0-008
0 20 40 60 80 100 120 140 160 180 200
SNR = 62.5dB
SFDR = 69.9dBc
SINAD = 61.1dB
IMAGE SPUR = 73.4dBc
2
3
45
6
X
FREQUENCY (MHz)
dB
N
Figure 8. FFT: fS = 400 MSPS, AIN = 128.123 MHz @ –1.0 dBFS;
X = Image Spur, N – Interleaved Offset Spur
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03735-0-009
0 20 40 60 80 100 120 140 160 180 200
SNR = 61.6dB
SFDR = 69.0dBc
SINAD = 60.0dB
IMAGE SPUR = 70.4dBc
23
456
X
N
FREQUENCY (MHz)
dB
Figure 9. FFT: fS = 400 MSPS, AIN = 180.123 MHz @ –1.0 dBFS;
X = Image Spur, N – Interleaved Offset Spur
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03735-0-010
0 20 40 60 80 100 120 140 160 180 200
SFDR = 76.3dBc
FREQUENCY (MHz)
dB
X1 N
F2 – F1
2F1 – F2
2F1 + F2
2F2 + F1
2F2 – F1
F2 + F1
X2
Figure 10. Two-Tone Intermodulation Distortion
(25.1 MHz and 28.1 MHz; fS = 400 MSPS);
X = Image Spur, N – Interleaved Offset Spur
03735-0-011
0 20 40 60 80 100 120 140 160 180 200
SFDR = 77.3dBc
FREQUENCY (MHz)
dB
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
F2 – F1
2F1 – F2
2F1 + F2
2F2 + F1
2F2 – F1
F2 + F1
X2 X1 N
Figure 11. Two-Tone Intermodulation Distortion
(70.1 MHz and 73.1 MHz; fS = 400 MSPS);
X = Image Spur, N – Interleaved Offset Spur
AD12400
Rev. A | Page 12 of 24
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03735-0-036
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
MAGNITUDE (dB)
F2 – F1
SFDR = 70dBc
F1 + F2
X2
X1
2F1 + F2
2F2 + F1
2F1 – F2
2F2 – F1
Figure 12. Two-Tone Intermodulation Distortion
(178.1 MHz and 182.1 MHz; fs = 400 MSPS), SFDR = 70 dBc;
X = Image Spur, N – Interleaved Offset Spur
03735-0-012
FREQUENCY (MHz)
GAIN (dB)
–0.4
–0.5
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
10.7 35.0 59.3 83.6 107.9 132.2 156.5 180.8 205.1 229.4
Figure 13. Interleaved Gain Flatness
03735-0-013
ANALOG INPUT LEVEL (dB)
DISTORTION (dBFS)
60
95
90
85
80
75
70
65
100
065040302010 70
0
THIRD HARMONIC
SECOND HARMONIC
IMAGE SPUR
Figure 14. Second/Third Harmonics and Image Spur vs. Analog Input Level;
fS = 400 MSPS, AIN = 70 MHz
03735-0-014
ANALOG INPUT FREQUENCY (MHz)
HARMONICS (dBc)
60
65
70
75
80
85
90
95
0 20 40 60 80 100 120 140 160 180
SECOND HARMONIC
IMAGE SPUR
THIRD HARMONIC
Figure 15. Harmonics vs. Analog Input Frequency
03735-0-015
ANALOG INPUT FREQUENCY (MHz)
SNR (dBFS)
62.8
64.4
64.2
64.0
63.8
63.6
63.4
63.2
63.0
64.6
0 20 40 60 80 100 120 140 160 180
Figure 16. SNR vs. Analog Input Frequency
03735-0-016
INPUT FREQUENCY (MHz)
VD SUPPLY CURRENT (A)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
0 20 40 60 80 100 120 140 160 180 200
Figure 17. VD Supply Current vs. AIN Frequency
AD12400
Rev. A | Page 13 of 24
THEORY OF OPERATION
The AD12400 uses two high speed, 12-bit ADCs in a time-
interleaved configuration to double the sample rate, while
maintaining a high level of dynamic range performance. The
digital output of each ADC channel is calibrated using a
proprietary digital postprocessing technique, Advanced Filter
Bank (AFB). AFB is implemented using a state-of-the-art field
programmable gate array (FPGA) and provides a wide
bandwidth and wide temperature match for any gain, phase,
and clock timing errors between each ADC channel.
TIME-INTERLEAVING ADCS
When two ADCs are time-interleaved, gain and/or phase
mismatches between each channel produce an image spur at
fs/2 − fAIN and an offset spur as shown in Figure 18. These
mismatches can be the result of any combination of device
tolerance, temperature, and frequency deviations.
.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
03735-0-017
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
dB
IMAGE SPUR
1
23
4
56
N
OFFSET SPUR
X
Figure 18. Image Spur due to Mismatches Between Two Interleaved ADCs
(No AFB Digital Postprocessing)
Figure 19 shows the performance of a similar converter with
on-board AFB postprocessing implemented. The –44 dBFS
image spur has been reduced to –77 dBFS and, as a result, the
dynamic range of this time-interleaved ADC is no longer
limited by the channel matching.
03735-0-018
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
dB
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
IMAGE SPUR OFFSET SPUR
1
23
4
56N
X
Figure 19. AD12400 with AFB Digital Postprocessing
The relationship between image spur and channel mismatches
is captured in Table 7 for specific conditions.
Table 7. Image Spur vs. Channel Mismatch
Gain Error (%) Aperture Delay Error (ps)
Image Spur
(dBc)
1 15 –40
0.25 2.7 –54
0.2 1.1 –62
0.025 0.5 –70
For a more detailed description of time-interleaving in ADCs
and a design example using the AD12400, refer to “Advanced
Digital Post-Processing Techniques Enhance Performance in
Time Interleaved ADC Systems,” published in the August, 2003
edition of Analog Dialogue. This article can be found at
http://www.analog.com/analogDialogue.
ANALOG INPUT
The AD12400 analog input is ac-coupled using a proprietary
transformer front-end circuit that provides 1 dB of gain flatness
over the first Nyquist zone and a –3 dB bandwidth of 450 MHz.
This front-end circuit provides a VSWR of 1.5 (50 ) over the
first Nyquist zone, and the typical full-scale input is 3.2 V p-p.
The Mini-Circuits® HELA-10 amplifier module can be used to
drive the input at these power levels.
CLOCK INPUT
The AD12400 requires a 400 MSPS encode that is divided by 2
and distributed to each ADC channel, 180° out of phase from
each other. Internal ac coupling and bias networks provide the
framework for flexible clock input requirements that include
single-ended sine wave, single-ended PECL, and differential
PECL. While the AD12400 is tested and calibrated using a
single-ended sine wave, properly designed PECL circuits that
provide fast slew rates (>1 V/ns) and minimize ringing result in
comparable dynamic range performance.
Aperture jitter and harmonic content are two major factors to
consider when designing the input clock circuit for the
AD12400. The relationship between aperture jitter and SNR can
be characterized using the following equation. The equation
assumes a full-scale, single-tone input signal.
SNR =
()
⎥
⎥
⎥
⎦
⎤
⎢
⎢
⎢
⎣
⎡
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛×
+
⎟
⎠
⎞
⎜
⎝
⎛ε+
×+××π−
2
2
2
2
22
2
1
51
1
020log20 N
NOISErms
N
JRMSA
V
.
tf
where:
fA = input frequency.
tJRMS = aperture jitter.
N = ADC resolution (bits).
ε
= ADCDNL (LSB).
VNOISE = ADC input noise (LSBrms).
AD12400
Rev. A | Page 14 of 24
Figure 20 displays the application of this relationship to a full-
scale, single-tone input signal on the AD12400, where the DNL
was assumed to be 0.4 LSB, and the input noise was assumed to
be 0.8 LSBrms. The vertical marker at 0.4 ps displays the SNR at
the jitter level present in the AD12400 evaluation system,
including the jitter associated with the AD12400 itself.
57
58
59
60
61
62
63
64
65
03735-0-037
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
APERTURE JITTER (ps rms)
SNR (dB)
A
IN
= 10MHz
A
IN
= 65MHz
A
IN
= 128MHz
A
IN
= 180MHz
Figure 20. SNR vs. Aperture Jitter
In addition to jitter, the harmonic content of the single-ended
sine wave clock sources must be controlled. The clock source
used in the test and calibration process has an harmonic
performance that is better than 60 dBc. Also, when using PECL
or other square-wave clock sources, unstable behavior, such as
overshoot and ringing, can affect phase matching and degrade
the image spur performance.
DIGITAL OUTPUTS
The AD12400’s digital postprocessing circuit provides two
parallel, 12-bit, 200 MSPS data output buses. By providing two
output busses that operate at one half the conversion rate, the
AD12400 eliminates the need for large, expensive, high power
demultiplexing circuits. The output data format is twos
complement, maintaining the standard set by other high speed
ADCs, such as the AD9430 and AD6645. Data-ready signals are
provided for facilitating proper timing in the data capture
circuit. The digital postprocessing circuit can be configured to
provide alternate data output formats.
POWER SUPPLIES
The AD12400 requires three different supply voltages: a 1.5 V
supply for the digital postprocessing circuit, a 3.3 V supply to
facilitate digital I/O through the system, and a 3.8 V supply for
the analog conversion and clock distribution circuits. The
AD12400 incorporates two key features that result in solid
PSRR performance. First, on-board linear regulators are used to
provide an extra level of power supply rejection for the analog
circuits. The linear regulator used to supply the ADCs provides
an additional 60 dB of rejection at 100 kHz. Second, in order to
address higher frequency noise (where the linear regulators’
rejection degrades), the AD12400 incorporates high quality
ceramic decoupling capacitors.
While this product has been designed to provide good PSRR
performance, system designers need to be aware of the risks
associated with switching power supplies and consider using
linear regulators in their high speed ADC systems. Switching
power supplies typically produces both conducted and radiated
energy that result in common-/differential-mode EMI currents.
Any system that requires 12-bit performance has very little
room for errors associated with power supply EMI. For exam-
ple, a system goal of 74 dB dynamic range performance on the
AD12400 requires noise currents that are less than 4.5 µA and
noise voltages of less than 225 µV in the analog input path.
START-UP AND RESET
The AD12400’s FPGA configuration is stored in the on-board
EPROM and loaded into the FPGA when power is applied to
the device. The RESET pin (active low) allows the user to reload
the FPGA in case of a low digital supply voltage condition or a
power supply glitch. Pulling the RESET pin low pulls the data
ready and output bits high until the FPGA is reloaded. The
RESET pin should remain low for a minimum of 200 ns. On the
rising edge of the reset pulse, the AD12400 starts loading the
configuration into the FPGA. The reload process requires a
maximum of 600 ms to complete. Valid signals on the data
ready pins indicate the reset process is complete. Also, system
designers must be aware of the thermal conditions of the
AD12400 at startup. If large thermal imbalances are present,
the AD12400 may require additional time to stabilize before
providing specified image spur performance.
LEAD/LAG
The LEAD/LAG pin is used to synchronize the collection of
data into external buffer memories. The LEAD/LAG pin can be
applied synchronously or asynchronously to the AD12400. If
applied asynchronously, LEAD/LAG must be held low for a
minimum of 5 ns to ensure correct operation. The function
shuts off DRA and DRB until the LEAD/LAG pin is set high
again. DRA and DRB resumes on the next valid DRA after
LEAD/LAG is released. If this feature is not required, tie this
pin to 3.3 V through a 3.74 k.
THERMAL CONSIDERATIONS
The module is rated to operate over a case temperature of 0°C
to 60°C. To maintain the tight channel matching and reliability
of the AD12400, care must be taken to assure that proper
thermal and mechanical considerations have been made and
addressed to ensure case temperature is kept within this range.
Each application requires evaluation of the thermal manage-
ment as applicable to the system design. This section provides
information that should be used in the evaluation of the
AD12400’s thermal management for each specific use.
AD12400
Rev. A | Page 15 of 24
In addition to the radiation of heat into its environment, the
AD12400 module enables flow of heat through the mounting
studs and standoffs as they contact the motherboard. As
described in the Package Integrity/Mounting Guidelines
section, the module should be secured to the motherboard
using 2-56 nuts (washer use is optional). The torque on the nuts
should not exceed 32-inch ounces. Using a thermal grease at the
standoffs results in better thermal coupling between the board
and module. Depending on the ambient conditions, airflow can
be necessary to ensure the components in the module do not
exceed their maximum operating temperature. For reliability,
the most sensitive component has a maximum junction
temperature rating of 125°C.
Figure 21 and Figure 22 provide a basic guideline for two key
thermal management decisions: the use of thermal interface
material between the module bottom cover/mother board and
airflow. Figure 21 characterizes the typical thermal profile of an
AD12400 that is not using thermal interface material. Figure 22
provides the same information for a configuration that uses
gap-filling thermal interface material (in this case, Thermagon
T-flex™ 600 series, 0.040” thickness was used). One can see
from these profiles that the maximum die temperature is
reduced by approximately 2°C when thermal interface material
is used. Figure 21 and Figure 22 also provide a guideline for
determining the airflow requirements for given ambient
conditions. For example, a goal of 120°C die temperature in a
40°C ambient environment without the use of thermal interface
material requires an airflow of 100 LFM.
From a channel-matching perspective, the most important
consideration is external thermal influences. It is possible for
thermal imbalances in the end application to adversely affect
the dynamic performance. Due to the temperature dependence
of the image spur, substantial deviation from the factory cali-
bration conditions can have a detrimental effect. Unbalanced
thermal influences can cause gradients across the module, and
performance degradation may result. Examples of unbalanced
thermal influences may include large heat dissipating elements
near one side of the AD12400, or obstructed airflow that does
not flow uniformly across the module. The thermal sensitivity
of the module can be affected by a change in thermal gradient
across the module of 2°C.
03735-0-019
AIRFLOW CONDITION
TEMPERATURE (°C)
20
30
40
50
60
70
80
90
100
110
120
130
TYPICAL JUNCTION
CASE
AMBIENT
NO AIRFLOW 100 LFM 300 LFM
Figure 21. Typical Temperature vs. Airflow with No Module/Board
Interface Material (Normalized to 60°C Module Case Temperature)
03735-0-020
AIRFLOW CONDITION
TEMPERATURE (°C)
20
30
40
50
60
70
80
90
100
110
120
130
TYPICAL JUNCTION
CASE
AMBIENT
NO AIRFLOW 100 LFM 300 LFM
Figure 22. Typical Temperature vs. Airflow with T-flex Module/Board
Interface Material (Normalized to 60°C Module Case Temperature Ambient)
PACKAGE INTEGRITY/MOUNTING GUIDELINES
The AD12400 is a printed circuit board (PCB)-based module
designed to provide mechanical stability and support the
intricate channel-to-channel matching necessary to achieve
high dynamic range performance. The module should be
secured to the motherboard using 2-56 nuts (washer use is
optional). The torque on the nuts should not exceed 32-inch
ounces.
The SMA edge connectors (AIN and ENC/ENC) are surface
mounted to the board in order to achieve minimum height of
the module. When attaching and routing the cables, one must
ensure they are stress-relieved and do not apply stress to the
SMA connector/board. The presence of stress on the cables may
degrade electrical performance and mechanical integrity of the
module. In addition to the routing precautions, the smallest
torque necessary to achieve consistent performance should be
used to secure the system cable to the AD12400’s SMA
connectors. The torque should never exceed 5-inch pounds.
AD12400
Rev. A | Page 16 of 24
Any disturbances to the AD12400 structure, including
removing the covers or mounting screws, invalidates the
calibration and results in degraded performance. Refer to the
Outline Dimensions section for mounting stud dimensions.
Refer also to Figure 37 for PCB interface locations. Mounting
stud length typically accommodates a PCB thickness of 0.093".
Consult the factory if board thickness requirements exceed this
dimension.
AD12400 EVALUATION KIT
The AD12400/KIT offers an easy way to evaluate the AD12400.
The AD12400/KIT includes the AD12400KWS mounted on an
adapter card, the AD12400 evaluation board, the power supply
cables, a 225 MHz buffer memory FIFO board, and the Dual
Analyzer software. The user must supply a clock source, an
analog input source, a 1.5 V power supply, a 3.3 V power supply,
a 5 V power supply, and a 3.8 V power supply. The clock source
and analog input source connect directly to the AD12400KWS.
The power supply cables (included) and a parallel port cable
(not included) connect to the evaluation board.
Power Connector
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
Table 8. Power Connector
VA 3.8 V Analog Supply for the ADC (950 mA typ)
VC 3.3 V Digital supply for the ADC outputs (200 mA typ)
VD 1.5 V1Digital supply for the FPGA (2.5 A max, 1.4 A typ)
VB 5.0 V Digital supply for the buffer memory board
(400 mA typ)
1 The power supply cable has an approximately 100 mV drop. The VD supply
current is dependent on the analog input frequency. Refer to Figure 17.
Analog Input
The analog input source connects directly to an SMA on the
AD12400KWS.
Encode
The single-ended or differential encode signal connects directly
to SMA connector(s) on the AD12400KWS. A single-ended
sine wave at 10 dBm connected to the encode SMA is recom-
mended. A low jitter clock source is recommended (<0.5 ps) to
properly evaluate the AD12400.
Data Outputs
The AD12400KWS digital outputs are available at the 80-pin
connector, P2, on the evaluation board. The AD12400/KIT
comes with a buffer memory FIFO board connected to P2
that provides the interface to the parallel port of a PC. The
Dual Analyzer software is compatible with Windows® 95,
Windows 98, Windows 2000, and Windows NT®.
The buffer memory FIFO board can be removed, and an
external logic analyzer, or other data acquisition module, can be
connected to this connector, if required.
Adapter Card
The AD12400KWS is attached to an adapter card that interfaces
to the evaluation board through a 120-pin connector, P1, which
is on the top side of the evaluation board.
Digital Postprocessing Control
The AD12400 has a two-pin jumper labeled AFB that allows
the user to enable/disable the digital postprocessing. The digital
postprocessing is active when the AFB jumper is applied. When
the jumper is removed, the FPGA is set to a passthrough mode,
which demonstrates to the user the performance of the AD12400
without the digital postprocessing.
RESET
The AD12400KWS’s FPGA configuration is stored in an
EEPROM and loaded into the FPGA when power is applied to
the AD12400. The RESET switch, SW1 (active low), allows the
user to reload the FPGA in case of a low voltage condition or a
power supply glitch. Depressing the RESET switch pulls the
data ready and output bits high. The RESET switch should
remain low for a minimum of 200 ns. On the rising edge of the
RESET pulse, the AD12400 starts loading the configuration into
the on-module FPGA. The reload process requires a maximum
of 600 ms to complete. Valid signals on the data-ready pins
indicate the reset process is complete.
The AD12400 is not compatible with the HSC-ADC-EVAL-
DC/SC hardware or software.
Table 9. Evaluation Board Bill of Materials (BOM)
Item No. Quantity REF-DES Device Package Value
1 2 C3, C5 Capacitors 603 0.1 μF, 25 V
2 2 C4, C6 Capacitors 805 10 μF, 6.3 V
3 1 R9 Resistor 603 4.02 kΩ, 1%
4 1 AFB 2-Pin Header/Jumper Pin Strip Molex/GC/Weldon
5 1 P2 80-Pin Dual Connector Assemble Surface Mount Post Header AMP
6 1 SW1 Switch Push Button SPST 6 MM Panasonic
7 3 J2, J3, J4 4-Pin Header Power Connecters Pin Strip Wieland
8 1 P1 60-Pin Dual-Socket Assembly Surface Mount SAMTEC
9 1 PCB AD12400 Interface Bd GS08054 PCB
AD12400
Rev. A | Page 17 of 24
03735-0-021
AFB
3.3VC
PASS
H/L_GAIN
3.3VC
H/L_GAIN
NYQ
3.3VC
NYQ
DITHER
JP2
E12 JP3
E13
SPARE1 E14
SPARE2 E18
3.3VC
OTHER
SPARE1
SPARE2
DGND
1.5VD
DIGITAL
J3
1
2
3
4
DGND
+VA
AGND
ANALOG
J2
1
2
3
4
DIGITAL
J4
3.3VC 3.8V
DGND
1
2
3
4
5V
C4
10μFC3
0.1μF
DGND DGND
5V 5V
C6
10μFC5
0.1μF
3.3VC
DGND DGND
3.3VD
3.3VD
SELECT D
JP4
E17
SELECT D
RESET
1.5V SENSE
E22
DGND
EVQ-PAC85R
1
23
4
E1
R8
4.02kΩ
R9
4.02kΩ
R10
4.02kΩ
R11
4.02kΩ
Figure 23. Evaluation Board
AD12400
Rev. A | Page 18 of 24
03735-0-022
DRB
DNC
3.3VC
DNC
DNC
3.3VC
DNC
RESET
DB10
DNC DNC
DNC
DB8
DB9
DB10
DB11
DB4
DB5
DB6
DB7
DB2
DB3
DB0
DB1
14
16
18
20
22
24
26
28
30
32
34
36
38
40
122
124
21
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
121
123
4
6
8
10
12
P1:A
DGND QSE–60–01–L–D–A–K DGND
DNC
DRB
DNC
DB8
DB6
DB4
DB2
DB0
GND
GND
GND
GND
DB11
DB9
DB7
DB5
DB3
DB1
DB11
PASS
1.5VD 1.5VD
DA10
DA11
DNC
DA8
DA7
DA10
DA9
DA4
DA3
DA6
DA5
DA2
DA1 DA0
DRALEAD/LAG
54
56
58
60
62
64
66
68
70
72
74
76
78
80
126
128
4241
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
125
127
44
46
48
50
52
P1:B
DGND QSE–60–01–L–D–A–K DGND
DNC
DA8
DA6
DA4
DA2
DA0
DRA
GND
GND
GND
GND
DA11
DA9
DA7
DA5
DA3
DA1
DNC
DNC
AGND AGND
3.3VC
DNC
DNC
DNC
WP
94
96
98
100
102
104
106
108
110
112
114
116
118
120
130
132
8281
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
129
131
84
86
88
90
92
P1:C
AGND AGND
QSE–60–01–L–D–A–K AGNDAGND
DNC
GND
GND
GND
E2
E19
DNC
DNC
DNC
DNC
DNC
+VA +VA
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DGND
P2:C
AMP104655-9
DRA
DA11
DA10
DRA
DA11
DA10 DA9
DA9 DA8
DA8 DA7
DA7 DA6
DA6 DA5
DA5
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P2:D
AMP104655-9
DA3
DA1
DA0
DA3 DA2
DA2
DA4
DA4
DA1
DA0
OR
OR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DGND
P2:A
AMP104655-9
DRB
DB11
DB10
DRB
DB11
DB10 DB9
DB9 DB8
DB8 DB7
DB7 DB6
DB6 DB5
DB5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P2:B
AMP104655-9
DB3
DB1
DB0
DB3 DB2
DB2
DB4
DB4
DB1
DB0
OR
OR
AD12400
Figure 24. Evaluation Board
AD12400
Rev. A | Page 19 of 24
03735-0-023
Figure 25. Power Plane 1
03735-0-024
Figure 26. Power Plane 2
03735-0-025
Figure 27. First Ground Plane
03735-0-026
Figure 28. Second Ground Plane
0
3735-0-027
Figure 29. Top Side Copper
03735-0-028
Figure 30. Bottom Side Copper
AD12400
Rev. A | Page 20 of 24
03735-0-029
Figure 31. Top Mask
03735-0-030
Figure 32. Top Silkscreen
03735-0-031
Figure 33. Bottom Silkscreen
03735-0-032
Figure 34. Evaluation Adapter Board—Top Silkscreen
03735-0-033
Figure 35. Evaluation Adapter Board—Analog and Digital Layers
03735-0-034
Figure 36. Evaluation Adapter Board—Bottom Silkscreen
AD12400
Rev. A | Page 21 of 24
LAYOUT GUIDELINES
The AD12400 requires a different approach to traditional high
speed ADC system layouts. While the AD12400’s internal PCB
isolates digital and analog grounds, these planes are tied
together through the product’s aluminum case structure.
Therefore, the decision of isolating the analog and digital
grounds on the system PCB has additional factors to consider.
For example, if the AD12400 is attached with conductive
thermal interface material to the system PCB, there is
essentially no benefit to keeping the analog and digital ground
planes separate. If neither thermal interface material nor
nonconductive interface material is used, system architects
must consider the ground loop that is created if analog and
digital planes are tied together directly under the AD12400.
This EMI-based decision must be considered on a case-by-case
basis and is largely dependent on the other sources of EMI in
the system. One critical consideration is that a 12-bit perform-
ance requirement (–74 dBc) requires keeping conducted EMI
currents (referenced to the input of the AD12400) below 4.5 A.
All the characterization and testing of the AD12400 is performed
using a system that isolated these ground planes.
If thermal interface material is used in the final system design,
the following layout factors need to be considered: open solder
mask on the area that contacts the interface material and the
thickness of the ground plane. While this should be analyzed in
each specific system design, the use of solder mask may negate
any advantage achieved by using the thermal interface material,
and its use should be carefully considered. The ground plane
thickness does not have a major impact on the thermal
performance, but if design margin is slight, additional thickness
can yield incremental improvements.
PCB INTERFACE
Figure 37 provides the mounting hole footprint for assembling
the AD12400 to the second-level assembly. The diagram is
referenced to the center of the mating QTE connector. Refer to
the QTE/QSE series connector documentation at
www.samtec.com for the SMT footprint of the mating
connector.
The top view of the second-level assembly footprint provides a
diagram of the second-level assembly locating tab locations for
mating the SAMTEC QTE-060-01-L-A-K-TR terminal strip on
the AD12400KWS to a QSE-060-01-L-A-K-TR socket on the
second-level assembly. The diagram is referenced to the center
of the QTE terminal strip on the AD12400KWS and the
mounting holds for the screws, which holds the AD12400KWS
to the second-level assembly board. The relationship of these
locating tabs is based on information provided by SAMTEC
(connector supplier) and should be verified with SAMTEC by
the customer.
Mating and unmating forces—the knifing or peeling action of
applying force to one end or one side—must be avoided to
prevent damage to the connector and guidepost.
03735-0-035
1.184 [30.0673]
1.184 [30.0673]
R.0470[R1.19] 6×
1.025 [26.0164] 2×
0.105 [2.6670] 2×
0.396 [10.0456] 2×
2.159 [54.8258] 2×
1.025 [26.0164] 2×
.000 [.0000]
0.000 [.0000]
0, 0 DATUM = CENTER OF CONNECTOR
Figure 37. Top View of Interface PCB Assembly
AD12400
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
TOP VIEW
SIDE VIEW
3.190 TYP
PIN 1
AIN
ENC
ENC
2.890 MAX BOARD
2.328 TYP
0.856 TYP
0.256 TYP
0.267 TYP
SAMTEC CONNECTOR
QTE-060-01-L-D-A-K-TR
BOTTOM VIEW
1.773
1.753
2.060
2.040
0.270 2×
0.505 TYP 2×
0.700 MAX
0.175 TYP 0.200 TYP
2-56 STUDS 4×
0.600 MAX
JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821
2.590 MAX 2.060
2.040
Figure 38. Outline Dimensions
Dimensions shown in inches
Tolerances:
0.xxx = ±5 mils
ORDERING GUIDE
Model Temperature Range Package Description
AD12400KWS 0°C to 60°C (Case) 2.9" × 2.6" × 0.6" Module
AD12400JWS 0°C to 60°C (Case) 2.9" × 2.6" × 0.6" Module
AD12400/KIT Evaluation Kit
AD12400
Rev. A | Page 23 of 24
NOTES
AD12400
Rev. A | Page 24 of 24
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03735–0–6/05(A)
