Bt8970 Single-Chip HDSL Transceiver The Bt8970 is a full-duplex 2B1Q transceiver based on Rockwells High-Bit-Rate Digital Subscriber Line (HDSL) technology. It supports transmission of more than 18,000 feet over 26 AWG copper telephone wire without repeaters. Small size and low power dissipation makes the Bt8970 ideal for line-powered digital access, voice pairgain, and HDSL systems. The Bt8970 is a highly integrated device that includes all of the active circuitry needed for a complete 2B1Q transceiver. In the receive portion of the Bt8970, a variable gain amplifier optimizes the signal level according to the dynamic range of the analog-to-digital converter. Once the signal is digitized, sophisticated adap- tive echo cancellation, equalization, and detection DSP algorithms reproduce the originally transmitted far-end signal. In the transmitter, the transmit source and scrambler operation is programma- ble via the microcomputer interface. A highly linear digital-to-analog converter with programmable gain sets the transmission power for optimal performance. A pulse-shaping filter and a low-distortion line driver generate the signal character- istics needed to drive a large range of subscriber lines at low-bit error rates. Startup and performance monitoring operations are controlled via the micro- processor interface. C-language source code supporting these operations is sup- plied under a no-fee license agreement from Rockwell. The Bt8970 includes a glueless interface to both Intel and Motorola microprocessors. Functional Block Diagram Analog Variable Analog- Digital Recovered Receive Gain | to-Digital w) Signal > Data and Amplifier Converter Processor Clock A AoA Framer/ A Channel Microcomputer | Unit we a Interface ff *) Interface y y Analog Line onus? Prograrn- |_| Transmit Transmit Driver Fitters Gain Data DAG @ Rockwell semiconductor Systems Distinguishing Features * Single-chip 2B1Q transceiver solution * All 2B1Q transceiver functions inte- grated into a single monolithic device Receiver gain control and A/D converter DSP functions including echo cancellation, equalization, timing recovery, and symbol detection Programmable gain transmit DAC, pulse-shaping filter, and line driver * Supports operation from 160 to 1552 kbps * Capable of transceiving over the ANSI T1E1.4/94-006 and ETSI ETR 152 HDSL test loops * Flexible Monitoring and Control Glueless interface to Intel 8051 and Motorola 68302 processors Access to embedded filters, per- formance meters and timers * Backwards compatible with Bt8952 and Bt8960 software API commands * Pin compatible with Bt8960 JTAG/IEEE Std 1149.1-1990 compliant Single +5 V power supply operation with option for 3.3 V to reduce power consumption * 100-pin PQFP package * 40C to +85C operation * 700 mW power consumption at 784 kbps (max using 3.3 V option) Applications * 1 and T1 HDSL transport * Voice/data pairgain systems * Internet connectivity * ISDN basic-rate interface concentrators Extended range fractional T1/E1 * Cellular/microcellular base stations * Personal Communications Systems (PCS) radio ports and cell switchesOrdering Information Order Number Package Ambient Temperature Bt8970EHF 100-Pin Plastic Quad Flat Pack (PQFP) -40C to +85C Copyright 1997 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: December 1997 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems, Inc. Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages resulting from such improper use or sale. Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC isa registered trademark of AT&T Technologies, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. Specifications are subject to change without notice. PRINTED IN THE UNITED STATES OF AMERICATable of Contents List Of Figures... 0.0... ene n tent n teens vii List of Tables. 0.00... nent enn n tent n eens ix 1.0 System Overview 0.0.0.0... 0. n tenet e nent ees 1 1.1 Functional Summary... 0.0.0... tte tes 1 1.1.1 Transmit Section. 0... eens 3 1.1.2 Receive Section. 0.0... 6. eee nett nee ees 3 1.1.3 Timing Recovery and Clock Interface... 0... eee 3 1.1.4 Microcomputer Interface .. 0... ete ees 4 1.1.5 Test and Diagnostic Interface (JTAG) 2.0.2... eee 4 1.2 Pin Descriptions . 2.0... tte tees 5 2.0 Functional Description .............. 00. e tenes 11 2.1 Transmit Section... 0.0... ttt 11 2.1.1 Symbol Source Selector/Scrambler .. 0.0.0... c cece ees 12 2.1.2 Variable Gain Digital-to-Analog Converter... 0... 00... cece ees 14 2.1.3 Pulse-Shaping Filter... 0.0... eek cette teens 14 2.1.4 Line Driver 2.0... 2.2 n eens 14 2.2 Receive Section... 00.0... tenet nae 15 2.2.1 Variable Gain Amplifier... 0.0.00... cece ete tenes 15 2.2.2 Analog-to-Digital Converter............ 00. cece eee teens 16 2.2.3 Digital Signal Processor .. 1.1... 6. eee teens 16 2.2.3.1 Digital Front-End... . nee 17 2.2.3.2 Offset Adjustment... 0.0... cee ees 18 2.2.3.3 DC Level Meter... 0... eens 18 2.2.3.4 Signal Level Meter... 0... eee 18 2.2.3.5 Overflow Detection and Monitoring ........ 00... cece eee eens 18 2.2.3.6 Far-End Level Meter... 0.0.0... ccc ccc 18 2.2.3.7 Far-End Level Alarm... 0... ee eee 18 2.2.4 Echo Canceller 2... 0... eect tte ees 19 2.2.4.1 Linear Echo Canceller (LEC) . 0.0.0.0... cece eee 19 Rockwell N8970DSB iiiTable of Contents Bt8970 Single-Chip HDSL Transceiver 2.2.4.2 Nonlinear Echo Canceller (NEC) ........ 00... c cece eee 19 2.2.5 EQUAIIZE cette tnt e teenies 20 2.2.5.1 Digital Automatic Gain Control (DAGC)...... 0.00... eee eee 20 2.2.5.2 Feed Forward Equalizer (FFE) .... 0.0... ee eee 20 2.2.5.3 Error Predictor (EP)... 0.0... cece ees 20 2.2.5.4 Decision Feedback Equalizer (DFE) ............... 0 cece eee 20 2.2.5.5 MiCrocoding ... 0.0... eect tte eee 20 2.2.6 Detector... 2. ene nn etn t tenes 21 2.2.6.1 Slicer... ttt tenes 21 2.2.6.2 Peak Detector (PKD) ....... 00... cece nee 21 2.2.6.3 Error Signals 2.0... eet ete 21 2.2.6.4 Scrambler Module... 2... . ee ees 21 2.2.6.5 Sync Detector... tenes 22 2.2.6.6 Detector Meters... 0... teens 23 2.3 Timing Recovery and Clock Interface........ 0... cee 24 2.3.0.7 Timing Recovery Circuit... 0.0... cece 25 2.3.0.8 Crystal Amplifier 0... 0... cee eens 25 2.4 Channel Unit Interface..... 0... tae 26 2.5 Microcomputer Interface... 00.0.0... eet nae 28 2.5.1 Source Code... cette net nee eee nees 28 2.5.2 Microcomputer Read/Write. ...... 0.00... cece eee nes 28 2.5.2.1 RAM Access Registers .......... 00 cc cece eee 29 2.5.2.2 Multiplexed Address/Data BUS..... 0.0.0... ccc eee 29 2.5.2.3 Separated Address/Data BUS... 1... 1. ee eee 29 2.5.3 Interrupt Request... 0... cette teen eenees 29 2.5.4 Reset... 0. eee eee tenet nett ees 30 2.5.5 Registers... 6. eee enn etn ees 30 2.5.6 TIMEMS. 0... eee een een e tenn n ees 30 2.6 Test and Diagnostic Interface (UTAG)..... 0.0... ne 32 3.0 Registers 0... nnn ent n teen es 33 3.1 Conventions. .... 0... teeta 33 3.2 Register Summary... 0.0.0... cette nae 34 3.2.1 0x00 Global Modes and Status Register (global_modes) .................. 39 3.2.2 0x01 Serial Monitor Source Select Register (serial_monitor_source)......... 39 3.2.3 0x02 Interrupt Mask Register Low (mask_low_reg) ...............-..00ee 40 3.2.4 0x03 Interrupt Mask Register High (mask_high_reg) ..............-...0.. 44 3.2.5 0x04 Timer Source Register (timer_source) ......... 00... cee eee eee 44 3.2.6 0x05 IRQ Source Register (irq_Source).... 0... ee eee ees 42 3.2.7 0x06 Channel Unit Interface Modes Register (cu_interface_modes).......... 42 3.2.8 0x07 Receive Phase Select Register (receive_phase_select)................ 43 3.2.9 0x08 Linear Echo Canceller Modes Register (linear_ec_modes)............. 44 3.2.10 0x09 Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes) ...... 45 3.2.11 Ox0A Decision Feedback Equalizer Modes Register (dfe_modes) ........... 45 iv N8970DSB @ RockwellBt8970 Table of Contents Single-Chip HDSL Transceiver 3.2.12 0x0B Transmitter Modes Register (transmitter_modes) .................. 46 3.2.13 0x0C Timer Restart Register (timer_restart) ............. 00. c cece eee 47 3.2.14 0x0D Timer Enable Register (timer_enable)...............0 2... cee 48 3.2.15 OxOE Timer Continuous Mode Register (timer_continuous) ............... 48 3.2.16 OxOF Test Register (reserved2) ... 0... eee ees 48 3.2.17 0x10, 0x11 Startup Timer 1 Interval Register (sut1_low, sut1_high)......... 48 3.2.18 0x12, 0x13 Startup Timer 2 Interval Register (sut2_low, sut2_high)......... 49 3.2.19 0x14, 0x15 Startup Timer 3 Interval Register (sut3_low, sut3_high)......... 49 3.2.20 0x16, 0x17 Startup Timer 4 Interval Register (sut4_low, sut4_high)......... 49 3.2.21 0x18, 0x19Meter Timer Interval Register (meter_low, meter_high)......... 49 3.2.22 0x1A, 0x1B SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high) ................0.2 00:0 eee ee eee aes 49 3.2.23 0x1C, 0x1D General Purpose Timer 3 Interval Register (t3_low, t8_high)..... 49 3.2.24 Ox1E, 0x1F- General Purpose Timer 4 Interval Register (t4_low, t4_high) ..... 49 3.2.25 0x20 Test Register (reserved9) ..... 0... cece eee eens 50 3.2.26 0x21 ADC Control Register (adc_control) ..... 0.0.0... e cece eee 50 3.2.27 0x22 PLL Modes Register (pll_modes) .......... 2.000 e cece ees 51 3.2.28 0x23 Test Register (reservedi0) .. 0.0... eects 52 3.2.29 0x24, 0x25 Timing Recovery PLL Phase Offset Register (pll_phase_offset_low, pll_phase_offset_high)...................00000) 52 3.2.30 0x26, 0x27 Receiver DC Offset Register (dc_offset_low, dc_offset_high)..... 52 3.2.31 0x28 Transmitter Calibration Register (tx_calibrate) ..................0.. 52 3.2.32 0x29 Transmitter Gain Register (tx_gain) ... 2.0... . eee eee eee 53 3.2.33 Ox2A, 0x2BNoise-Level Histogram Threshold Register (noise_histogram_th_low, noise_histogram_th_high) ........ 2... cece ee eee eee 54 3.2.34 0x2C, 0x2D Error Predictor Pause Threshold Register (ep_pause_th_low, ep_pause_th_high)........... cece eet 54 3.2.35 Ox2E Scrambler Synchronization Threshold Register (scr_sync_th)......... 54 3.2.36 0x30, 0x31 Far-End High Alarm Threshold Register (far_end_high_alarm_th_low, far_end_high_alarm_th_high).............. 54 3.2.37 0x32, 0x33 Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low, far_end_low_alarm_th_high)............... 54 3.2.38 0x34, 0x35 SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high) ............ 00.20 c cece cece eet ete eee 55 3.2.39 0x36, 0x37 Cursor Level Register (cursor_level_low, cursor_level_high)..... 55 3.2.40 0x38, 0x39 DAGC Target Register (dagc_target_low, dagc_target_high)...... 55 3.2.41 0x3A Symbol Detector Modes Register (detector_modes) ................ 55 3.2.42 0x3B Peak Detector Delay Register (peak_detector_delay) ................ 57 3.2.43 0x3C Digital AGC Modes Register (dagc_modes) ..............0020. eee 57 3.2.44 0x3D Feed Forward Equalizer Modes Register (ffe_modes)................ 58 3.2.45 Ox3E Error Predictor Modes Register (ep_modes) ...............-..00- 58 3.2.46 0x40, 0x41 Phase Detector Meter Register (pdm_low, pdm_high).......... 59 3.2.47 0x42 Overflow Meter Register (overflow_meter)...............0020 eee 59 3.2.48 0x44, 0x45 DC Level Meter Register (dc_meter_low, dc_meter_high) ....... 59 3.2.49 0x46, 0x47 Signal Level Meter Register (sim_low, slm_high).............. 60 3.2.50 0x48, 0x49 Far-End Level Meter Register (felm_low, felm_high)............ 60 O Rockwell N8970DSB VvTable of Contents Bt8970 Single-Chip HDSL Transceiver 3.2.51 Ox4A, 0x4B Noise Level Histogram Meter Register (noise_histogram_low, noise_histogram_high)......... 0... cece ete teens 60 3.2.52 0x4C, 0x4DBit Error Rate Meter Register (ber_meter_low, ber_meter_high) .................2.0 cee eee eee eaee 61 3.2.53 0x4E Symbol Histogram Meter Register (symbol_histogram).............. 61 3.2.54 0x50, 0x51 Noise Level Meter Register (nlm_low, nlm_high) .............. 61 3.2.55 Ox5E, Ox5F PLL Frequency Register (pll_frequency_low, pll_frequency_high) .............. cece eee eee eee 62 3.2.56 0x70 LEC Read Tap Select Register (linear_ec_tap_select_read)............ 62 3.2.57 0x71LEC Write Tap Select Register (linear_ec_tap_select_write)........... 62 3.2.58 0x72 NEC Read Tap Select Register (nonlinear_ec_tap_select_read) ........ 63 3.2.59 0x73 NEC Write Tap Select Register (nonlinear_ec_tap_select_write)........ 63 3.2.60 0x74 DFE Read Tap Select Register (dfe_tap_select_read) ................ 63 3.2.61 0x75 DFE Write Tap Select Register (dfe_tap_select_write)................ 63 3.2.62 0x76 Scratch Pad Read Tap Select (sp_tap_select_read) ................. 64 3.2.63 0x77 Scratch Pad Write Tap Select (sp_tap_select_write)................. 64 3.2.64 0x78 Equalizer Read Select Register (eq_add_read) .................005. 65 3.2.65 0x79 Equalizer Write Select Register (eq_add_write) .................0.. 66 3.2.66 0x7A Equalizer Microcode Read Select Register (eq_microcode_add_read) 0.2.0... eee tee eee 66 3.2.67 0x7B Equalizer Microcode Write Select Register (eq_microcode_add_write)...... 0... ccc cece ete 66 3.2.68 0x7C-0x7F Access Data Register (access_data_byte3:0) ................. 66 4.0 Electrical & Mechanical Specifications ................... 0... cece eee eee 67 4.1 Absolute Maximum Ratings........... 0.0... eect nae 67 4.2 Recommended Operating Conditions.............. 0... cee 68 4.3 Electrical Characteristics.... 0.0... 0. cette 69 4.4 Clock Timing .... 0.0... ect ttt 70 4.5 Channel Unit Interface Timing. .......... 0... cee cts 72 4.6 Microcomputer Interface Timing .......... 0.0... cece cette 76 4.6.1 Test and Diagnostic Interface Timing ......... 2... eee eee eee ees 81 4.6.2 Analog Specifications .. 0.0... 0. ees 83 4.6.3 Test Conditions... 0... tenet tenets 86 4.7 Timing Measurements. ........ 0.00.00 c etna 88 4.8 Mechanical Specifications...........0. 00.0 e cette 90 vi N8970DSB RockwellBt8970 List of Figures Single-Chip HDSL Transceiver List of Figures Figure 1-1. HDSLT1/E1 Terminal....... 0... cect ett 1 Figure 1-2. Bt8970 Detailed Block Diagram .. 0.1... cee teas 2 Figure 1-3. Pin Diagram 2... tent tna 5 Figure 2-1. Transmit Section Block Diagram ... 00... . cee 11 Figure 2-2. First-Order Echo Cancellation Using the Variable Gain Amplifier ................... 15 Figure 2-3. Receiver Digital Signal Processing.......... 0... cc cece eee ete 16 Figure 2-4. Digital Front-End Block Diagram ....... 0... cee ccc e es 17 Figure 2-5. Timing Recovery and Clock Interface Block Diagram. ........ cece ee eee eee 24 Figure 2-6. Serial Sign-Bit First Mode... 0.20... eee eee 26 Figure 2-7. Parallel Master Mode... 0.0... cece eee 26 Figure 2-8. Parallel Slave Mode .... 0... ete teens 27 Figure 4-1. MCLK Timing Requirements ...... 0.0... cc cece eee eet teed 70 Figure 4-2. Clock Control Timing... 0.0... tte tet t ene 71 Figure 4-3. Channel Unit Interface Timing, Parallel Master Mode............. 0... e cece eee eee 72 Figure 4-4. Channel Unit Interface Timing, Parallel SlaveMode............. ec cere ee eee ee 74 Figure 4-5. Channel Unit Interface Timing, Serial Mode... 1.0.0.0... . cece eee eee 75 Figure 4-6. MCI Write Timing, Intel Mode (MOTEL =0)........... cece eee eee 78 Figure 4-7. MCI Write Timing, MotorolaMode (MOTEL =1)........... eee eee eee eee 78 Figure 4-8. MCI Read Timing, Intel Mode (MOTEL =0)........... cee eee eee 79 Figure 4-9. MCI Read Timing, Motorola Mode (MOTEL =1) ........ cece eee eee 79 Figure 4-10. Internal Write Timing... 6... cette tte 80 Figure 4-11. JTAG Interface Timing .. 0... cece teen eteeee 82 Figure 4-12. SMON TIMING... 0... tne teens 82 Figure 4-13. Transmitted Pulse Template... 0... ees 85 Figure 4-14. Transmitter Test Circuit... 0.0... eee eee ae 86 Figure 4-15. Standard Output Load (Totem Pole and Three-State Outputs)..................0.. 87 Figure 4-16. Open-Drain Output Load (IRQ).... 0... eee teeta 87 Figure 4-17. Input Waveforms for Timing TeStS...... 00... cece eee eee teens 88 Figure 4-18. Output Waveforms for Timing Tests ........... 0c cece eects 88 Figure 4-19. Output Waveforms for Three-state Enable and Disable Tests...................005 89 Figure 4-20. 100-Pin Plastic Quad Flat Pack (POFP) .............. ccc e eet 90 @& Rockwell N8970DSB viiList of Figures Bt8970 Single-Chip HDSL Transceiver viii N8970DSB @ RockwellBt8970 List of Tables Single-Chip HDSL Transceiver List of Tables Table 1-1. Pin Descriptions... 00... .. cece teeta 6 Table 1-2. Hardware Signal Definitions... 0.0... cette 7 Table 2-1. Symbol Source Selector/Scrambler Modes ............... 0c cece eee eens 12 Table 2-2. Four-Level Bit-to-Symbol ConversionS..... 0... 0... cece eect eee 13 Table 2-3. Two-Level Bit-to-Symbol Conversions ........ 0.0... cece eee eee 13 Table 2-4. Two-Level Symbol-to-Bit Conversion. ..... 00.0... ccc cect eee 21 Table 2-5. | Four-Level Symbol-to-Bit Conversion... ..... cee ee eee eee eee eee 22 Table 2-6. Crystal Oscillator Circuit Component Values ....... 0... cece cece eee 25 Table 2-7. TIMES 2... nett teeta 31 Table 2-8. JTAG Device Identification Register... 0... eects 32 Table 3-1. Register Table... 0... eee tenets 34 Table 4-1. AbsoluteMaximum RatingS...... 0... 0... cece eee ees 67 Table 4-2. _ Recommended Operating Conditions... 0.0... . cc cece eects 68 Table 4-3. Electrical Characteristics 0.0... cette eens 69 Table 4-4. External Clock Timing Requirements (MCLK)............. 0. cece eee eee eee 70 Table 4-5. HCLK Switching Characteristics... 0.0... 70 Table 4-6. Symbol Clock (QCLK) Switching Characteristics ........... 0.0... ccc eee eee eee 71 Table 4-7. Channel Unit Interface Timing Requirements, Parallel Master Mode................ 72 Table 4-8. Channel Unit Interface Switching Characteristics, Parallel Master Mode............. 72 Table 4-9. Channel-Unit Interface Timing Requirements, Parallel Slave Mode................. 73 Table 4-10. Channel Unit Interface Switching Characteristics, Parallel Slave Mode .............. 73 Table 4-11. Channel Unit Interface Timing Requirements, SerialMode ...................005. 74 Table 4-12. Channel Unit Interface Switching Characteristics, Serial Mode .................00. 74 Table 4-13. Microcomputer Interface Timing Requirements......... 0... cette eee eee eee 76 Table 4-14. Microcomputer Interface Switching CharacteristicS....... 0... cece eee eee a7 Table 4-15. Test and Diagnostic Interface Timing Requirements ........... 2... cece eee eee eee 81 Table 4-16. Test and Diagnostic Interface Switching Characteristics .......... 0... eee eee 81 Table 4-17. Receiver Analog Requirements and Specifications............... 000 cece eee eee 83 Table 4-18. Transmitter Analog Requirements and Specifications ................... 00 eee 84 Table 4-19. Transmitted Pulse Template... 2... ike ee ttt eens 85 Table 4-20. Transmitter Test Circuit Component Values ......... 0... cece eee eee 87 @& Rockwell N8970DSB ixList of Tables Bt8970 Single-Chip HDSL Transceiver X N8970DSB @ Rockwell1.0 System Overview 1.1 Functional Summary The Bt8970 HDSL transceiver is an integral component of Rockwell's HDSL chipset. System performance of the chipset allows 2-pair T1, 2-pair El, and 3- pair El transmission. The major building blocks of a typical HDSL T1/E1 termi- nal are shown in Figure 1-1. Figure 1-1. HDSL T1/E1 Terminal + < Transformer HDSL Bt8970 : and Twisted ~ Transceiver Hybrid Pair T1/E1 Receive +4 Bts069B fe Bts360/70 fe] BtS953A Line T1 Framer T1/E1 Interface or HDSL Bt8970 Transformer HDSL TH/E4 Unit Bt8510 Channel Transceiver and > Twisted Transmit#| (T1 Only) --*|E1 Framer--] Unit . a *] Hybrid Pair Line | ee re ee ee ee fine ns Sees meme ~t | Transformer | HDSL | Bt8970 and {> Twisted > Transceiver _| Hybrid Pair | | | OPTIONAL THIRD PAIR | ee Ee ee SC _ _ al O Rockwell N8970DSB 11.0 System Overview Bt8970 1.1 Functional Summary Single-Chip HDSL Transceiver The Bt8970 comprises five major functions: a transmit section, a receive sec- tion, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. Figure 1-2 details the connections within and between each of these functional blocks. Figure 1-2. Bt8970 Detailed Block Diagram Receive Section RXP - Digital Receive Echo wm RQ[1)//RDAT RXN > re ADC OF Front canceller [-#] Equalizer }##| Detector Channel ] VGA Interface Ff RQ[OVBCLK RXBP. > A RXBN > eo | RBCLK | + 1 . Timing we HCOLK Microcomputer } Recovery/ aoLk Interface and = . System Control Clock Multiplier AD[7:0] > 6 | ! XTALI/MCLK ADDRI[?:0] > ontro| Crystal XTALO and Amplifier MUXED tr status > XOUT Registers MOTEL > WR/R/W | Microcomputer = RBIAS RD/DS - Interface = VCOMO ie te neterence | [von ALE 2 Generator mVCCAP RST al &VRXP,VRXN pee Timers _ READY ~e mVTXP,VTXN IRQ~# Diag- _ nostics = SMON TMS at TDI JTAG TCK = TDO Transmit Section | | | soi ~<tt i Transmit TXP Line Pulse- Vatable- . Symbor _ Channel TQ[1VTDAT Driver Shaping ain Scrambler] Unit TXN-# L Filter DAC Interface ft TQ[O] TXLOIN! Yoxpen TXLDIP TXPSP 2 N8970DSB #& RockwellBt8970 1.0 System Overview Single-Chip HDSL Transceiver 1.1 Functional Summary 1.1.1 Transmit Section The source of transmitted symbols is programmable through the microcomputer interface. The primary choices include external 2B1Q-encoded data presented to the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back receive symbols from the detector, or a constant all ones source. The symbols are then optionally scrambled. Isolated pulses can also be generated to support the testing of pulse templates. The digital symbols are transformed to an analog signal via the DAC, which is highly linear in order to maximize the echo cancellation and detection properties of the signal. In addition, the transmit power level of the DAC may be adjusted via the Transmitter Gain Register [tx_gain; 0x29] to optimize performance. The Transmitter Calibration Register [tx_calibrate; 0x28] contains the nominal setting for the transmitter gain which is calibrated and hard-coded at the factory. The pulse-shaping filter then conditions the signal to prevent crosstalk to adjacent sub- scriber lines. Finally, the differential line driver provides the current driving capa- bilities and low-distortion characteristics needed to drive a large range of subscriber lines at low-bit error rates. 1.1.2 Receive Section The differential Variable Gain Amplifier (VGA) receives the data from the sub- scriber line. Balancing inputs (RXBP, RXBN) are provided to accommodate first- order transmit echo cancellation via an external hybrid. The gain is programma- ble so that the dynamic range of the Analog-to-Digital Converter (ADC) can be maximized according to the attenuation of the subscriber line. Digitized receive data is passed to the Digital Signal Processor (DSP) portion of the Bt8970. After DC offset cancellation, a replica of the transmit signal is sub- tracted from the total receive signal by a digital echo canceller. The resultant far- end signal is then conditioned by an equalization stage consisting of Automatic Gain Control (AGC), a feed-forward equalizer, a decision-feedback equalizer, and an error predictor. A mode-dependent detector is then used to recover the 2B1Q-encoded data from the equalized signal. The channel unit interface then provides an optional descrambling function followed by parallel or serial output of the sign and magnitude bits on pins RQ[1,0]/RDAT. A number of meters are implemented within the receiver to provide average level indications at various points in the receive signal path. The receive section also performs remote unit clock recovery through an on-chip Phase Lock Loop (PLL) circuit. 1.1.3 Timing Recovery and Clock Interface The clock interface includes a crystal amplifier module to reduce the external components needed for clock generation. The crystal frequency must be 16 times the desired symbol rate. When configured as a remote unit, the PLL module recovers the incoming data clock and outputs it on the QCLK pin (and also the BCLK pin for serial mode operation). The HCLK output, which is synchronized to the QCLK signal, can be configured to cycle at 16, 32, or 64 times the symbol rate. @& Rockwell N8970DSB 31.0 System Overview Bt8970 1.1 Functional Summary Single-Chip HDSL Transceiver 1.1.4 Microcomputer Interface The Microcomputer Interface (MCI) provides access to a 256-byte address space within the transceiver. A combination of direct and indirect addressing methods are used to access all internal locations. The MCI is designed to interface with both Intel- and Motorola-style processors with no additional glue logic. A MOTEL control pin is provided to configure the bus interface control/handshake lines to conform to common Motorola/Intel conventions. A MUXED control pin is provided to configure the bus interface address and data lines for multiplexed or independent data/address bus operation. Little-endian data formatting (least sig- nificant byte of a multibyte word stored at the lowest byte-address location) is used in all cases, regardless of MOTEL pin selection. A READY control pin is provided to support wait-state insertion. An Interrupt Request (IRQ) output pin supports low-latency responses to time-critical events within the transceiver. Eight 16-bit timers and ten measurement meters are integrated into the trans- ceiver. The timers support various metering functions within the receiver section and off-load the external microcomputer from complex timing operations associ- ated with startup procedures. Control and monitoring access to the timers and meters is provided through the microcomputer interface. 1.1.5 Test and Diagnostic Interface (JTAG) The Test and Diagnostic Interface comprises a test access port and a Serial Moni- tor Output (SMON). The test access port conforms to IEEE Std 1149.1-1990, (IEEE Standard Test Access Port and Boundary Scan Architecture). Also referred to as Joint Test Action Group (JTAG), this interface provides direct serial access to each of the transceivers I/O pins. This capability can be used during an in-cir- cuit board test to increase the testability and reduce the cost of the in-circuit test process. The serial monitor output can be viewed as a real-time virtual probe for look- ing at the transceivers internal signals. The programmable signal source is shifted out serially at 16 times the symbol rate. The majority of the receive signal path is accessible through this output. 4 N8970DSB @ RockwellBt8970 1.0 System Overview Single-Chip HDSL Transceiver 1.2 Pin Descriptions 1.2 Pin Descriptions The Bt8970 is packaged in a 100-Pin Plastic Quad Flat Pack (PQFP). The pin assignments are shown in Figure 1-3. A listing of pin labels, numbers, and I/O assignments is given in Table 1-1. Signal definitions are provided in Table 1-2. The coding used in the I/O column is: O = digital output, OA = analog output, OD = open-drain output, I = digital input, [A = analog input, and I/O = bidirec- tional. Figure 1-3. Pin Diagram ve ge 6 KO [LO me QQq lp SM=ny ara 58S Sa OHH OS SSO S55RGS AaSPFFFbberee*6Frasds OOOO OOOO OOO OoOwmorRowWU TMNT OAAMArROWTMOAS ODAAAAIAIAIAIAMHAADDDDDDDA DO VDD1 Fy 108 804 RXBN _ oS Cf 2 79] RXBP _RD/DS CL] 3 784 RXN WRIRWW Co 4 77 ~RXP ALE 5 76 [4 AGND IRQ cy 6 75 [4 AGND READY Cy] 7 74 TXN AD[O] CL] 8 731] AGND AD[1] [4 9 7214 VAA AD[2] (4 10 71 TXP AD[3] (4 11 7014 TXLDIN AD[4] Cy 12 694 ~TXLDIP AD[5] Cy 13 68141 TXPSN note i is 67 TXPSP Cy 66 [4 ATEST2 DGND C4 16 Bts970 65{4 ATEST1 VDD2 Cy 17 649 VAA AD[7] Cy 18 63 VAA MOTEL CF] 19 62[O AGND MUXED C4 20 61 VTXN ADDR[7] C] 21 60 ~VTXP ADDR[6] [] 22 591-1 VCCAP ADDR[5] CF] 23 581 ~VCOMO ADDR[4] [] 24 57 ~VCOMI ADDR[3] E] 25 56[- RBIAS ADDR[2] CE} 26 55 VAA ADDR[1] CE} 27 549 VAA ADDR[O] C4 28 531 AGND SMON CL] 29 52(9) VRXN VDD1 [ 30 51] VRXP TNOTWO OR DMAOTYTAMTOOR DAO YOMMNMNOMNMANMMAMYT TAY TITtTTTw WVU UUUUUUUUUUUUUUUUUU Y aa i aa st BoA S5SaQSaor Re AoFOS SGOMOOgODKOSONRASONGG aag> Txa-Cs7operp"-apete a qaaa a = ~~ 6) Rockwell N8970DSB 51.0 System Overview Bt8970 1.2 Pin Descriptions Table 1-1. Pin Descriptions Single-Chip HDSL Transceiver Pin} jf, | vo || Pin | Pintabel | vo |} Pin | jf" | vO || Pin | Pintabel | 6 1 VDD1 - 26 ADDR[2] | 51 VRXP OA 76 AGND - 2 cs | 27 ADDR{1] | 52 VRXN OA 77 RXP IA 3 RD/DS | 28 ADDR[O] | 53 AGND - 78 RXN IA 4 WR/R/W | 29 SMON 0 54 VAA - 79 RXBP IA 5 ALE | 30 VDD1 - 55 VAA - 80 RXBN IA 6 IRQ oD 31 DGND - 56 RBIAS OA 81 VAA - 7 READY | OD 32 DGND - 57 VCOMI OA 82 AGND - 8 AD[0] /0 33 VDD2 - 58 VCOMO | OA 83 VDD1 - 9 AD[1] /0 34 RST | 59 VCCAP OA 84 DGND - 10 AD[2] /0 35 HCLK 0 60 VTXP OA 85 | TOQ1/TDAT | | 11 AD[3] /0 36 XOUT 0 61 VTXN OA 86 TQ(0] | 12 AD[4] /0 37 DGND - 62 AGND - 87 QCLK 0 13 AD[5] /0 38 VDD1 - 63 VAA - 88 | RQ[1]/RDAT | O 14 AD[6] /0 39 XTALO 0 64 VAA - 89 | RQ[OJ/BCLK | O 15 DGND - 40 | XTALI/MCLK | | 65 ATEST1 IA 90 RBCLK | 16 DGND - 44 VPLL - 66 ATEST2 IA 91 TBCLK | 17 VDD2 - 42 PGND - 67 TXPSP OA 92 DTEST5 | 18 AD[7] /0 43 DTEST1 | 68 TXPSN OA 93 DTEST6 | 19 MOTEL | 44 DTEST2 | 69 TXLDIP IA 94 TDO 0 20 | MUXED | 45 DTEST3 | 70 TXLDIN IA 95 TDI | 21 | ADDR[7] | 46 VPLL - 71 TXP OA 96 TS | 22 | ADDR[6] | 47 PGND - 72 VAA - 97 TCK | 23 | ADDR[S5] | 48 DTEST4 73 AGND - 98 vDD2 - 24 | ADDR[4] | 49 AGND - 74 TXN OA 99 DGND - 25 | ADDR[3] | 50 AGND - 75 AGND - 100 DGND - 6 N8970DSB O RockwellBt8970 1.0 System Overview Single-Chip HDSL Transceiver 1.2 Pin Descriptions Table 1-2. Hardware Signal Definitions (1 of 4) Pin Label Signal Name 0 Definition Microcomputer Interface (MCI) MOTEL Motorola/intel | Selects between Motorola and Intel handshake conventions for the RD/DS and WR/R/W signals. _ MOTEL = 1 for Motorola protocol: DS, R/W MOTEL = 0 for Intel protocol: RD, WR ALE Address Latch Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or Enable ADDR[7:0] when MUXED = 0, is internally latched on the falling edge of ALE. CS Chip Select Active-low input used to enable read/write operations on the Microcomputer Interface (MCI). RD/DS Read/Data Strobe Bimodal input for controlling read/write access on the MCI. __When MOTEL = 1 and CS = 0, RD/DS behaves as an active-low data strobe DS. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data is internally latched from AD[7:0] on the rising edge of DS when R/W = 0. ___When MOTEL = 0 and CS = 0, RD/DS behaves as an active-low read strobe RD. Internal data is output on AD[7:0] when RD = 0. Write operations are not controlled by RD in this mode. WR/R/W Write/ Bimodal input for controlling read/write access on the MCI. Read/Write _When MOTEL = 1 and CS = 0, WR/R/W behaves as a read/write select line R/W. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data is internally latched trom AD[7:0] on the rising edge of DS when R/W = 0. ___When MOTEL = 0 and CS = 0, WR/R/W behaves as an active-low write strobe WR. External data is internally latched from AD[7:0] on the rising edge of WR. Read operations are not controlled by WRin this mode. AD[7:0] Address- /0 8-bit bidirectional multiplexed address-data bus. AD[7] = MSB, AD[0] = LSB. Data[7:0] Usage is controlled using the MUXED. ADDR[?:0] Address Bus (not Provides a glueless interface to microcomputers with separate address and data multiplexed)[ 7:0] buses. ADDR[7] = MSB, ADDR[0] = LSB. Usage is controlled using the MUXED. MUXED Addressing Controls the MCI addressing mode. Mode Select When MUXED = 1, the MCI uses AD[7:0] as a multiplexed signal for address and data (typical of Intel processors). When MUXED = 0, the MCI uses ADDR[7:0] as the address input, and AD[7:0] for data only (typical of Motorola processors). READY Ready OD Active-low, open-drain output that indicates that the MCI is ready to transfer data. Can be used to signal the microcomputer to insert wait states. IRQ Interrupt Request OD Active-low, open-drain output that indicates requests for interrupt. Asserted whenever at least one unmasked interrupt flag is set. Remains inactive whenever no unmasked interrupt flags are present. RST Reset Asynchronous, active-low, level-sensitive input that places the transceiver in an inactive state by setting the power-down mode bit of the Global Modes and Sta- tus Register [global_modes; 0x00], and zeroing the clk_freq[ 1,0] bits of the PLL Modes Register [pll_modes; 0x22] and the hclk_freq[1,0] bits of the Serial Mon- itor Source Select Register [serial_monitor_source; 0x01]. All RAM contents are lost. Does not affect the state of the test access port which is reset automatically at power-up only. @& Rockwell N8970DSB 71.0 System Overview Bt8970 1.2 Pin Descriptions Single-Chip HDSL Transceiver Table 1-2. Hardware Signal Definitions (2 of 4) Pin Label Signal Name VO Definition Channel Unit Interface RQ[1]/ RDAT RQ{O]/ BCLK Receive Quat 1/ Receive Data Receive Quat 0/ Bit Clock RQ[1]/RDAT and RQ[0]/BCLK are bimodal outputs that represent the sign and magnitude bits of the received quaternary output symbol in parallel channel unit modes (RQ[1], RQ[0]), and the serial-data and bit-clock outputs in serial chan- nel unit modes (RDAT, BCLK). Behavior of these outputs is configurable through the Channel Unit Interface Modes Register [CU_interface_modes; 0x06] for par- allel master, parallel slave, serial magnitude-bit-first and serial sign-bit-first operations. For parallel mode operation: RQ[1] = Sign bit output RQ[0] = Magnitude bit output Both outputs are updated at the symbol rate on the rising edge of QCLK (master mode) or the rising/falling edge (programmable) of RBCLK (slave mode). For serial mode operation: RDAT = Serial quaternary data output BCLK = Bit-rate (two times symbol rate) clock output RDAT is updated at the bit rate on the rising edge of BCLK TQ[1]/ TDAT TQ[0] Transmit Quat 1/ Transmit Data Transmit Quat 0 TQ[1]/TDAT and TQ[0] are bimodal inputs that represent the sign and magnitude bits of the quaternary input symbol to be transmitted in parallel channel unit modes (TQ[1], TQ[0]), and the serial data input in serial channel unit modes (TDAT). Interpretation of these inputs is configurable through the Channel Unit Interface Modes Register [CU_Interface_modes; 0x06] for parallel master, par- allel slave, serial magnitude-bit-first and serial sign-bit-first operations. For parallel mode operation: TQ[1] = Sign bit input TQ[0] = Magnitude bit input Both inputs are sampled at the symbol rate on the falling edge of QCLK (mas- ter mode) or the rising/falling edge (programmable) of TBCLK (slave mode). For serial mode operation: TDAT = Serial quaternary data input TQO = Dont care (tie or pull up to supply rail) TDAT is sampled at the bit rate (two times the symbol rate) on the falling edge of BCLK. QCLK Quaternary Clock Runs at the symbol rate. It defines the data on the TQ and RQ interfaces. QCLK is also used to frame transmit/receive quats in serial mode. TBCLK Transmit Baud- Rate Clock Functions as the transmit baud-rate clock input. It must be frequency locked to QCLK. This input is used only when the channel unit interface is in parallel slave mode. If it is unused, it should be tied to VDD2 or DGND. RBCLK Receive Baud- Rate Clock Functions as the receive baud-rate clock input. It must be frequency locked to QCLK. This input is used only when the channel unit interface is in parallel slave mode. If it is unused, it should be tied to VDD2 or DGND. N8970DSB @ RockwellBt8970 1.0 System Overview Single-Chip HDSL Transceiver 1.2 Pin Descriptions Table 1-2. Hardware Signal Definitions (3 of 4) Pin Label Signal Name 0 Definition Analog Transmit Interface TXP, TXN Transmit Positive, OA Differential Transmit Line Driver Outputs. These signals are used to drive the Negative subscriber line after passing through the hybrid and line transformer. TXLDIP, Transmit Line IA Differential Transmit Line Driver Inputs. These inputs should be connected to the TXLDIN Driver In Positive, TXPSP, TXPSN outputs after passing through an external RC filter. Negative TXPSP, Transmit Pulse- OA Differential Transmit Pulse-Shaping Filter Outputs. These outputs should be con- TXPSN Shaping Filter nected to an external RC filter, which is then connected to the TXLDIP and TXL- Positive, Negative DIN inputs. Analog Receive Interface RXP, RXN Receive Positive, IA Differential Receiver Inputs. RXP and RXN receive the signal from the subscriber Negative line. RXBP, RXBN Receive Balance IA Differential Receiver Balance Inputs. RXBP and RXBN are used to subtract the Positive, Negative echo of the signal being transmitted on the subscriber line. They should be con- nected to the TXP, TXN output pins through the hybrid circuit. This signal is sub- tracted from the signal being received by the RXP and RXN inputs in the Variable Gain Amplifier (VGA). Voltage Reference Generator Interface RBIAS Resistor Bias OA Connection point for external bias resistor. VCOMO Common Mode OA Common mode voltage for the analog circuitry. This pin should be connected to Voltage Outputs an external filtering capacitor. VCOMI Common Mode OA Common mode voltage for the analog circuitry. This pin should be connected to Voltage Inputs an external filtering capacitor. VCCAP Voltage Compen- OA Analog Voltage Compensation Capacitor. This pin should be connected to an sation Capacitor external filtering capacitor. VRXP, VRXN Receiver Voltage OA Analog Receive Circuitry Reference Voltages. These pins should be connected to Reference Posi- external filtering capacitors. tive, Negative VTXP, VTXN Transmit Voltage OA Analog Transmit Circuitry Reference Voltages. These pins should be connected Reference Posi- to external filtering capacitors. tive, Negative Clock Interface XTALI/ Crystal In/Master A bimodal input that can be used as the crystal input or as the master clock MCLK Clock input. If an external clock is connected to this input, XTALO should be left float- ing. The frequency of the crystal or clock should be 16 times the symbol rate (8 times the data rate). XTALO Crystal Output Connection point for the crystal. HCLK High Speed 0 HCLK can be configured to run at 16, 32, or 64 times the symbol rate. Upon Clock Out reset, it is set to 16 times the symbol rate. This clock will be phase locked to the incoming data when the Bt8970 is configured as the remote unit. XOUT Crystal Clock Out 0 Buffered-crystal oscillator output. @& Rockwell N8970DSB 91.0 System Overview Bt8970 1.2 Pin Descriptions Single-Chip HDSL Transceiver Table 1-2. Hardware Signal Definitions (4 of 4) Pin Label Signal Name 0 Definition Test and Diagnostic Interface TDI JTAG Test Data JTAG test data input per IEEE Std 1149.1-1990. Used for loading all serial Input instructions and data into internal test logic. Sampled on the rising edge of TCK. TDI can be left unconnected if it is not being used because it is pulled-up inter- nally. TMS JTAG Test Mode JTAG test mode select input per IEEE Std 1149.1-1990. Internally pulled-up Select input signal used to control the test-logic state machine. Sampled on the rising edge of TCK. TMS can be left unconnected if it is not being used because it is pulled-up internally. TDO JTAG Test Data 0 JTAG test data output per IEEE Std 1149.1-1990. Three-state output used for Output reading all serial configuration and test data from internal test logic. Updated on the falling edge of TCK. TCK JTAG Test Clock JTAG test clock input per IEEE Std 1149.1-1990. Used for all test interface and Input internal test logic operations. If unused, TCK should be pulled low. SMON Serial Monitor 0 Serial data output used for real-time monitoring of internal signal-path registers. The source register is selected through the Serial Monitor Source Select Regis- ter [serial_monitor_source; 0x01]. 16-bit words are shifted out, LSB first, at 16 times the symbol rate. The rising edge of QCLK defines the start Least Signif- icant Bit (LSB) of each word. The output is updated on the rising edge of an internal clock running at 16 times QCLK. DTEST[ 1:4] Digital Tests 1-4 Active-high test inputs used by Rockwell to enable internal test modes. These inputs should be tied to Digital Ground (DGND). DTEST[5, 6] Digital Test 5, 6 Active-low test inputs used by Rockwell to enable internal test modes. These inputs should be tied to the I/O buffer power supply (VDD2). ATEST[1,2] Analog Test 1, 2 IA Analog test inputs used by Rockwell for internal test modes. These inputs should be left floating (No Connect, NC). Power and Ground VDD1 Core Logic Power - Dedicated supply pins powering the digital core logic functions. Can be con- Supply nected to +5 V or 3.3 V. VDD2 1/0 Buffer Power - Dedicated supply pins powering the digital I/O buffers. Supply VPLL PLL Power Sup- - Dedicated supply pins powering the PLL and the crystal amplifier. ply PGND PLL Ground - Dedicated ground pins for the PLL and the crystal amplifier. Must be held at the same potential as DGND and AGND. DGND Digital Ground - Dedicated ground pins for the digital circuitry. Must be held at same potential as AGND and PGND. VAA Analog Power - Dedicated supply pins powering the analog circuitry. Supply AGND Analog Ground - Dedicated ground pins for the analog circuitry. Must be held at the same poten- tial as DGND and PGND. 10 N8970DSB @ Rockwell2.0 Functional Description 2.1 Transmit Section The transmit section is illustrated in Figure 2-1. It comprises four major func- tions: a symbol source selector/scrambler, a variable gain digital-to-analog con- verter (DAC), a pulse-shaping filter, and a line driver. Figure 2-1. Transmit Section Block Diagram Transmit Channel Unit | Symbol . . - . TQ[1,0] } erface tree) |e Variable-Gain ue Line |_|. TxP apin ; ~ Scrambler DAC Filter: Driver TXN A Isolated Pulses Detector Loopback Ones (1s) Control Registers External |_| RC Filter O Rockwell N8970DSB 112.0 Functional Description Bt8970 2.1 Transmit Section Single-Chip HDSL Transceiver 2.1.1 Symbol Source Selector/Scrambler The input source selector/scrambler can be configured through the Transmitter Modes Register [transmitter_modes; OxOB] data_source [2:0] bits to select the source of the data to be transmitted and determine whether or not the data is scrambled. The symbol source selector/scrambler modes are specified in Table 2-1. Table 2-1. Symbol Source Selector/Scrambler Modes data_source[2:0] Symbol Source Selector/Scrambler Mode 000 Isolated pulse. Level selected by isolated_pulse[ 1,0]. The meter timer must be enabled and in the con- tinuous mode. The pulse repetition interval is determined by the meter-timer-countdown interval. 001 Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are scram- bled and looped back to the transmitter. Feedback polynomial determined by the htur_lfsr control bit. 010 Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the transmit channel unit. 011 Four-level scrambled ones. Transmits a scrambled, constant high-logic level as a four-level (2B1Q) sig- nal. Feedback polynomial determined by the htur_lfsr control bit. 100 Reserved. 101 Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit. 110 Two-level unscrambled data. Constantly forces the magnitude bit from the transmit channel unit inter- face to a logic zero, and transmits the resulting two-level signal (as determined by the sign bit) without scrambling. Valid output levels limited to +3, -3. 111 Two-level scrambled ones. Transmits a scrambled, constant high-logic level, as a two-level signal. Feed- back polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a constant logic zero. Valid output levels limited to +3, -3. 12 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver The bit stream is converted into symbols for the four-level cases as shown in Table 2-2. Table 2-2. Four-Level Bit-to-Symbol Conversions 2.1 Transmit Section Fi Aaa Bit aan) Output Symbol 0 0 3 0 1 a { 1 +1 { 0 +3 In two-level mode, the magnitude bit is forced to a zero. This forces the sym- bols to be +3 and 3, as shown in Table 2-3. Table 2-3. Two-Level Bit-to-Symbol Conversions First Input Bit Second Input Bit (sign) (magnitude) Output Symbol 0 dont care -3 1 dont care +3 The scrambler is essentially a 23-bit-long Linear Feedback Shift Register (LFSR). The feedback points are programmable for central office and remote ter- minal applications using the htur_Ifsr bit of the Transmitter Modes Register. The LFSR polynomials for local (HTU-C/LTU) and remote (HTU-R/NTU) unit oper- ations are: local >x-3 @x5@1 remote>x23@x8O@1 The scrambler operates differently depending on whether a two-level or four- level mode is specified. In two-level scrambled-ones mode, the LFSR is clocked once-per-symbol; in four-level mode, the LFSR is clocked twice-per-symbol. The Transmitter Modes Register can also be used to zero the output of the transmitter using the transmitter_off control bit. The Bt8970 can generate isolated pulses to support the testing of pulse tem- plates. When in the isolated pulse mode, the output consists of a single pulse sur- rounded by zeros. noTe: Zero is not a valid 2B1Q level and only occurs in this special mode or when the transmitter is off. The repetition rate of the pulses is controlled by the meter timer. Any of the four 2B1Q levels may be chosen via the Transmitter Modes Registers isolated_pulse[1,0] control bits. O Rockwell N8970DSB 132.0 Functional Description Bt8970 2.1 Transmit Section Single-Chip HDSL Transceiver 2.1.2 Variable Gain Digital-to-Analog Converter A four-level Digital-to-Analog Converter (DAC) is integrated into the Bt8970 to accurately convert the output of the symbol source to analog form. The normal- ized values of these four analog levels are: +3, +1, 1 and 3. Each represents a symbol or quat. To provide precise adjustment of the transmitted power, the level of the DAC may be adjusted. The Transmitter Gain Register [tx_gain; 0x29] sets the level. During the manufacturing of the Bt8970, one source of variation in the trans- mitter levels is process variations. The Transmitter Calibration Register [tx_calibrate; 0x28] contains a read-only value which nulls this variation. The value of this register is determined for each Bt8970 device during production test- ing. Upon initialization, the Transmitter Gain Register should be loaded based on the transmitter calibration register. If there are other sources of transmit power variation (e.g., a nonstandard hybrid or attenuative lightening protection), the transmitter gain must be adjusted to include these affects. 2.1.3 Pulse-Shaping Filter 2.1.4 Line Driver The pulse-shaping filter filters the quats output from the variable-gain DAC. This filter, when combined with other filtering in the signal path, produces a transmit- ted signal on the line that meets the power spectral density, transmitted power, and pulse-shaping requirements, as specified in the Electrical Specifications sec- tion of this datasheet. The line driver buffers the output of the pulse-shaping filter to drive diverse loads. The output of the line driver is differential. 14 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.2 Receive Section 2.2 Receive Section Like the transmit section, the receive section consists of both analog and digital circuitry. The Variable Gain Amplifier (VGA) provides the interface to the analog signals received from the line and the hybrid. The Analog-to-Digital Converter (ADC) then digitizes the analog signal so it can be further processed in the Digital Signal Processing (DSP) section of the receiver. The receiver DSP section includes: front-end processing, echo cancellation, equalization, and symbol detection. 2.2.1 Variable Gain Amplifier The Variable Gain Amplifier (VGA) has two purposes. The first is to provide a dual-differential analog input so the pseudo-transmit signal created by the hybrid can be subtracted from the signal from the line transformer. This subtraction pro- vides first-order echo cancellation, which results in a first-order approximation of the signal received from the line. Figure 2-2 illustrates the recommended echo- cancellation circuit interconnections. All off-chip circuitry, including the hybrid and anti-alias filters, consists entirely of passive components. Further echo can- cellation occurs in the receiver DSP. Figure 2-2. First-Order Echo Cancellation Using the Variable Gain Amplifier Line Transformer + Anti-alias Filter Line (Twisted Pair) To ADC WW * Line = Driver ae RXBP Matching | P| Anti-alias Gain[2:0] Resistors _ Hybrid Filter RXBN I | | | NNN Lo | | | | I Off-Chip Circuitry The second purpose of the VGA is to provide programmable gain of the received signal prior to passing it to the ADC. This reduces the resolution required for the ADC. There are six gain settings ranging from 0 dB to 15 dB. The gain is controlled via the gain[2:0] control bits in the ADC Control Register [adc_control; 0x21]. See the Registers section of this datasheet for a more detailed description of the gain[2:0] control bits. @& Rockwell N8970DSB 152.0 Functional Description Bt8970 2.2 Receive Section Single-Chip HDSL Transceiver 2.2.2 Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) provides 16 bits of resolution. The ana- log input from the variable gain amplifier is converted into digital data and output at the symbol rate. 2.2.3 Digital Signal Processor The Digital Signal Processor (DSP) includes five Least Mean Squared (LMS) fil- ters: an Echo Canceller (EC), a Digital Automatic Gain Controller (DAGC), a Feed Forward Equalizer (FFE), an Error Predictor (EP), and a Decision Feedback Equalizer (DFE). These filters are used to equalize the received signal so that the symbols transmitted from the far-end can be reliably recovered. The DSP uses symbol rate sampling for all processing functions. Their interconnections and relationships to the digital front-end and the detector are illustrated in Figure 2-3. Figure 2-3. Receiver Digital Signal Processing r Detector Ch | Digital me Onit Front-End Interface Transmit Symbol 16 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.2.3.1 Digital Front-End 2.2 Receive Section Prior to the main signal processing, the input signal must be adjusted for any DC offset. The front-end module also monitors the input signal level, which includes measuring DC and AC input signal levels, detecting and counting overflows, and detecting alarms based on the far-end signal level. Figure 2-4 summarizes the fea- tures of the digital front-end module. Figure 2-4. Digital Front-End Block Diagram rc ToT 41 Cc TtcTT 4 High Threshold Fenn Absolute | | 3 from MCI + Comparator I high_felm from NEC Value | | | Interrupt If! | | A | | | C | low_felm | [Accumulator] | Low Threshold _ | omparator |" Interrupt from MCl | ! | | Far-End | Result : Alarms | Register | b------dJ | | | Far-End | Level Meter + r, To EC ADC Data Cp > 7 [7 ~ TF TT PT I | | | Absolute | | Accumulator | | Value | Dc Offset | | 1 | from MCI | | | Result 7 A | | Register l ccumulator l | | | ti! | | | Result | Register | | | | DC Level 11 Signal Level | Meter Meter Le ee IL Se r =|" 7-7-7 TTT 4 | Overflow | | | | ! | Overflow Counter | | Detector | | | Result | | Register | | ; | Overflow Monitor Lee SO 4 O Rockwell N8970DSB 172.0 Functional Description Bt8970 2.2 Receive Section 2 2.2.3.2 Offset Adjustment .2.3.3 DC Level Meter 2.2.3.4 Signal Level Meter 2.2.3.5 Overflow Detection and Monitoring 2.2.3.6 Far-End Level Meter 2.2.3.7 Far-End Level Alarm Single-Chip HDSL Transceiver A nonzero DC level on the input can be corrected by a DC offset value [dc_offset_low, dc_offset_high; 0x26, 0x27] which is subtracted from the input. The DC offset is a 16-bit number and is programmed via the microcomputer interface. The DC level meter provides the monitoring needed for adaptive offset compen- sation. The offset-adjusted input signal is accumulated over the meter timer inter- val [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed into the DC Level Meter Registers [dc_meter_low, dc_meter_high; 0x44, 0x45]. The signal level meter provides the monitoring needed for adjusting the analog gain circuit located prior to the ADC. This value is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed in the Signal Level Meter Registers [slm_low, slm_high; 1; 0x46, 0x47]. The overflow sensor detects ADC overflows. The overflow monitor counts the number of overflows, as indicated by the overflow sensor during the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The counter is limited to 8 bits. In the case of 256 or more overflows during the measurement interval, the counter will hold at 255. The counter is loaded into the Overflow Meter Register [overflow_meter; 0x42] at the end of each measurement interval. The far-end level meter monitors the output of the echo canceller. Since the echo canceller output had the echo of the transmitted signal subtracted from it, it is called the far-end signal. This value is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed into the Far-End Level Meter Register [felm_low, felm_high; 0x48, 0x49]. The result of the far-end level meter is compared to two thresholds. When exceeded, an interrupt is sent to the microcomputer interface, if enabled. The threshold is determined by the value in the Far-End High Alarm Threshold Regis- ters [far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30, 0x31] and the Far-End Low Alarm Threshold Registers [far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x32, 0x33]. The interrupts high_felm and low_felm, are bits 2 and 1, respectively of the IRQ Source Register [irq_source; 0x05]. The interrupts high_felm and low_felm, can be masked by writing a one to bits 2 and 1, respectively of the Interrupt Mask Register High [mask_high_reg; 0x03]. 18 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.2.4 Echo Canceller 2.2.4.1 Linear Echo Canceller (LEC) 2.2.4.2 Nonlinear Echo Canceller (NEC) 2.2 Receive Section The Echo Canceller (EC) removes images of the transmitted symbols from the received signal and consists of two blocks: a linear and nonlinear echo canceller. The organization of the blocks is displayed in Figure 2-3. The Linear Echo Canceller (LEC) is a conventional LMS, Finite Impulse Response (FIR) filter, which removes linear images of the transmitted symbols from the received signal. It consists of a 60-tap FIR filter with 32-bit linear adapted coefficients. When enabled, the last data tap of the echo canceller is treated specially. This serves to cancel any DC offset that may be present. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. An additional mode exists to zero the output of the FIR with no effect on the coefficients; it is also enabled through the microcomputer interface. Individual EC coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. The Nonlinear Echo Canceller (NEC) reduces the residual echo power in the echo canceller output caused by nonlinear effects in the transmitter DAC, receiver ADC, analog hybrid circuitry, or line cables. The delay of the transmit-symbol input to the NEC can be specified via the microcomputer interface, Nonlinear Echo Canceller Mode _ Register [nonlinear_ec_modes; 0x09]. This allows the NEC to operate on the peak of the echo regardless of differing delays in the echo path. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. An additional mode exists to zero the output of the look-up table with no effect on the coefficients. It is also enabled through the microcomputer interface. The 64, 14-bit, individual NEC coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. @& Rockwell N8970DSB 192.0 Functional Description Bt8970 2.2 Receive Section 2.2.5 Equalizer 2.2.5.1 Digital Automatic Gain Control (DAGC) 2.2.5.2 Feed Forward Equalizer (FFE) 2.2.5.3 Error Predictor (EP) 2.2.5.4 Decision Feedback Equalizer (DFE) 2.2.5.5 Microcoding Single-Chip HDSL Transceiver Four LMS filters are used in the equalizer to process the echo canceller output so that received symbols can be reliably recovered. The filters are a digital automatic gain controller, a feed forward equalizer, an error predictor, and a decision feed- back equalizer. Their interconnections are shown in Figure 2-3. The Digital Automatic Gain Control (DAGC) scales the echo-free signal to the optimum magnitude for subsequent processing. Its structure is that of an LMS fil- ter, but it is a degenerate case because there is only one tap. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient update only. The DAGC gain coefficient can be read or written through the microcomputer interface. Adaptation should be frozen prior to reading or writing the coefficient. The Feed Forward Equalizer (FFE) removes precursors from the received signal. The FFE may be operated in a special adapt last mode. In this mode, which is useful during startup, only the last coefficient is updated. The last coefficient is the one which is multiplied with the oldest data sample (sample #7). A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. Indi- vidual FFE coefficients can be read and written through the microcomputer inter- face. Adaptation should be frozen prior to reading or writing coefficients. The Error Predictor (EP) improves the performance of the equalizer by prognosti- cating errors before they occur. A freeze coefficient mode may be specified via the microcomputer interface. This mode disables the coefficient updates only. A special mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. Individual EP coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to read- ing or writing coefficients. The Decision Feedback Equalizer (DFE) removes postcursors from the received signal. A freeze coefficient mode may be specified via the microcomputer inter- face. This mode disables the coefficient updates only. A zero coefficients mode exists to zero all of the coefficients; it is also enabled through the microcomputer interface. A zero filter output mode exists to zero the output of the FIR with no effect on the coefficients. It is also enabled through the microcomputer interface. Individual DFE coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. The DAGC, FFE, and EP filters are implemented using an internal micropro- grammable Digital Signal Processor (DSP) optimized for LMS filters. Internal DSP micro-instructions are stored in an on-chip RAM. This microcode RAM is loaded after powerup through the microcomputer interface when the transceiver is initialized. 20 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.2.6 Detector 2.2.6.1 Slicer 2.2.6.2 Peak Detector 2.2.6.3 Error Signals 2.2.6.4 Scrambler (PKD) Module 2.2 Receive Section The detector converts the equalized received signal into a 2B1Q symbol and pro- duces two error signals used in adapting the receiver equalizers. The signal detec- tion uses two sub-blocks, a slicer, and a peak detector. Additionally, the detector contains a scrambler and Bit Error Rate (BER) meter for use during the startup sequence. The slicer thresholds the equalized signal to produce a 2B1Q symbol. The input to the slicer is the FFE output minus the DFE and EP outputs. The slicer can operate in two modes: two-level and four-level. In the two-level mode, used during the part of startup when the only transmitted symbols are +3 or 3, the slicer threshold is set at zero. When in four-level mode, the cursor level is specified via the microcomputer interface. It is a 16-bit, 2s complement number, but must be positive and less than Ox2AAA for proper operation. The PKD is only used during the two-level transmission part of startup. It oper- ates on the echo-free signal. A signal is detected to be a +3 if it is higher than both of its neighbors, or a 3 if it is lower than both of its neighbors. If neither of the peaked conditions exist, the output of the slicer is used. The detector computes two error signals for use in the equalizer: a 16-bit slicer and a 16-bit equalizer. The scrambler may operate as either a scrambler or as a descrambler. The scram- bler block is used during the scrambled-ones part of the startup sequence. This provides an error-free signal for equalizer adaptation. This scrambler is essen- tially a 23-bit-long Linear Feedback Shift Register (LFSR) with feedback. The feedback point depends on whether the transceiver is being used in a central- office or remote-terminal application. When operating as a descrambler, the input source is the detector output. The symbol is converted to a bit stream, as shown in Table 2-4 for the two-level case. Table 2-4. Two-Level Symbol-to-Bit Conversion Input Symbol Output Bit -3 0 +3 1 O Rockwell N8970DSB 212.0 Functional Description Bt8970 2.2 Receive Section 2.2.6.5 Sync Detector Single-Chip HDSL Transceiver The symbol is converted to a bit stream, as shown in Table 2-5 for the four- level case. Table 2-5. Four-Level Symbol-to-Bit Conversion 3 0 0 -1 0 1 +1 1 { +3 1 0 The LFSR operates in the same way in both cases, except in the two-level case it is clocked once-per-symbol and in the four-level case it is clocked twice-per- symbol. When operating as a scrambler, the LFSR must first be locked to the far-end source. Once locked, it is then able to replicate the far-end input sequence, when its input is held at all ones. The locking sequence is controlled internally, initiated through the microcomputer interface by setting the Ifsr_lock bit of the detector_modes register. The locking sequence consists of the following four steps: 1. Operate the LFSR as a descrambler for 23 bits. 2. Operate the LFSR as a scrambler for 127 bits. The syne detector is active during this period. 3. Go to Step 1 if synchronization was not achieved, otherwise continue to Step 4. 4. Send an interrupt to the microcomputer if unmasked, indicating successful locking and continue operating as a scrambler. The sequence continues until the lfsr_lock control bit is cleared by the micro- computer. The sync detector compares the output of the scrambler with the output of the symbol detector. The number of equivalent bits is accumulated for 128 compari- sons. The result is then compared to a Scrambler Synchronization Threshold Reg- ister [scr_sync_th; 0x2E], lock is declared, and the sync bit of the irq_source register is set if the count is greater than the threshold. For a count less than or equal to the threshold, no lock condition is declared and the sync bit is unaffected. 22 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.2.6.6 Detector Meters 2.2 Receive Section The detector consists of five meters: a BER meter, a symbol histogrammer, a noise-level meter, a noise-level histogram meter, and an SNR alarm meter. The BER meter provides an estimate of the bit error rate when the received symbols are known to be scrambled ones. When the LFSR is operating as a descrambler, the meter counts the number of ones on the descrambler output. When the LFSR is operating as a scrambler, the BER meter counts the number of equal scrambler and symbol detector outputs. The counter operates over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. The counter is saturated to 16 bits. At the end of the measurement interval the counter is loaded into the Bit Error Rate Meter Registers [ber_meter_low, ber_meter_high; 0x4C, Ox4D]. The symbol histogrammer computes a coarse histogram of the received sym- bols. It operates by counting the number of ones received during meter timer interval [meter_low, meter_high; 0x18, 0x19]. That is, at the start of the measure- ment interval a counter is cleared. For each detector output which is +1 or 1, the counter is incremented. If the detector output is +3 or 3, the count is held at its previous value. The count is saturated to 16 bits. At the end of the measurement interval, the 8 MSBs of the counter are loaded into the Symbol Histogram Meter Register [symbol_histogram; Ox4E]. The noise level meter estimates the noise at the input to the slicer. It operates by accumulating the absolute value of the slicer error over meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of the measurement interval, the 16 MSBs of the 32-bit accumulator are loaded into the Noise Level Histogram Meter Register [nlm_low, nlm_high; 0x50, 0x51]. The SNR alarm provides a rapid indication of impulse noise disturbances and loss of signal so that corrective action can be taken. The alarm is based on a sec- ond noise level meter. The meter is the same as the preceding noise level meter except it operates on a dedicated timer, the SNR alarm timer. The absolute value of the slicer error is accumulated during the timer period. At the end of the mea- surement interval, the 16 MSBs of the accumulator are compared against the SNR Alarm Threshold Register [snr_alarm_th_low, snr_alarm_th_high; 0x34, 0x35]. If the result is greater than this threshold, an interrupt is set in the irq_source reg- ister. The threshold is set via the microcomputer interface. @& Rockwell N8970DSB 232.0 Functional Description Bt8970 2.3 Timing Recovery and Clock Interface Single-Chip HDSL Transceiver 2.3 Timing Recovery and Clock Interface The timing recovery and clock interface block diagram consists of the timing recovery circuit and the crystal amplifier, as detailed in Figure 2-5. The main pur- pose of this circuitry is to recover the clock from the received data. Control fields include the hclk_freq[1,0] bits of the Serial Monitor Source Select Register [serial_monitor_source; 0x01], the PLL Modes Register [pll_modes; 0x22], the Timing Recovery PLL Phase Offset Register [pll_phase_offsset_low, pll_phase_offset_high; 0x24, Ox25] and the PLL Frequency Register [pll_frequency_low, pll_frequency_high; Ox5E, Ox5F]. See the Register section of this datasheet for descriptions of these control fields. Figure 2-5. Timing Recovery and Clock Interface Block Diagram Phase Detector Control Meter Register Registers [0x40, 0x41] || Symbol Timing QCLK (87) Recovery : Circuit Equalizer __,J }_____ HCLK (35) _______ XOUT (36) Crystal Amplifier XTALI (40) XTALO (39) inl VW Digital Ground 24 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.3.0.7 Timing Recovery Circuit 2.3.0.8 Crystal Amplifier 2.3 Timing Recovery and Clock Interface The timing recovery circuit uses the Bt8970s internal detected symbol and equal- izer error signals to regenerate the received data symbol clock (QCLK). The HCLK output is synchronized with the edges of the symbol clock (QCLK), unlike the XOUT output which is a buffered output of the crystal amplifier. HCLK can be programmed for rates of 16, 32, or 64 times the symbol rate. The timing recovery circuit includes a phase detector meter that measures the average value of the phase correction signal. This information can be used during startup to set the phase offset in the Receive Phase Select Register [receive_phase_select; 0x07]. The output of the phase detector is accumulated over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of the measurement interval, the value is loaded into the Phase Detector Meter Reg- ister [pdm_low, pdm_high; 0x40, 0x41]. The user can also bypass the timing recovery circuit and directly specify the fre- quency via the PLL Frequency Register [pll_frequency_low, pll_frequency_high; OxSE, Ox5F]. The crystal amplifier reduces the support circuitry needed for the Bt8970 by elim- inating the need for an external Voltage-Controlled Crystal Oscillator (VCXO) or a Crystal Oscillator (XO). A crystal can be connected directly to the XTALI and XTALO pins. Table 2-6 gives the recommended component values for this cir- cuit. The crystal amplifier can also accommodate an extemal clock input by con- necting the external clock to the XTALI input pin. Table 2-6. Crystal Oscillator Circuit Component Values Component Value Y1 8 times the data rate O Rockwell N8970DSB 252.0 Functional Description Bt8970 2.4 Channel Unit Interface Single-Chip HDSL Transceiver 2.4 Channel Unit Interface The quaternary signals of the channel unit interface have four modes which are programmable through bits 0 and 1 of the Channel Unit Interface Modes Register [cu_interface_modes; 0x06]. They are: serial sign-bit first, serial magnitude-bit first, parallel master, and parallel slave. In serial mode, a Bit-Rate Clock (BCLK) is output at twice the symbol rate. The sign and magnitude bits of the receive data are output through RDAT on the rising edge of BCLK. The sign and magnitude bits of the transmit data are sam- pled on the falling edge of BCLK at the TDAT input. The sign bit is transferred first, followed by the magnitude bit of a given symbol in sign-bit first mode, while the opposite occurs in magnitude-bit first mode. The clock relationships for serial sign-bit first mode are illustrated in Figure 2-6. Figure 2-6. Serial Sign-Bit First Mode Bit-Rate Clock ck ff \ ff \_f RDAT Signo XX Wacnitudes Sign, XX Masnitude: Signa x TDAT Signg XX Wagnitudes Sign, XX Masritudes\ Signo x In parallel master mode, the sign and magnitude receive data is output through RQ[1] and RQ[O], respectively, on the rising edge of QCLK. The quaternary transmit data is sampled on the falling edge of QCLK. This clock and data rela- tionship is illustrated in Figure 2-7. Figure 2-7. Parallel Master Mode RQ[1VTQ1] Signo x Sign, x Signs RQ[0]/TQ[O] Magnitudeg x Magnitude, x Magnitudes 26 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.4 Channel Unit Interface Parallel slave mode uses RBCLK and TBCLK inputs to synchronize data transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the use of two internal FIFOs allow an arbitrary phase relationship to QCLK. TQ[1] and TQ[0] are sampled on the active edge of TBCLK, as programmed through the MCI. RQ[1] and RQ[O] are output on the active edge of RBCLK, also as pro- grammed through the MCI. The clock relationships for the case where TBCLK is programmed to be falling-edge active and RBCLK is rising-edge active are illus- trated in Figure 2-8. Figure 2-8. Parallel Slave Mode TQ] Signo x Sign, Signs TQ([0] Magnitudeg x Magnitude, x Magnitude RQ[1] Signo x Signy x Signo RQ[O} Magnitudeg x Magnitude, x Magnitude @& Rockwell N8970DSB 272.0 Functional Description Bt8970 2.5 Microcomputer Interface 2.5.1 Source Code Single-Chip HDSL Transceiver 2.5 Microcomputer Interface The microcomputer interface provides operational mode control and status through internal registers. A microcomputer write sets the operating modes to the appropriate registers. A read to a register verifies the operating mode or provides the status. The microcomputer interface can be programmed to generate an inter- rupt on certain conditions. Rockwell provides portable C-source code under a no-cost licensing agreement. This source code provides a startup procedure, as well as diagnostic and system monitoring functions. 2.5.2 Microcomputer Read/Write The microcomputer interface uses either an 8-bit-wide multiplexed address-data bus (Intel-style), or an 8-bit-wide data bus and another separate 8-bit-wide address bus (Motorola-style) for external data communications. The interface provides access to the internal control and status registers, coefficients, and microcode RAM. The interface is compatible with Intel or Motorola microcom- puters, and is configured with the inputs, MOTEL and MUXED. MOTEL low selects Intel-type microcomputer and control signals: ALE, CS, RD, and WR. MOTEL high selects Motorola-type microcomputer and control signals: ALE, CS, DS, and R/W. MUXED high configures the interface to use the multiplexed address-data bus with both the address and data on the AD[7:0] pins. MUXED low configures the interface to use separate address and data bused with the data on the AD[7:0] pins and the address on the ADDR[7:0] pins. The READY pin is provided to indicate when the Bt8970 is ready to transfer data and can be used by the microcomputer to insert wait states in read or write cycles. The microcomputer interface provides access to a 256-byte internal address space. These registers provide configuration, control, status, and monitoring capa- bilities. Meter values are read lower-byte then upper-byte. When the lower-byte is read, the upper-byte is latched at the corresponding value. This ensures that multi- ple byte values correspond to the same reading. Most information can be directly read or written; however, the filter coefficients require an indirect access. 28 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.5.2.1 RAM Access Registers 2.5.2.2 Multiplexed Address/Data Bus 2.5.2.3 Separated Address/ Data Bus 2.5 Microcomputer Interface The internal RAMs of the transmit filter, LEC, NEC, DFE, equalizer, and micro- code are accessed indirectly. They all share a common data register which is used for both read and write operations, Access Data Register [access_data_byte[3:0]; [Ox7COx7F]. Each RAM has an individual read select and write select register. These registers specify the location to access and trigger the actual RAM read or write. To perform a read, the address of the desired RAM location is first written to the corresponding read tap select register. Two symbol periods afterwards, the individual bytes of that location are available for reading from the Access Data Register. To perform a write, the value to be written is first stored in the Access Data Register. The address of the affected RAM location is then written to the corre- sponding write tap select register. When writing the same value to multiple loca- tions, it is not necessary to rewrite the Access Data Register. To assure reliable access to the embedded RAMs, internal read and write operations are performed synchronous to the symbol clock. This has the effect of limiting access to these internal RAMs to one every other cycle. When reading or writing multiple filter coefficients, it may be desirable to freeze adaptation so that all values will correspond to the same state. The timing for a read or write cycle is stated explicitly in the Electrical and Mechanical Specifications section. During a read operation, an external micro- computer places an address on the address-data bus which is then latched on the falling edge of ALE. Data is placed on the address-data bus after CS, RD, or DS go low. The read cycle is completed with the rising edge of CS, RD, or DS. A write operation latches the address from the address-data bus at the falling edge of ALE. The microcomputer places data on the address-data bus after CS, WR, or DS go low. Motorola MCI will have R/W falling edge preceding the fall- ing edge of CS and DS. The rising edge of R/W will occur after the rising edge of CS and DS. Data is latched on the address-data bus on the rising edge of WR or DS. The timing for a read or write cycle using the separated address and data buses is essentially the same as over the multiplexed bus. The one exception is that the address must be driven onto the ADDR[7:0] bus rather than the AD[7:0] bus. 2.5.3 Interrupt Request The twelve interrupt sources consist of: eight timers, a far-end signal high alarm, a far-end signal low alarm, a SNR alarm, and a scrambler synchronization detec- tion. All of the interrupts are requested on a common pin, IRQ. Each interrupt may be individually enabled or disabled through the Interrupt Mask Registers [mask_low_reg, mask_high_reg; 0x02, 0x03]. The cause of an interrupt is deter- mined by reading the Timer Source Register [timer_source; 0x04] and the IRQ Source Register [irq_source; 0x05]. The timer interrupt status is set only when the timer transitions to zero. Alarm interrupts cannot be cleared while the alarm is active. In other words, it cannot be cleared while the condition still exists. IRQ is an open-drain output and must be tied to a pull-up resistor. This allows IRQ to be tied together with a common interrupt request. @& Rockwell N8970DSB 292.0 Functional Description Bt8970 2.5 Microcomputer Interface 2.5.4 Reset 2.5.5 Registers 2.5.6 Timers Single-Chip HDSL Transceiver The reset input (RST) is an active-low input that places the transceiver in an inac- tive state by setting the mode bit (0) in the Global Modes and Status Register [global_modes; 0x00]. An internal supply monitor circuit ensures that the trans- ceiver will be in an inactive state upon initial application of power to the chip. The Bt8970 has many directly addressable registers. These registers include con- trol and monitoring functions. Write operations to undefined registers will have unpredictable effects. Read operations from undefined registers will have unde- fined results. Eight timers are integrated into the Bt8970 to control the various on-chip meters and to aid the microcomputer in stepping through the events of the startup sequence. The structure of each timer includes down counter, zero detect logic, and con- trol circuitry, which determines when the counter is reloaded or decremented. For each of the eight timers, there is a 2-byte timer interval register that deter- mines the value from which the timer decrements. There are three 8-bit registers: the Timer Restart Register [timer_restart; OxOC], the Timer Enable Register [timer_enable; OxOD], and the Timer Continuous Mode _ Register [timer_continuous; OxOE]. These registers control the operation of the timers. Each bit of the 8-bit registers corresponds to a timer. Each logic-high bit in timer_restart acts as an event that causes the corresponding timer to reload. Each logic-high bit in timer_enable acts to enable the corresponding timer. Each logic- high bit in trmer_continuous acts to reload the counter after timing out. Each counter is loaded with the value in its interval register. The counter dec- rements until it reaches zero. Upon reaching zero, an interrupt is generated if enabled by the Interrupt Mask Low Register [mask_low_reg, mask_high_reg; 0x02, 0x03]. The interrupt is edge-triggered so that only one interrupt will be caused by a single time out. 30 N8970DSB @ RockwellBt8970 2.0 Functional Description Single-Chip HDSL Transceiver 2.5 Microcomputer Interface A prescaler may precede the timer. This increases the time span available at the expense of resolution. Only the startup timers have prescalers. Table 2-7 pro- vides summary information on the timers. Table 2-7. Timers Timer Name Purpose Clock Rate Control Bits Startup Timer 1 Startup Events Symbol rate+ 1024 sut 1 Startup Timer 2 Startup Events Symbol rate+ 1024 sut 2 Startup Timer 3 Startup Events Symbol rate+ 1024 sut 3 Startup Timer 4 Startup Events Symbol rate+ 1024 sut 4 SNR Alarm Timer SNR Measurement Symbol rate snr Meter Timer Measurement Symbol rate meter General Purpose Timer 3 Miscellaneous Symbol rate t3 General Purpose Timer 4 Miscellaneous Symbol rate t4 Four timers are provided for use in timing startup events. These timers share a single prescaler which divides the symbol clock by 1,024 and supplies this slow clock to the four counters. The timers are: Startup Timer 1, Startup Timer 2, Star- tup Timer 3, and Startup Timer 4. Each one is independent, with separate interval timer values and interrupts. Two timers control the measurement intervals for the various meters: the SNR Alarm Timer and the Meter Timer. The SNR Alarm Timer is used only by the low SNR, while the Meter Timer is used by all other meters, excluding the low SNR meter. Their respective interrupts are set when each of these two timers expire. There are no prescalers for these timers; they count at the symbol rate. Both tim- ers are normally used in the continuous mode. Two timers are provided for general use: General Purpose Timer 3 and Gen- eral Purpose Timer 4. Both timers are identical. There are no prescalers for these timers; they count at the symbol rate. Each timer signals an interrupt when it expires. @& Rockwell N8970DSB 312.0 Functional Description Bt8970 2.6 Test and Diagnostic Interface (JTAG) Single-Chip HDSL Transceiver 2.6 Test and Diagnostic Interface (JTAG) As the complexity of communications chips increases, the need to easily access individual chips for PCB verification is becoming vital. As a result, special cir- cuitry has been incorporated within the transceiver which complies fully with IEEE standard 1149.1-1990, Standard Test Access Port and Boundary Scan Architecture set by the Joint Test Action Group (JTAG). JTAG has four dedicated pins that comprise the Test Access Port (TAP): Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDD, and Test Data Out (TDO). Verification of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these four TAP pins. JTAGs approach to testability utilizes boundary scan cells placed at each dig- ital pin, both inputs and outputs. All scan cells are interconnected into a bound- ary-scan register which applies or captures test data used for functional verification of the PC board interconnection. JTAG is particularly useful for board testers using functional testing methods. With boundary-scan cells at each digital pin, the ability to apply and capture the respective logic levels is provided. Since all of the digital pins are intercon- nected as a long shift register, the TAP logic has access and control of all neces- sary pins to verify functionality. For mixed signal ICs, the chip boundary definition is expanded to include the on-chip interface between digital and analog circuitry. Internal supply monitor circuitry ensures that each pin is initialized to operate as an 2B1Q transceiver, instead of JTAG test mode during a powerup sequence. The JTAG standard defines an optional device identification register. This reg- ister is included and contains a revision number, a part number, and a manufactur- ers identification code specific to Rockwell. Access to this register is through the TAP controller via the standard JTAG instruction set (see Table 2-8). A variety of verification procedures can be performed through the TAP con- troller. Board connectivity can be verified at all digital pins through a set of four instructions accessible through the use of a state machine standard to all JTAG controllers. Refer to the IEEE 1149.1 specification for details concerning the Instruction Register and JTAG state machine. A Boundry Scan Description Lan- guage (BSDL) file for the Bt8970 is also available from the factory upon request. Table 2-8. JTAG Device Identification Register Version/1) Part Number Manufacturer ID 0} O} 0 QO} 1) 1) O; OF OF OF 1] OF 1} OF OF OF OF 1) 1] OF 1) OF 1] 1) ~0 ry 0x0 0x230A (Bt8970) 0x0D6 TDO 4 bits 16 bits 11 bits Note: (1). Consult factory for current version number 32 N8970DSB @ Rockwell3.0 Registers 3.1 Conventions Unless otherwise noted, the following conventions apply to all applicable register descriptions: For storage of multiple-bit data fields within a single byte-wide register, the Least Significant Bits (LSBs) of the field are located at the lower register-bit positions, while the Most Significant Bits (MSBs) are located at the higher positions. If only a single data field is stored in a byte-wide register, the field will be justified such that the LSB of the field is located in the lowest register-bit position, bit 0. For storage of multiple-byte data words across multiple byte-wide registers, the least significant bytes of the word are located at the lower byte-address locations, while the most significant bytes are located at the higher byte-address locations. When writing to any control or data register with less than all 8-bit positions defined, a logic zero value must be assigned to each unused/undefined/reserved position. Writing a logic one value to any of these positions may cause undefined behavior. When reading from any control/status or data register with less than all 8-bit positions defined, an inde- terminate value will be returned from each unused/undefined/reserved position. Register values are not affected by RST pin assertion, except for the mode bit of the Global Modes and Status Register [global_modes; 0x00], the hclk_freg[1,0] field of the Serial Monitor Source Select Reg- ister [serial_monitor_source; 0x01] and the clk_freq[1,0] field of the PLL Modes Register [pll_modes; 0x22]. Upon RST pin assertion, all RAM is lost except for the equalizer microcode and scratch pad RAM. The initial values of all registers and RAM are undefined after power is applied. Exceptions include the mode bit of the Global Modes and Status Register, the hclk_freq[1,0] field of the Serial Monitor Source Select Register and the clk_freq[1,0] field of the PLL Modes Register. In addition, the JTAG state is reset when power is applied. The register and bit mnemonics used here are based on the mnemonics used in the Rockwell bit pump software. O Rockwell N8970DSB 33be aSdoZ68n = 3.2 Register Summary Table 3-1. Register Table (1 of 5) ADDR Register Read PEN inbe! (hex) Label Write 7 6 5 4 3 9 1 0 0x00 global_modes R/W hw_revision[3] | hw_revision[2] | hw_revision[1] | hw_revision[0] part_id[2] part_id[ 1] part_id[0] mode 0x01 serial_monitor_source R/W helk_freq[1] helk_freq[0] smon[5] smon[4] smon{[3] smon[2] smon[1] smon[0] 0x02 mask_low_reg R/W t4 3 snr meter sut4 sut3 sut2 sut1 0x03 mask_high_reg R/W _ _ _ _ sync high_felm low_felm low_snr 0x04 timer_source R/W t4 8 snr meter sut4 sut3 sut2 sut1 0x05 irq_source R/W _ _ _ _ sync high_felm low_felm low_snr 0x06 cu_interface_modes R/W _ _ _ tbclk_pol rbclk_pol fifos_mode interface_mode1 |interface_mode[0] 0x07 receive_phase_select R/W _ _ _ _ rphs[3] rphs[2] rphs[1] rphs[0] 0x08 linear_ec_modes R/W _ _ enable_dc_tap |adapt_coefficients | zero_coefficients zero_output adapt_gain[1] adapt_gain[0] 0x09 nonlinear_ec_modes R/W negate_symbol | symbol_delay[2] | symbol_delay[1] | symbol_delay[0] |adapt_coefficients| zero_coefficients zero_output adapt_gain 0x0A dfe_modes R/W _ _ _ _ adapt_coefficients| zero_coefficients zero_output adapt_gain 0x0B transmitter_modes R/W _ isolated_pulse[ 1] }isolated_pulse[0]| transmitter_off htur_lfsr data_source[2] | data_source[1] data_source[0] 0x0C timer_restart R/W t4 3 snr meter sut4 sut3 sut2 sut1 0x0D timer_enable R/W t4 3 snr meter sut4 sut3 sut2 sut1 Ox0E timer_continuous R/W t4 3 snr meter sut4 sut3 sut2 sut1 Ox0F reserved2 R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0x10 sut1_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Ox11 sut1_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9} D[8] Areuiuing sajs|bay AIAIDISUDAT, TSCH Gy) -asurs OLO8314 slaisibay o'HOnAyI0" Wp aSdoZ68n Ge Table 3-1. Register Table (2 of 5) ADDR Register Read Bit Number (hex) Label Write 2 4 ; , ; ; ; oxt2 sut2_low RIW [7] DI6] DIS] iA] D1) 012 Dit) DIO} 0x13 sut2_high RIW D415] D[t4] p13] Dl12] Dit] D[ 19] DIS] [8] Oxt4 sut3_low RIW DI7] DI6] DIS] D4] Dr] 012] Ot) O10 Oxt5 sut3_high RIW D415] D[t4] p13] Dit] Dit] Dl10} 019) Da Oxt6 sutd_low RIW DI7] DI6] DIS] D4] Dr] 012] Ot) O10 Oxt7 sut4_high RIW p15] D[14] p13] Dr12] brit] Di10] P13] O18) Oxt8 meter_low RW DI7] DI6] DIS] D4] Dr] D2] Ot) O10 Oxt9 meter_high RW p15] D[14] p13] Dr12] brit] Di10] P13] O18) OxtA snt_timer_low RW DI7] DI6] DIS] D4] Dr] D2] Ot) O10 OxiB snr_timer_high RW p15] p14] D139] Dt12} Dt] Dit0) 019) O18 OxiC 13 low RW DI7] DI6] DIS] D4] Dr] D2] Ot) O10 Ox1D 13 high RW p15] D[14] p13] Dr12] brit] Di10] P13] O18) OxtE t4_low RW D[7] D{6] DIS] D4] Dra] D12) DI DIO) OxtF t4_high RW p15] Dit] p13] Dr12] brit] Di10] 013) O18) 0x20 reserved R/W 017] D{6] D{5] DI4] [3] DI] MET DIO} 0x21 ade_control RW loop_back[1] | loop back{0] _ gain(2] gain] gain(0] 0x22 pll_modes RW | clk freg[ 1] clk_freq[ 0] _ Pant) Pant) freeze_pll pll_gain{ 1] pll_gain{0] 0x28 reserved 0 R/W {7 D{6] DIS] DIA] [3] DI] DIA} DIO} 0x24 pll_phase_offset_low RW [7] DI6] DiS] iA] 013) 012 Dit] 010) 0x25 | pll_phase_offset_high RW p15] Dit] Di 13] Drt2] br] Di10] 013) oie) AIAIDISUDAT, ISCH Gy -apsurs Areuiuing sajs|bay OLO8314 siaisibay O9 aSdoZ68n HannyyI0g vp Table 3-1. Register Table (3 of 5) ADDR Register Read EN inbe! (hex) Label Write 7 6 5 4 3 9 1 0 0x26 dc_offset_low RIW D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x27 dc_offset_high RIW D[15] D[14] D[13] D[12] D[11] D[10] DI9] D8] 0x28 tx_calibrate R/W _ _ tx_calibrate[3] | tx_calibrate[2] tx_calibrate[1] | tx_calibrate[0] _ _ 0x29 tx_gain R/W - - tx_gain[3] tx_gain[2] tx_gain[ 1] tx_gain[0] - - Ox2A noise_histogram_th_low RIW D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x2B | noise_histogram_th_high RIW D[15] D[14] D[13] D[12] D[11] D[10] DI9] D8] 0x2 ep_pause_th_low RIW D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x2D ep_pause_th_high RIW D[15] D[14] D[13] D[12] D[11] D[10] DI9] D8] Ox2E scr_syne_th RIW D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x30 | far_end_high_alarm_th_low | R/W D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x31 | far_end_high_alarm_th_high | R/W D[15] D[14] D[13] D[12] D[11] D[10] DI9] D8] 0x32 | far_end_low_alarm_th_low | R/W D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x33 | far_end_low_alarm_th_high | R/W D[15] D[14] D[13] D[12] D[11] D[10] DI9] Dg] 0x34 snr_alarm_th_low RIW D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x35 snr_alarm_th_high RIW D[15] D[14] D[13] D[12] D[11] D[10] DI9] Dg] 0x36 cursor_level_low R/W DI7] DI6] D5] D4] DI3] D2] D[1] DIO] 0x37 cursor_level_high R/W D[15] D[14] D[13] D[12] D[11] D[10] DI9] Dg] 0x38 dage_target_low RW D[7] D[] D[5] D[4] D[3] D2] D[1] DIO] 0x39 dage_target_high RW D[15] D[14] D[13] D[12] D[11] D[10] DI9I D8] Ox3A detector_modes R/W ene speak contol ) - contra) - scr_out_to_dfe two_level Ifsr_lock htur_Ifsr descr_on Areuiuing sajs|bay AIAIDISUDAT, TSCH Gy) -asurs OLO8314 slaisibay o'HOnAyI0" Wp aSdoZ68n Ze Table 3-1. Register Table (4 of 5) ADDR Register Read EN inbe! (hex) Label Write 7 6 5 4 3 9 1 0 0x3B peak_detector_delay R/W _ _ _ _ D[3] D[2] D[1] D[0] 0x3C dagc_modes R/W - - - - - adaption adapt_coefficient adapt_gain 0x3D ffe_modes R/W _ _ _ _ adapt_last_coeff | zero_coefficients | adapt_coefficient adapt_gain Ox3E ep_modes R/W - - - - zero_output | zero_coefficients | adapt_coefficients adapt_gain 0x40 pdm_low R/W D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] Ox41 pdm_high R/W D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] 0x42 overflow_meter RAW D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[O] 0x44 dc_meter_low RAW D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] 0x45 de_meter_high RAW D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] 0x46 sim_low RW D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] 0x47 sim_high RW D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] 0x48 felm_low RW D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] 0x49 felm_high RW D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] Ox4A noise_histogram_low RAW D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[O] 0x4B noise_histogram_high RAW D[15] D[14] D[13] D[12] D141] D[10] D[9] D[8] 0x4 ber_meter_low RAW D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[O] 0x4D ber_meter_high RAW D[15] D[14] D[13] D[12] D141] D[10] D[9] D[8] Ox4E symbol_histogram RAW D[7] D[6] DIS] D[4] D[3] D[2] D[1] D[O] 0x50 nim_low RW D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] 0x51 nim_high RW D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] AIAIDISUDAT, ISCH Gy -apsurs Areuiuing sajs|bay OLO8314 siaisibay O8e aSdoZ68n HannyyI0g vp Table 3-1. Register Table (5 of 5) ADDR Register Read EN inbe! (hex) Label Write 7 6 5 4 3 9 1 0 Ox5E pll_frequency_low R/W D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] Ox5F pll_frequency_high R/W D[30] D[29] D[28] D[27] D[26] D[25] D[24] D[23] 0x70 | linear_ec_tap_select_read RW D[] D5] D4] D[3] D2] D[1] DIO] 0x71 | linear_ec_tap_select_write | R/W D[] D5] D4] D[3] D[2] D[1] DIO} 0x72 | nonlinear_ec_tap_select_read| R/W D5] D4] D[3] D[2] D[1] DIO} 0x73 |nonlinear_ec_tap_select_write| R/W D5] D4] D[3] D[2] D[1] DIO} 0x74 dfe_tap_select_read RW D[] D5] D4] D[3] D2] D[1] DIO} 0x75 dfe_tap_select_write RW D[] D5] D4] D[3] D2] D[1] DIO} 0x76 sp_tap_select_read RW D5] D4] D[3] D2] D[1] DIO} 0x77 sp_tap_select_write R/W D5] D4] D[3] D2] D[1] DIO} 0x78 eq_add_read R/W DI5] D4] D[3] D2] D[1] DIO} 0x79 eq_add_write R/W D5] D4] D[3] D2] D[1] DIO} Ox7A eq_microcode_add_read R/W DI5] D4] D[3] D2] D[1] D[0] 0x7B eq_microcode_add_write R/W D5] D4] D[3] D2] D[1] D[0] Ox7C access_data_byte0 R/W D[7] D[] D5] D4] D[3] D2] D[1] D[0] 0x7D access_data_byte1 R/W D[15] D[14] D[13] D[12] D[11] D[ 10] D[9] D8] Ox7E access_data_byte2 R/W D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[ 16] Ox7F access_data_byte3 R/W DI31] D[30] D[29] p28] D[27] D[26] D[25] D[24] Areuiuing sajs|bay AIAIDISUDAT, TSCH Gy) -asurs OLO8314 slaisibay o'Bt8970 3.0 Registers Single-Chip HDSL Transceiver 3.1 Conventions 3.2.1 0x00 Global Modes and Status Register (global_ modes) 7 6 5 4 3 2 1 0 hw_revision[3] hw_revision[2] hw_revision[ 1] hw_revision[0] part_id[2] part_id[ 1] part_id[0] mode hw_revision[3:0] part_id[2:0] mode Chip Revision NumberRead-only unsigned binary field encoded with the chip revision number. Smaller values represent earlier versions, while larger values represent later versions. The zero value represents the original prototype release. Consult factory for current values and revision. Part IDRead-only binary field set to binary 010 identifying the part as Bt8970. Power Down ModeRead/write control bit. When set, stops all filter processing and zeros the transmit output for reduced power consumption. All RAM contents are preserved. The mode bit is automatically set by RST assertion and upon initial power application. It can be cleared only by writing a logic zero, at which time filter processing and transmitter operation can pro- ceed. 3.2.2 0x01Serial Monitor Source Select Register (serial_monitor_source) 7 6 5 4 3 2 1 0 helk_freq[ 1] helk_freq[0] smon[5] smon[4] smon[3] smon[2] smon[1] smon[0] helk_freq[1,0] HCLK Frequency SelectRead/write binary field selects the frequency of the HCLK output. helk_freq{1] helk_freq[0] HCLK Frequency 0 0 Symbol Frequency (Foc, ) times 16 hclk_freq[ 1,0] is set to 00 upon assertion of the RST pin and power-on detection. 0 1 Symbol Frequency (Foci) times 16 1 0 Symbol Frequency (Foci) times 32 Symbol Frequency (Foci) times 64 @& Rockwell N8970DSB 39Registers Bt8970 Conventions smon[5:0] Single-Chip HDSL Transceiver Serial Monitor Source SelectRead/write binary field selects the Serial Monitor (SMON) out- put source. smon{[5:0] Decimal Binary 0-47 00 0000 - 10 1111 Equalizer Register File 48 11 0000 Digital Front-End Output/LEC Input 49 110001 Linear Echo Replica 50 110010 DFE Subtractor Output/EP Input 51 110011 EP Subtractor Output/Slicer Input 52 11.0100 Timing Recovery Phase Detector Output/Loop Filter Input 53 110101 Timing Recovery Loop Filter Output/Frequency Synthesizer Input 3.2.3 0x02Interrupt Mask Register Low (mask_low_reg) Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A logic one represents the masked condition. A logic zero represents the unmasked condition. All mask bits behave identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corre- sponding interrupt flag from affecting the IRQ output. Clearing a mask allows the interrupt flag to affect IRQ output. Unmasking an active interrupt flag will immediately cause the IRQ output to go active, if currently inac- tive. Masking an active interrupt flag will cause IRQ to go inactive, if no other unmasked interrupt flags are set. 7 6 5 4 3 2 1 0 t4 t3 snr meter su4 sut3 sut2 sutt 14 General Purpose Timer 4 13 General Purpose Timer 3 snr SNR Alarm Timer meter Meter Timer sut4 Startup Timer 4 sut3 Startup Timer 3 sut2 Startup Timer 2 sutt Startup Timer 1 40 N8970DSB O RockwellBt8970 Single-Chip HDSL Transceiver 3.0 Registers 3.1 Conventions 3.2.4 0x03Interrupt Mask Register High (mask_high_reg) Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags. Indi- vidual mask bit behavior is identical to that specified for Interrupt Mask Register Low [mask_low_reg; 0x02]. 7 6 5 4 3 2 1 0 - - - - sync high_felm low_felm low_snr sync Sync Indication high_felm Far-End Level Meter High Alarm low_felm Far-End Level Meter High Alarm low_snr Signal-to-Noise Ratio Low Alarm 3.2.5 0x04 Timer Source Register (timer_source) Independent read/write (zero only) interrupt flags, one for each of eight internal timers. Each flag bit is set and stays set when its corresponding timer value transitions from one to zero. If unmasked, this event will cause the IRQ output to be activated. Flags are cleared by writing them with a logic zero value. Once cleared, a steady- state timer value of zero will not cause a flag to be reasserted. Clearing an unmasked flag will cause the IRQ output to return to the inactive state, if no other unmasked interrupt flags are set. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 14 General Purpose Timer 4 13 General Purpose Timer 3 snr SNR Alarm Timer meter Meter Timer sut4 Startup Timer 4 sut3 Startup Timer 3 sut2 Startup Timer 2 sutt Startup Timer 1 @& Rockwell N8970DSB 41Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.6 0x05IRQ Source Register (irq_source) Independent read/write (zero only) interrupt flags, one for each of four internal sources. Each flag bit is set and stays set when its corresponding source indicates that a valid interrupt condition exists. If unmasked, this event will cause the IRQ output to be activated. Writing a logic zero to an interrupt flag whose underlying condition no longer exists will cause the flag to be immediately cleared. Attempting to clear a flag whose underlying con- dition still exists will not immediately clear the flag, but will allow it to remain set until the underlying condition expires, at which time the flag will be cleared automatically. The clearing of an unmasked flag will cause the TRQ output to return to an inactive state, if no other unmasked interrupt flags are set. le 6 5 4 3 2 1 0 - - - - sync high_felm low_felm low_snr sync Sync IndicationActive when the sync detector is enabled and its accumulated equivalent comparisons exceeds (greater than) the threshold value stored in the Scrambler Sync Thresh- old Register [scr_sync_th; 0x2E]. high_felm Far-End Level Meter High AlarmActive when the far-end level meter value exceeds (greater than) the threshold stored in the Far-End High Alarm Threshold Registers [far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30-0x31]. low_felm Far-End Level Meter Low AlarmActive when the far-end level meter value exceeds (less than) the threshold stored in the Far-End Low Alarm Threshold Registers [far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x320x33]. low_snr Signal-to-Noise Ratio Low AlarmActive when the SNR Alarm meter value exceeds (greater than) the threshold stored in the SNR Alarm Threshold Registers [snr_alarm_th_low, snr_alarm_th_high; 0x340x35]. 3.2.7 0x06 Channel Unit Interface Modes Register (cu_interface_modes) 7 6 5 4 3 2 1 0 - - - tbclk_pol rbclk_pol fifos_mode _|interface_modef[ 1] | interface_mode[0] tbclk_pol Transmit Baud Clock PolarityRead/write control bit defines the polarity of the TBCLK input while in the parallel slave interface mode. When set, TQ[1,0] is sampled on the falling edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge. rbclk_pol Receive Baud Clock PolarityRead/write control bit defines the polarity of the RBCLK input while in the parallel slave interface mode. When set, RQ[1,0] is updated on the falling edge of RBCLK; when cleared, RQ[1,0] is updated on the rising edge. fifos_mode FIFOs ModeRead/write control bit used to stagger the transmit and receive FIFOs read and write pointers while in the parallel slave interface mode. A logic one forces the pointers to a staggered position, while a logic zero allows them to operate normally. Must be first set, then cleared once after QCLK-TBCLK-RBCLK frequency lock is achieved to maximize phase- error tolerance. 42 N8970DSB @ RockwellBt8970 3.0 Registers Single-Chip HDSL Transceiver 3.1 Conventions interface_ mode[1,0] Interface ModeRead/write binary field specifies one of four operating modes for the channel unit interface. Interface Pin Functions mode Mode [1:0] 91 90 88 89 85 86 00 Parallel Master Parallel quat transfer Not Not RQ 1] RQ[0] TQ 1] TQ(O] synchronized to QCLK out. used used 01 Parallel Slave Parallel quat transfer TBCLK RBCLK RQ[ 1] RQ[O] TQ[1] TQ(O] synchronized to separate TBCLK and RBCLK inputs. 10 Serial, Magnitude First. Serial quat Not Not RDAT BCLK TDAT Not transfer synchronized to BCLK out; used used used magnitude-bit first followed by sign bit. 11 Serial, Sign First. Serial quat transfer Not Not RDAT BCLK TDAT Not synchronized to BCLK out; sign-bit first used used used followed by magnitude bit. 3.2.8 0x07 Receive Phase Select Register (receive_phase_select) 7 6 5 4 3 2 1 0 - - - rphs[3] rphs[2] rphs[ 1] rphs[0] rphs[3:0] Receive Phase SelectRead/write binary field that defines the relative phase relationship between QCLK and the sampling point of the ADC. The rising edges of QCLK corresponds to the ADC sampling point when rphs = 0000. Each binary increment of rphs represents a one- sixteenth QCLK period delay in the sampling point relative to QCLK. @& Rockwell N8970DSB 43Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.9 Ox08 Linear Echo Canceller Modes Register (linear_ec_modes) - - enable_dc_taj adapt_ zero_coefficients | zero_output adapt_gain[ 1] adapt_gain[0] oe"aP coefficients - oulp pt_g pt_g enable_dc_tap adapt_coefficents zero_coefficients zero_output adapt_gain[1,0] Enable DC TapRead/write control bit which, when set, forces a constant +1 value into the last data tap of the Linear Echo Canceler (LEC). This condition enables cancellation of any residual DC offset present at the input to the LEC. When cleared, the last data tap operates nor- mally, as the oldest transmit data sample. Adapt CoefficientsRead/write control bit which enables coefficient adaptation when set; dis- ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis- abled. Zero CoefficientsRead/write control bit that continuously zeros all coefficients when set; allows normal coefficient updates, if enabled, when cleared. This behavior differs slightly from the similar function (zero_coefficients) of the FFE and EP filters. Zero OutputRead/write control bit which, when set, zeros the echo replica before subtrac- tion from the input signal. Achieves the affect of disabling or bypassing the echo cancellation function. Does not disable coefficient adaptation. When cleared, normal echo canceller opera- tion is performed. Adaptation GainRead/write binary field which specifies the adaptation gain. adapt_gain{1,0] Normalized Gain 00 1 01 4 10 64 11 512 44 N8970DSB @ RockwellBt8970 3.0 Registers Single-Chip HDSL Transceiver 3.1 Conventions 3.2.10 0x09 Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes) 6 5 4 3 2 1 0 negate_symbol symbol_delay[2] adapt_ symbol_delay[1] coefficients symbol_delay[0] zero_coefficients | zero_output adapt_gain negate_symbol symbol_delay[2:0] adapt_coefficients zero_coefficients zero_output adapt_gain Negate SymbolRead/write control bit which, when set, inverts (2s complement) the receive signal path at the output of the nonlinear echo canceller. When cleared, the signal path is unaf- fected. This function is independent of all other NEC mode settings. Symbol DelayRead/write binary field which specifies the number of symbol delays inserted in the transmit symbol input path. Adapt CoefficientsSame function as LEC Modes Register [linear_ec_modes; 0x08]. Zero CoefficientsSame function as LEC Modes Register. Zero OutputSame function as LEC Modes Register. Adaptation GainRead/write control bit which specifies the adaptation gain. When set, the adaptation gain is 8 times higher than when cleared. 3.2.11 0x0A Decision Feedback Equalizer Modes Register (dfe_modes) 6 5 4 3 2 1 0 adapt_ we zero_coefficients coefficients - zero_output adapt_gain adapt_coefficents zero_coefficients zero_output adapt_gain Adapt CoefficientsRead/write control bit which enables coefficient adaptation when set; dis- ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis- abled. Zero CoefficientsRead/write control bit which continuously zeros all coefficients when set; allows normal coefficient updates, if enabled, when cleared. Zero OutputRead/write control bit which, when set, zeros the equalizer correction signal before subtraction from the input signal. Achieves the affect of disabling or bypassing the equalization function. Does not disable coefficient adaptation. When cleared, normal equalizer operation is performed. Adaptation GainRead/write control bit which specifies the adaptation gain. When set, the adaptation gain is 8 times higher than when cleared. @& Rockwell N8970DSB 45Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.12 0x0B Transmitter Modes Register (transmitter_modes) 6 5 4 3 2 1 0 - isolated_pulse[1] | isolated_pulse[0] | transmitter_off htur_lfsr data_source[2] | data_source[1] | data_source[0] isolated_pulse[1,0] Isolated Pulse Level SelectRead/write binary field that selects one of four output pulse lev- transmitter_off htur_lfsr data_source[2:0] els while in the isolated pulse transmitter mode. isolated pulse[1,0] Output Pulse Level 00 -3 01 -1 10 +3 11 +1 Transmitter OffRead/write control bit that zeros the output of the transmitter when set; allows normal transmitter operation (as defined by data_source[2:0]) when cleared. Remote Unit (HTU-R/NTU) Polynomial SelectRead/write control bit selects one of two feedback polynomials for the transmit scrambler. When set, this bit selects the remote unit transmit polynomial (x 3 7 1); when cleared, it selects the local unit (HTU-C/LTU) polynomial (x23 4 xo + 1). Data SourceRead/write binary field that selects the data source and mode of the transmitter output. The transmitter must be enabled (transmitter_off = 0) for these modes to be active. dale Source Transmitter Mode [2:0] 000 Isolated pulse. Level selected by isolated_pulse[1:0]. The meter timer must be enabled and in the continuous mode. The pulse repetition interval is determined by the meter timer countdown interval. 001 Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are scrambled and looped back to the transmitter. Feedback polynomial deter- mined by the htur_lfsr control bit. 010 Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the channel unit transmit interface without scrambling. 011 Four-level scrambled ones. Transmits a scrambled, constant high-logic level as a four- level (2B1Q) signal. Feedback polynomial determined by the htur_lfsr control bit. 46 N8970DSB @& RockwellBt8970 3.0 Registers Single-Chip HDSL Transceiver 3.1 Conventions data source [2:0] Transmitter Mode 100 Reserved. 101 Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and mag- nitude bits from the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit. 110 Two-level unscrambled data. Constantly forces the magnitude bit from the channel unit transmit interface to a logic zero and transmits the resulting two-level signal (as deter- mined by the sign bit) without scrambling. Valid output levels limited to +3, 3. 114 Two-level scrambled ones. Transmits a scrambled, constant high-logic level as a two- level signal. Feedback polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate (half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a constant logic zero. Valid output levels limited to +3, -3. 3.2.13 Ox0CTimer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For the four symbol-rate timers (meter, snr, t3, t4), reloading will occur within one symbol period. For the four start-up timers (sutl4), reloading will occur within 1,024 symbol periods. Once reloaded, the restart bit is automatically cleared. If a restart bit is set and then cleared (by writing a logic zero) before the reload actually takes place, no timer reload will occur. Once reloaded, if enabled in the Timer Enable Register [timer_enable; OxOD], the timer will begin counting down toward zero; otherwise, it will hold at the interval register value. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sutt 14 General Purpose Timer 4 13 General Purpose Timer 3 snr SNR Alarm Timer meter Meter Timer sut4 Startup Timer 4 sut3 Startup Timer 3 sut2 Startup Timer 2 sutt Startup Timer 1 O Rockwell N8970DSB 47Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.14 0x0DTimer Enable Register (timer_enable) Independent read/write enable bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is enabled for counting down from its current value toward zero. For the four symbol-rate timers (meter, snr, t3, t4), counting will begin within one symbol period. For the four start-up timers (sut1-4), counting will begin within 1,024 symbol periods. When an enable bit is cleared, the timer is disabled from counting while it holds its current value. If an enable bit is set and then cleared before a count actually takes place, no timer countdown will occur. 7 6 5 4 3 2 1 0 t4 t3 snr meter sut4 sut3 sut2 sut1 14 General Purpose Timer 4 13 General Purpose Timer 3 snr SNR Alarm Timer meter Meter Timer sut4 Startup Timer 4 sut3 Startup Timer 3 sut2 Startup Timer 2 sutt Startup Timer 1 3.2.15 Ox0E Timer Continuous Mode Register (timer_continuous) Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is placed in the continuous count mode. While in this mode, after reaching the zero count, an enabled timer will reload the contents of its interval register and continue counting. When a mode bit is cleared, the timer is taken out of the continuous mode. While in this configuration, after reaching the zero count, an enabled timer will simply stop counting and remain at zero. t4 t3 snr meter sut4 sut3 sut2 sut1 3.2.16 Ox0F Test Register (reserved2) A 1-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x00 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.17 0x10, 0x11 Startup Timer 1 Interval Register (sut1_low, sut1_high) A 2-byte read/write register stores the countdown interval for Startup Timer 1 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its asso- ciated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 48 N8970DSB O RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.18 0x12, 0x13 Startup Timer 2 Interval Register (sut2_low, sut2_high) A 2-byte read/write register stores the countdown interval for Startup Timer 2 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its asso- ciated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.19 0x14, 0x15 Startup Timer 3 Interval Register (sut3_low, sut3_ high) A 2-byte read/write register stores the countdown interval for Startup Timer 3 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its asso- ciated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.20 0x16, 0x17 Startup Timer 4 Interval Register (sut4_low, sut4_high) A 2-byte read/write register stores the countdown interval for Startup Timer 4 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its asso- ciated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.21 0x18, 0x19 Meter Timer Interval Register (meter_low, meter_high) A 2-byte read/write register stores the countdown interval for the Meter Timer in unsigned binary format. Each increment represents one symbol period. The contents of this register are automatically loaded into its associ- ated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.22 0x1A, 0x1BSNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high) A 2-byte read/write register stores the countdown interval for the SNR Alarm Timer in unsigned binary format. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continuous mode. 3.2.23 0x1C, 0xiD General Purpose Timer 3 Interval Register (t3_low, t3_high) A 2-byte read/write register stores the countdown interval for General Purpose Timer 3 in unsigned binary for- mat. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continu- ous mode. 3.2.24 0x1E, 0x1FGeneral Purpose Timer 4 Interval Register (t4_low, t4_high) A 2-byte read/write register stores the countdown interval for General Purpose Timer 4 in unsigned binary for- mat. Each increment represents one symbol period. The contents of this register are automatically loaded into its associated timer after the timers timer_restart bit is set, or after it counts down to zero while in the continu- ous mode. O Rockwell N8970DSB 49Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.25 0x20 Test Register (reserved9) A 1-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x00 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.26 0x21 ADC Control Register (adc_control) 6 5 4 3 2 1 0 - loop_back{ 1] loop_back[ 0] - gain[2] gain[ 1] gain[ 0] loop_back[1,0] Loopback ControlRead/write binary field specifies if loopback is enabled, and the type of loopback that is enabled. During transmitting loopback, the differential receiver inputs (RXP, RXN) are disabled. The loopback path is intended to go from the transmitter outputs (TXP, TXN) through the external hybrid circuit and back into the differential receiver balance inputs (RXBP, RXBN). During silent loopback, the transmitter is turned off.The output of the pulse- shaping filter in the transmit section is internally connected to the input of the ADC in the receive section. loop_back[1,0] Function 00 Normal Operation (Loopback Disabled) 01 Hybrid Inputs Disabled (RXBP, RXBN) 10 Transmitting Loopback 11 Silent Loopback gain[2:0] Gain ControlRead/write binary field specifies the gain of the VGA. gain{ 2:0] VGA Gain 000 0dB 001 3 dB 010 6 dB 011 9 dB 100 12 dB 101 15 dB 110 15 dB 111 15 dB 50 N8970DSB RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.27 0x22 PLL Modes Register (pll_ modes) 7 6 5 4 3 2 1 0 clk freq[ 1] clk freq[0] | negate_symbol Pent) Ba) freeze_pll pll_gain{ 1] pll_gain{0] clk_freq[1,0] Clock Frequency SelectRead/write binary field specifies one of four data rate ranges for phase_detector_ gain[1,0] Bt8970 operation. The 00 state is automatically selected by RST assertion and upon initial power application. The crystal or external clock frequency must be equal to 8 times the data rate. clk freq[1,0] Data Rate Range 00 968 to 1368 kbps 01 656 to 968 kbps 10 160 to 656 kbps 11 Above 1368 kbps Phase Detector GainRead/write binary field specifies one of four gain settings for the tim- ing-recovery phase detector function. phase_detector_gain[1,0] Normalized Gain 00 1 01 2 10 4 11 Reserved @& Rockwell N8970DSB 51Registers Bt8970 Conventions Single-Chip HDSL Transceiver freeze_pll Freeze PLLRead/write control bit. When set, this bit zeros the proportional term of the loop compensation filter and disables accumulator updates causing the PLL to hold its current fre- quency. When cleared, proportional term effects and accumulator updates are enabled allowing the PLL to track the phase of the incoming data. pll_gain[1,0] PLL GainRead/write binary field specifies the gain (proportional and integral coefficients) of the loop compensation filter. Il gain{1:0] Normalized Normalized pg ' Proportional Coefficients Integral Coefficients 00 1 1 01 4 32 10 16 256 11 64 4096 3.2.28 0x23 Test Register (reserved10) A 3-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x000000 upon RST assertion and initial power application. This register must be initialized according to the device driver provided by Rockwell. 3.2.29 0x24, 0x25 Timing Recovery PLL Phase Offset Register (pll_phase_offset_low, pll_phase_offset_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The value of this register is sub- tracted from the output of the timing-recovery phase detector after the phase-detector meter, but before the loop compensation filter. 3.2.30 0x26, 0x27 Receiver DC Offset Register (dc_offset_low, dc_offset_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The value of this register is sub- tracted from the receiver signal path at the output of the digital front ends format conversion block, ahead of the DC level and signal level meters. 3.2.31 0x28 Transmitter Calibration Register (tx_calibrate) 6 5 4 3 2 - tx_calibrate[3] tx_calibrate[2] tx_calibrate[ 1] tx_calibrate[ 0] tx_calibrate[3:0] Transmit Calibrate4-bit, 2s-complement, read-only field containing the nominal setting for the transmitter gain. The value of the Transmit Calibration Register is set during manufactur- ing testing by Rockwell and corresponds to the value required to operate the Bt8970 at a nom- inal 13.5 dBm transmit power, assuming the recommended transformer coupling/hybrid circuit is used. Users may override this calibration by writing their own value into the Transmitter Gain Register [tx_gain; 0x29]. 52 N8970DSB @ RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.32 0x29 Transmitter Gain Register (tx_gain) 7 6 5 4 3 2 1 0 - - tx_gain[3] tx_gain[2] tx_gain[1] tx_gain[0] - - tx_gain[3:0] Transmit GainA 4-bit, 2s-complement, read/write field controlling the transmitter gain. Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] may be written into this register by software to set the transmitter gain to the nominal value, or the user may set it to another desired value. tx_gain[3:0] Relative Transmitter Gain (dB) 1000 -1.60 1001 -1.36 1010 -1.13 1011 -0.91 1100 -0.69 1101 -0.48 1110 -0.27 1111 -0.07 0000 0.13 0001 0.32 0010 0.51 0011 0.70 0100 0.88 0101 1.05 0110 1.23 0111 1.40 @& Rockwell N8970DSB 53Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.33 0x2A, 0x2BNoise-Level Histogram Threshold Register (noise_histogram_th_low, noise_histogram_th_high) Two-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox7FFF. The value of this register is compared to the absolute value of the slicer error signal produced by the detector. A count of error samples that exceeds this threshold (greater than) is accumulated in the noise-level histogram meter. 3.2.34 0x2C, 0x2DError Predictor Pause Threshold Register (ep_pause_th_low, ep_pause_th_high) Two-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox7FFF. The value of this register is compared to the absolute value of the slicer error signal produced by the detector. The result of this comparison (slicer error greater than this threshold) is used to initiate a pause condition by zeroing the output of the error predictor correction signal before subtraction from the receive signal path. Error predictor coefficient updates are not affected. The pause condition lasts for a fixed 5-symbol period from the time the threshold was last exceeded. 3.2.35 Ox2EScrambler Synchronization Threshold Register (scr_sync_th) A 7-bit read/write register representing an unsigned binary number. The contents of this register are used to test for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector. The test passes when the count of equivalent scrambler and detector output bits exceeds (greater than) the value of this register. When the auto-scrambler sync mode is not enabled, the contents of this register are not used. 7 6 5 4 3 2 1 0 - D[] D[5] D[4] D[3] D[2] D[1] D[O] 3.2.36 0x30, 0x31 Far-End High Alarm Threshold Register (far_end_high_alarm_th_low, far_end_high_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox7FFF. The value of this register is compared to the value of the far-end level meter. If the meter reading exceeds (greater than) this threshold, the high_felm interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. 3.2.37 0x32, 0x33 Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low, far_end_low_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox7FFF. The value of this register is compared to the value of the far-end level meter. If the meter reading exceeds (less than) this threshold, the low_felm interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. 54 N8970DSB O RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.38 0x34, 0x35 SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox7FFF. The value of this register is compared to the value of the SNR alarm meter. If the meter reading exceeds (greater than) this threshold, the low_snr interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. 3.2.39 0x36, 0x37 Cursor Level Register (cursor_level_low, cursor_level_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox2AAA (one-third of the maximum positive value). The value of this register represents the expected level of a noise-free +1 receive symbol at the output of the DFE. It is multiplied by 2 to produce the positive and negative slicing levels, in addition to zero, used by the symbol detec- tor in four-level slicing mode. This value is also used to scale the detector output when computing the equalizer error and slicer error signals. The detected symbol (3, 1, +1, +3) is multiplied by the value of this register to produce the scaled output. 3.2.40 0x38, 0x39DAGC Target Register (dagc_target_low, dagc_target_high) A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and Ox7FFF. The value of this register is subtracted from the abso- lute value of the receive signal at the output of the Digital Automatic Gain Control (DAGC) function. The dif- ference is used as the error input to the DAGC while in the self-adaptation mode. In the DAGCs equalizer-error adaptation mode, the contents of this register are not used. 3.2.41 0x3ASymbol Detector Modes Register (detector_modes) 7 6 5 4 3 2 1 0 enable_peak_det | output_mux_con | output_mux_con scr_out_to_dfe two_level lfsr_lock htur_Ifsr descr_on ector trol[ 1] trol[0] enable_peak_ detector Enable Peak DetectorRead/write control bit that enables the peak detection function when set; disables the function when cleared. When enabled, the peak detector output overrides the slicer output if the peak detection criteria are met. If the criteria are not met, or if the function is disabled, the slicer output is used and peak detector output is ignored. output_mux_ control[1, 0] Output Multiplexer ControlRead/write binary field that selects the source of the detector output connected to the channel unit receive interface. output_mux_control[1,0] Detector Output to CU Receive Interface 00 Same as scr_out_to_dfe selection 01 Transmitter loopback output from CU transmit interface 10 Scrambler/descrambler output 11 Reserved O Rockwell N8970DSB 55Registers Bt8970 Conventions scr_out_to_dfe two_level lfsr_lock htur_lfsr descr_on Single-Chip HDSL Transceiver Scrambler Output to DFERead/write control bit that selects the source of the detector output connected to the DFE and timing recovery module inputs, and the transmitters detector loop- back input. When set, this bit selects the scrambler/descrambler function; when cleared, it selects the slicer/peak detector output. Two-Level ModeRead/write control bit that selects two-level mode when set, four-level mode when cleared. Affects the slicer and the scrambler/descrambler function. In two-level mode, the slicer uses a single threshold set at zero to recover sign bits only; all magnitude information is lost. Scrambler/descrambler updates are slowed to the symbol rate (half the nor- mal bit rate) to process only sign information as well; all magnitude output bits are sourced with a constant logic zero value producing two-level symbols constrained to +3 and 3 values. In four-level mode, the slicer uses two thresholds derived from the Cursor Level Register [cursor_level_low, cursor_level_high; 0x360x37], as well as the zero threshold, to recover both sign and magnitude information. The scrambler/descrambler is updated at the full bit rate to process both sign and magnitude bits as well. LFSR LockRead/write control bit that enables the auto-scrambler synchronization mode (lfsr_lock) in the detector when set; disables this mode when cleared. Affects the behavior of the scrambler/descrambler function, overriding the descr_on setting. When enabled, the scrambler/descrambler is forced into the descrambler mode for 23 cycles. It is then switched to the scrambled-ones mode for 128 cycles. While in this mode, the outputs of the scrambler and the slicer/peak detector are compared against one another. The number of equivalent bits (equal comparisons) is accumulated and compared to the value of the Scrambler Synchroniza- tion Threshold Register [scr_sync_th; 0x2E]. At any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync interrupt flag is set in the IRQ source register [irq_source; 0x05] and the process terminates with the scrambler/descrambler left in the scrambled-ones mode. (The sync interrupt flag can- not be cleared while Ifsr_lock remains high.) After 128 cycles, if the threshold is not exceeded, the accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another 23 cycles, and the process repeats until either sync is achieved or this mode is dis- abled. Once disabled, the sync interrupt flag can be cleared (if active) and the scram- bler/descrambler returns to the mode specified by descr_on. Remote Unit (HTU-R/NTU) Polynomial SelectRead/write control bit that selects one of two feedback polynomials for the scrambler/descrambler. When set, this bit selects the remote unit (HTU-R/NTU) receive polynomial (x 3 +x>4 1); when cleared, is selects the local unit (HTU-C/LTUV) polynomial (x 23 4x 184 1). Descrambler/Scrambler SelectRead/write control bit that configures the scrambler/descram- bler function as a descrambler when set, and as a scrambler when cleared. As a scrambler, this bit can only generate a scrambled-all-ones sequence (constant high logic-level input); all incoming data is ignored. In the auto-scrambler synchronization mode (lfsr_lock = 1), this selection is overwritten though the value of the control bit is unaffected. 56 N8970DSB @ RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.42 0x3BPeak Detector Delay Register (peak_detector_delay) A 4-bit read/write register interpreted as an unsigned binary number. Specifies a number of additional symbol delays inserted in the peak detector input path of the symbol detector. Must be set to a value that equalizes the total path delay in each of the peak detector and slicer input paths according to the following formula: peak detector delay register value = DAGC delays + FFE delays fixed peak detector input delays. The DAGC and FFE delays are not fixed, but result from the microprogrammed implementation of these functions. If used unmodified, they equal 0 and 7, respectively. The fixed peak detector input delay is equal to 3. i 6 5 4 3 2 1 0 - - - - D[3] D[2] D[1] D[0] 3.2.43 0x3C Digital AGC Modes Register (dagc_modes) 1 6 5 4 3 A 5 - ~ ~ - - eq_error_ . adaptation adapt_coefficient adapt_gain eq_error_ adaptation Equalizer Error AdaptationRead/write control bit that selects between the equalizer-error adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error adapta- tion uses the equalizer error signal produced by the slicer as the DAGC error input signal. In self adaptation, the value of the DAGC Target Register [dagc_target_low, dagc_target_high; Ox38-0x39] is subtracted from the absolute value of the receive signal at the output of the DAGC, and this difference is used as the error input signal. adapt_coefficient Adapt CoefficientsRead/write control bit that enables coefficient adaptation when set; dis- ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis- abled. adapt_gain Adaptation GainRead/write control bit that specifies the adaptation gain. When set, the adaptation gain is eight times higher than when cleared. O Rockwell N8970DSB 57Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.44 0x3D Feed Forward Equalizer Modes Register (ffe_modes) 6 5 4 3 2 1 0 adapt_ adapt_last_coeff coefficents zero_coefficents adapt_gain adapt_last_coeff zero_coefficients adapt_coefficents adapt_gain Adapt Last CoefficientRead/write control bit enables adaptation of the last (oldest) coeffi- cient only when set; allows all coefficient adaptation when cleared. Overall coefficient adapta- tion must be enabled (adapt_coefficients = 1) for this behavior to occur. If coefficient adaptation is disabled (adapt_coefficients = 0), the value of this control bit is not used. Zero CoefficientsRead/write control bit which, with coefficient adaptation enabled (adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal coeffi- cient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0), this control bit has no affect. This behavior differs slightly from the similar function (zero_coefficients) of the LEC, NEC, and DFE filters. Adapt CoefficientsRead/write control bit enables coefficient adaptation when set; dis- ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis- abled. This overall coefficient adaptation must be enabled for adapt_last_coeff to have an affect. Adaptation GainRead/write control bit specifies the adaptation gain. When set, the adapta- tion gain is four times higher than when cleared. 3.2.45 Ox3EError Predictor Modes Register (ep_modes) 6 5 4 3 2 1 0 adapt_ zero_output coefficients zero_coefficients adapt_gain zero_output zero_coefficients adapt_coefficents Zero OutputRead/write control bit which, when set, zeros the error predictor correction sig- nal before subtraction from the input signal. Achieves the affect of disabling, or bypassing, the error predictor function. Does not disable coefficient adaptation. When cleared, normal error predictor operation is performed. Zero CoefficientsRead/write control bit which, with coefficient adaptation enabled (adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal coeffi- cient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0), this control bit has no affect. This behavior differs slightly from the similar function (zero_coefficients) of the LEC, NEC, and DFE filters. Adapt CoefficientsRead/write control bit enables coefficient adaptation when set; dis- ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis- abled. adapt_gain Adaptation GainRead/write control bit specifies the adaptation gain. When set, the adapta- tion gain is four times higher than when cleared. 58 N8970DSB 68 RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.46 0x40, 0x41 Phase Detector Meter Register (pdm_low, pdm_high) A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2s-complement phase detector meter accu- mulator. This meter sums the output of the timing recovery modules phase detectorprior to being offset by the Phase Offset Register [pll_phase_offset_low, pll_phase_offset_high; 0x24, 0x25]over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to Ox5F). 7 6 5 4 3 2 D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] 3.2.47 0x42 Overflow Meter Register (overflow_meter) A single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. This meter counts the number of ADC overflow conditions which occur during each Meter Timer countdown interval, lim- ited to a maximum count of 255 (OxFF). The meter register is automatically loaded at the end of each count- down interval. i 6 5 4 3 2 1 0 D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[o] 3.2.48 0x44, 0x45 DC Level Meter Register (dc_meter_low, dc_meter_high) A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2s-complement DC-level meter accumulator. This meter sums the value of the receive signal input pathafter format conversion and DC offset correction but before echo cancellationover each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to OxSF). 7 6 5 4 3 2 1 0 D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] @& Rockwell N8970DSB 59Bt8970 Single-Chip HDSL Transceiver Registers Conventions 3.2.49 0x46, 0x47 Signal Level Meter Register (sIm_low, slm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned signal-level meter accumulator. This meter sums the absolute value of the receive signal input pathafter format conversion and DC offset correc- tion but before echo cancellation (same point as the DC level meter)over each Meter Timer countdown inter- val. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to Ox5F). 7 6 5 4 3 2 1 0 D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] 3.2.50 0x48, 0x49Far-End Level Meter Register (felm_low, felm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned far-end level meter accumulator. This meter sums the absolute value of the receive signal pathafter echo cancellation but before the DAGC func- tionover each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to Ox5F). 7 6 5 4 3 2 1 0 D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] 3.2.51 0x4A, 0x4BNoise Level Histogram Meter Register (noise_histogram_low, noise_histogram_high) A 2-byte read-only register containing all 16 bits of the unsigned noise-level histogram meter accumulator. This meter counts the number of high-noise-level conditions which occur during each Meter Timer countdown inter- val. A high-noise-level condition is defined as the absolute value of the slicer error signal exceeding (greater than) the threshold specified in the Noise-level Histogram Threshold Register [Ox2A, 2B]. Automatically loaded at the end of each countdown interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to OxSF). 7 6 5 4 3 2 1 0 D[7] D6] D[5] D[4] D[3] D[2] DI 1] DIO] Dl 15] DI 14] Dl 13] D[12] D[11] D[ 10] D[9] D[8] 60 N8970DSB @ RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.52 0x4C, 0x4D Bit Error Rate Meter Register (ber_meter_low, ber_meter_high) A 2-byte read-only register containing all 16 bits of the unsigned bit-error-rate meter accumulator. This meter counts the number of error-free bits recovered by the detector during each Meter Timer countdown interval. An error-free bit is defined as a match (equal comparison) of the detectors slicer/peak detector output and its scrambler/descrambler output, when operating as a scrambler. When operating as a descrambler, the meter sim- ply counts the number of logic ones produced by the descrambler. The meter register is automatically loaded at the end of each countdown interval, and must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to Ox5F). 7 6 5 4 3 2 1 0 D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[o] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] 3.2.53 0x4ESymbol Histogram Meter Register (symbol_histogram) A single-byte read-only register containing 8 MSBs of the 16-bit unsigned symbol histogram meter accumula- tor. This meter counts the number of plus-one or minus-one symbols (+1, 1) detected during each Meter Timer countdown interval. No increment occurs when a plus-three or minus-three symbol (+3, 3) is detected. The meter register is automatically loaded at the end of each countdown interval. 7 6 5 4 3 2 1 0 D[7] D[] D[5] D[4] D[3] D[2] D[1] D[O] 3.2.54 0x50, 0x51 Noise Level Meter Register (nim_low, nlm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This meter sums the absolute value of the detectors slicer-error signal over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to Ox5F). 1 6 5 4 3 2 1 0 D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] O Rockwell N8970DSB 61Bt8970 Single-Chip HDSL Transceiver Registers Conventions 3.2.55 Ox5E, 0xSF PLL Frequency Register (pll_frequency_low, pll_frequency_high) A 2-byte read/write register comprising 16 MSBs of the 31-bit, 2s-complement timing recovery loop compen- sation filter accumulator. Treated much like a meter register, the frequency register must be read low byte first, followed by high byte, unseparated by any other Meter access (addresses 0x40 to OxSF). Writes must occur in the same order, with the low byte written first, followed by the high byte. Write accesses may be separated by any number of other read or write accesses. 7 6 5 4 3 2 1 0 D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[30] D[29] D[28] D[27] D[26] D[25] D[24] D[23] 3.2.56 Ox70LEC Read Tap Select Register (linear_ec_tap select_read) A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal. When written, it causes the selected 32-bit coefficient of the LEC to be subsequently loaded into the Access Data Register [access_data_byte[3:0]; 0x7COx7F] within two symbol periods. Does not affect the value of the coefficient. No other data access may occur between the time the Read Tap Select Register is written and the time the Access Data Register is read or the data may be corrupted. 7 6 5 4 3 2 1 0 - D[] D[5] D[4] D[3] D[2] D[1] D[O] 3.2.57 0x71LEC Write Tap Select Register (linear_ec_tap_select_write) A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal. When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; O0x7COx7F] to be sub- sequently written to the selected LEC coefficient within two symbol periods. Does not affect the value of the access data register. 7 6 5 4 3 2 1 0 - D[] D[5] D[4] D[3] D[2] D[ 1] D[O] 62 N8970DSB @ RockwellBt8970 Registers Single-Chip HDSL Transceiver Conventions 3.2.58 0x72 NEC Read Tap Select Register (nonlinear_ec_tap select_read) A 6-bit read/write register representing an unsigned binary address defined over a range of O to 63 decimals. When written, it causes the selected 14-bit coefficient of the NEC to be subsequently loaded into the lowest- order bits of the Access Data Register [access_data_byte[3:0]; 0x7COx7F] within two symbol periods. Does not affect the value of the coefficient. No other data access may occur between the time the Read Tap Select Register is written and the time the Access Data Register is read or the data may be corrupted. 7 6 5 4 3 2 1 0 - - D[5] D[4] D[3] D[2] D[1] D[o] 3.2.59 Ox73 NEC Write Tap Select Register (nonlinear_ec_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range of O to 63 decimals. When written, it causes the lowest-order 14 bits of the Access Data Register [access_data_byte[3:0]; 0x7C Ox7F] to be subsequently written to the selected NEC coefficient within two symbol periods. Does not affect the value of the access data register. 7 6 5 4 3 2 1 0 - - D[5] D[4] D[3] D[2] D[1] D[o] 3.2.60 0x74 DFE Read Tap Select Register (dfe_tap_select_read) A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 113 decimals. When written, it causes the selected 16-bit coefficient of the DFE to be subsequently loaded into the lowest- order bits of the Access Data Register [access_data_byte[3:0]; 0x7COx7F] within two symbol periods. Does not affect the value of the coefficient. No other data access may occur between the time the Read Tap Select Register is written and the time the Access Data Register is read or the data may be corrupted. 7 6 5 4 3 2 1 0 - D[6] D[5] D[4] D[3] D[2] D[1] D[o] 3.2.61 0x75 DFE Write Tap Select Register (dfe_tap select_write) A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 113 decimals. When written, it causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C Ox7F] to be subsequently written to the selected DFE coefficient within two symbol periods. Does not affect the value of the access data register. - D[6] D[5] D[4] D[3] D[2] D[1] D[o] O Rockwell N8970DSB 63Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.62 0x76 Scratch Pad Read Tap Select (sp_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range of O to 63 decimals. When written, it causes the selected 8-bit scratch pad memory location to be subsequently loaded into the low- est-order bits of the Access Data Register [access_data_byte[3:0]; 0x7COx7F] within two symbol periods. Does not affect the value of the memory. No other data access may occur between the time the Read Tap Select Register is written and the time the Access Data Register is read or the data may be corrupted. 7 6 5 4 3 2 1 0 - - D[5] D[4] D[3] D[2] D[1] D[o] 3.2.63 0x77 Scratch Pad Write Tap Select (sp tap _select_write) A 6-bit read/write register representing an unsigned binary address defined over a range of O to 63 decimals. When written, it causes the lowest-order 8 bits of the Access Data Register [access_data_byte[3:0]; 0x7C Ox7F] to be subsequently written to the selected scratch pad memory location within two symbol periods. Does not affect the value of the access data register. - - D[5] D[4] D[3] D[2] D[1] D[o] 64 N8970DSB O RockwellBt8970 Registers Single-Chip HDSL Transceiver 3.2.64 0x78 Equalizer Read Select Register (eq_add_read) Conventions A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals. When written, it causes the selected 16-bit location of the equalizer register file to be subsequently loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7COx7F] within two symbol peri- ods. Does not affect the value of the register file location. An address map of the shared register file, as defined by the factory-delivered microcode, is shown below. No other data access may occur between the time the Read Tap Select Register is written and the time the Access Data Register is read or the data may be corrupted. 7 5 4 3 2 1 0 - D[5] D[4] D[3] D[2] D[1] D[0] D[5:0} Stored Parameter Decimal Binary 0-7 00 0000-00 0111 FFE Coefficients 0-7 8-15 00 1000-00 1111 FFE Data Taps 0-7 16-20 01 0000-01 0100 EP Coefficients 0-4 21-25 01 0101-01 1001 EP Data Taps 0-4 26 01 1010 DAGC Gain - Least-Significant Word 27 01 1011 DAGC Gain - Most-Significant Word 28 01 1100 DAGC Output 29 01 1101 FFE Output 30 011110 DAGC Input 31 011111 FFE Output, Delayed 1 Symbol Period 32 10 0000 DAGC Error Signal 33 10 0001 Equalizer Error Signal 34 10 0010 Slicer Error Signal 35-47 10 0011-10 1111 Reserved O Rockwell N8970DSB 65Registers Bt8970 Conventions Single-Chip HDSL Transceiver 3.2.65 0x79 Equalizer Write Select Register (eq_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals. When written, it causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C Ox7F] to be subsequently written to the selected equalizer register file location within two symbol periods. Does not affect the value of the access data register. An address map of the shared register file, as defined by the fac- tory-delivered microcode, is shown above. 7 6 5 4 3 2 1 0 - - D[5] D[4] D[3] D[2] D[1] D[o] 3.2.66 0x7A Equalizer Microcode Read Select Register (eq_microcode_add_read) A 6-bit read/write register representing an unsigned binary address defined over a range of O to 63 decimals. When written, it causes the selected 32-bit location of the equalizer microprogram store to be subsequently loaded into the Access Data Register [access_data_byte[3:0]; Ox7COx7F] within two symbol periods. Does not affect the value of the microprogram store location. No other data access may occur between the time the Read Tap Select Register is written and the time the Access Data Register is read, or the data may be corrupted. 7 6 5 4 3 2 1 0 - - D[5] D[4] D[3] D[2] D[1] D[o] 3.2.67 0x7B Equalizer Microcode Write Select Register (eq_microcode_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range of O to 63 decimals. When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7COx7F] to be sub- sequently written to the selected equalizer microprogram store location within two symbol periods. Does not affect the value of the access data register. Factory-developed equalizer microcode is included with the no-fee licensed HDSL transceiver software available from Rockwell. i 6 5 4 3 2 1 0 - - D[5] D[4] D[3] D[2] D[1] D[O] 3.2.68 0x7C0x7F Access Data Register (access_data_byte3:0) A 4-byte read/write register stores filter coefficient, equalizer register file, and equalizer microprogram store contents during indirect accesses to these RAM-based locations. Writes to addresses 0x70 through 0x7B, utilize the contents of this shared register as specified in each of the individual register descriptions. 66 N8970DSB @ Rockwell4.0 Electrical & Mechanical Specifications 4.1 Absolute Maximum Ratings Stresses above those listed may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units Vsupply Supply Voltage -0.5 +7 V Vi Input Voltage on any Signal Pin? -0.5 Vppe + 0.5 V Tst Storage Temperature -65 +125 C Tysot Vapor-Phase Soldering Temperature (1 minute) +220 C Notes: (1). Vpp1, Vpps, relative to DGND. Va, relative to AGND. (2). Relative to DGND. O Rockwell N8970DSB 674.0 Electrical & Mechanical Specifications Bt8970 4.2 Recommended Operating Conditions 4.2 Recommended Operating Conditions Table 4-2. Recommended Operating Conditions Single-Chip HDSL Transceiver Symbol Parameter Minimum Typical Maximum | Units Vpp1 Digital Core-Logic Supply Voltage (+5 V) 4.75 5.0 5.25 V Vpp1 Digital Core-Logic Supply Voltage (+3.3 V) 3.0 3.3 3.6 V Vpp2 Digital |/O-Butfer Supply Voltage 4.75 5.0 5.25 V VaA Analog Supply Voltage 4.75 5.0 5.25 V Vin High-Level Input Voltage 2.0 Vppe2 + 0.3 V Vit Low-Level Input Voltage -0.3 +0.8 V Vinx High-Level Input Voltage for XTALI / MCLK 0.8* Vppe Vppe + 0.3 V ViLx Low-Level Input Voltage for XTALI / MCLK -0.3 0.2* Vppe V CL Output Capacitive Loading 60 pF Ta Ambient Operating Temperature -40 +85 C Notes: (1). Capacitive loading over which all digital output switching characteristics are guaranteed. (2). Still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaran- teed. 68 N8970DSB RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.3 Electrical Characteristics 4.3 Electrical Characteristics Typical characteristics measured at nominal operating conditions: T, = 25 C; Vppjaa = 5.0 V minimum/maxi- mum characteristics guaranteed over extreme operating conditions: min < T, < max; min < Vppya,a S max. Table 4-3. Electrical Characteristics Symbol Parameter Minimum Typical Maximum | Units Von | High-Level Output Voltage @ Ioy = -400 pA 2.4 V Voy | Low-Level Output Voltage @ Ig, = 6 mA (IRQ and READY) 0.4 Vv VoL Low-Level Output Voltage @ Ig, = 3 mA (All Other Outputs) 0.4 V I Input Leakage Current @ Vggo = Vi < Vppe +10 HA loz High-I|mpedance Output Leakage Current @ Vgge = Vo < Vppe +10 HA IpR Resistive Pull-Up Current @ V| = Vggo (TDI and TMS) -100 -800 HA Isvtor_ | Total Supply Current @ Foc) x = 80 kHz TBD 126 mA Isvtor_ | Total Supply Current @ Fag) x = 584 kHz TBD 246 mA Isypant | Partial Supply Current @ Fog) x = 80 kHz TBD 104 mA Isypant | Partial Supply Current @ Fog) x = 584 kHz) TBD 119 mA Igy | Vpp Supply Current @ Fac) , = 80 kHz? TBD 13 mA Igy | Vpp Supply Current @ Fag, = 584 kHz" TBD 81 mA Ipp _| Total Power-Down Current @ Fag, x = 80 kHz TBD mA Ipp _| Total Power-Down Current @ Fog, x = 584 kHz? TBD mA CQ Input Capacitance 10 pF Coz High-Impedance Output Capacitance 10 pF Notes: (1). Isytor =!pp1 + Ippe + !ag during normal operation. (2). Isypart = !pp2 + laa during normal operation. (3). Igy =Ipp4 during normal operation using 3.3 V. (4). Itorat = Ipp1 + Ipp2 + aq during power-down operation. O Rockwell N8970DSB 694.0 Electrical & Mechanical Specifications Bt8970 4.4 Clock Timing 4.4 Clock Timing Table 4-4, External Clock Timing Requirements (MCLK) Single-Chip HDSL Transceiver Symbol Parameter Minimum Maximum Units 1 MCLK Period (Tye. x) 80 782 ns 2 MCLK Pulse-Width Low 30 ns 3 MCLK Pulse-Width High 30 ns Note: (1). If an external clock is applied to XTALI/MCLK, it is referred to as MCLK. Figure 4-1. MCLK Timing Requirements Il I 1 | 3 ely 2 __,l | | | MCLK I I | Table 4-5. HCLK Switching Characteristics Symbol Parameter Minimum Typical Maximum Units 4 HCLK Period (Tye, x), helk_freq[ 1:0] = 11 (N=6) Tacik +64 Tact +64 Tact +64 5 HCLK Period (Tueik)s helk_freq[ 1 :0) = 00 or 01 Tack +16 Tack +16 Tack +16 (N=2) (7 6 HCLK Period (Tyy x), helk_freq[ 1:0] = 10 (N=4) Tacik +32 Tack +32 Tack +32 7 HCLK Pulse-Width High Tuck +2-10 THCLK +2 THCLK +2410 ns 8 HCLK Pulse-Width Low Tuck +2-10 THCLK +2 THCLK +2+10 ns Notes: (1). The hcelk_freq[ 1:0] control bits are located in the Serial Monitor Source Select Register [addr. 0x01]. 70 N8970DSB RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.4 Clock Timing Table 4-6. Symbol Clock (QCLK) Switching Characteristics Symbol Parameter Minimum Maximum Units 9 QCLK Period (Tac x)! K x THcLk KX THeLk 10 QCLK Pulse-Width High Tock 2-20 | Tock +2 +20 ns 11 QCLK Pulse-Width Low Tock 2-20 | Tock +2 +20 ns 12 QCLK Hold after HCLK Rising Edge -20 13 QCLK Delay after HCLK High 20 Note: (1). K = 16, 32, or 64 according to hclk_freq[ 1,0]. QCLK can be frequency locked to the incoming data symbol rate. Figure 4-2. Clock Control Timing 45,6 7 > HCLK | J\I\S\ J\IW 8 13 + 9 > |<_ {0 12 QCLK O Rockwell N8970DSB 714.0 Electrical & Mechanical Specifications Bt8970 4.5 Channel Unit Interface Timing Single-Chip HDSL Transceiver 4.5 Channel Unit Interface Timing Table 4-7. Channel Unit Interface Timing Requirements, Parallel Master Mode Symbol Parameter Minimum | Maximum | Units 14 TQ[1,0] Setup prior to QCLK Falling Edge 100 ns 15 TQ[1,0] Hold after QCLK Low 25 ns Table 4-8. Channel Unit Interface Switching Characteristics, Parallel Master Mode Symbol Parameter Minimum | Maximum | Units 16 RQ[1,0] Hold after QCLK Rising Edge -50 ns 17 RQ[1,0] Delay after QCLK High 50 ns Figure 4-3. Channel Unit Interface Timing, Parallel Master Mode RQ[1,0] 16 } 1 7 ocx / 15 TQ[1,0] 72 N8970DSB @ RockwellBt8970 Single-Chip HDSL Transceiver Table 4-9. Channel-Unit Interface Timing Requirements, Parallel Slave Mode 4.0 Electrical & Mechanical Specifications 4.5 Channel! Unit Interface Timing Symbol Parameter Minimum | Maximum | Units 18 TBCLK, RBCLK Period Tack Tack 19 TBCLK, RBCLK Pulse-Width High Tacik + 4 20 TBCLK, RBCLK Pulse-Width Low Tacik + 4 21 TQ[1,0] Setup prior to TBCLK Active Edge 25 ns 22 TQ[1,0] Hold after TBCLK High/Low? 25 ns Notes: (1). TBCLK and RBCLK must be frequency locked to QCLK though they may have independent phase relationships to QCLK and to one another. (2). TBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes 0x06]. Table 4-10. Channel Unit Interface Switching Characteristics, Parallel Slave Mode Symbol Parameter Minimum | Maximum | Units 23 RQ[1,0] Hold after RBCLK Active Edge 0 ns 24 RQ[1,0] Delay after RBCLK High/Low 100 ns 0x06]. Notes: (1). RBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes; @& Rockwell N8970DSB 734.0 Electrical & Mechanical Specifications Bt8970 4.5 Channel Unit Interface Timing Single-Chip HDSL Transceiver Figure 4-4. Channel Unit Interface Timing, Parallel Slave Mode + 18 > RBCLK bo $ $<] Qa 2. }< 2 4_____| }2:3+ RQ[1:0] < 18 > TBCLK < 19 m be 20 > 21 | | 22 | TQ[1:0] Note: TBCLK and RBCLK polarities are programmable through the CU Interface Modes register. The figure depicts both clocks programmed to falling-edge active. Table 4-11. Channel Unit Interface Timing Requirements, Serial Mode Symbol Parameter Minimum | Maximum | Units 25 TDAT Setup prior to BCLK Falling Edge 100 ns 26 TDAT Hold after BCLK Low 25 ns Table 4-12. Channel Unit Interface Switching Characteristics, Serial Mode Symbol Parameter Minimum Maximum | Units 27 BCLK Period Tacik + 2 Taek + 2 28 BCLK Pulse-Width High Tacik+ 4-20 | Tog x +4+20] ns 29 BCLK Pulse-Width Low Tacik + 4-20 | Tacik+4+20] ns 30 BCLK Hold after HCLK Rising Edge 0 ns 31 BCLK Delay after HCLK High 50 ns 32 RDAT, QCLK Hold after BCLK Rising Edge -50 ns 33 RDAT, QCLK Delay after BCLK High 50 ns 74 N8970DSB @ RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver Figure 4-5. Channel Unit Interface Timing, Serial Mode 4.5 Channel! Unit Interface Timing HCLK BCLK QCLK RDAT TDAT 31 [UNV UN\E UN UY at 28. 30 e-3 3a 32> 25 26 @& Rockwell N8970DSB 754.0 Electrical & Mechanical Specifications Bt8970 4.6 Microcomputer Interface Timing Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing Table 4-13. Microcomputer Interface Timing Requirements Symbol Parameter Minimum Maximum Units 34 ALE Pulse-Width High 30 ns 35 | Address Setup prior to ALE Falling Edge! 12 ns 36 | Address Hold after ALE Low? 5 ns 37 _| ALE low prior to Write Strobe Falling Edge 20 ns 38 | ALE low prior to Read Strobe Falling Edge?,4/ -27 ns 39 | Write Strobe Pulse-Width Low) 0.5 Tmclk +25 ns 40 Read Strobe Pulse- Width Low'?) 0.5* Tmelk +25 ns 44 Data In Setup prior to Write Strobe Rising Edge 30 ns 42 Data In Hold after Write Strobe High 5 ns 43 RW Setup prior to Read/Write Strobe Falling Edge 10 ns 44 R/W Hold after Read/Write Strobe High 10 ns 45 ALE Falling Edge after Write Strobe High 20 ns 46 ALE Falling Edge after Read Strobe High 20 ns 47 | RST Pulse-Width Low 50 ns 48 Write Strobe Rising Edge after READY low 0 ns Notes: (1). Address is defined as AD[7:0] when MUXED = 1, and ADDR[7:0] when MUXED = 0. _ (2). In Intel mode, Write Strobe is defined as WR and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W is low. _ _ _ (3). In Intel mode, Read Strobe is defined as RD and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W is high. (4). Parameter 38 is -27 ns only if separate address and data busses are used (i.e., muxed = 0). If muxed = 1, then parameter 38 is 20 ns. (5). The timing listed is for the synchronous mode of the MCI. It can also be set to asynchronous mode by setting bit 0 of the reserved2 register (address Ox0F) to a1. In this case the minimum timing changes to 40 us for symbol 39, and 50 ns for symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no signif- icant performance degradation has been measured as a result of using the asynchronous mode. 76 N8970DSB Oo RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing Table 4-14. Microcomputer Interface Switching Characteristics Symbol Parameter Minimum Maximum Units 49 | Data Out Enable (Low Z) after Read Strobe Falling Edge 2 ns 50 _| Data Out Valid after Read Strobe Low. 7) 0.5* Tmclk +25 | ns 51 Data Out Hold after Read Strobe Rising Edge? 2 ns 52 | Data Out Disable (High Z) after Read Strobe High 25 ns 53 | IRQHold after Write Strobe Rising Edge 5 ns 54 _| IRQ Delay after Write Strobe High) Tqclk +32+20 | ns 55 Internal Register Delay after Write Strobe High Tqclk + 32 ns 56 Internal RAM Delay after Write Strobe High) 2* Tqclk ns 57 | Access Data Register Delay after Write Strobe High4 2* Taclk ns 58 | READY Falling Edge after Write Strobe Low? 0 0.5" Tmclk +25 | ns 59 _| READY Rising Edge after Write Strobe High! 0 50 ns 60 _| READY Falling Edge after Read Strobe Low! 0 0.5Tmclk +25 | ns 61 | READY Rising Edge after Read Strobe High! 0 50 ns 62 | Data Out Valid after READY low 10 ns Notes: (1). Read Strobe is defined as RD and CS asserted in Intel mode, and DS and CS asserted when R/W is high in Motorola mode. (2). When writing an interrupt mask or status register. _ _ (3). Write Strobe is defined as WR and CS asserted in Intel mode, and DS and CS asserted when R/W is low in Motorola mode, (4). Writes to internal registers are synchronized to an internal 64-times symbol-rate clock. Data is available for reading after the specified time. This parameter may extend the overall read access time from internal register locations under high bus speed/low symbol rate conditions. (5). When performing an indirect write to RAM-based locations using a write select register [odd addresses: 0x7 10x7B] and the Access Data Register. Subsequent writes to any read/write select register or the Access Data Register, as initiated by a Write Strobe falling edge, is prohibited for the specified time. This parameter will extend the overall write access time to RAM-based locations under normal bus speed/symbol rate conditions. (6). When performing an indirect read from RAM -based locations using a read select register [even addresses: 0x70-0x7A] and the Access Data Register. Subsequent writes to any read/write select register, as initiated by a Write Strobe falling-edge, is prohibited for the specified time. Data is available for reading from the Access Data Register after the specified time. This parameter will extend the overall read access time from RAM-based locations under normal bus speed/symbol rate conditions. Direct writes to the Access Data Register are as specified for internal registers. (7). The timing listed is for the synchronous mode of the MCI. It can also be set to asynchronous mode by setting bit 0 of the reserved2 register (address Ox0F) to a1. In this case the minimum timing changes to 40 us for symbol 39, and 50 ns for symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no signif- icant performance degradation has been measured as a result of using the asynchronous mode. O Rockwell N8970DSB 774.0 Electrical & Mechanical Specifications Bt8970 4.6 Microcomputer Interface Timing Figure 4-6. MCI Write Timing, Intel Mode (MOTEL = 0) Single-Chip HDSL Transceiver AD[7:0] or Address Data (Input) ADDR[7:0] e354 36 + [a4.2_$+ Write Strobe 3 /______ -<39_+| 4 m 45. > 4. 8 __p| ALE / \ 58 59 READY / Figure 4-7. MCI Write Timing, Motorola Mode (MOTEL = 1) ADI7:0] Address Data (Input) or ADDR[?:0] le-35-| | 36 4. |] _ <_P> a4. 2 _-| Write Strobe a 37. > oe la 4.8___p RW | 43 | 44 34 45 > 58 ALE _ / \ 59 READY / 78 N8970DSB O RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing Figure 4-8. MCI Read Timing, Intel Mode (MOTEL = 0) ADI7:0] or Address Data (Output) ADDRI7:0] a-35-| 36 49 <P /<_} 1 - <8 | [e504 < 52 Read 62 Strobe _ 40: > 34 _ 46 ~ ALE / \ at: 61 _ READY 60 YY Figure 4-9. MCI Read Timing, Motorola Mode (MOTEL = 1) AD[7:0 [ | Address Data (Output) ADDRI7:0] at- 3 5-| 36 _A9 54 38 + me 5O |} 5 2 _____ 62 Read |<} Strobe < 40______-| RAW / 34 ALE / \ O Rockwell N8970DSB 794.0 Electrical & Mechanical Specifications Bt8970 4.6 Microcomputer Interface Timing Single-Chip HDSL Transceiver Figure 4-10. Internal Write Timing Write \ Strobe <5 4___| [5 5 $s Internal Register Internal RAM Access Data Register 80 N8970DSB @ RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing 4.6.1 Test and Diagnostic Interface Timing Table 4-15. Test and Diagnostic Interface Timing Requirements Symbol Parameter Minimum | Maximum | Units 63 TCK Pulse-Width High 80 ns 64 TCK Pulse-Width Low 80 ns 65 TMS, TDI Setup prior to TCK Rising Edge 20 ns 66 TMS, TDI Hold after TCK High" 20 ns Notes: (1). Also applies to functional inputs for SAMPLE/PRELOAD and EXTEST instructions. Table 4-16. Test and Diagnostic Interface Switching Characteristics Symbol Parameter Minimum | Maximum | Units 67 TDO Hold after TCK Falling Edge 0 ns 68 TDO Delay after TCK Low? 50 ns 69 TDO Enable (Low Z) after TCK Falling Edge 2 ns 70 TDO Disable (High Z) after TCK Low 25 ns 71 SMON Hold after HCLK Rising Edge 0 ns 72 SMON Delay after HCLK High? 50 ns Notes: (1). Also applies to functional outputs for the EXTEST instruction. (2). HCLK must be programmed to operate at 16 times the symbol rate (16 x Foc). O Rockwell N8970DSB 814.0 Electrical & Mechanical Specifications Bt8970 4.6 Microcomputer Interface Timing Figure 4-11. JTAG Interface Timing Single-Chip HDSL Transceiver TDO 69 TCK TDI TMS Xy a6 7 po ba6: 3p} ba 68 _ 65 66 1+ 64 }~ 7 0+ Figure 4-12. SMON Timing HCLK SMON L 7 2| 71| TN TFN 82 N8970DSB RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing 4.6.2 Analog Specifications Table 4-17. Receiver Analog Requirements and Specifications Parameter Comments Min Typ Max Units Input Signals RXP, RXN, RXBP, and RXBN Input Voltage Range Balanced Differential -4.5 +45 V Input Resistance DC to 1 MHz TBD kQ. Common Mode Voltage VCOMI 0.4* VAA Variable Gain Amplifier (VGA) Six gains from 0 dB to +15 dB Gain Step 2.55 3.0 3.42 dB Gain Error +H10 % Analog-to-Digital Converter Output Symbol Rate (Foc, x) QCLK frequency (Data Rate/2) 200 584 kHz Differential Voltage Range (Full Scale (Vaxp-Vaxn) (Vaxep-VRxBn) 5.4 6.0 6.6 Vp Input, FS) Timing Recovery PLL Pull-In Range +64 ppm Notes: (1). Corresponds to the voltages that will produce a full scale reading from the ADC when the VGA gain equals OdB. Input voltage range is reduced proportionally as VGA gain is increased. O Rockwell N8970DSB 834.0 Electrical & Mechanical Specifications Bt8970 4.6 Microcomputer Interface Timing Table 4-18. Transmitter Analog Requirements and Specifications Single-Chip HDSL Transceiver Parameter Comments Min Typ Max Units Transmit Symbol Rate (fgcix) QCLK Frequency (Data Rate/2) 200 584 kHz Pulse Template! 2 9 See Figure 4-13, Ry = 135 Q Average Power: 2 4 DC to 2xFag x, Ry = 135 , OdB gain 13.4 14.0 dBm setting Gain Adjustment Step Controlled by Transmit Gain Register 0.17 0.20 0.24 dB [0x29]. Seven steps above and eight steps below 0 dB. Output Referred Offset Voltage 25 mV Output Current 125 mA Common-Mode Voltage VCOMO VAA/2 V Output Impedance DC to 1 MHz 2 Q Linearity At Output Symbol Peak 0.01 % FSR Harmonic Distortion 3 kHz, 3.4 V Peak Sine Wave Output, R, -70 dB =0Q0 0x28] to the Transmitter (5). FSRis Full Scale Range. Notes: (1). Guaranteed by design and characterization. (2). See 4-14 of the Test Conditions section of this datasheet for test circuit. (3). Measured after the transmitter is calibrated by writing the value in the Transmitter Calibration Register [tx_calibrate; Gain Register [tx_gain; 0x29]. (4). Measured with a pseudo-random code sequence of pulses. 84 N8970DSB RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing Figure 4-13. Transmitted Pulse Template -0.4T 0.4T B = 1.07 I C = 1.00 D =0.93 _ T = t/FacL 1.257 A=0.01 E =0.03 i A=0.01 F=o01 | Tos = 00 -1.2T =-0. -0.6T | 0.5T G=0.16 ar so Table 4-19. Transmitted Pulse Template Normalized Level Quaternary Symbols +3 +1 -1 -3 A 0.01 0.0264 0.0088 -0.0088 -0.0264 B 1.07 2.8248 0.9416 -0.9416 -2,8248 C 1.00 2.6400 0.8800 -0.8800 -2,.6400 D 0.93 2.4552 0.8184 -0.8184 -2,.4552 E 0.03 0.0792 0.0264 -0.0264 -0.0792 F -0.01 -0.0264 -0.0088 0.0088 0.0264 G -0.16 -0.4224 -0.1408 0.1408 0.4224 H 0.05 -0.1320 -0.0440 0.0440 0.1320 O Rockwell N8970DSB 854.0 Electrical & Mechanical Specifications Bt8970 4.6 Microcomputer Interface Timing Single-Chip HDSL Transceiver 4.6.3 Test Conditions Figure 4-14. Transmitter Test Circuit 3.01 kQ 1 kQ 1kQ TXP (714 TXPSP (67) WW TXLDIP (69) P (71) c8 ane > 1kQ 1kQ river TXPSN (68) Wy Wy TXLDIN (70) - TN (74) 3.01 ka 16.20 1:2 + NW Line + 16.20 Transformer_ Ri Note: See Table 4-20 for C8 and transformer values. 86 N8970DSB @ RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.6 Microcomputer Interface Timing Table 4-20. Transmitter Test Circuit Component Values Data Rate Component 784 kbps 1168 kbps C8 680 pF 470 pF L (Primary Inductance - Line Side) 3.0 mH 2.0mH Figure 4-15. Standard Output Load (Totem Pole and Three-State Outputs) From Bt8970 1.5V Figure 4-16. Open-Drain Output Load (IRQ) From Bt8970 O Rockwell N8970DSB 874.0 Electrical & Mechanical Specifications Bt8970 4.7 Timing Measurements Single-Chip HDSL Transceiver 4.7 Timing Measurements Figure 4-17 illustrates input waveforms. Output waveforms are displayed in Figures 4-18 and 4-19. Figure 4-17. Input Waveforms for Timing Tests 3V 2.0V 0.8V OV Input Input Input Input High Low Low High Figure 4-18. Output Waveforms for Timing Tests =VDD 24V 0.4V =0V Output Output Output Output High Low Low High 88 N8970DSB @ RockwellBt8970 4.0 Electrical & Mechanical Specifications Single-Chip HDSL Transceiver 4.7 Timing Measurements Figure 4-19. Output Waveforms for Three-state Enable and Disable Tests Vou -0.2V 1.7V 15V S \ 13V ( VoL + 0.2V Output Output Output Disabled Enabled Disabled O Rockwell N8970DSB 894.0 Electrical & Mechanical Specifications Bt8970 4.8 Mechanical Specifications Single-Chip HDSL Transceiver 4.8 Mechanical Specifications Figure 4-20. 100-Pin Plastic Quad Flat Pack (PQFP) TOP VIEW BOTTOM VIEW ALL DIMENSIONS IN MILLIMETERS Tomz<w MIN. |NOM. | MAX. A | *%e [3.04 | 3.40 Ai | 0.25 [0.33 | Az | 2.57 | 2.71 | 2.87 AD D 23.20 BSC. Di | 20.00 BSC. E 17.20 BSC. E: | 14.00 BSC. {____. L | 0.65] 0.70| 0.95 | L i e 0.65 BSC (280 EF. b [0.22|~ |0.38 90 N8970DSB @ RockwellPlease mail or fax this form to: Rockwell Semiconductor Systems Manager, Technical Publications Dept. (619) 597-4338 READER RESPONSE PAGE e welcome your evaluation of this publication. Your comments and sug- gestions will help us make improve- ments to all current and future documents. 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