REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change drawing CAGE code to 67268. Add case outline. Device type 02JX no longer available from an approved source. Technical and editorial changes throughout. 91-11-01 M. A. Frye B Changes in accordance with NOR 5962-R101-93. 93-03-23 Monica L. Poelking C D Changes in accordance with NOR 5962-R148-93. Add vendor CAGE F8859. Add device class V criteria. Editorial changes throughout - gap. Add case outline X. Add delta limits for class V devices. Editorial changes throughout - gap. Change the delta limit for the VOH parameter in table III. Update boilerplate to latest MIL-PRF-38535 requirements. - CFS 93-09-16 Monica L. Poelking 99-11-23 Raymond Monnin 00-07-27 Raymond Monnin 01-01-17 Thomas M. Hess E F G Add case outline Z. - jak 01-07-23 Thomas M. Hess H Add section 1.5, radiation features. Update boilerplate to MIL-PRF-38535 requirements and to include radiation hardness assured requirements. Editorial changes throughout. - LTG 05-03-14 Thomas M. Hess Add appendix A to document. Update radiation hardness assurance requirements. - LTG 07-06-21 Thomas M. Hess J CURRRENT CAGE CODE 67268 REV SHEET REV SHEET J J J J J J J J J J J J 15 16 17 18 19 20 21 22 23 24 25 26 REV J J J J J J J J J J J J J J SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A PREPARED BY Marcia B. Kelleher DEFENSE SUPPLY CENTER COLUMBUS CHECKED BY Thomas J. Riccuiti COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 87-06-23 REVISION LEVEL J MICROCIRCUITS, DIGITAL, ADVANCED CMOS, OCTAL BUFFER/LINE DRIVER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON SIZE CAGE CODE A 14933 5962-87552 SHEET 1 OF DSCC FORM 2233 APR 97 26 5962-E226-07 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device classes M and Q: 5962 - Federal stock class designator \ 87552 RHA designator (see 1.2.1) 01 X A Device type (see 1.2.2) Case outline (see 1.2.4) Lead finish (see 1.2.5) 01 V X A Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number For device class V: 5962 F Federal stock class designator \ RHA designator (see 1.2.1) 87552 Device type (see 1.2.2) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 Generic number Circuit function 54AC244 54AC11244 Octal buffer/line driver with three-state outputs Octal buffer/line driver with three-state outputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device. Device class M Q or V Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 2 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter J K L R S X Z 2 3 Descriptive designator GDIP1-T24 or CDIP2-T24 GDFP2-F24 or CDFP3-F24 GDIP3-T24 or CDIP4-T24 GDIP1-T20 or CDIP2-T20 GDFP2-F20 or CDFP3-F20 See figure 1 GDFP1-G20 CQCC1-N20 CQCC1-N28 Terminals 24 24 24 20 20 20 20 20 28 Package style Dual-in-line Flat pack Dual-in-line Dual-in-line Flat pack Flat pack Flat pack Square leadless chip carrier Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) .................................................................................. -0.5 V dc to +7.0 V dc DC input voltage range (VIN) ................................................................................ -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) ........................................................................... -0.5 V dc to VCC + 0.5 V dc Clamp diode current (IIK, IOK)................................................................................ 20 mA DC output current (per output pin) ....................................................................... 50 mA DC VCC or GND current (per output pin) .............................................................. 25 mA 4/ Maximum power dissipation (PD) ......................................................................... 500 mW Storage temperature range (TSTG) ....................................................................... -65C to +150C Lead temperature (soldering, 10 seconds): Case outline X.................................................................................................... +260C All other case outlines except case X ................................................................ +245C Thermal resistance, junction-to-case (JC) ........................................................... See MIL-STD-1835 Junction temperature (TJ) .................................................................................... +175C 5/ 1.4 Recommended operating conditions. 2/ 3/ 6/ Supply voltage range (VCC) .................................................................................. +2.0 V dc to +6.0 V dc Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC Case operating temperature range (TC) ............................................................... -55C to +125C Input rise or fall times (tr, tf): Device type 01: VCC = 3.6 V and 5.5 V .................................................................................... 0 to 8 ns/V Device type 02: Data (VCC = 3.6 V and 5.5 V) ......................................................................... 0 to 10 ns/V mOE (VCC = 3.6 V and 5.5 V) ....................................................................... 0 to 5 ns/V 1/ 2/ 3/ 4/ 5/ 6/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Unless otherwise noted, all voltages are referenced to GND. The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -55C to +125C. For devices with multiple VCC or GND pins, this value represents the total VCC or GND current. Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Operation from 2.0 V dc to 3.0 V dc is provided for compatibility with data retention and battery back-up systems. Data retention implies no input transition and no stored data loss with the following conditions: VIH 70% VCC, VIL 30% VCC, VOH 70% VCC @ -20 A, VOL 30% VCC @ 20 A. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 3 1.5 Radiation features. Device type 01: Total dose (dose rate = 50 - 300 rads (Si)/s) ................................................. 300 krads (Si) Single Event Latchup (SEL)............................................................................ 93 MeV-cm2/mg 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXXX and 54/74ACTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http://www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of semiconductor Devices. (Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 4 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein, or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 5 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 37 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 6 TABLE IA. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ Positive input clamp voltage 3022 Negative input clamp voltage 3022 High level output voltage 3006 Symbol Test conditions 2/ 3/ -55C TC +125C +3.0 V VCC +5.5 V unless otherwise specified VIC+ For input under test, IIN = 1.0 mA VIC- For input under test, IIN = -1.0 mA VOH VIN = VIH minimum or VIL maximum IOH = -50 A 5/ Device type and device class All V VIN = VIH minimum or VIL maximum IOH = -12 mA VIN = VIH minimum or VIL maximum IOH = -24 mA Low level output voltage 3007 VOL 5/ High level input voltage VIH Min Max 1.5 V All V Open 1 -0.4 -1.5 V All All All All All All All All 3.0 V 1, 2, 3 2.9 4.5 V 1, 2, 3 4.4 5.5 V 1, 2, 3 5.4 3.0 V 1 2.56 5.5 V 2, 3 1 2, 3 1 2, 3 1, 2, 3 2.40 3.86 3.70 4.86 4.70 3.85 3.0 V 1, 2, 3 0.1 4.5 V 1, 2, 3 0.1 5.5 V 1, 2, 3 0.1 3.0 V 1 0.36 5.5 V 2, 3 1 2, 3 1 2, 3 1, 2, 3 0.50 0.36 0.50 0.36 0.50 1.65 3.0 V 1, 2, 3 2.1 4.5 V 1, 2, 3 3.15 5.5 V 1, 2, 3 3.85 All All All All All All 6/ Unit 0.4 All All All All All All VIN = VIH minimum or VIL maximum IOL = 50 mA Limits 4/ 1 All All All All All All All All VIN = VIH minimum or VIL maximum IOL = 12 mA VIN = VIH minimum or VIL maximum IOL = 24 mA Group A subgroups 0.0 V All All All All All All VIN = VIH minimum or VIL maximum IOH = -50 mA VIN = VIH minimum or VIL maximum IOL = 50 A VCC 4.5 V 5.5 V 4.5 V 5.5 V V V V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 7 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Low level input voltage Symbol Test conditions 2/ 3/ -55C TC +125C +3.0 V VCC +5.5 V unless otherwise specified VIL 6/ Device type and device class All All All All All All All All VCC Group A subgroups Limits 4/ Min Unit Max 3.0 V 1, 2, 3 0.9 V 4.5 V 1, 2, 3 1.35 5.5 V 1, 2, 3 1.65 5.5 V 1 -0.1 A Input leakage current low 3009 Input leakage current high 3010 Quiescent supply current, output high 3005 IIL VIN = 0.0 V IIH VIN = 5.5 V All All 5.5 V 2, 3 1 -1.0 0.1 A ICCH VIN = VCC or GND All All 5.5 V 2, 3 1 1.0 4 A 2, 3 1 80 50 Quiescent supply current, output low 3005 ICCL 5.5 V 1 2, 3 1 4 80 50 A Quiescent supply current, output three-state 3005 ICCZ 5.5 V 1 2, 3 1 4 80 50 A Three-state output leakage current high 3021 IOZH All All 5.5 V 1, 2, 3 +5.0 A Three-state output leakage current low 3020 IOZL All All 5.5 V 1, 2, 3 -5.0 A Input capacitance 3012 Power dissipation capacitance Functional tests 3014 CIN All All All All All All GND 4 8.0 pF 5.0 V 4 60.0 pF 3.0 V 7, 8 L H 5.5 V 7, 8 L H M, D, P, L, R, F 7/ VIN = VCC or GND M, D, P, L, R, F 7/ 01 Q, V All All 01 Q, V VIN = VCC or GND M, D, P, L, R, F 7/ All All 01 Q, V mOE = VIH min or VIL max All other inputs = VCC or GND VOUT = 5.5 V, test with each mOE = VIH min CPD 8/ 9/ mOE = VIH min or VIL max All other inputs = VCC or GND VOUT = GND, test with each mOE = VIH min See 4.4.1c TC = +25C See 4.4.1c TC = +25C, f = 1 MHz See 4.4.1b VIN = VIH min or VIL max Verify output VOUT See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 8 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Propagation delay time, mAn to mYn 3003 Symbol tPHL Test conditions 2/ 3/ -55C TC +125C +3.0 V VCC +5.5 V unless otherwise specified CL = 50 pF minimum RL = 500 See figure 5 10/ tPLH 10/ Device type and device class 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All VCC 3.0 V Group A subgroups 9 10, 11 4.5 V 9 10, 11 3.0 V 9 10, 11 4.5 V 9 10, 11 Limits 4/ Min Max 1.0 10.5 1.0 8.6 1.0 12.0 1.0 10.5 1.0 8.0 1.0 6.4 1.0 9.0 1.0 7.4 1.0 11.0 1.0 9.3 1.0 12.5 1.0 10.8 1.0 8.5 1.0 6.7 1.0 9.5 1.0 7.7 Unit ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 9 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Propagation delay time, output disable, mOE to mYn 3003 Symbol tPHZ Test conditions 2/ 3/ -55C TC +125C +3.0 V VCC +5.5 V unless otherwise specified CL = 50 pF minimum RL = 500 See figure 5 10/ tPLZ 10/ Device type and device class 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All VCC 3.0 V Group A subgroups 9 10, 11 4.5 V 9 10, 11 3.0 V 9 10, 11 4.5 V 9 10, 11 Limits 4/ Min Max 1.0 10.0 1.0 7.9 1.0 12.5 1.0 8.7 1.0 9.0 1.0 7.0 1.0 10.5 1.0 7.6 1.0 11.0 1.0 9.4 1.0 13.0 1.0 10.4 1.0 9.0 1.0 7.8 1.0 11.0 1.0 8.6 Unit ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 10 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Propagation delay time, output enable, mOE to mYn 3003 Symbol tPZH Test conditions 2/ 3/ -55C TC +125C +3.0 V VCC +5.5 V unless otherwise specified CL = 50 pF RL = 500 See figure 5 10/ tPZL 10/ Device type and device class 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All 01 All 02 All VCC 3.0 V Group A subgroups 9 10, 11 4.5 V 9 10, 11 3.0 V 9 10, 11 4.5 V 9 10, 11 Limits 4/ Min Max 1.0 10.5 1.0 10.7 1.0 11.5 1.0 12.9 1.0 7.5 1.0 7.7 1.0 9.0 1.0 9.3 1.0 11.0 1.0 10.6 1.0 13.0 1.0 12.9 1.0 8.5 1.0 7.6 1.0 10.5 1.0 9.1 Unit ns 1/ For tests not listed in the referenced MIL-STD-883, [e.g. VIH, VIL], utilize the general test procedure under the conditions listed herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table IA herein. Output terminals not designated shall be high level logic, low level logic, or open, except as follows: a. VIC (pos) tests, the GND terminal can be open. TC = +25C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25C. c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the circuit such that all current flows through the meter. 3/ RHA parts for device type 01 of this drawing have been characterized through all levels M, D, P, L, R, and F of irradiation. However, these devices are only tested at the 'F' level. Pre and post irradiation values are identical unless otherwise specified in table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25C. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 11 TABLE IA. Electrical performance characteristics - Continued. 4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table IA, as applicable, at 3.0 V VCC 3.6 V and 4.5 V VCC 5.5 V. 5/ The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for other values of VCC. Limits shown apply to operation at VCC = 3.3 V 0.3 V and VCC = 5.0 V 0.5 V. Tests with input current at +50 mA or -50 mA are performed on only one input at a time with duration not to exceed 10 ms. Transmission driving tests may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = VIH minimum and VIL maximum. 6/ The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests. 7/ The maximum limit for this parameter at 100 krads (Si) is 4 A. 8/ Power dissipation capacitance (CPD) determines both the dynamic power consumption (PD) and dynamic current consumption (IS). Where: PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC) IS = (CPD + CL) VCCf + ICC f is the frequency of the input signal and CL is the external output load capacitance. 9/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 3 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. Allowable tolerances in accordance with MIL-STD-883 for the input voltage levels may be incorporated. For VOUT measurements, L 0.3VCC and H 0.7VCC. 10/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. AC limits at VCC = 3.6 V are equal to the limits at VCC = 3.0 V and guaranteed by testing at VCC = 3.0 V. Minimum ac limits for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all paths must be tested. 1/ 2/ TABLE IB. SEP test limits. Device type SEP TC = temperature 10C VCC Effective LET 01 SEL +25C 3.6 V and 5.5 V 93 MeV-cm2/mg 1/ For SEP test conditions, see 4.4.4.2 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 12 Case X Dimensions Symbol Inches Millimeters Min Max Min Max A .045 .085 1.14 2.16 b .015 .019 0.38 0.48 c .003 .006 0.076 0.152 D .505 .515 12.83 13.08 E .275 .285 6.99 7.24 e .045 .055 1.14 1.40 L .250 .370 6.35 9.39 Q .010 --- 0.25 --- N 20 20 FIGURE 1. Case outlines. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 13 Device types Case outlines 01 R, S, X, Z Terminal number 02 2 J, K, L Terminal symbol 3 Terminal symbol 1 1OE 1OE 1Y1 NC 2 1A1 1A1 1Y2 VCC 3 2Y4 2Y4 1Y3 1A4 4 1A2 1A2 1Y4 1A3 5 2Y3 2Y3 GND 1A2 6 1A3 1A3 GND 1A1 7 2Y2 2Y2 GND 1OE 8 1A4 1A4 GND NC 9 2Y1 2Y1 2Y1 1Y1 10 GND GND 2Y2 1Y2 11 2A1 2A1 2Y3 1Y3 12 1Y4 1Y4 2Y4 1Y4 13 2A2 2A2 2OE GND GND 14 1Y3 1Y3 2A4 15 2A3 2A3 2A3 NC 16 1Y2 1Y2 2A2 GND 17 2A4 2A4 2A1 GND 18 1Y1 1Y1 VCC 2Y1 19 2OE 2OE VCC 2Y2 20 VCC VCC 1A4 2Y3 21 --- --- 1A3 2Y4 22 --- --- 1A2 NC 23 --- --- 1A1 2OE 24 --- --- 1OE 2A4 25 --- --- --- 2A3 26 --- --- --- 2A2 27 --- --- --- 2A1 28 --- --- --- VCC NC = No connection FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 14 (Each Buffer) Outputs Inputs mOE H L X Z mAn mYn L L L L H H H X Z = = = = High voltage level Low voltage level Immaterial High impedance FIGURE 3. Truth table. FIGURE 4. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 15 NOTES: 1. 2. 3. 4. 5. 6. 7. VTEST = open for tPLH, tPHL, tPHZ, and tPZH. VTEST = 2 x VCC for tPLZ and tPZL. CL = 50 pF or equivalent (includes test jig and probe capacitance). RL = 500 or equivalent. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR 1 MHz; ZO = 50; tr 3.0 ns; tf 3.0 ns; tr and tf shall be measured from 10% of VCC to 90% of VCC and from 90% of VCC to 10% of VCC, respectively; duty cycle = 50 percent. Timing parameters shall be tested at a minimum input frequency of 1MHz. The outputs are measured one at a time with one transition per measurement. FIGURE 5. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 16 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). TABLE IIA. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Subgroups (in accordance with MIL-PRF-38535, table III) Device class M Device class Q Interim electrical parameters (see 4.2) --- --- 1 Final electrical parameters (see 4.2) 1/ 1, 2, 3, 7, 8, 9 1/ 1, 2, 3, 7, 8, 9 2/, 3/ 1, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (see 4.4) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 3/ 1, 2, 3, 7,8, 9, 10, 11 Group D end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 Device class V 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1, 7, and deltas. 3/ Delta limits, as specified in table IIB, shall be required where specified, and the delta limits shall be completed with reference to the zero hour electrical parameters. TABLE IIB. Burn-in and operating life test, delta parameters (+25C). 1/ Parameter 2/ Supply current Symbol ICCH, ICCL, ICCZ Delta limits Input current low level IIL 20 nA Input current high level Output voltage low level (VCC = 5.5 V, IOL = 24 mA) Output voltage high level (VCC = 5.5 V, IOH = -24 mA) 300 nA IIH 20 nA VOL 0.04 V VOH 0.20 V 1/ This table is representation of what vendor CAGE F8859 has experienced and is guaranteed and not meant to be construed as a quality assurance requirement for any other vendor. 2/ These parameters shall be recorded before and after the required burn-in and life tests to determine the delta limits. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 17 4.4.1 Group A inspection a. Tests shall be as specified in table IIA herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 3 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 3, herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table IA herein. For CIN and CPD, test all applicable pins on five devices with zero failures. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. b. TA = +125C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25C 5C, after exposure, to the subgroups specified in table IIA herein. c. RHA tests for device classes M, Q, and V for levels M, D, P, L, R, and F shall be performed through each level to determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial qualification and after design or process changes which may affect the RHA performance of the device. d. Prior to irradiation, each selected sample shall be assembled in its qualification package. It shall pass the specified group A electrical parameters in table IA for subgroups specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 18 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883, method 1019, condition A, and as specified herein. Prior to and during total dose irradiation characterization and testing, the devices for characterization shall be biased so that 50 percent are at inputs high and 50 percent are at inputs low, and the devices for testing shall be biased to the worst case condition established during characterization. Devices shall be biased as follows: Device type 01: a. Inputs tested high, VCC = 5.5 V dc 5%, VIN = 5.0 V dc +10%, RIN = 1k 20%, and all outputs are open. b. Inputs tested low, VCC = 5.5 V dc 5%, VIN = 0.0 V dc, RIN = 1k 20%, and all outputs are open. 4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on classes M, Q, and V devices requiring a RHA level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at +25C 5C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP testing. The test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive (i.e. 0 angle 60). No shadowing of the ion beam due to fixturing or package related effects is allowed. b. The fluence shall be 100 errors or 107 ions/cm2. c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e. The upset test temperature shall be +25C and the latchup test temperature is maximum rated operating temperature 10C. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. For SEP test limits, see table IB herein. 4.5 Methods of inspection. Methods of inspection shall be specified as follows: 4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 19 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990 or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be supplied. a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Number of transients (SEP). e. Occurrence of latchup (SEP). . STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 20 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87552 A.1 SCOPE A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number (PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN. A.1.2 PIN. The PIN is as shown in the following example: 5962 F Federal stock class designator RHA designator (see A.1.2.1) \ 87552 01 V 9 A Device type (see A.1.2.2) Device class designator Die code Die details (see A.1.2.4) / (see A.1.2.3) \/ Drawing number A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash (-) indicates a non-RHA die. A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 Generic number Circuit function 54AC244 Octal buffer/line driver with three-state outputs A.1.2.3 Device class designator. Device class Q designator will not be included in the PIN and will not be marked on the device since the device class designator has been added after the original issuance of this drawing. Device class Q or V Device requirements documentation Certification and qualification to the die requirements of MIL-PRF-38535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 21 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87552 A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and variant supplied to this appendix. A.1.2.4.1 Die physical dimensions. Die type Figure number 01 A-1 A.1.2.4.2 Die bonding pad locations and electrical functions. Die type Figure number 01 A-1 A.1.2.4.3 Interface materials. Die type Figure number 01 A-1 A.1.2.4.4 Assembly related information. Die type Figure number 01 A-1 A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details. A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 22 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87552 A.2. APPLICABLE DOCUMENTS A.2.1 Government specification, standards, and handbooks. The following specification, standard, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARD MIL-STD-883 - Test Method Standard Microcircuits. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. A.3 REQUIREMENTS A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein and the manufacturer's QM plan for device classes Q and V. A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1. A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as specified in A.1.2.4.2 and on figure A-1. A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1. A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1. A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein. A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.6 herein. A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this document. A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table I. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 23 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87552 A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the certification mark, the manufacturer's identification and the PIN listed in A.1.2 herein. The certification mark shall be a "QML" or "Q" as required by MIL-PRF-38535. A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein. A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuit die delivered to this drawing. A.4 VERIFICATION A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modifications in the QM plan shall not affect the form, fit, or function as described herein. A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturer's QM plan. As a minimum, it shall consist of: a. Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007. b. 100% wafer probe (see paragraph A.3.4 herein). c. 100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the alternate procedures allowed in MIL-STD-883, method 5004. A.4.3 Conformance inspection. A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of packaged die shall be as specified in table II herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein. A.5 DIE CARRIER A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer's QM plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and electrostatic protection. A.6 NOTES A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and logistics purposes. A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio 43218-3990 or telephone (614) 692-0547. A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 24 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87552 Die physical dimensions. 2408 x 2250 m 285 25 m Die size: Die thickness: Die bonding pad locations and electrical functions. 18 17 16 15 14 13 12 11 19 10 20 10 20 1 9 2 Pad size: 3 4 5 6 7 8 Optional Manufacturer's Logo Pad numbers 1 to 9 and 11 to 19: 100 x 100 m Pad numbers 10 (GND) and 20 (VCC): 100 x 280 m NOTE: Pad numbers reflect terminal numbers when placed in case outline X (see figure 1). FIGURE A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 25 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87552 Interface materials. Top metallization: Al Si Cu Backside metallization: None 0.85 m Glassivation. Type: Thickness: Substrate: P. Vapox + Nitride 0.5 m - 0.7 m Silicon Assembly related information. Substrate potential: Floating or tied to GND Special assembly instructions: Bond pad #20 (VCC) first FIGURE A-1 - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87552 A REVISION LEVEL J SHEET 26 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 07-06-21 Approved sources of supply for SMD 5962-87552 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ 5962-8755201RA Vendor CAGE number Vendor similar PIN 2/ 01295 0C7V7 01295 0C7V7 01295 0C7V7 SNJ54AC244J 54AC244DMQB SNJ54AC244W 54AC244FMQB SNJ54AC244FK 54AC244LMQB 5962-8755201ZA 0C7V7 54AC244WG-QML 5962-8755201VRA 01295 SNV54AC244J 5962-8755201VSA 01295 SNV54AC244W 5962-8755201XA 3/ 54AC244K02Q 5962-8755201XC 3/ 54AC244K01Q 5962-8755201VXA 3/ 54AC244K02V 5962-8755201VXC 3/ 54AC244K01V 5962F8755201XA F8859 5962-8755201SA 5962-87552012A RHFAC244K02Q 5962F8755201XC F8859 RHFAC244K01Q 5962F8755201VXC F8859 RHFAC244K01V 5962F8755201VXA F8859 RHFAC244K02V 5962F8755201RA F8859 RHFAC244D04Q 5962F8755201RC F8859 RHFAC244D03Q 5962F8755201VRA F8859 RHFAC244D04V 5962F8755201VRC F8859 RHFAC244D03V 5962F8755201V9A F8859 5962-8755202JA AC244DIE2V 3/ 54AC11244 5962-8755202KA 3/ 54AC11244 5962-8755202LA 3/ 54AC11244 5962-87552023A 3/ 54AC11244 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ No longer available from an approved source of supply. Sheet 1 of 2 STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued. Vendor CAGE number Vendor name and address F8859 ST Microelectronics 3 rue de Suisse CS 60816 35208 RENNES cedex2 - FRANCE 01295 Texas Instruments Incorporated Semiconductor Group 8505 Forest Ln. P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 0C7V7 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Sheet 2 of 2