19-0174, Bev 1: 7/95 SAA AL/VI CMOS uP-Compatible 12-Bit DAC ____s Gernerrail Description The MX7542 is a CMOS 12-Bit digital-to-analog con- verter (DAC) which directly interfaces to both 8-bit and 4-bit microprocessors. Input data is loaded as three 4-bit bytes, and is then transferred to an internal 12-bit DAC register. Data load and transfer interface timing is similar to that of a static RAM write cycle. A clear input is also provided which resets the DAC register to all zeros. This can be used to initialize the device on power up or during software calibration routines. Low power consumption, +5V operation, and multi- plying capability make the MX7542 suitable for numerous high precision processor controlled DAC applications. The MX7542 is supplied in 16-lead DIP and Small Outline packages. Applications Programmable Power Sources Portable Test Equipment Digitally Controiled Filters Auto-Calibration Circuitry Motion Control Systems a ____ Functional Diagram MAXIM nur MX7542 12-BIT MULTIPLYING DAC 2 12-BYT DAC REGISTER Voo OGND H-BYTE M-BYTE L-BYTE JATA ADDRESS DATA OECODE LOGIC DATA REGISTER REGISTER REGISTER (LS8) (MSB) Features @ 12-Bit Resolution @ +1/2 LSB Linearity Over Temperature @ +1 LSB Gain Accuracy (MX7542G) @ 5Sppm/C Max. Gain Drift @ Microprocessor Compatible @ 40mW Max. Power Dissipation @ +5V Operation Ordering Information PART TEMP. RANGE PACKAGE* ERROR MX7542JN OC to +70C ~Plastic.: DIP +1 LSB MX7542KN OC to +70C ~~ Plastic DIP + LSB MX7542GKN O to +70C ~ Plastic DIP +2 LSB MX7542JCWE OC to +70C ~- Small Outline +1 LSB MX7542KCWE 0C to +70C = Small Outline + LSB MX7542GKCWE 0Cto+70C Small Outline LSB | MX7542J/D 0C to +70C Dice " 41L8B MX7542AD -25C to +85C Ceramic +1 LSB MxX7542BD -25C to +85C Ceramic + LSB MX7542GBD -26C to +85C Ceramic +'% LSB MX7542AQ -25C to +85C ~ CERDIP** +1 LSB MX7542BQ -25C to +85C = GERDIP*" 1% LSB MX7542GBQ _-25C to +85C ~- CERDIP** ts LSB MX7542SD -55C to +125C =9Ceramic +1 LSB MX7542TD ~55C to +125C Ceramic ts LSB MX7542GTD -55C to +125C =9Ceramic tie LSB MX7542SQ -55C to +125C CERDIP** +1 LSB MX7542TQ -55C to +125C + CERDIP"* + LSB MX7542GTQ = -55C to #125C ~=CERDIP* +. LSB All devices 16 lead packages ** Maxim reserves the right to ship Ceramic packages tn feu of CEROIP packages Pin Configuration MAXIM MX7542 MAXIMA Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. coUSZXINMX7542 CMOS uP-Compatible 12-Bit DAC ABSOLUTE MAXIMUM RATINGS Vop tO AGNO 00.000. e cece cette teen ees -0.3V, +7V Von 10 DGND ...... 0. cece cece eee eres -0.3V, +7V AGND to DGND 2.0.0.2... eee e cect een e tenn ees Voo DGND to AGND 20... 0.00.50 cece cette eee e eee Digital Input Voltage to DGND (Pins 4-11, 13) Vow: Vping tO AGND .... ee eee eee -0.3V, Vop + 0.3V Vaee tO AGND 2262s +25V Varg tO AGND 21... ccc cee eee +25V Power Dissipation ................. 0.0 ..02.-00005 (derate 6mMW/C above +70C) Operating Temperature Range Commercial MX7542J, K, GK ..... 0... Industrial MX7542A, B, GB.........,... Military MX7542S, T, GT.............. Storage Temperature Lead Temperature (Soldering 10 sec) 0Cc to +70C -25C to +85C -55C to +125C -65C to +150C *300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (T, = Tin tO Tuax Von = +8. Veer = +10, Vout: = Yout2 = GND, unless otherwise specified) PARAMETER [SYMBOL | CONDITIONS MIN TYP MAX | UNITS DC ACCURACY Resolution 12 Bits MX7542J/A/S +4 Non-Linearity MX7542K/B/T +0.5 LSB MX7542GK/GB/GT +0.5 MX7542J/A/S (Note 1) +2 Differential Non-Linearity MX7542K/B/T (Note 2) 41 LSB MX7542GK/GB/GT (Note 2) +1 MX7542J/K/A/B/S/T Ty, = 25C 412.3 MX7542J/K/A/B Tyan to Trax 413.5 MX7542S/T T to T +145 Gain Error MIN MAX LSB MX7542GK/GB/GT Ty, = 25C +H MX7542GK/GB Turin tO Trax +1 MX7542GT Tun tO Trax +2 Gain Temperature Coefficient o AGain/ATemperature (Note 4) @ ppm/C oo. _ T, = 25C 0.005 Power Supply Rejection PSRR Vop = +4.75V to +5.25V Toni tO Tax 0.01 %/%V oo Ta = 25C 1 Output Leakage Current MX7542J/K/GK Twin tO Tyax 10 nA lout loure (Note 3) MX7542A/B/GB Tain tO Tuax 10 MX7542S/T/GT Tuan to Trax 200 DYNAMIC PERFORMANCE (Note 4) Output Current Settling Time To 1/2 LSB, Out1 Load = 1009 2 US Feedthrough Error Var = 10V 10kHz sine wave 2.5 mVpp REFERENCE INPUT Input Resistance (pin 15) | Rrer | 8 15 25 kQ ANALOG OUTPUT (Note 4) Court DAC Register 0000 0000 0000 75 Cour | DAC Register 1111 4111 1111 260 Output Capacitance ours | DAC Register 11111111 1111 75 pF out2 | DAC Register 0000 0000 0000 260 MAAILSVICMOS .P-Compatible 12-Bit DAC ELECTRICAL CHARACTERISTICS (Continued) (Ta = Twin tO Twax: Yoo = +5. Vaer = *10V. Vout = Vouta GND, unless otherwise specified) PARAMETER [syMBOL | CONDITIONS MIN MAX | UNITS LOGIC INPUTS Logic HIGH Voltage Vinny +3.0 V Logic LOW Voltage Vint +0.8 Logic Input Current lin OV oF Vop 1 HA Input Capacitance (Note 4) Cw 8 pF | SWITCHING CHARACTERISTICS (see Figure 6) (Note 5 : . T, = 28C 120 Write Pulse Width t A wR Tin tO Tax 220 -to-| i i Ta = 25C 50 Address-to-Write Hold Time tawH Tran 10 Trax 65 nc . . Ty = 25C 50 Chip Select-to-Write Hold t A P OWH | Tory tO Traax 100 . - Ty = 25C 200 Minimum CLEAR Pulse Width | t A a Tain tO Tmax 300 BYTE LOADING . Ty = 26C 60 Chip Select-to-WRITE Set t A Ip velec up CWS) Than to Trax 130 , . Ta = 25C 80 Address Valid-to-Write Setup taws Torin tO Traax 180 ns . Ta = 25C 50 Data Setup Time t A p ps Tin tO Tmax 85 . Ty = 25C 50 Data Hold Time t A DA Twin tO Tomax 85 DAC LOADING . T, = 25C 60 Chip Select-to-WRITE Setup t A CWS Tain tO Tyax 150 ns . . Ty = 25C 120 Add alid-to-Write Set t A ress valid-to-Wri up AWS Teun 10 Trax 240 POWER SUPPLY Supply Voltage Voo 5V + 5% 4.75 5.25 Vv } | Supply Current lbp 2.5 mA Note 1: Monotonic to 11 bits from Tyyy to Tyax Note 2: Monotonic to 12 bits from Tyyy tO Trax Note 3: Iy7, tested with DAC register loaded to ail 0's. loutz tested with DAC register loaded to all 1's. Note 4: Guaranteed by design but not tested. Note 5: Sample tested at +25C to ensure compliance. MAAISVI 3 coSZXWMX7542 CMOS P-Compatible 12-Bit DAC .._. Detailed Description The basic MX7542 DAC circuit consists of a laser- trimmed, thin-film R-2R resistor array with NMOS current switches as shown in Figure 1. Binarily weighted currents are switched to either OUT1 or OUT2 depending on the status of each input bit. Although the current at OUT1 or OUT2 will depend on the digital input code, the sum of the two output currents is always equal to the input current at Vag minus the termination resistor current (Ry). Either current output can be converted into a voltage externally by adding an output amplifier (Figure 4). The Veer input accepts a wide range of signals in- cluding fixed and time varying voltage or current inputs. If a current source is used for the reference input, then a low temperature coefficient external resistor should be used for Reg to minimize gain variation with temperature. Equivalent Circuit Analysis Figures 2 and 3 show the equivalent circuits for the R-2R_ ladder when all digital inputs are LOW and HIGH respectively. The input resistance at Vper is nominally 15kQ and does not change with digital input code. The Ipe-/4096 current source, which is actually the ladder termination resistor (Ry, Figure 1), results in an intentional 1-bit current loss to GND. The lreakaGe Current sources represent junction and surface leakage currents. Capacitors Coyty and Coy represent the switches ON and OFF capacitances respectively. When all inputs are switched from LOW to HIGH, the capaci- tance at OUT1 changes from approximately 75pF to 260pF. This capacitance is code-dependent and is a function of the number of ON switches that are con- nected to a specific output. 15K 15K 15K VREF Rr 30K 30K 30K 2 30K st $3 SN | ( \ 1 Pup py ay | H+ te + OUT2 + ~ OUTI Lk pty we BIT1(MSB) BIT2 BIT3 BIT N (LSB) Switches Shown For Inputs High Figure 1. MX7542 Functional Diagram _______ Circuit Configurations Unipolar Operation The most common configuration for the MX7542 is shown in Figure 4. The circuit is used for unipolar binary operation and/or 2-quadrant multiplication. The code table is given in Table 1. Note that the polarity of the output is the inverse of the reference input. In many applications, gain adjustment of the MxX7542 will not be necessary. In those cases, and also when gain is trimmed but only at the reference source, resistors R1 and R2 in Figure 4 can be omitted. However, if the trims are desired and the DAC is to operate over a wide temperature range, then low tempco (<300ppm/C) resistors should be used at R1 and R2. ~ OUT2 R = 15K VREF BWW _> IREF Rep R OUT1 JREF 4 609 4096 LEAKAGE L ouT2 8 ILEAKAGE + 75pF OD: Figure 2. MX7542 DAC Equivalent Circuit, All Digital Inputs LOW Figure 3. MX7542 DAC Equivalent Circurt, All Digital Inputs HIGH _. MAXICMOS P-Compatible 12-Bit DAC +5V R2* 15 VIN > LY Veer MAXIM RI" | MX7542 OuT2/2 DGND AGND 3 >t Vout MAXIM MAX400 TRIM resistor | YA/S | K/B/T R41 1000 1000 R2 479 330 Figure 4. Unipolar Binary Operation R4 AGND Vout [DGND = J 5kQ 10% TRIM resistor | A/S | K/B/T Ri toon | 1009 Re 470 330 Figure 5. Bipolar Operation (4-Quadrant Multiplication) Bipolar Operation With the circuit configuration in Figure 5, the MX7542 operates in the bipolar, or 4-quadrant multiplying mode. A second amplifier and three matched resistors are required. Matching to 0.01% is recommended for 12 bit performance. The code table for the output, which is offset binary, is listed in Table 2. In multi- plying applications, the MSB determines output po- larity while the other 11 bits control amplitude. MAAILWI Table 1. Code TableUnipolar Binary DIGITAL INPUT MSB LSB ANALOG OUTPUT 4144411914171 Vaer | 2098 REF \ 4096 1000 0000 0000 2048 | _ _ Vcr REF | 4096 2 1 1 _ -_ 0000 0000 000 Veer ass | 0000 0000 COo0D ov Table 2. Code Table Bipolar (Offset Binary) Operation DIGITAL INPUT MSB LSB ANALOG OUTPUT 2047 1147411111171 REE soa | 1000 0000 0001 Veer | saua | 1000 0000 0000 ov Oo111 14111141141 1 -V, AEF | 204 | co 0000 0000 0000 Veer | 24 2048 | To adjust the circuit, load the DAC with a code of 1000 0000 0000 and trim R1 for a OV output. With R1 and R2 omitted, an alternative zero trim is to adjust the ratio of R3 and R4 for OV out. Full scale can be trimmed by loading the DAC with all zeros or all ones and adjusting the amplitude of Veer or varying R5 until the desired positive or negative output is obtained. If gain and offset trims are not required, R1 and R2 in Figure 5 can be omitted. cpSlXiMX7542 CMOS P-Compatible 12-Bit DAC Interface Logic Interface Logic Information The MX7542 Truth Table is shown in Table 3. The high, middle and low byte, 4 bit data registers are loaded separately. The 12-bit DAC register is then loaded with the contents of the 3 data registers. The interface timing (Figure 6) is the same as writing to static RAM. The CLR input asynchronously resets the 12-Bit DAC Register to Code 0000 0000 0000. In a unipolar mode the DAC output will be set to 0 volts. In the bipolar mode a CLR input resets the DAC output to -Vper. Notes: 1. 1 indicates logic HIGH 2. 0 indicates logic LOW 3. X indicates don't care 4.F indicates LOW to HIGH transition 5. MSB = XXXX XXXX XXXX - LSB high middie low byte byte byte 6. These control signals are level triggered. Table 3. MX7542 Truth Table MX7542 Control Inputs MX7542 Operation A, | A, | CS | WR (CLR X |X) xX xX O |Resets DAC 12-Bit Register to Code 0000 0000 0000 xX | X 1 X 1 | No Operation Device Not Selected o}o}o f- 1 | Load LOW Byte Data Register On Edge As Shown Load 0/1] 0 | F | 1 [Load MIDDLE Byte) Applicable : Data Data Register On Edge As Shown _| Register With Data 1} 0] 0 | F/ 1 |Load HIGH Byte | At D,-D, Data Register On Edge As Shown 1 1 0 1 |Load 12-Bit DAC Register With Data In LOW Byte, M IDDLE Byte & HIGH Byte Data Registers ADDRESS BUS VALID-__ A0-A1 Vix (PINS 10. 11) Vib | | tawH | cs | (PIN 8) | | Le tcws | }~ town WR \ / (PIN 9} if __ taws twr - | | tos {<m| tou 03-D0 ViH (PINS 4-7) Vin NOTE ~_ DATA BUS VALID TIMING MEASUREMENT REFERENCE LEVEL IS Viy > Vic : | Figure 6 MX7542 Timing Diagram MAALWVICMOS uP-Compatible 12-Bit DAC _______..... Application Information Output Amplifier Offset For best linearity, OUT1 and OUT2 should be termi- nated exactly OV. In most applications OUT1 is con- nected to the summing junction of an inverting op- amp. The amplifiers input offset voltage can degrade the linearity of the DAC by causing OUT1 to be terminated to a non-zero voltage. The resulting error is: Error Voltage = Vog(1 + Reg/Ro), where Vog is the op-amps offset voltage and Ro is the output resistance of the DAC. Ro is a function of the digital input code, and varies from approximately 15kQ to 45kQ. The error voltage range is then typically 4/3V gg tO 2Vgg, a change of 2/3Vgg. An amplifier with 3mV of offset will therefore degrade the linearity by 2mvV, almost a full LSB with a 10V reference voltage. For best linearity, a low-offset amplifier such as the MAX400 should be used, or the amplifier offset must be trimmed to zero. A good rule of thumb is that Vos, should be no more than 1/10 of an LSBs value. The output amplifier input bias current (Ip) can also limit performance since Ig x Reg generates an offset error, lg should therefore be much less than the DAC output current for 1 LSB, typically 250nA with Vac = 10V. One tenth of this value, 25nA, is recommended. Offset and linearity can also be impaired if the output amplifiers noninverting input is grounded through a biaS current compensation resistor. This resistor adds to offset at this pin and should not be used. Best performance is obtained when the noninverting input is directly connected to ground. Dynamic Considerations In static or DC applications, the AC characteristics of the output amplifier are not critical. In higher speed applications, where either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the AC parameters of the output op-amp must be considered. Another error source in dynamic applications is para- sitic coupling of signal from the Veer terminal to OUT1 or OUT2. This is normally a function of board layout and package lead-to-lead capacitance. Signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually dependent on circuit board layout and on- chip capacitive coupling. Layout induced feedthrough can he mimimized with guard traces between digital inputs, Vee, and the DAC outputs. MAXIM Compensations A compensation capacitor, C1, may be needed when the DAC is used with a high speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DACs output capacitance and internal feedback resistance. Its value depends on the type of op-amp used but typical values range from 10 to 33pF. Too small a value causes output ringing while excess capacitance overdamps the output. The size of C1 can be minimized, and output settling perform- ance improved, by keeping the PC board trace and stray capacitance at OUT1 as small as possible. Grounding and Bypassing Since OUT1, OUT2 and the output amps noninverting inputs are sensitive to offset voltages, nodes that are to be grounded should be connected directly to single point" ground through a separate, very low resistance (less than 0.20) path. The current at OUT1 and OUT2 varies with input code, creating a code dependent error if these terminals are connected to ground (or a virtual ground) through a resistive path. A 1uF bypass capacitor, in parallel with a O.01yF ceramic cap, should be connected as close to the DACs Vpp and GND pins as possible. The MX7542 has high-impedance digital inputs. To minimize noise pick-up, they should be tied to either Vpp or GND when not used. It is also good practice to connect active inputs to Vpp or GND through high valued resistors (1MQ) to prevent static charge accumulation if these pins are left floating, such as when a circuit card is left unconnected. Chip Topography 14 13 12 n Voo CLR DGND Al V a Sd ee eve Ee 10 REF = 15 . SSS AD Ree eee Ep ee 16 _.t00 |g 2.54mm WR OUT? | ppm 1 8 OUuT2 L-scs 2 7 AGND 3 DO 4 5 6 D3 D201 109" <__- _____ 2.77mm 7 cvpSZlXW