22.27.02
FS6128-04 / FS6128-05 / FS6128- 06
FS6128-04 / FS6128-05 / FS6128- 06FS6128-04 / FS6128-05 / FS6128- 06
FS6128-04 / FS6128-05 / FS6128- 06
PLL Clock Gener ator IC with VCXO
PLL Clock Gener ator IC with VCXOPLL Clock Gener ator IC with VCXO
PLL Clock Gener ator IC with VCXO
ISO9001
ISO9001ISO9001
ISO9001
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN TYPE NAME DESCRIPTION
1 AI XIN VCXO Feedback
2 P VDD Power Supply (+3.3V)
3 AI XTUNE VCXO Tune
4 P VSS Ground
5 DO CLK Clock Output
6 - n/c No Connection
7 DO VSS Ground
8 A O XOUT VCXO Drive
3.0 Functional Bl ock Descripti on
3.1 Voltage-Controlled Crystal
Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6128 system components.
Loading capacitance for the crystal is internal to the
FS6128. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequenc y is accom-
plished by varying the voltage on the XTUNE pin. The
value of this voltage controls the effective capacitance
presente d to the cryst al. The actua l amount that this loa d
capacitance change will alter the oscillator frequency de-
pends on the characteristics of the crystal as well as the
oscillator circuit itself.
It is important that the crystal load capacitance is speci-
fied correctly to “center” the tuning range. See Table 5.
A simple formula to obtain the “pulling” capability of a
crystal oscillator is:
()
()()
CCCC CCC
ppmf LL
LL
1020
6
121
210
)( +×+× ×−×
=∆
where:
C0 = the shunt (or holder) capacitance of the crystal
C1 = the motional capacitance of the crystal
CL1 and CL2 = t he t wo ex tr emes (minimum and max im um )
of the applied load capacitance presented by the
FS6128.
EXAMPLE: A crystal with the following parameters is
used: C1 = 0.025pF and C0 = 6pF. Using the minimum
and maximum CL1 = 10pF, and CL2 = 20pF, the tuning
range (peak-to-peak) is:
()
()()
ppm
.
f300
1062062 106
10200250 =
+×+× ×−×
=∆ .
3.2 Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase-
lock ed loop archi tec tur e. The PLL multip lies t he r ef er ence
oscillator frequency to the desired output frequency by a
ratio of integers. The frequency multiplication is exact
with a zero synthesis error (unless otherwise specified).