19-4773; Rev 0; 7/98 KIT ATION EVALU E L B AVAILA Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface Features 12-Bit Resolution, 1/2 LSB Linearity +5V Single-Supply Operation I2C-Compatible, 2-Wire Serial Interface Four Software-Selectable Input Ranges MAX127: 0 to +10V, 0 to +5V, 10V, 5V MAX128: 0 to +VREF, 0 to +VREF/2, VREF, VREF/2 8 Analog Input Channels 8ksps Sampling Rate 16.5V Overvoltage-Tolerant Input Multiplexer Internal 4.096V or External Reference Two Power-Down Modes 24-Pin Narrow DIP or 28-Pin SSOP Packages Typical Operating Circuit +5V The MAX127/MAX128 are available in 24-pin DIP or space-saving 28-pin SSOP packages. 0.1F C VDD SHDN Applications CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Industrial Control Systems ANALOG INPUTS Data-Acquisition Systems Robotics Automatic Testing 1k SCL SDA A0 A1 A2 Medical Instruments REF REFADJ PART TEMP. RANGE PIN-PACKAGE INL (LSB) MAX127ACNG 0C to +70C 24 Narrow Plastic DIP 1/2 MAX127ACNG 0C to +70C 24 Narrow Plastic DIP 1 4.7F 0.01F SDA MAX127 MAX128 Battery-Powered Instruments Ordering Information SCL DGND AGND Ordering Information continued at end of data sheet. Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX127/MAX128 General Description The MAX127/MAX128 are multirange, 12-bit data acquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that may span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: 10V, 5V, 0 to +10V, 0 to +5V for the MAX127; and VREF, VREF/2, 0 to +VREF, 0 to +VREF/2 for the MAX128. This range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface 4-20mA, 12V, and 15V-powered sensors directly to a single +5V system. In addition, these converters are fault protected to 16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, an 8ksps throughput rate, and the option of an internal 4.096V or external reference. The MAX127/MAX128 feature a 2-wire, I2C-compatible serial interface that allows communication among multiple devices using SDA and SCL lines. A hardware shutdown input (SHDN) and two softwareprogrammable power-down modes (standby and full power-down) are provided for low-current shutdown between conversions. In standby mode, the referencebuffer remains active, eliminating start-up delays. MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0-CH7 to AGND ......................................................... 16.5V REF to AGND..............................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) A0, A1, A2 to DGND...................................-0.3V to (VDD + 0.3V) SHDN, SCL, SDA to DGND ......................................-0.3V to +6V Max Current into Any Pin ....................................................50mA Continuous Power Dissipation (TA = +70C) 24-Pin Narrow DIP (derate 13.33mW/C above +70C)..1067mW 28-Pin SSOP (derate 9.52mW/C above +70C) ...............762mW Operating Temperature Ranges MAX127_ C_ _/MAX128_ C_ _.............................0C to +70C MAX127_ E_ _/MAX128_ E_ _ ..........................-40C to +85C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10sec) ............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note 1) Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL 1/2 MAX127B/MAX128B 1 1 Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching MAX127A/MAX128A 3 MAX127B/MAX128B 5 MAX127A/MAX128A 5 MAX127B/MAX128B 0.1 Bipolar 0.3 Gain Error (Note 2) Bipolar LSB LSB LSB 10 Unipolar Unipolar Gain Tempco (Note 2) Bits MAX127A/MAX128A LSB MAX127A/MAX128A 7 MAX127B/MAX128B 10 MAX127A/MAX128A 7 MAX127B/MAX128B LSB 10 Unipolar 3 Bipolar 5 ppm/C DYNAMIC SPECIFICATIONS (800Hz sine-wave input, 10Vp-p (MAX127) or 4.096Vp-p (MAX128), fSAMPLE = 8ksps) Signal-to-Noise plus Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Channel-to-Channel Crosstalk 70 Up to the 5th harmonic dB -87 81 -80 dB dB 4kHz, VIN = 5V (Note 3) -86 DC, VIN = 16.5V -96 dB Aperture Delay 200 ns Aperture Jitter 10 ns 2 _______________________________________________________________________________________ Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface (VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 s ANALOG INPUT Track/Hold Acquisition Time -3dB rolloff Small-Signal Bandwidth 10V or VREF range 5 5V or VREF/2 range 2.5 0 to 10V or 0 to VREF range 2.5 0 to 5V or 0 to VREF/2 range Unipolar, Table 3 MAX128 Input Voltage Range VIN MAX127 Bipolar, Table 3 MAX127 IIN MAX127 Bipolar MAX128 VIN IIN Input Resistance Input Capacitance 0 5 0 VREF 0 VREF/2 -10 10 -5 5 -VREF VREF VREF/2 0 to 10V range -10 720 0 to 5V range -10 360 MAX128 Input Current 10 -VREF/2 MAX128 Unipolar 1.25 0 MAX127 MHz -10 0.1 10 10V range -1200 720 5V range -600 360 VREF range -1200 10 VREF/2 range -600 10 Unipolar 21 Bipolar 16 (Note 4) V A k 40 pF 4.116 V INTERNAL REFERENCE REFOUT Voltage VREF REFOUT Tempco TC VREF TA = +25C 4.076 4.096 MAX127_C/MAX128_C 15 MAX127_E/MAX128_E 30 Output Short-Circuit Current Load Regulation (Note 5) 0 to 0.5mA output current Capacitive Bypass at REF Buffer Voltage Gain 30 mA 10 mV 4.7 REFADJ Output Voltage REFADJ Adjustment Range ppm/C 2.465 Figure 12 F 2.500 2.535 V 1.5 % 1.638 V/V _______________________________________________________________________________________ 3 MAX127/MAX128 ELECTRICAL CHARACTERISTICS (continued) MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.18 V REFERENCE INPUT (buffer disabled, reference input applied to REF) Input Voltage Range 2.4 VREF = 4.18V Input Current Input Resistance Normal, or STANDBY power-down mode FULL power-down mode 10 k FULL power-down mode 5 M VDD - 0.5 V VDD 4.75 5.25 Normal mode, bipolar ranges Supply Current Power-Supply Rejection Ratio (Note 7) IDD PSRR A 1 Normal or STANDBY power-down mode REFADJ Threshold for Buffer Disable POWER REQUIREMENTS Supply Voltage 400 18 Normal mode, unipolar ranges 6 10 STANDBY power-down mode (Note 6) 700 850 FULL power-down mode 120 220 External reference = 4.096V 0.1 0.5 Internal reference 0.5 V mA A LSB TIMING External Clock Frequency Range Conversion Time fCLK 0.4 tCONV 6.0 7.7 Throughput Rate Bandgap Reference Start-Up Time Power-up (Note 8) Reference Buffer Settling Time To 0.1mV, REF bypass capacitor fully discharged s 8 ksps 200 CREF = 4.7F 8 CREF = 33F 60 MHz 10.0 s ms DIGITAL INPUTS (SHDN, A2, A1, A0) Input High Threshold Voltage VIH Input Low Threshold Voltage VIL Input Leakage Current IIN VIN = 0 or VDD CIN (Note 4) Input Capacitance Input Hysteresis 4 VHYS 2.4 V 10 A 15 pF 0.8 V 0.1 0.2 _______________________________________________________________________________________ V Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface (VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SDA, SCL) Input High Threshold Voltage VIH Input Low Threshold Voltage VIL Input Hysteresis 0.7 x VDD 0.3 x VDD VHYS V 0.05 x VDD Input Leakage Current IIN VIN = 0 or VDD Input Capacitance CIN V V 0.1 10 A (Note 4) 15 pF ISINK = 3mA 0.4 ISINK = 6mA 0.6 (Note 4) 15 DIGITAL OUTPUTS (SDA) Output Low Voltage Three-State Output Capacitance VOL COUT V pF TIMING CHARACTERISTICS (VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz 2-WIRE 2-WIREFAST FASTMODE MODE SCL Clock Frequency fSCL Bus Free Time Between a STOP and START Condition tBUF 1.3 s tHD,STA 0.6 s Low Period of the SCL Clock tLOW 1.3 s High Period of the SCL Clock tHIGH 0.6 s Set-Up Time for a Repeated START Condition tSU,STA 0.6 s Data Hold Time tHD,DAT 0 Data Setup Time Hold Time (Repeated) START Condition 0.9 tSU,DAT 100 Rise Time for Both SDA and SCL Signals (Receiving) tR Cb = Total capacitance of one bus line in pF 20 + 0.1 x Cb 300 Fall Time for Both SDA and SCL Signals (Receiving) tF Cb = Total capacitance of one bus line in pF 20 + 0.1 x Cb 300 Fall Time for Both SDA and SCL Signals (Transmitting) tF Cb = Total capacitance of one bus line in pF 20 + 0.1 x Cb 250 Set-Up Time for STOP Condition tSU,STO Capacitive Load for Each Bus Line Cb Pulse Width of Spike Suppressed tSP ns 0.6 0 s ns ns ns s 400 pF 50 ns _______________________________________________________________________________________ 5 MAX127/MAX128 ELECTRICAL CHARACTERISTICS (continued) MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface TIMING CHARACTERISTICS (continued) (VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS 2-WIRE STANDARD MODE SCL Clock Frequency fSCL Bus Free Time Between a STOP and START Condition tBUF 4.7 s tHD,STA 4.0 s Low Period of the SCL Clock tLOW 4.7 s High Period of the SCL Clock tHIGH 4.0 s Setup Time for a Repeated START Condition tSU, STA 4.7 s Data Hold Time tHD, DAT 0 Data Setup Time tSU, DAT 250 Hold Time (Repeated) START Condition 100 kHz 0.9 s ns Rise Time for Both SDA and SCL Signals (Receiving) tR 1000 ns Fall Time for Both SDA and SCL Signals (Receiving) tF 300 ns Fall Time for Both SDA and SCL Signals (Transmitting) tF Setup Time for STOP Condition tSU, STO Capacitive Load for Each Bus Line Cb Pulse Width of Spike Suppressed tSP Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: 6 Cb = total capacitance of one bus line in pF, up to 6mA sink 20 + 0.1 x Cb 250 4.0 0 s 400 pF 50 ns Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits is guaranteed by PowerSupply Rejection test. External reference: VREF = 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB. Ground "on" channel, sine wave applied to all "off" channels. Guaranteed by design. Not tested. Use static external load during conversion for specified accuracy. Tested using internal reference. PSRR measured at full scale. Tested for the 10V (MAX127) and 4.096V (MAX128) input ranges. Not subject to production testing. Provided for design guidance only. _______________________________________________________________________________________ ns Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface 10 6.1 5.9 5.7 5 MAX127/8-03 650 INTERNAL REFERENCE 550 450 350 250 EXTERNAL REFERENCE 150 5.5 0 1 2 3 4 5 6 7 -15 10 35 60 85 -40 -15 10 35 60 85 FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE EXTERNAL REFERENCE 110 90 INTERNAL REFERENCE 70 MAX127/8-05 130 1.001 NORMALIZED REFERENCE VOLTAGE 150 1.000 0.999 0.998 0.997 0.996 -15 10 35 60 -40 85 -15 10 35 60 TEMPERATURE (C) CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE INTEGRAL NONLINEARITY vs. DIGITAL CODE 0.6 UNIPOLAR MODE 0.5 0.4 0.3 BIPOLAR MODE 0.1 0.10 0.05 0 -0.05 -15 10 35 TEMPERATURE (C) 60 85 0.15 0.10 UNIPOLAR MODE 0.05 0 -40 -15 10 35 60 85 VDD = 5V fIN = 800Hz fSAMPLE = 8kHz -20 -40 -60 -80 -100 -0.15 -40 0.20 FFT PLOT -0.10 0.2 0.25 0 AMPLITUDE (dB) 0.7 0.15 MAX127/8-08 MAX127/8-07 0.8 85 BIPOLAR MODE 0.30 TEMPERATURE (C) TEMPERATURE (C) INTEGRAL NONLINEARITY (LSB) -40 0.35 MAX127/8-06 TEMPERATURE (C) CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB) TEMPERATURE (C) 50 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) 50 -40 SUPPLY VOLTAGE (V) MAX127/8-04 FULL POWER-DOWN SUPPLY CURRENT (A) 0 MAX127/8-09 15 750 STANDBY SUPPLY CURRENT (A) 6.3 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 20 MAX127/8-02 6.5 max127/8-01 25 STANDBY SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE -110 0 819 1638 2457 DIGITAL CODE 3276 4095 0 800 1600 2400 3200 4000 FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX127/MAX128 Typical Operating Characteristics (VDD = +5V, external reference mode, VREF = 4.096V; 4.7F at REF; external clock, fCLK = 400kHz; TA = +25C; unless otherwise noted.) Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128 Pin Description PIN FUNCTION SSOP 1, 2 1, 2 VDD +5V Supply. Bypass with a 0.1F capacitor to AGND. 3, 9, 22, 24 4, 7, 8, 11, 22, 24, 25, 28 N.C. No Connect. No internal connection. 4 3 DGND 5 5 SCL 6, 8, 10 6, 10, 12 A0, A2, A1 7 9 SDA 11 13 SHDN Shutdown Input. When low, device is in full power-down (FULLPD) mode. Connect high for normal operation. Analog Ground Digital Ground Serial Clock Input Address Select Inputs Open-Drain Serial Data I/O. Input data is clocked in on the rising edge of SCL, and output data is clocked out on the falling edge of SCL. External pull-up resistor required. 12 14 AGND 13-20 15-21, 23 CH0-CH7 21 26 REFADJ Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect to VDD when using an external reference at REF. REF Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF. 23 8 NAME DIP 27 Analog Input Channels _______________________________________________________________________________________ Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface A2 A1 A0 SCL SERIAL INTERFACE LOGIC SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 REF ANALOG INPUT MUX AND SIGNAL CONDITIONING MAX127/MAX128 SDA INT CLOCK OUT VDD AGND DGND CLOCK IN T/H 12-BIT SAR ADC REF 2.5V REFERENCE 10k AV = 1.638 MAX127 MAX128 REFADJ Figure 1. Block Diagram Detailed Description BIPOLAR Converter Operation The MAX127/MAX128 multirange, fault-tolerant ADCs use successive approximation and internal track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. Figure 1 shows the block diagram for these devices. UNIPOLAR 5.12k OFF R1 CH_ CHOLD S2 Input Range and Protection The MAX127/MAX128 have software-selectable input ranges. Each analog input channel can be independently programmed to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table 1). The MAX127 has selectable input ranges extending to 10V (VREF x 2.441), while the MAX128 has selectable input ranges extending to VREF. Note that when an external reference is applied at REFADJ, the voltage at REF is given by VREF = 1.638 x VREFADJ (2.4 < V REF < 4.18). Figure 2 shows the equivalent input circuit. A resistor network on each analog input provides a 16.5V fault protection for all channels. This circuit limits the current going into or out of the pin to less than 1.2mA, whether or not the channel is on. This provides an added layer of protection when momentary overvoltages occur at the selected input channel, and when a negative signal is applied at the input even though T/H OUT ON Analog-Input Track/Hold The T/H circuitry enters its tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word and enters its hold/conversion mode when the master issues a STOP condition. For timing information, see the Start a Conversion section. VOLTAGE REFERENCE S1 S3 R2 HOLD S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH TRACK TRACK HOLD S4 R1 = 12.5k (MAX127) OR 5.12k (MAX128) R2 = 8.67k (MAX127) OR (MAX128) Figure 2. Equivalent Input Circuit the device may be configured for unipolar mode. Overvoltage protection is active even if the device is in power-down mode or VDD = 0. Digital Interface The MAX127/MAX128 feature a 2-wire serial interface consisting of the SDA and SCL pins. SDA is the data I/O and SCL is the serial clock input, controlled by the master device. A2-A0 are used to program the MAX127/MAX128 to different slave addresses. (The MAX127/MAX128 only work as slaves.) The two bus lines (SDA and SCL) must be high when the bus is not in use. External pull-up resistors (1kor greater) are required on SDA and SCL to maintain I2C compatibility. Table 1 shows the input control-byte format. _______________________________________________________________________________________ 9 MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface Table 1. Control-Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 BIT NAME DESCRIPTION The logic "1" received after acknowledge of a write bit (R/W = 0) defines the beginning of the control byte. 7 (MSB) START 6, 5, 4 SEL2, SEL1, SEL0 3 RNG 2 BIP Selects unipolar or bipolar conversion mode (Table 3). 1, 0 (LSB) PD1, PD0 These two bits select the power-down modes (Table 4). These three bits select the desired "ON" channel (Table 2). Selects the full-scale input voltage range (Table 3). Table 2. Channel Selection Table 4. Power-Down and Clock Selection SEL2 SEL1 SEL0 CHANNEL 0 0 0 CH0 PD1 PD0 0 0 1 CH1 0 X Normal Operation (always on) 0 1 0 CH2 1 0 Standby Power-Down Mode (STBYPD) 0 1 1 CH3 1 1 Full Power-Down Mode (FULLPD) 1 0 0 CH4 1 0 1 CH5 1 1 0 CH6 1 1 1 CH7 MODE Table 3. Range and Polarity Selection INPUT RANGE (V) RNG BIP NEGATIVE FULL SCALE (V) ZERO SCALE (V) FULL SCALE (V) MAX127 0 to 5 0 0 - 0 VREF x 1.2207 0 to 10 1 0 - 0 VREF x 2.4414 5 0 1 -VREF x 1.2207 0 VREF x 1.2207 10 1 1 -VREF x 2.4414 0 VREF x 2.4414 0 to VREF/2 0 0 - 0 VREF/2 0 to VREF 1 0 - 0 VREF VREF/2 0 1 -VREF/2 0 VREF/2 VREF 1 1 -VREF 0 VREF MAX128 10 ______________________________________________________________________________________ Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface Conversion Control The master signals the beginning of a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 4). The bus is then free for another transmission. Figure 5 shows the timing diagram for signals on the 2-wire interface. The address-byte, control-byte, and data-byte are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit words. Nine clock cycles are required to transfer the data in or out of the MAX127/MAX128. (Figures 9 and 10). SLAVE ADDRESS 0 1 0 1 A2 A1 A0 R/W ACK SDA SDA LSB SCL SCL STOP CONDITION START CONDITION SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS A2, A1, AND A0. Figure 3. Address Byte Figure 4. START and STOP Conditions SDA tSU, DAT tBUF tSU, STA tHD, STA tLOW tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. 2-Wire Serial-Interface Timing Diagram ______________________________________________________________________________________ 11 MAX127/MAX128 Slave Address The MAX127/MAX128 have a 7-bit-long slave address. The first four bits (MSBs) of the slave address have been factory programmed and are always 0101. The logic state of the address input pins (A2-A0) determine the three LSBs of the device address (Figure 3). A maximum of eight MAX127/MAX128 devices can therefore be connected on the same bus at one time. A2-A0 may be connected to V DD or DGND, or they may be actively driven by TTL or CMOS logic levels. The eighth bit of the address byte determines whether the master is writing to or reading from the MAX127/ MAX128 (R/W = 0 selects a write condition. R/W = 1 selects a read condition). MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface Start a Conversion (Write Cycle) A conversion cycle begins with the master issuing a START condition followed by seven address bits (Figure 3) and a write bit (R/W = 0). Once the eighth bit has been received and the address matches, the MAX127/MAX128 (the slave) issues an acknowledge by pulling SDA low for one clock cycle (A = 0). The master then writes the input control byte to the slave (Figure 8). After this byte of data, the slave issues another acknowledge, pulling SDA low for one clock cycle. The master ends the write cycle by issuing a STOP condition (Figure 6). When the write bit is set (R/W = 0), acquisition starts as soon as Bit 2 (BIP) of the input control-byte has been latched and ends when a STOP condition has been issued. Conversion starts immediately after acquisition. The MAX127/MAX128's internal conversion clock frequency is 1.56MHz, resulting in a typical conversion time of 7.7s. Figure 9 shows a complete write cycle. 1 7 1 1 8 1 1 S SLAVE ADDRESS W A CONTROL-BYTE A P START CONDITION MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 8 1 8 1 1 S SLAVE ADDRESS R A DATA-BYTE A DATA-BYTE A P START CONDITION MSB 1 STOP CONDITION NOT ACKNOWLEDGE ACKNOWLEDGE READ START SEL2 SEL1 SEL0 RNG BIP MSB 2 W LSB A 8 9 7 START CONDITION PD0 ACK LSB SCL START: FIRST LOGIC "1" RECEIVED AFTER ACKNOWLEDGE OF A WRITE. ACK: ACKNOWLEDGE BIT. THE MAX127/MAX128 PULL SDA LOW DURING THE 9TH CLOCK PULSE. Figure 8. Command Byte CONTROL BYTE A/D STATE S BIP PD1 MSB 10 PD0 A LSB 11 15 16 17 ACQUISITION 18 CONVERSION STOP CONDITION Figure 9. Complete 2-Wire Serial Write Transmission 12 PD1 SDA 1 SDA NO. OF BITS Figure 7. Read Cycle SLAVE ADDRESS BYTE SCL STOP CONDITION ACKNOWLEDGE Figure 6. Write Cycle Read a Conversion (Read Cycle) Once a conversion starts, the master does not need to wait for the conversion to end before attempting to read the data from the slave. Data access begins with the master issuing a START condition followed by a 7-bit address (Figure 3) and a read bit (R/W = 1). Once the eighth bit has been received and the address matches, the slave issues an acknowledge by pulling low on SDA for one clock cycle (A = 0) followed by the first byte of serial data (D11-D4, MSB first). After the first byte has been issued by the slave, it releases the bus for the master to issue an acknowledge (A = 0). After receiving the acknowledge, the slave issues the second byte (D3-D0 and four zeros) followed by a NOT acknowledge (A = 1) from the master to indicate that the last data byte has been received. Finally, the master issues a STOP condition (P), ending the read cycle (Figure 7). 0 WRITE ACKNOWLEDGE MASTER TO SLAVE SLAVE TO MASTER NO. OF BITS ______________________________________________________________________________________ Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface LSB DATA BYTE 1 MSB 1 MSB DATA BYTE 2 7 R LSB A 8 9 D11 MSB 10 11 MAX127/MAX128 SLAVE ADDRESS BYTE 0 D4 LSB A 17 18 D3 MSB 19 D0 FILLED WITH 4 ZEROS A LSB 22 23 26 27 STOP CONDITION START CONDITION Figure 10. Complete 2-Wire Serial Read Transmission The MAX127/MAX128 ignore acknowledge and NOTacknowledge conditions issued by the master during the read cycle. The device waits for the master to read the output data or waits until a STOP condition is issued. Figure 10 shows a complete read cycle. In unipolar input mode, the output is straight binary. For bipolar input mode, the output is two's complement. For output binary codes see the Transfer Function section. Applications Information Power-On Reset The MAX127/MAX128 power up in normal operating mode, waiting for a START condition followed by the appropriate slave address. The contents of the input and output data registers are cleared at power-up. Internal or External Reference The MAX127/MAX128 operate with either an internal or an external reference (Figures 11a-11c). An external reference is connected to either REF or to REFADJ. The REFADJ internal buffer gain is trimmed to 1.6384 to provide 4.096V at REF from a 2.5V reference. Internal Reference The internally trimmed 2.50V reference is amplified through the REFADJ buffer to provide 4.096V at REF. Bypass REF with a 4.7F capacitor to AGND and bypass REFADJ with a 0.01F capacitor to AGND (Figure 11a). The internal reference voltage is adjustable to 1.5% (65 LSBs) with the reference-adjust circuit of Figure 12. External Reference To use the REF input directly, disable the internal buffer by connecting REFADJ to VDD (Figure 11b). Using the REFADJ input eliminates the need to buffer the reference externally. When the reference is applied at REFADJ, bypass REFADJ with a 0.01F capacitor to AGND (Figure 11c). At REF and REFADJ, the input impedance is a minimum of 10k for DC currents. During conversions, an external reference at REF must be able to drive a 400A DC load, and must have an output impedance of 10 or less. If the reference has higher input impedance or is noisy, bypass REF with a 4.7F capacitor to AGND as close to the chip as possible. With an external reference voltage of less than 4.096V at REF or less than 2.5V at REFADJ, the increase in RMS noise to the LSB value (full-scale voltage/4096) results in performance degradation and loss of effective bits. Power-Down Mode To save power, put the converter into low-current shutdown mode between conversions. Two programmable power-down modes are available, in addition to the hardware shutdown. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. In all powerdown modes, the interface remains active and conversion results may be read. Input overvoltage protection is active in all power-down modes. ______________________________________________________________________________________ 13 MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface REF CREF 4.7F MAX127 MAX128 +5V 510k 100k AV = 1.638 REFADJ REFADJ 0.01F 0.01F 24k 10k MAX127 MAX128 2.5V Figure 11a. Internal Reference Figure 12. Reference-Adjust Circuit REF 4.096V CREF 4.7F MAX127 MAX128 AV = 1.638 VDD REFADJ To power-up from a software initiated power-down, a START condition followed by the correct slave address must be received (with R/W = 0). The MAX127/MAX128 power-up after receiving the next bit. For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately and any conversion in progress is aborted. Choosing Power-Down Modes 10k 2.5V Figure 11b. External Reference, Reference at REF REF CREF 4.7F MAX127 MAX128 AV = 1.638 REFADJ 10k 2.5V 0.01F 2.5V The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7F capacitor at REF. This is a "DC" state that does not degrade after standby power-down of any duration. In FULLPD mode, only the bandgap reference is active. Connect a 33F capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-down ends. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50s for settling time. Auto-Shutdown Selecting STBYPD on every conversion automatically shuts the MAX127/MAX128 down after each conversion without requiring any start-up time on the next conversion. Figure 11c. External Reference, Reference at REFADJ 14 ______________________________________________________________________________________ Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface Layout, Grounding, and Bypassing Careful printed circuit board layout is essential for best system performance. For best performance, use a ground plane. To reduce crosstalk and noise injection, keep analog and digital signals separate. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1F and 4.7F capacitors to AGND to minimize highand low-frequency fluctuations. If the supply is excessively noisy, connect a 5 resistor between the supply and VDD, as shown in Figure 14. OUTPUT CODE FULL-SCALE TRANSITION 11... 111 1 LSB = FS 4096 11... 110 11... 101 SUPPLY GND +5V 4.7F R* = 5 00... 011 0.1F 00... 010 ** 00... 001 VDD 00... 000 0 1 2 AGND DGND +5V DGND FS 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB MAX127 MAX128 DIGITAL CIRCUITRY Figure 13a. Unipolar Transfer Function * OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE. OUTPUT CODE 1 LSB = 011... 111 2FS 4096 Figure 14. Power-Supply Grounding Connection 011... 110 000... 001 000... 000 111... 111 100... 010 100... 001 100... 000 -FS 0 +FS - 1 LSB INPUT VOLTAGE (LSB) Figure 13b. Bipolar Transfer Function ______________________________________________________________________________________ 15 MAX127/MAX128 Transfer Function Output data coding for the MAX127/MAX128 is binary in unipolar mode with 1LSB = (FS/4096) and two's complement binary in bipolar mode with 1LSB = [(2 x | FS | ) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 13a and 13b show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale (FS) values, refer to Table 3. MAX127/MAX128 Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface Ordering Information (continued) PIN-PACKAGE INL (LSB) PART TEMP. RANGE MAX127ACAI 0C to +70C 28 SSOP 1/2 MAX127BCAI 0C to +70C 28 SSOP 1 MAX127AENG -40C to +85C 24 Narrow Plastic DIP 1/2 MAX127BENG -40C to +85C 24 Narrow Plastic DIP 1 MAX127AEAI -40C to +85C 28 SSOP 1/2 MAX127BEAI -40C to +85C 28 SSOP 1 MAX128ACNG 0C to +70C 24 Narrow Plastic DIP 1/2 MAX128BCNG 0C to +70C 24 Narrow Plastic DIP 1 MAX128ACAI 0C to +70C 28 SSOP 1/2 MAX128BCAI 0C to +70C 28 SSOP 1 MAX128AENG -40C to +85C 24 Narrow Plastic DIP 1/2 MAX128BENG -40C to +85C 24 Narrow Plastic DIP 1 MAX128AEAI -40C to +85C 28 SSOP 1/2 MAX128BEAI -40C to +85C 28 SSOP 1 Chip Information TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED to AGND Pin Configurations TOP VIEW VDD 1 28 N.C. VDD 2 27 REF DGND 3 N.C. 4 SCL 5 MAX127 MAX128 VDD 1 24 N.C. 26 REFADJ VDD 2 23 REF 25 N.C. N.C. 3 22 N.C. 24 N.C. DGND 4 21 REFADJ MAX127 MAX128 23 CH7 SCL 5 N.C. 7 22 N.C. A0 6 19 CH6 N.C. 8 21 CH6 SDA 7 18 CH5 SDA 9 20 CH5 A2 8 17 CH4 A2 10 19 CH4 N.C. 9 16 CH3 N.C. 11 18 CH3 A1 10 15 CH2 A1 12 17 CH2 SHDN 11 14 CH1 SHDN 13 16 CH1 AGND 12 13 CH0 AGND 14 15 CH0 A0 6 20 CH7 DIP SSOP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.