Lattice ispLSI' 2128E snente Soruceaton In-System Programmable SuperFAST High Density PLD SUTIN teen ices * SUPERFAST HIGH DENSITY IN-SYSTEM 0 (EEE) GE EEE) = PROGRAMMABLE Loaic ! Output Routing Poot (ORP} ] | Output Routing Poo! (ORF) | 6000 PLD Gates 07 08 [25] fo] [oe | [2 [or] Coe | 128 0 Pins, Eight Dedicated Inputs n0 i -~ 128 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional/JEDEC Upward Compatible with ispLSI 2128 Devices HIGH PERFORMANCE ECMOS TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay TTL Compatible Inputs and Outputs 5V Programmable Logic Core a : We ispJTAG In-System Programmable via IEEE 1149.1 80 | [er || ae | es | [ells 25) | 66 | 66 || =| : | = eeuepcuaN[uasaganaagceuajueuajearapueeay | 4 put Routing Pool {ORP} ig SITS Lei t Routing Pool (ORP) Coy pn 2p ef - heed LL [ Output ting Poo! (ORP) La GLB . oO ' O41 iw o LoL por a oy Global Routing Pool (GRP) BO 5 (JTAG) Test Access Port | Output Houting Foal (GRP) jutput Routing Poot (ORP) i? , User-Seiectable 3.3V or SV I/O Supports Mixed- Oo BS GS Gen oe fas (as EEF 6 Voltage Systems wae PCI Compatible Outputs a Open-Drain Output Option Electrically Erasable and Reprogrammabie . Non-Volatile The ispLS! 2128E is a High Density Programmable Logic Unused Product Term Shutdown Saves Power Device. The device contains 128 Registers, 128 Univer- ispLSI OFFERS THE FOLLOWING ADDED FEATURES sal I/O pins, eight Dedicated Input pins, three Dedicated Increased Manufacturing Yields, Reduced Time-to- Clock Input pins, two dedicated Global OE input pins and Market and Improved Product Quality a Global Routing Pool (GRP). The GRP provides com- Reprogram Soldered Devices for Faster Prototyping plete interconnectivity between all of these elements. OFFERS THE EASE OF USE AND FAST SYSTEM The ispLS! 2128E features 5V in-system programmabil- SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY "tY and in-system diagnostic capabilities. The ispLS| OF FIELD PROGRAMMABLE GATE ARRAYS 2128E offers non-volatile reprogrammability of all logic, Complete Programmable Device Can Combine Glue 48 well as the interconnect to provide truly reconfigurable Logic and Structured Designs systems. Enhanced Pin Locking Capability The basic unit of logic on the ispLSI 2128E device is the ~ Three Dedicated Clock Input Pins Generic Logic Block (GLB). The GLBs are labeled AO, A1 Synchronous and Asynchronous Clocks .. D7 (see Figure 1). There are a total of 32 GLBs in the Programmable Output Slew Rate Control to Minimize Switching Noise isoLSI 2128E device. Each GLB is made up of four Flexible Pin Placement macroceills. Each GLB has 18 inputs, a programmable Optimized Global Routing Pool Provides Global AND/OR/Exclusive OR array, and four outputs which can Interconnectivity be configured to be either combinatorial or ispEXPERT LOGIC COMPILER AND COMPLETE registered.Inputs to the GLB come from the GRP and ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS dedicated inputs. All of the GLB outputs are brought back THROUGH IN-SYSTEM PROGRAMMING into the GRP so that they can be connected to the inputs Superior Quality of Results of any GLB on the device. Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore The device also has 128 I/O cells, each of which is Tools, Timing Simulator and isspANALYZER directly connected to an 1/O pin. Each 1/O cell can be PC and UNIX Platforms Copyright & 1998 Lattice Semicanductor Corp. All brand or product names ave trademarks or registered trademarks of their respective holders. The specifications and informaton herein are subject to change without notice LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. November 1998 Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http-./Awww.latticesemi.com 55Lattice * Semiconductor Corporation Specifications ispLSi 2128E Functional Block Diagram Figure 1. ispLSi 2128E Functional Block Diagram gas Output Routing Poct (OPP! L EEE EGE bee de. oer _ ro La oS a | Gutpun Routing Poo! (AFA L. eT reo Giobei Routing Paol iGRP} REDE GIGS ieee) a ese Tr inpat Gus LEE FEES PEs Ga individually programmed to be a combinatorial input, output or bi-directional (/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, {/O output leveis can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O pins provide PCl-compatible output drive. Eight GLBs, 32 1/0 ceils, two dedicated inputs and two OPPs are connected tagether to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal |/O cells by the two ORPs. Each ispLS! 2128E device contains four Megablocks. The GRP has as its inputs, the outputs from ail of the GLBs and all of the inputs from the bi-directional {/O cells. Allofthese signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSi 2128E device are selected using the dedicated clock pins. Three dedicated clock pins (YO, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2128E are individually program- mable, either as a standard totem-poie output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading anc pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration wher the device is in bulk erased state is totem-pole configuration. The open-drainjtotem-pole option is selectable through the isoEXPERT software tools. 96: Lattice Specifications ispLS/i 2128E ane Corporation External Timing Parameters Over Recommended Operating Conditions PARAMETER | LEST | DESCRIPTION 80 135 100 ___| units | COND. / MIN. |MAX.| MIN. |MAX.| MIN. |MAX. todi A 1 | Data Prop Delay. 4PT Bypass, ORP Bypass -~ '50/ - |75) ~ |100;) ns tod2 A 2 | Data Prop Delay - |}75 1) ~ 1100) ~ |18.0} ns fmax A 3 | Clk Freq with internal Feedback 180 ~ 135 -~ 1100) - MHz fax (Ext.) ~ 4 | Clk Freq with External Feedback (i771) 1251 - | 100} - 177.0; | MHz fmax (Tog.} - & | Clk Frequency, Max. Toggle 200} ~- | 143] - |} 100; | MHz tsut ~ 6 | GLB Reg Setup Time before Cik, 4 PT Bypass | 4.0 - 5.0) ~ 6.5 ~ ns tco1 A 7 | GLB Reg Clk to Output Delay, ORP Bypass ~ | 30 ~ | 4.0 - | 5.0 ns thi ~ 8 | GLB Reg Hold Time after Clk, 4 PT Bypass 00; - | 00; - j; a0] - ns tsu2 - 9 | GLB Reg Setup Time before Clk 50; -~ | 60; - - 80] - ns tco2 ~ | 10] GLB Reg Cik to Output Delay | - 35] - |45) - | eo] as the i - |11|GLBRegHoldTimeafterck | 00/ ~ [oo | ~ 00] - | ns tr ' A | 12] External Reset Pin to Output Delay - |70} - (100) |135| ns tw - 13 | External Reset Pulse Duration 40] - 5.0 ~ 65 | ns tptoeen B 14 | Input to Output Enable ~ 110.0) ~ 1120) - 145.0] ns tptoedis C | 18 Input to Output Disable ~TTao0} ft20] [150] ns | tgoeen : B _ | 16| Global OE Output Enabie ~ |50) ~ |} 70} - '9o0] ns tgoedis ' 117|Giobal OE Output Disable - |50,- 170] - 901 ns twh - 18 | External Synch Clk Pulse Duration, High 25] - |35 ~ | 50, - ns twi - '19)xternal Synch Cik Pulse Duration, Low 25 ~ 3.5 5.0 _ ns | . Unless noted otherwise, all parameters use a GRP load of four GLBs. 20 PTXOR path, ORP and YO clock. "#*?-0090A/2128e . Refer to Timing Model in this data sheet for further details. . Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. PON 57