Ultraprecision, Low Noise, 2.048 V/2.500 V/
3.00 V/5.00 V XFET® Voltage References
ADR420/ADR421/ADR423/ADR425
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low noise (0.1 Hz to 10 Hz)
ADR420: 1.75 μV p-p
ADR421: 1.75 μV p-p
ADR423: 2.0 μV p-p
ADR425: 3.4 μV p-p
Low temperature coefficient: 3 ppm/°C
Long-term stability: 50 ppm/1,000 hours
Load regulation: 70 ppm/mA
Line regulation: 35 ppm/V
Low hysteresis: 40 ppm typical
Wide operating range
ADR420: 4 V to 18 V
ADR421: 4.5 V to 18 V
ADR423: 5 V to 18 V
ADR425: 7 V to 18 V
Quiescent current: 0.5 mA maximum
High output current: 10 mA
Wide temperature range: −40°C to +125°C
APPLICATIONS
Precision data acquisition systems
High resolution converters
Battery-powered instrumentation
Portable medical instruments
Industrial process control systems
Precision instruments
Optical network control circuits
PIN CONFIGURATION
02432-001
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP 1
VIN 2
NIC 3
GND 4
TP8
NIC7
VOUT
6
TRIM
5
Figure 1. 8-Lead SOIC, 8-Lead MSOP
GENERAL DESCRIPTION
The ADR42x are a series of ultraprecision, second-generation
eXtra implanted junction FET (XFET) voltage references
featuring low noise, high accuracy, and excellent long-term
stability in SOIC and MSOP footprints.
Patented temperature drift curvature correction technique and
XFET technology minimize nonlinearity of the voltage change
with temperature. The XFET architecture offers superior
accuracy and thermal hysteresis to the band gap references. It
also operates at lower power and lower supply headroom than
the buried Zener references.
The superb noise and the stable and accurate characteristics of
the ADR42x make them ideal for precision conversion
applications such as optical networks and medical equipment.
The ADR42x trim terminal can also be used to adjust the out-
put voltage over a ±0.5% range without compromising any
other performance. The ADR42x series voltage references
offer two electrical grades and are specified over the extended
industrial temperature range of −40°C to +125°C. Devices have
8-lead SOIC or 30% smaller, 8-lead MSOP packages.
ADR42x PRODUCTS
Table 1.
Initial Accuracy
Model Output Voltage (VO) mV % Temperature Coefficient (ppm/°C)
ADR420 2.048 1, 3 0.05, 0.15 3, 10
ADR421 2.50 1, 3 0.04, 0.12 3, 10
ADR423 3.00 1.5, 4 0.04, 0.13 3, 10
ADR425 5.00 2, 6 0.04, 0.12 3, 10
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
ADR420 Electrical Specifications................................................... 3
ADR421 Electrical Specifications................................................... 4
ADR423 Electrical Specifications................................................... 5
ADR425 Electrical Specifications................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Parameter Definitions.................................................................... 15
Theory of Operation ...................................................................... 16
Device Power Dissipation Considerations.............................. 16
Basic Voltage Reference Connections...................................... 16
Noise Performance ..................................................................... 16
Turn-On Time ............................................................................ 16
Applications..................................................................................... 17
Output Adjustment .................................................................... 17
Reference for Converters in Optical Network
Control Circuits.......................................................................... 17
A Negative Precision Reference
Without Precision Resistors...................................................... 17
High Voltage Floating Current Source.................................... 18
Kelvin Connections.................................................................... 18
Dual-Polarity References........................................................... 18
Programmable Current Source ................................................ 19
Programmable DAC Reference Voltage.................................. 19
Precision Voltage Reference for Data Converters.................. 20
Precision Boosted Output Regulator....................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
6/05—Rev. F to Rev. G
Changes to Table 1............................................................................ 1
Changes to Ordering Guide .......................................................... 22
2/05—Rev. E to Rev. F
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
7/04—Rev. D to Rev. E.
Changes to Ordering Guide ............................................................ 5
3/04—Rev. C to Rev. D.
Changes to Table I ............................................................................ 1
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions....................................................... 16
1/03—Rev. B to Rev. C.
Changed Mini_SOIC to MSOP ........................................Universal
Changes to Ordering Guide.............................................................4
Corrections to Y-axis labels in TPCs 21 and 24 ............................9
Enhancement to Figure 13 ............................................................ 15
Updated Outline Dimensions....................................................... 16
3/02—Rev. A to Rev. B.
Edits to Ordering Guide ...................................................................4
Deletion of Precision Voltage Regulator section........................ 15
Addition of Precision Boosted Output Regulator section ....... 15
Addition of Figure 13..................................................................... 15
Rev. 0 to Rev. A.
Addition of ADR423 and ADR425 to
ADR420/ADR421...............................................................Universal
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 3 of 24
ADR420 ELECTRICAL SPECIFICATIONS
@ VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage, A Grade VO 2.045 2.048 2.051 V
Initial Accuracy VOERR −3 +3 mV
−0.15 +0.15 %
Output Voltage, B Grade VO 2.047 2.048 2.049 V
Initial Accuracy VOERR −1 +1 mV
−0.05 +0.05 %
Temperature Coefficient A Grade, TCVO−40°C < TA < +125°C 2 10 ppm°C
Temperature Coefficient, B Grade 1 3 ppm/°C
Supply Voltage Headroom VIN – VO 2 V
Line Regulation ΔVO/ΔVIN VIN = 5 V to 18 V 10 35 ppm/V
−40°C < TA < +125°C
Load Regulation ΔVO/ΔILOAD ILOAD = 0 mA to 10 mA 70 ppm/mA
−40°C < TA < +125°C
Quiescent Current IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
Voltage Noise eN p-p 0.1 Hz to 10 Hz 1.75 μV p-p
Voltage Noise Density eN1 kHz 60 nV/√Hz
Turn-On Settling Time tR 10 μs
Long-Term Stability ΔVO1,000 hours 50 ppm
Output Voltage Hysteresis VO_HYS 40 ppm
Ripple Rejection Ratio RRR fIN = 10 kHz 75 dB
Short Circuit to GND ISC 27 mA
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 4 of 24
ADR421 ELECTRICAL SPECIFICATIONS
@ VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage, A Grade VO 2.497 2.500 2.503 V
Initial Accuracy VOERR −3 +3 mV
−0.12 +0.12 %
Output Voltage, B Grade VO 2.499 2.500 2.501 V
Initial Accuracy VOERR −1 +1 mV
−0.04 +0.04 %
Temperature Coefficient, A Grade TCVO −40°C < TA < +125°C 2 10 ppm/°C
Temperature Coefficient, B Grade 1 3 ppm/°C
Supply Voltage Headroom VIN − VO 2 V
Line Regulation ΔVO/ΔVIN VIN = 5 V to 18 V 10 35 ppm/V
−40°C < TA < +125°C
Load Regulation ΔVO/ΔILOAD ILOAD = 0 mA to 10 mA 70 ppm/mA
−40°C < TA < +125°C
Quiescent Current IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
Voltage Noise eN p-p 0.1 Hz to 10 Hz 1.75 μV p-p
Voltage Noise Density eN 1 kHz 80 nV/√Hz
Turn-On Settling Time tR 10 μs
Long-Term Stability ΔVO 1,000 hours 50 ppm
Output Voltage Hysteresis VO_HYS 40 ppm
Ripple Rejection Ratio RRR fIN = 10 kHz 75 dB
Short Circuit to GND ISC 27 mA
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 5 of 24
ADR423 ELECTRICAL SPECIFICATIONS
@ VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage, A Grade VO 2.996 3.000 3.004 V
Initial Accuracy VOERR −4 +4 mV
−0.13 +0.13 %
Output Voltage, B Grade VO 2.9985 3.000 3.0015 V
Initial Accuracy VOERR −1.5 +1.5 mV
−0.04 +0.04 %
Temperature Coefficient, A Grade TCVO−40°C < TA < +125°C 2 10 ppm/°C
Temperature Coefficient, B Grade 1 3 ppm/°C
Supply Voltage Headroom VIN − VO 2 V
Line Regulation ΔVO/ΔVIN VIN = 5 V to 18 V 10 35 ppm/V
−40°C < TA < +125°C
Load Regulation ΔVO/ΔILOAD ILOAD = 0 mA to 10 mA 70 ppm/mA
−40°C < TA < +125°C
Quiescent Current IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
Voltage Noise eN p-p 0.1 Hz to 10 Hz 2 μV p-p
Voltage Noise Density eN1 kHz 90 nV/√Hz
Turn-On Settling Time tR 10 μs
Long-Term Stability ΔVO1,000 hours 50 ppm
Output Voltage Hysteresis VO_HYS 40 ppm
Ripple Rejection Ratio RRR fIN = 10 kHz 75 dB
Short Circuit to GND ISC 27 mA
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 6 of 24
ADR425 ELECTRICAL SPECIFICATIONS
@ VIN = 7.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage, A Grade VO 4.994 5.000 5.006 V
Initial Accuracy VOERR −6 +6 mV
−0.12 +0.12 %
Output Voltage, B Grade VO 4.998 5.000 5.002 V
Initial Accuracy VOERR −2 +2 mV
−0.04 +0.04 %
Temperature Coefficient, A Grade TCVO−40°C < TA < +125°C 2 10 ppm/°C
Temperature Coefficient, B Grade 1 3 ppm/°C
Supply Voltage Headroom VIN − VO 2 V
Line Regulation ΔVO/ΔVIN VIN = 7 V to 18 V 10 35 ppm/V
−40°C < TA < +125°C
Load Regulation ΔVO/ΔILOAD ILOAD = 0 mA to 10 mA 70 ppm/mA
−40°C < TA < +125°C
Quiescent Current IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
Voltage Noise eN p-p 0.1 Hz to 10 Hz 3.4 μV p-p
Voltage Noise Density eN1 kHz 110 nV/√Hz
Turn-On Settling Time tR 10 μs
Long-Term Stability ∆VO1,000 hours 50 ppm
Output Voltage Hysteresis VO_HYS 40 ppm
Ripple Rejection Ratio RRR fIN = 10 kHz 75 dB
Short Circuit to GND ISC 27 mA
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
These ratings apply at 25°C, unless otherwise noted.
Table 6.
Parameter Rating
Supply Voltage 18 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range R, RM Packages −65°C to +150°C
Operating Temperature Range ADR42x −40°C to +125°C
Junction Temperature Range R, RM Packages −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Table 7.
Package Type θJA1Unit
8-Lead MSOP (RM) 190 °C/W
8-Lead SOIC (R) 130 °C/W
1 θJA is specified for the worst-case conditions, that is, θJA is specified for
devices soldered in the circuit board for surface-mount packages.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02432-002
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP 1
VIN 2
NIC 3
GND 4
TP8
NIC7
VOUT
6
TRIM
5
Figure 2. Pin Configuration for 8-Lead SOIC
02432-003
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP 1
VIN 2
NIC 3
GND 4
TP8
NIC7
VOUT
6
TRIM
5
Figure 3. Pin Configuration for 8-Lead MSOP
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8 TP Test Pin. There are actual connections in TP pins but they are reserved for factory testing purposes. Users should not
connect anything to TP pins; otherwise, the device may not function properly.
2 VIN Input Voltage.
3, 7 NIC No Internal Connect. NICs have no internal connections.
4 GND Ground Pin = 0 V.
5 TRIM
Trim Terminal. It can be used to adjust the output voltage over a ±0.5% range without affecting the temperature
coefficient.
6 VOUT Output Voltage.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–40 –10 20 50 80 125110
02432-004
TEMPERATURE (°C)
V
OUT
(V)
2.0495
2.0493
2.0491
2.0489
2.0487
2.0485
2.0483
2.0481
2.0479
2.0477
2.0475
Figure 4. ADR420 Typical Output Voltage vs. Temperature
–40 –10 20 50 80 125110
02432-005
TEMPERATURE (°C)
V
OUT
(V)
2.4995
2.4997
2.4999
2.5001
2.5003
2.5005
2.5007
2.5009
2.5011
2.5013
2.5015
Figure 5. ADR421 Typical Output Voltage vs. Temperature
–40 –10 20 50 80 125110
02432-006
TEMPERATURE (°C)
V
OUT
(V)
3.0010
3.0008
3.0006
3.0004
3.0002
3.0000
2.9998
2.9996
2.9994
2.9992
2.9990
Figure 6. ADR423 Typical Output Voltage vs. Temperature
–40 –10 20 50 80 125110
02432-007
TEMPERATURE (°C)
V
OUT
(V)
5.0025
5.0023
5.0021
5.0019
5.0017
5.0015
5.0013
5.0011
5.0009
5.0007
5.0005
Figure 7. ADR425 Typical Output Voltage vs. Temperature
468101214
02432-008
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25 15
+125°C
+25°C
–40°C
Figure 8. ADR420 Supply Current vs. Input Voltage
468101214
02432-009
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
15
Figure 9. ADR421 Supply Current vs. Input Voltage
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 10 of 24
15468101214
02432-010
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
Figure 10. ADR423 Supply Current vs. Input Voltage
6 8 10 12 1514
02432-011
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
Figure 11. ADR425 Supply Current vs. Input Voltage
–40 –10 20 50 80 110 125
02432-012
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
70
50
60
40
30
20
10
0
I
L
= 0mA TO 5mA
V
IN
= 4.5V
V
IN
= 6V
Figure 12. ADR420 Load Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-013
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
70
50
60
40
30
20
10
0
I
L
= 0mA TO 5mA
V
IN
= 6.5V
V
IN
= 5V
Figure 13. ADR421 Load Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-014
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
70
50
60
40
30
20
10
0
I
L
= 0mA TO 10mA
V
IN
= 15V
V
IN
= 7V
Figure 14. ADR423 Load Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-015
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
35
25
30
20
15
10
5
0
V
IN
= 15V
I
L
= 0mA TO 10mA
Figure 15. ADR425 Load Regulation vs. Temperature
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 11 of 24
–40 –10 20 50 80 110 125
02432-016
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
6
4
5
3
2
1
0
V
IN
= 4.5V TO 15V
Figure 16. ADR420 Line Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-017
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
6
4
5
3
2
1
0
V
IN
= 5V TO 15V
Figure 17. ADR421 Line Regulation vs. Temperature
–40 –10 20 50 80 110
02432-018
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
9
6
8
4
5
7
3
2
1
0
V
IN
= 5V TO 15V
Figure 18. ADR423 Line Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-019
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
14
10
12
8
6
4
2
0
V
IN
= 7.5V TO 15V
Figure 19. ADR425 Line Regulation vs. Temperature
012345
02432-020
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+85°C
+25°C
Figure 20. ADR420 Minimum Input/Output Voltage
Differential vs. Load Current
012345
02432-021
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+125°C
+25°C
Figure 21. ADR421 Minimum Input/Output Voltage
Differential vs. Load Current
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 12 of 24
012345
02432-022
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+125°C
+25°C
Figure 22. ADR423 Minimum Input/Output Voltage
Differential vs. Load Current
012345
02432-023
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+125°C
+25°C
Figure 23. ADR425 Minimum Input/Output Voltage
Differential vs. Load Current
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
MORE
02432-024
DEVIATION (ppm)
NUMBER OF PARTS
30
20
25
15
10
5
0
SAMPLE SIZE – 160
TEMPERATURE
+25°C–40°C
+125°C +25°C
Figure 24. ADR421 Typical Hysteresis
02432-025
TIME (1s/DIV)
1μV/DIV
Figure 25. ADR421 Typical Noise Voltage 0.1 Hz to 10 Hz
02432-026
TIME (1s/DIV)
50μV/DIV
Figure 26. Typical Noise Voltage 10 Hz to 10 kHz
02432-027
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/ Hz)
ADR423
ADR421
ADR420
ADR425
10 100
10
100
1k
1k 10k
Figure 27. Voltage Noise Density vs. Frequency
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 13 of 24
02432-028
TIME (100
μ
s/DIV)
500mV/DIV
LINE INTERRUPTION
500mV/DIV
C
BYPASS
= 0
μ
F
V
IN
V
OUT
Figure 28. ADR421 Line Transient Response, no CBYPASS
02432-029
TIME (100
μ
s/DIV)
500mV/DIV
LINE INTERRUPTION
500mV/DIV
C
BYPASS
= 0.1
μ
F
V
IN
V
OUT
Figure 29. ADR421 Line Transient Response, CBYPASS = 0.1 μF
02432-030
TIME (100
μ
s/DIV)
2V/DIV
1V/DIV
C
L
= 0
μ
F
LOAD ON
LOAD OFF
V
OUT
1mA LOAD
Figure 30. ADR421 Load Transient Response, no CL
02432-031
TIME (100
μ
s/DIV)
2V/DIV
1V/DIV
C
L
= 100nF
LOAD ON
LOAD OFF
V
OUT
1mA LOAD
Figure 31. ADR421 Load Transient Response, CL = 100 nF
02432-032
TIME (4
μ
s/DIV)
V
IN
2V/DIV
V
OUT
2V/DIV
C
IN
= 0.01
μ
F
NO LOAD
Figure 32. ADR421 Turn-Off Response
02432-033
TIME (4
μ
s/DIV)
V
IN
2V/DIV
V
OUT
2V/DIV
C
IN
= 0.01
μ
F
NO LOAD
Figure 33. ADR421 Turn-On Response
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 14 of 24
02432-034
TIME (4
μ
s/DIV)
V
IN
2V/DIV
V
OUT
2V/DIV
C
LOAD
= 0.01
μ
F
NO INPUT CAP
Figure 34. ADR421 Turn-Off Response
02432-035
TIME (4
μ
s/DIV)
V
IN
2V/DIV
V
OUT
2V/DIV
C
LOAD
= 0.01
μ
F
NO INPUT CAP
Figure 35. ADR421 Turn-On Response
02432-036
TIME (100
μ
s/DIV)
2V/DIV
5V/DIV
V
IN
V
OUT
C
BYPASS
= 0.1
μ
F
R
L
= 500
Ω
C
L
= 0
Figure 36. ADR421 Turn-On/Turn-Off Response
ADR425
ADR420
ADR421
ADR423
10 100 1k 10k 100k
02432-037
FREQUENCY (Hz)
OUTPUT IMPEDANCE (
Ω
)
50
45
40
35
30
25
20
15
10
5
0
Figure 37. Output Impedance vs. Frequency
10 100 10k1k 100k 1M
02432-038
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Figure 38. Ripple Rejection vs. Frequency
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 15 of 24
PARAMETER DEFINITIONS
Temperature Coefficient
The change of output voltage over the operating temperature
range is normalized by the output voltage at 25°C, and
expressed in ppm/°C as
()
(
)
(
)
()
()
6
10
25 ×
−×°
−
=°
12
O
1
O
2
O
OTTCV
TVTV
C/ppmTCV
where:
VO (25°C) = VO at 25°C.
VO (T1) = VO at Temperature 1.
VO (T2) = VO at Temperature 2.
Line Regulation
The change in output voltage due to a specified change in input
voltage. It includes the effects of self-heating. Line regulation is
expressed in either percent-per-volt, parts-per-million per volt,
or microvolts-per-volt change in input voltage.
Load Regulation
The change in output voltage due to a specified change in load
current. It includes the effects of self-heating. Load regulation is
expressed in either microvolts-per-milliampere, parts-per-
million per milliampere, or ohms of dc output resistance.
Long-Term Stability
Typical shift of output voltage at 25°C on a sample of parts
subjected to operation life test of 1,000 of hours at 125°C
(
)
()
1
O
0
OO tVtVV −=Δ
()
(
)
(
)
()
6
10×
−
=Δ
0
O
1
O
0
O
OtV
tVtV
ppmV
where:
VO (t0) = VO at 25°C at Time 0.
VO (t1) = VO at 25°C after 1,000 hours operation at 125°C.
Thermal Hysteresis
The change of output voltage after the device is cycled through
temperatures from +25°C to −40°C to +125°C and back to
+25°C. This is a typical value from a sample of parts put
through such a cycle
(
)
TC_O
OHYS_O VCVV
−
°
=
25
()
(
)
()
6
10
25
25 ×
°
−°
=CV
VCV
ppmV
O
TC_O
O
HYS_O
where:
VO (25°C) = VO at 25°C.
VO_TC = VO at 25 °C after temperature cycle at +25°C to −40°C
to +125°C and back to +25°C.
Input Capacitor
Input capacitors are not required on the ADR42x. There is no
limit for the value of the capacitor used on the input, but a 1 μF
to 10 μF capacitor on the input improves transient response in
applications where the supply suddenly changes. An additional
0.1 μF capacitor in parallel also helps to reduce noise from the
supply.
Output Capacitor
The ADR42x do not need output capacitors for stability under
any load condition. An output capacitor, typically 0.1 μF, filters
out any low level noise voltage and does not affect the operation
of the part. On the other hand, the load transient response can
be improved with an additional 1 μF to 10 μF output capacitor
in parallel. A capacitor here acts as a source of stored energy for
sudden increase in load current. The only parameter that
degrades by adding an output capacitor is the turn-on time, and
it depends on the size of the selected capacitor.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 16 of 24
THEORY OF OPERATION
The ADR42x series of references uses a new reference genera-
tion technique known as XFET (eXtra implanted junction FET).
This technique yields a reference with low supply current, good
thermal hysteresis, and exceptionally low noise. The core of the
XFET reference consists of two junction field-effect transistors
(JFET), one having an extra channel implant to raise its pinch-
off voltage. By running the two JFETs at the same drain current,
the difference in pinch-off voltage can be amplified and used to
form a highly stable voltage reference.
The intrinsic reference voltage is about 0.5 V with a negative
temperature coefficient of about −120 ppm/°C. This slope is
essentially constant to the dielectric constant of silicon and can
be closely compensated by adding a correction term generated
in the same fashion as the proportional-to-temperature (PTAT)
term used to compensate band gap references. The primary
advantage over a band gap reference is that the intrinsic
temperature coefficient is approximately 30 times lower
(therefore requiring less correction). This results in much lower
noise because most of the noise of a band gap reference comes
from the temperature compensation circuitry.
Figure 39 shows the basic topology of the ADR42x series. The
temperature correction term is provided by a current source
with a value designed to be proportional to absolute
temperature. The general equation is
VOUT = G × (ΔVP − R1 × IPTAT) (1)
where:
G is the gain of the reciprocal of the divider ratio.
ΔVP is the difference in pinch-off voltage between the two JFETs.
IPTAT is the positive temperature coefficient correction current.
ADR42x are created by on-chip adjustment of R2 and R3 to
achieve 2.048 V or 2.500 V at the reference output, respectively.
02432-039
*
R3
GND
*EXTRA CHANNEL IMPLANT
V
OUT
= G(ΔV
P
– R1 × I
PTAT
)
R2
I
PTAT
ΔV
P
R1
V
IN
V
OUT
ADR420/ADR421/
ADR423/ADR425
I
1
I
1
Figure 39. Simplified Schematic
DEVICE POWER DISSIPATION CONSIDERATIONS
The ADR42x family of references is guaranteed to deliver load
currents to 10 mA with an input voltage that ranges from 4.5 V
to 18 V. When these devices are used in applications at higher
currents, the following equation should be used to account for
the temperature effects due to power dissipation increases:
TJ = PD × θJA + TA (2)
where:
TJ and TA are the junction and ambient temperatures,
respectively.
PD is the device power dissipation.
θJA is the device package thermal resistance.
BASIC VOLTAGE REFERENCE CONNECTIONS
Voltage references, in general, require a bypass capacitor
connected from VOUT to GND. The circuit in Figure 40
illustrates the basic configuration for the ADR42x family of
references. Other than a 0.1 μF capacitor at the output to help
improve noise suppression, a large output capacitor at the
output is not required for circuit stability.
02432-040
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP
1
V
IN 2
NIC
3
4
TP
8
NIC
7
OUTPUT
6
TRIM
5
0.1μF
0.1μF10μF+
Figure 40. Basic Voltage Reference Configuration
NOISE PERFORMANCE
The noise generated by ADR42x references is typically less
than 2 μV p-p over the 0.1 Hz to 10 Hz band for the ADR420,
ADR421, and ADR423. Figure 25 shows the 0.1 Hz to 10 Hz
noise of the ADR421, which is only 1.75 μV p-p. The noise
measurement is made with a band-pass filter made of a 2-pole
high-pass filter with a corner frequency at 0.1 Hz and a 2-pole
low-pass filter with a corner frequency at 10 Hz.
TURN-ON TIME
At power-up (cold start), the time required for the output
voltage to reach its final value within a specified error band is
defined as the turn-on settling time. Two components typically
associated with this are the time for the active circuits to settle
and the time for the thermal gradients on the chip to stabilize.
Figure 32 to Figure 36 show the turn-on settling time for the
ADR421.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 17 of 24
APPLICATIONS
OUTPUT ADJUSTMENT
The ADR42x trim terminal can be used to adjust the output
voltage over a ±0.5% range. This feature allows the system
designer to trim system errors out by setting the reference to
a voltage other than the nominal. This is also helpful if the
part is used in a system at temperature to trim out any error.
Adjustment of the output has a negligible effect on the
temperature performance of the device. To avoid degrading
temperature coefficients, both the trimming potentiometer
and the two resistors need to be low temperature coefficient
types, preferably <100 ppm/°C.
02432-041
ADR420/
ADR421/
ADR423/
ADR425
R2
V
IN
INPUT
GND TRIM
R1
470kΩR
P
10kΩ
10kΩ (ADR420)
15kΩ (ADR421)
OUTPUT
V
O
= ±0.5%
V
O
2
4
5
6
Figure 41. Output Trim Adjustment
REFERENCE FOR CONVERTERS IN OPTICAL
NETWORK CONTROL CIRCUITS
In the high capacity, all-optical router network of Figure 42,
arrays of micromirrors direct and route optical signals from
fiber to fiber, without first converting them to electrical form,
which reduces the communication speed. The tiny micro-
mechanical mirrors are positioned so that each is illuminated
by a single wave length that carries unique information and
can be passed to any desired input and output fiber. The mirrors
are tilted by the dual-axis actuators controlled by precision
analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs) within the system. Due to the microscopic
movement of the mirrors, not only is the precision of the
converters important, but the noise associated with these
controlling converters is extremely critical, because total noise
within the system can be multiplied by the numbers of
converters used. Consequently, the exceptional low noise of the
ADR42x is necessary to maintain the stability of the control
loop for this application.
02432-042
DAC DACADC
DSP
CONTROL
ELECTRONICS
ACTIVATOR
LEFT
LASER BEAM
SOURCE FIBER
GIMBAL + SENSOR DESTINATION
FIBER
ACTIVATOR
RIGHT
MEMS MIRROR
AMPLPREAMPAMPL
ADR421
ADR421
ADR421
Figure 42. All-Optical Router Network
A NEGATIVE PRECISION REFERENCE
WITHOUT PRECISION RESISTORS
In many current-output CMOS DAC applications where the
output signal voltage must be of the same polarity as the
reference voltage, a current-switching DAC is often recon-
figured into a voltage-switching DAC with a 1.25 V reference,
an op amp, a pair of resistors, and an additional operational
amplifier at the output to reinvert the signal. A negative voltage
reference should be used because an additional operational
amplifier is not required for either reinversion (current-
switching mode) or amplification (voltage-switching mode) of
the DAC output voltage. In general, any positive voltage
reference can be converted into a negative voltage reference
through the use of an operational amplifier and a
pair of matched resistors in an inverting configuration. The
disadvantage to this approach is that the largest single source of
error in the circuit is the relative matching of the resistors used.
A negative reference can easily be generated by adding a
precision op amp and configuring as shown in Figure 43. VOUT
is at virtual ground and, therefore, the negative reference can be
taken directly from the output of the op amp. The op amp must
be dual-supply, low offset and have rail-to-rail capability if
negative supply voltage is close to the reference output.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 18 of 24
02432-043
A1
2
6
4
ADR420/
ADR421/
ADR423/
ADR425
V
IN
+V
DD
–V
DD
–V
REF
GND
A1 = OP777, OP193
V
OUT
Figure 43. Negative Reference
HIGH VOLTAGE FLOATING CURRENT SOURCE
The circuit in Figure 44 can be used to generate a floating
current source with minimal self-heating. This particular
configuration can operate on high supply voltages determined
by the breakdown voltage of the N-channel JFET.
02432-044
+V
S
–V
S
SST111
VISHAY
V
IN
GND
V
OUT
ADR420/
ADR421/
ADR423/
ADR425
2N3904
R
L
2.10kΩ
OP09
2
4
6
Figure 44. High Voltage Floating Current Source
KELVIN CONNECTIONS
In many portable instrumentation applications where PC board
cost and area are important considerations, circuit intercon-
nects are often narrow. These narrow lines can cause large
voltage drops if the voltage reference is required to provide load
currents to various functions. In fact, a circuit’s interconnects
can exhibit a typical line resistance of 0.45 mΩ/square (1 oz. Cu,
for example). Force and sense connections, also referred to as
Kelvin connections, offer a convenient method of eliminating
the effects of voltage drops in circuit wires. Load currents flow-
ing through wiring resistance produce an error (VERROR = R × IL)
at the load. However, the Kelvin connection in Figure 45
overcomes the problem by including the wiring resistance
within the forcing loop of the op amp. Because the op amp
senses the load voltage, op amp loop control forces the output to
compensate for the wiring error and to produce the correct
voltage at the load.
02432-045
A1
V
IN
V
IN
R
LW
A1 = OP191
R
LW
R
L
V
OUT
SENSE
V
OUT
FORCE
GND
V
OUT
ADR420/
ADR421/
ADR423/
ADR425
2
4
6
Figure 45. Advantage of Kelvin Connection
DUAL-POLARITY REFERENCES
Dual-polarity references can easily be made with an op amp and
a pair of resistors. In order not to defeat the accuracy obtained
by the ADR42x, it is imperative to match the resistance toler-
ance and the temperature coefficient of all components.
02432-046
V
IN
1
μ
F 0.1
μ
F
R1
10k
Ω
R3
5k
Ω
R2
10k
Ω
+5V
–5V
+10V
–10V
6
2
4
5
V+
V–
U1
ADR425
U2
OP1177
V
OUT
V
IN
TRIM
GND
Figure 46. +5 V and −5 V Reference Using ADR425
02432-047
R1
5.6kΩ
R2
5.6kΩ
+2.5V
+
10V
–10V
–2.5V
U1
ADR425
6
2
4
5
V+
V–
VOUT
VIN
TRIM
GND
U2
OP1177
Figure 47. +2.5 V and −2.5 V Reference Using ADR425
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 19 of 24
PROGRAMMABLE CURRENT SOURCE
Together with a digital potentiometer and a Howland current
pump, the ADR425 forms the reference source for a program-
mable current as
W
B
B
A
LV
R2
R1
R2R2
I×
⎟
⎠
⎞
⎜
⎝
⎛+
= (3)
and
REF
NV
D
VW ×= 2 (4)
where:
D = Decimal equivalent of the input code.
N = Number of bits.
02432-048
U1
ADR425
V
OUT
V
IN
V
DD
V
DD
V
SS
TRIM
GND A
WB
U2
AD5232
U2
DIGITAL POT
IL
V+
V–
2
5
6
4
A1
OP2177
V
DD
V
SS
V+
V–
A2
OP2177
LOAD
VL
R1
50kΩR2
A
1kΩ
R2
B
10Ω
C2
10pF
R2'
1kΩ
R1'
50kΩ
C1
10pF
Figure 48. Programmable Current Source
R1' and R2' must be equal to R1 and R2A + R2B, respectively.
Theoretically, R2
PROGRAMMABLE DAC REFERENCE VOLTAGE
With a multichannel DAC, such as the quad, 12-bit voltage
output AD7398, one of its internal DACs, and an ADR42x
voltage reference can be used as a common programmable
VREFX for the rest of the DACs. The circuit configuration is
shown in Figure 49. The relationship of VREFX to VREF depends
on the digital code and the ratio of R1 and R, and is given by
⎟
⎠
⎞
⎜
⎝
⎛×+
⎟
⎠
⎞
⎜
⎝
⎛+×
=
1
2
2
1
1
2
1
R
RD
R
R
V
V
N
REF
REFX (5)
where:
D = Decimal equivalent of input code.
N = Number of bits.
VREF = Applied external reference.
VREFX = Reference voltage for DACs A to D.
Table 9. VREFX vs. R1 and R2
R1, R2 Digital Code VREF
R1 = R2 0000 0000 0000 2 VREF
R1 = R2 1000 0000 0000 1.3 VREF
R1 = R2 1111 1111 1111 VREF
R1 = 3R2 0000 0000 0000 4 VREF
R1 = 3R2 1000 0000 0000 1.6 VREF
R1 = 3R2 1111 1111 1111 VREF
02432-049
VIN
DACA
DACB
DACC
DACD
AD7398
ADR425
VREF
VREFAVOUTAR1
±0.1%
R2
±0.1%
VOB = VREFX (DB)
VOC = VREFX (DC)
VOD = VREFX (DD)
VOUTB
VOUTC
VOUTD
VREFB
VREFC
VREFD
B
BB can be made as small as needed to achieve
the current needed within A2 output current driving capability.
In the example shown in Figure 48, OP2177 is able to deliver a
maximum of 10 mA. Because the current pump uses both
positive and negative feedback, Capacitors C1 and C2 are
needed to ensure that negative feedback prevails and, therefore,
avoids oscillation. This circuit also allows bidirectional current
flow if the inputs VA and VB of the digital potentiometer are
supplied with the dual-polarity references as previously shown.
B
Figure 49. Programmable DAC Reference
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 20 of 24
PRECISION VOLTAGE REFERENCE FOR DATA
CONVERTERS
The ADR42x family has a number of features that make it ideal
for use with ADCs and DACs. The exceptionally low noise,
tight temperature coefficient, and high accuracy characteristics
make the ADR42x ideal for low noise applications such as
cellular base station applications.
AD7701 is an example of an ADC that is well suited for the
ADR42x. The ADR421 is used as the precision reference for
the converter in Figure 50. The AD7701 is a 16-bit ADC with
on-chip digital filtering intended for measuring wide dynamic
range and low frequency signals, such as those representing
chemical, physical, or biological processes. It contains a charge-
balancing (Σ-Δ) ADC, calibration microcontroller with on-chip
static RAM, clock oscillator, and serial communications port.
02432-050
AD7701
ADR420/
ADR421/
ADR423/
ADR425
V
IN
AV
DD
DV
DD
SLEEP
MODE
DRDV
CS
SCLK
SDATA
DATA READY
READ (TRANSMIT)
SERIAL CLOCK
SERIAL CLOCK
CLKIN
CLKOUT
SC1
SC2
DGND
DV
SS
V
REF
BP/UP
CAL
A
IN
AGND
AV
SS
0.1μF
0.1μF10μF
+5V
ANALOG
SUPPLY
RANGES
SELECT
CALIBRATE
ANALOG
INPUT
ANALOG
GROUND
–5V
ANALOG
SUPPLY
GND
V
OUT
0.1μF
0.1μF
0.1μF
0.1μF10μF
Figure 50. Voltage Reference for 16-Bit ADC AD7701
PRECISION BOOSTED OUTPUT REGULATOR
A precision voltage output with boosted current capability
can be realized with the circuit shown in Figure 51. In this
circuit, U2 forces VO to be equal to VREF by regulating the turn
on of N1. Therefore, the load current is furnished by VIN. In
this configuration, a 50 mA load is achievable at VIN of 5 V.
Moderate heat is generated on the MOSFET, and higher current
can be achieved by replacing the larger device. In addition, for
a heavy capacitive load with step input, a buffer may be added
at the output to enhance the transient response.
02432-051
V
IN
V
O
R
L
25Ω
N1
5
6
U12
4
U2
AD8601
5V
2N7002
V+
V–
+
–
ADR421
V
IN
V
OUT
TRIM
GND
Figure 51. Precision Boosted Output Regulator
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 21 of 24
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.80
0.60
0.40
8°
0°
4
8
1
5
4.90
BSC
PIN 1 0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 22 of 24
ORDERING GUIDE
Temp Package Package Top Output Initial Accuracy Temp Co.
Model Range (°C) Description Option Mark Voltage (VO) mV % (ppm/°C)
ADR420AR −40 to +125 SOIC_N R-8 ADR420 2.048 3 0.15 10
ADR420AR-REEL7 −40 to +125 SOIC_N R-8 ADR420 2.048 3 0.15 10
ADR420ARZ1−40 to +125 SOIC_N R-8 ADR420 2.048 3 0.15 10
ADR420ARZ-REEL71−40 to +125 SOIC_N R-8 ADR420 2.048 3 0.15 10
ADR420ARM −40 to +125 MSOP RM-8 R4A 2.048 3 0.15 10
ADR420ARM-REEL7 −40 to +125 MSOP RM-8 R4A 2.048 3 0.15 10
ADR420ARMZ1−40 to +125 MSOP RM-8 L0C 2.048 3 0.15 10
ADR420ARMZ-REEL71−40 to +125 MSOP RM-8 L0C 2.048 3 0.15 10
ADR420BR −40 to +125 SOIC_N R-8 ADR420 2.048 1 0.05 3
ADR420BR-REEL7 −40 to +125 SOIC_N R-8 ADR420 2.048 1 0.05 3
ADR420BRZ1−40 to +125 SOIC_N R-8 ADR420 2.048 1 0.05 3
ADR420BRZ-REEL71−40 to +125 SOIC_N R-8 ADR420 2.048 1 0.05 3
ADR421AR −40 to +125 SOIC_N R-8 ADR421 2.50 3 0.12 10
ADR421AR-REEL7 −40 to +125 SOIC_N R-8 ADR421 2.50 3 0.12 10
ADR421ARZ1−40 to +125 SOIC_N R-8 ADR421 2.50 3 0.12 10
ADR421ARZ-REEL71−40 to +125 SOIC_N R-8 ADR421 2.50 3 0.12 10
ADR421ARM −40 to +125 MSOP RM-8 R5A 2.50 3 0.12 10
ADR421ARM-REEL7 −40 to +125 MSOP RM-8 R5A 2.50 3 0.12 10
ADR421ARMZ1−40 to +125 MSOP RM-8 R06 2.50 3 0.12 10
ADR421ARMZ-REEL71−40 to +125 MSOP RM-8 R06 2.50 3 0.12 10
ADR421BR −40 to +125 SOIC_N R-8 ADR421 2.50 1 0.04 3
ADR421BR-REEL7 −40 to +125 SOIC_N R-8 ADR421 2.50 1 0.04 3
ADR421BRZ1−40 to +125 SOIC_N R-8 ADR421 2.50 1 0.04 3
ADR421BRZ-REEL71−40 to +125 SOIC_N R-8 ADR421 2.50 1 0.04 3
ADR423AR −40 to +125 SOIC_N R-8 ADR423 3.00 4 0.13 10
ADR423AR-REEL7 −40 to +125 SOIC_N R-8 ADR423 3.00 4 0.13 10
ADR423ARZ1−40 to +125 SOIC_N R-8 ADR423 3.00 4 0.13 10
ADR423ARZ-REEL71−40 to +125 SOIC_N R-8 ADR423 3.00 4 0.13 10
ADR423ARM −40 to +125 MSOP RM-8 R6A 3.00 4 0.13 10
ADR423ARM-REEL7 −40 to +125 MSOP RM-8 R6A 3.00 4 0.13 10
ADR423BR −40 to +125 SOIC_N R-8 ADR423 3.00 1.5 0.04 3
ADR423BR-REEL7 −40 to +125 SOIC_N R-8 ADR423 3.00 1.5 0.04 3
ADR423ARMZ1−40 to +125 MSOP RM-8 R0U 3.00 4 0.13 10
ADR423ARMZ-REEL71−40 to +125 MSOP RM-8 R0U 3.00 4 0.13 10
ADR423BRZ1−40 to +125 SOIC_N R-8 ADR423 3.00 1.5 0.04 3
ADR423BRZ-REEL71−40 to +125 SOIC_N R-8 ADR423 3.00 1.5 0.04 3
ADR425AR −40 to +125 SOIC_N R-8 ADR425 5.00 6 0.12 10
ADR425AR-REEL7 −40 to +125 SOIC_N R-8 ADR425 5.00 6 0.12 10
ADR425ARZ1−40 to +125 SOIC_N R-8 ADR425 5.00 6 0.12 10
ADR425ARZ-REEL71−40 to +125 SOIC_N R-8 ADR425 5.00 6 0.12 10
ADR425ARM −40 to +125 MSOP RM-8 R7A 5.00 6 0.12 10
ADR425ARM-REEL7 −40 to +125 MSOP RM-8 R7A 5.00 6 0.12 10
ADR425ARMZ1−40 to +125 MSOP RM-8 R0V 5.00 6 0.12 10
ADR425ARMZ-REEL71−40 to +125 MSOP RM-8 R0V 5.00 6 0.12 10
ADR425BR −40 to +125 SOIC_N R-8 ADR425 5.00 2 0.04 3
ADR425BR-REEL7 −40 to +125 SOIC_N R-8 ADR425 5.00 2 0.04 3
ADR425BRZ1−40 to +125 SOIC_N R-8 ADR425 5.00 2 0.04 3
ADR425BRZ-REEL71−40 to +125 SOIC_N R-8 ADR425 5.00 2 0.04 3
1 Z = Pb-free part.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 23 of 24
NOTES
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 24 of 24
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02432-0-6/05(G)
