Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. B
12/01/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
128K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 35ns, 45ns, 55ns
• CMOS low power operation:
12 mW (typical) operating
4 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
1.65V--2.2V Vdd (62WV1288dALL)
2.3V--3.6V Vdd (62WV1288dBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and automotive temperature support
• Lead-free available
DESCRIPTION
The ISSI IS62/65WV1288DALL and IS62/65WV1288DBLL
are high-speed, 1M bit static RAMs organized as
128K words by 8 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65WV1288DALL and IS62/65WV1288DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPEI),
sTSOP (TYPEI), SOP, and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
DECEMBER 2010
A0-A16
CS1
OE
WE
128K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
CS2
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
PIN DESCRIPTIONS
A0-A16 Address Inputs
CS1 Chip Enable 1 Input
CS2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
NC No Connection
Vdd Power
GND Ground
36-pin mini BGA (B) (6mm x 8mm)
32-pin TSOP (TYPE I) (T),
32-pin sTSOP (TYPE I) (H)
PIN CONFIGURATION
32-pin SOP (Q)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
OE
A10
CS2
WE
NC
NC
CS1
A11
A3
A4
A5
NC
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
V
DD
GND
I/O2
I/O3
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CS2
A15
VDD
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V
Vdd Vdd Relates to GND –0.3 to 4.0 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
Cin Input Capacitance Vin = 0V 6 pF
Ci/O Input/Output Capacitance VOut = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vdd = 3.3V.
TRUTH TABLE
Mode WE CS1 CS2 OE I/O Operation VDD Current
Not Selected X H X X High-Z isB1, isB2
(Power-down) X X L X High-Z isB1, isB2
Output Disabled H L H H High-Z iCC
Read H L H L dOut iCC
Write L L H X din iCC
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
AC TEST LOADS
Figure 1.
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
Figure 2.
AC TEST CONDITIONS
Parameter Unit Unit Unit
(2.3V-3.6V) (3.3V + 5%) (1.65V-2.2V)
Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V
Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns
Input and Output Timing VDD /2 VDD + 0.05 0.9V
and Reference Level (VRef) 2
Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2
R1 ( Ω ) 317 317 13500
R2 ( Ω ) 351 351 10800
Vtm (V) 3.3V 3.3V 1.8V
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.3V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VOh Output HIGH Voltage Vdd = Min., iOh = –1.0 mA 1.8 — V
VOL Output LOW Voltage Vdd = Min., iOL = 2.1 mA — 0.4 V
Vih Input HIGH Voltage 2.0 Vdd + 0.3 V
ViL Input LOW Voltage(1) –0.3 0.8 V
iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA
iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter Test Conditions Min. Max. Unit
VOh Output HIGH Voltage Vdd = Min., iOh = –1 mA 2.4 — V
VOL Output LOW Voltage Vdd = Min., iOL = 2.1 mA — 0.4 V
Vih Input HIGH Voltage 2 Vdd + 0.3 V
ViL Input LOW Voltage(1) –0.3 0.8 V
iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA
iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter Test Conditions VDD Min. Max. Unit
VOh Output HIGH Voltage iOh = -0.1 mA 1.65-2.2V 1.4 — V
VOL Output LOW Voltage iOL = 0.1 mA 1.65-2.2V — 0.2 V
Vih Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V
ViL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA
iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35 -45 -55
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
iCC Vdd Dynamic Operating Vdd = Max., Com. — 8 — 6 — 5 mA
Supply Current iOut = 0 mA, f = fmAx Ind. — 12 — 8 — 7
CS1 = ViL Auto. — 15 — 12 — 12
Vin ≥ Vdd – 0.3V, or typ.(2) 4
Vin ≤ 0.4V
iCC1 Operating Vdd = Max., Com. — 2.5 — 2.5 — 2.5 mA
Supply Current iOut = 0 mA, f = 0 Ind. — 2.5 — 2.5 — 2.5
CS1 = ViL Auto. — 3 — 3 — 3
Vin ≥ Vdd – 0.3V, or
Vin ≤ 0.4V
isB2 CMOS Standby Vdd = Max., Com. — 2 — 2 — 2
µ
A
Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V, Ind. — 4 — 4 — 4
Vin ≥ Vdd – 0.2V, or Auto. — 18 — 18 — 18
Vin ≤ 0.2V
, f = 0 typ.(2) 0.6
Note:
1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
OPERATING RANGE (VDD)
Range Ambient Temperature VDD (45 nS) VDD (35 nS)
Commercial 0°C to +70°C 2.3V-3.6V 3.3V+5%
Industrial –40°C to +85°C 2.3V-3.6V 3.3V+5%
OPERATING RANGE (VDD)
Range Ambient Temperature VDD Speed
Commercial 0°C to +70°C 1.65V-2.2V 45ns
Industrial –40°C to +85°C 1.65V-2.2V 55ns
Automotive –40°C to +125°C 1.65V-2.2V 55ns
OPERATING RANGE (VDD)
Range Ambient Temperature VDD (45 nS)
Automotive –40°C to +125°C 2.3V-3.6V
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
35 ns
45 ns 55 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trC Read Cycle Time 35 — 45 — 55 — ns
tAA Address Access Time — 35 — 45 — 55 ns
tOhA Output Hold Time 10 — 10 — 10 — ns
tACs1/tACs2 CS1/CS2 Access Time — 35 — 45 — 55 ns
tdOe OE Access Time — 10 — 20 — 25 ns
thzOe(2) OE to High-Z Output — 10 — 15 — 20 ns
tLzOe(2) OE to Low-Z Output 3 — 5 — 5 — ns
thzCs1/thzCs2(2) CS1/CS2 to High-Z Output 0 10 0 15 0 20 ns
tLzCs1/tLzCs2(2) CS1/CS2 to Low-Z Output 5 — 10 — 10 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = ViL, Cs2 = WE = Vih)
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA
tOHA
tRC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= ViL. Cs2=WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW and Cs2 high transition.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS1/
t
ACS2
t
LZCS1/
t
LZCS2
t
HZOE
HIGH-Z
DATA VALID
t
HZCS
ADDRESS
OE
CS1
CS2
DOUT
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
35ns 45ns 55 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 35 — 45 — 55 — ns
tsCs1/tsCs2 CS1/CS2 to Write End 25 — 35 — 45 — ns
tAW Address Setup Time to Write End 25 — 35 — 45 — ns
thA Address Hold from Write End 0 — 0 — 0 — ns
tsA Address Setup Time 0 — 0 — 0 — ns
tPWe WE Pulse Width 25 — 35 — 40 — ns
tsd Data Setup to Write End 20 — 20 — 25 — ns
thd Data Hold from Write End 0 — 0 — 0 — ns
thzWe(3) WE LOW to High-Z Output — 10 — 20 — 20 ns
tLzWe(3) WE HIGH to Low-Z Output 3 — 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCS1
tSCS2
tAW
tHA
t
PWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
CS1
CS2
WE
DOUT
DIN
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
DOUT
DIN
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.2 3.6 V
idr Data Retention Current Vdd = 1.2V, CS1 ≥ Vdd – 0.2V Com. — 0.5 2 µA
Ind. 4
Auto. 18
tsdr Data Retention Setup Time See Data Retention Waveform 0 — ns
trdr Recovery Time See Data Retention Waveform trC — ns
Note: 1. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
DATA RETENTION WAVEFORM (CS2 Controlled)
V
DD
CS1 ≥ V
DD -
0.2V
t
SDR
t
RDR
V
DR
CS1
GND
Data Retention Mode
V
DD
CS2 ≤ 0.2V
t
SDR
t
RDR
V
DR
CS2
GND
Data Retention Mode
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
ORDERING INFORMATION
IS62WV1288DALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
55 IS62WV1288DALL-55TI TSOP-I
IS62WV1288DALL-55TLI TSOP-I, Lead-free
IS62WV1288DALL-55HI sTSOP-I
IS62WV1288DALL-55HLI sTSOP-I, Lead-free
IS62WV1288DALL-55BI mini BGA (6mm x 8mm)
IS62WV1288DALL-55BLI mini BGA (6mm x 8mm), Lead-free
ORDERING INFORMATION
IS62WV1288DBLL (2.3V - 3.6V)
Industrial Range: –40°C to +85°C1
Speed (ns) Order Part No. Package
45 IS62WV1288DBLL-45TI TSOP-I
IS62WV1288DBLL-45TLI TSOP-I, Lead-free
IS62WV1288DBLL-45HI sTSOP-I
IS62WV1288DBLL-45HLI sTSOP-I, Lead-free
IS62WV1288DBLL-45QI SOP
IS62WV1288DBLL-45QLI SOP, Lead-free
IS62WV1288DBLL-45BI mini BGA (6mm x 8mm)
IS62WV1288DBLL-45BLI mini BGA (6mm x 8mm), Lead-free
Automotive Range: –40°C to +125°C
Speed (ns) Order Part No. Package
45 IS65WV1288DBLL-45TLA3 TSOP-I, Lead-free
IS65WV1288DBLL-45HLA3 sTSOP-I, Lead-free
IS65WV1288DBLL-45QLA3 SOP, Lead-free
Notes:
1. Speed = 35ns for temperature range of 0oC to +70oC or for Vdd = 3.3V ± 5%.
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. B
12/01/2010
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IS65WV1288DALL/DBLL
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. B
12/01/2010
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IS65WV1288DALL/DBLL
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
NOTE :
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
08/12/2008
Package Outline
