LTC6812-1
1
Rev. A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
15-Cell Battery Stack Monitor
with Daisy Chain Interface
The LTC
®
6812-1 is a multicell battery stack monitor that
measures up to 15 series connected battery cells with
a total measurement error of less than 2.2mV. The cell
measurement range of 0V to 5V makes the LTC6812-1
suitable for most battery chemistries. All 15 cells can be
measured in 245µs, and lower data acquisition rates can
be selected for high noise reduction.
Multiple LTC6812-1 devices can be connected in series,
permitting simultaneous cell monitoring of long, high
voltage battery strings. Each LTC6812-1 has an isoSPI
interface for high speed, RF immune, long distance com-
munications. Multiple devices are connected in a daisy
chain with one host processor connection for all devices.
This daisy chain can be operated bidirectionally, ensuring
communication integrity, even in the event of a fault along
the communication path.
The LTC6812-1 can be powered directly from the battery
stack or from an isolated supply. The LTC6812-1 includes
passive balancing for each cell, with individual PWM duty
cycle control for each cell. Other features include an on-
board 5V regulator, nine general purpose I/O lines and a
sleep mode, where current consumption is reduced to 6µA.
Cell 15 Measurement Error
vs Temperature
APPLICATIONS
n Measures Up to 15 Battery Cells in Series
n 2.2mV Maximum Total Measurement Error
n Stackable Architecture for High Voltage Systems
n Built-In isoSPI™ Interface
n 1Mb Isolated Serial Communications
n Uses a Single Twisted Pair, Up to 100 Meters
n Low EMI Susceptibility and Emissions
n Bidirectional for Broken Wire Protection
n 245µs to Measure All Cells in a System
n Synchronized Voltage and Current Measurement
n 16-Bit Delta-Sigma ADC with Programmable
3rdOrder Noise Filter
n Engineered for ISO 26262-Compliant Systems
n Passive Cell Balancing Up to 200mA (Max) with
Programmable Pulse-Width Modulation
n 9 General Purpose Digital I/O or Analog Inputs
n Temperature or Other Sensor Inputs
n Configurable as an I2C or SPI Master
n 6µA Sleep Mode Supply Current
n 64-Lead eLQFP Package
n AEC-Q100 Qualified for Automotive Applications
n Electric and Hybrid Electric Vehicles
n Backup Battery Systems
n Grid Energy Storage
n High Power Portable Equipment
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8908779, 9182428, 9270133.
+
+
68121 TA01a
LTC6812-1
ISOLATED
DATA WITH
WIRE BREAK
PROTECTION
+
+
•
•
•
CELL 15
CELL 14
CELL 2
CELL 1
15-Cell Monitor and Balance IC
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–2.0
–1.5
–1.0
–0.5
0.5
1.0
1.5
2.0
MEASUREMENT ERROR (mV)
68121 TA01b
LTC6812-1
2
Rev. A
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TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings .............................. 3
Order Information .......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics ................................. 4
Typical Performance Characteristics ................... 9
Pin Functions .............................................. 15
Block Diagram ............................................. 16
Improvements from the LTC6811-1 .................... 17
Operation................................................... 18
State Diagram ......................................................... 18
Core LTC6812-1 State Descriptions ........................ 18
isoSPI State Descriptions ....................................... 19
Power Consumption ............................................... 19
ADC Operation ........................................................ 20
Data Acquisition System Diagnostics .....................25
Watchdog and Discharge Timer ..............................32
Reset Behaviors ......................................................34
S Pin Pulse-Width Modulation for Cell Balancing ...35
Discharge Timer Monitor ........................................35
I2C/SPI Master on LTC6812-1 Using GPIOs ............36
S Pin Pulsing Using the S Pin Control Settings ......39
S Pin Muting ...........................................................41
Serial Interface Overview ........................................ 41
4-Wire Serial Peripheral Interface (SPI) Physical
Layer .......................................................................42
2-Wire Isolated Interface (isoSPI) Physical Layer ...42
Data Link Layer .......................................................52
Network Layer ........................................................52
Applications Information ................................ 69
Providing DC Power ................................................69
Internal Protection and Filtering ..............................70
Cell Balancing .........................................................73
Discharge Control During Cell Measurements ........ 74
Digital Communications ..........................................77
Enhanced Applications ............................................85
Reading External Temperature Probes ....................87
Package Description ..................................... 88
Revision History .......................................... 89
Typical Application .......................................90
Related Parts .............................................. 90
LTC6812-1
3
Rev. A
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Total Supply Voltage
V+ to V– ............................................................93.75V
Supply Voltage (Relative to C10)
V+ to C10...............................................................50V
Input Voltage (Relative to V–)
C0 ............................................................ –0.3V to 6V
C15 ........................ –0.3V to MIN (V+ + 5.5V, 93.75V)
C(n), S(n) .......................–0.3V to MIN (8 • n, 93.75V)
IPA, IMA, IPB, IMB ........... –0.3V to VREG + 0.3V, ≤ 6V
DRIVE ...................................................... –0.3V to 7V
All Other Pins ........................................... –0.3V to 6V
Voltage Between Inputs
C(n) to C(n–1), S(n) to C(n–1) .................. –0.3V to 8V
C13 to C10 ............................................. –0.3V to 21V
C8 to C5 ................................................. –0.3V to 21V
C3 to C0 ................................................. –0.3V to 21V
Current In/Out of Pins
All Pins Except VREG, IPA, IMA, IPB, IMB,
C(n), S(n) .............................................................. 10mA
IPA, IMA, IPB, IMB .............................................30mA
Specified Junction Temperature Range
LTC6812I-1 ..........................................–40°C to 85°C
LTC6812H-1 ....................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Device HBM ESD Classification Level 1C
Device CDM ESD Classification Level C5
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V+
NC
NC
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
NC
NC
C10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S10
C9
S9
C8
S8
C7
S7
C6
S6
NC
NC
C5
S5
C4
S4
C3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
IPB
IMB
SCK (IPA)*
CSB (IMA)*
V–
V–**
ICMP
IBIAS
WDT
ISOMD
SDO (NC)*
SDI (NC)*
DTEN
VREF1
VREF2
DRIVE
VREG
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
C0
S1
C1
S2
C2
S3
TOP VIEW
LWE PACKAGE
64-LEAD (10mm × 10mm) PLASTIC eLQFP
TJMAX = 150°C, θJA = 17°C/W, θJC = 2.5°C/W
EXPOSED PAD (PIN 65) IS V
–
, MUST BE SOLDERED TO PCB
65
V–
*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD:
ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IPA, IMA, NC, NC
**THIS PIN MUST BE CONNECTED TO V–
ORDER INFORMATION
AUTOMOTIVE PRODUCTS**
TRAY (160PC) TAPE AND REEL (1500PC) PART MARKING* PACKAGE DESCRIPTION MSL RATING
SPECIFIED JUNCTION
TEMPERATURE
RANGE
LTC6812ILWE-1#3ZZPBF LTC6812ILWE-1#3ZZTRPBF LTC6812LWE-1 64-Lead Plastic eLQFP 3 –40°C to 85°C
LTC6812HLWE-1#3ZZPBF LTC6812HLWE-1#3ZZTRPBF LTC6812LWE-1 64-Lead Plastic eLQFP 3 –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
LTC6812-1
4
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ADC DC Specifications
Measurement Resolution 0.1 mV/Bit
ADC Offset Voltage (Note 2) 0.1 mV
ADC Gain Error (Note 2) 0.01 %
Total Measurement Error (TME) in
Normal Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±0.2 mV
C(n) to C(n–1) = 2.0 ±1.6 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812Il±1.8 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812H l±2.0 mV
C(n) to C(n–1) = 3.3 ±2.2 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812Il±3.0 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812H l±3.3 mV
C(n) to C(n–1) = 4.2 ±2.8 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812Il±3.8 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812H l±4.2 mV
C(n) to C(n–1), GPIO(n) to V– = 5.0 ±1 mV
Sum of All Cells l±0.05 ±0.35 %
Internal Temperature, T = Maximum Specified
Temperature ±5 °C
VREG Pin l–1 –0.15 0 %
VREF2 Pin l–0.05 0.05 0.20 %
Digital Supply Voltage, VREGD l–0.5 0.5 1.5 %
Total Measurement Error (TME) in
Filtered Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±0.1 mV
C(n) to C(n–1) = 2.0 ±1.6 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812Il±1.8 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812H l±2.0 mV
C(n) to C(n–1) = 3.3 ±2.2 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812Il±3.0 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812H l±3.3 mV
C(n) to C(n–1) = 4.2 ±2.8 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812Il±3.8 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812H l±4.2 mV
C(n) to C(n–1), GPIO(n) to V– = 5.0 ±1 mV
Sum of All Cells l±0.05 ±0.35 %
Internal Temperature, T = Maximum Specified
Temperature ±5 °C
VREG Pin l–1 –0.15 0 %
VREF2 Pin l–0.05 0.05 0.20 %
Digital Supply Voltage, VREGD l–0.5 0.8 1.5 %
LTC6812-1
5
Rev. A
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Total Measurement Error (TME) in
FastMode C(n) to C(n–1), GPIO(n) to V– = 0 ±2 mV
C(n) to C(n–1), GPIO(n) to V– = 2.0 l±4 mV
C(n) to C(n–1), GPIO(n) to V– = 3.3 l±6 mV
C(n) to C(n–1), GPIO(n) to V– = 4.2 l±8.3 mV
C(n) to C(n–1), GPIO(n) to V– = 5.0 ±10 mV
Sum of All Cells l±0.15 ±0.5 %
Internal Temperature, T = Maximum Specified
Temperature ±5 °C
VREG Pin l–1.5 –0.15 1 %
VREF2 Pin l–0.18 0.05 0.32 %
Digital Supply Voltage, VREGD l–2.5 –0.4 2 %
Input Range C(n) n = 1 to 15 lC(n–1) C(n–1) + 5 V
C0 l0 1 V
GPIO(n) n = 1 to 9 l0 5 V
ILInput Leakage Current When Inputs Are
Not Being Measured C(n) n = 0 to 15 l10 ±250 nA
GPIO(n) n = 1 to 9 l10 ±250 nA
Input Current When Inputs Are Being
Measured (State: Core = MEASURE) C(n) n = 0 to 15 ±1 μA
GPIO(n) n = 1 to 9 ±1 μA
Input Current During Open Wire
Detection
l70 100 130 μA
Voltage Reference Specifications
VREF1 1st Reference Voltage VREF1 Pin, No Load l3.0 3.15 3.3 V
1st Reference Voltage TC VREF1 Pin, No Load 3 ppm/°C
1st Reference Voltage Thermal
Hysteresis VREF1 Pin, No Load 20 ppm
1st Reference Voltage Long Term Drift VREF1 Pin, No Load 20 ppm/√khr
VREF2 2nd Reference Voltage VREF2 Pin, No Load l2.993 3 3.007 V
VREF2 Pin, 5k Load to V–l2.992 3 3.008 V
2nd Reference Voltage TC VREF2 Pin, No Load 10 ppm/°C
2nd Reference Voltage Thermal
Hysteresis VREF2 Pin, No Load 100 ppm
2nd Reference Voltage Long Term Drift VREF2 Pin, No Load 60 ppm/√khr
General DC Specifications
IVP V+ Supply Current
(See Figure1: LTC6812-1 Operation
StateDiagram)
State: Core = SLEEP,
isoSPI = IDLE VREG = 0V 6.1 11 µA
VREG = 0V l6.1 18 µA
VREG = 5V 3 5 µA
VREG = 5V l3 9 µA
State: Core = STANDBY
l
9
614
14 22
28 µA
µA
State: Core = REFUP
l
0.4
0.375 0.55
0.55 0.8
0.825 mA
mA
State: Core = MEASURE
l
0.65
0.6 0.95
0.95 1.35
1.4 mA
mA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
LTC6812-1
6
Rev. A
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IREG(CORE) VREG Supply Current
(See Figure1: LTC6812-1 Operation
State Diagram)
State: Core = SLEEP,
isoSPI = IDLE VREG = 5V 3.1 6 µA
VREG = 5V l3.1 9 µA
State: Core = STANDBY
l
10
635
35 60
65 µA
µA
State: Core = REFUP
l
0.4
0.3 0.9
0.9 1.4
1.5 mA
mA
State: Core = MEASURE
l
14
13.5 15
15 16
16.5 mA
mA
IREG(isoSPI) Additional VREG Supply Current
if isoSPI in READY/ACTIVE States
Note: ACTIVE State Current
Assumes tCLK = 1µs, (Note 3)
ISOMD = 0,
RB1 + RB2 = 2k READY l3.6 4.5 5.2 mA
ACTIVE l5.6 6.8 8.1 mA
ISOMD = 1,
RB1 + RB2 = 2k READY l4.0 5.2 6.5 mA
ACTIVE l7.0 8.5 10.5 mA
ISOMD = 0,
RB1 + RB2 = 20k READY l1.0 1.8 2.4 mA
ACTIVE l1.3 2.3 3.3 mA
ISOMD = 1,
RB1 + RB2 = 20k READY l1.6 2.5 3.5 mA
ACTIVE l1.8 3.1 4.8 mA
V+ Supply Voltage TME Specifications Met l16 50 75 V
V+ to C15 Voltage TME Specifications Met l–0.3 V
V+ to C10 Voltage TME Specifications Met l40 V
C11 Voltage TME Specifications Met l2.5 V
C6 Voltage TME Specifications Met l1 V
VREG VREG Supply Voltage TME Supply Rejection < 1mV/V l4.5 5 5.5 V
DRIVE Output Voltage Sourcing 1µA
l
5.4
5.2 5.7
5.7 5.9
6.1 V
V
Sourcing 500µA l5.2 5.7 6.1 V
VREGD Digital Supply Voltage l2.7 3 3.6 V
Discharge Switch ON Resistance VCELL = 3.6V l4 10 Ω
Thermal Shutdown Temperature 150 °C
VOL(WDT) Watch Dog Timer Pin Low WDT Pin Sinking 4mA l0.4 V
VOL(GPIO) General Purpose I/O Pin Low GPIO Pin Sinking 4mA (Used as Digital Output) l0.4 V
ADC Timing Specifications
tCYCLE
(Figure3,
Figure4,
Figure6)
Measurement + Calibration Cycle Time
When Starting from the REFUP State in
Normal Mode
Measure 15 Cells l1692 1956 2077 µs
Measure 3 Cells l352 407 432 µs
Measure 15 Cells and 2 GPIO Inputs l2382 2753 2924 µs
Measurement + Calibration Cycle Time
When Starting from the REFUP State in
Filtered Mode
Measure 15 Cells l145.2 167.8 178.2 ms
Measure 3 Cells l29.1 33.6 35.7 ms
Measure 15 Cells and 2 GPIO Inputs l203.2 234.9 249.5 ms
Measurement + Calibration Cycle Time
When Starting from the REFUP State in
Fast Mode
Measure 15 Cells l811 937 996 µs
Measure 3 Cells l176 203 215 µs
Measure 15 Cells and 2 GPIO Inputs l1149 1328 1410 µs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
LTC6812-1
7
Rev. A
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSKEW1
(Figure6) Skew Time. The Time Difference
Between GPIO2 and Cell 1
Measurements, Command = ADCVAX
Fast Mode l168 194 206 µs
Normal Mode l470 543 577 µs
tSKEW2
(Figure3) Skew Time. The Time Difference
Between Cell 15 and Cell 1
Measurements, Command = ADCV
Fast Mode l162 187 198 µs
Normal Mode l464 536 569 µs
tSKEW3
(Figure6) Skew Time. The Time Difference
Between Cell 15 and GPIO1
Measurements, Command = ADCVAX
Fast Mode l127 147 156 µs
Normal Mode l354 409 434 µs
tWAKE Regulator Start-Up Time VREG Generated from DRIVE Pin (Figure32) l200 400 µs
tSLEEP
(Figure26) Watchdog or Discharge Timer DTEN Pin = 0 or DCTO[3:0] = 0000 l1.8 2 2.2 sec
DTEN Pin = 1 and DCTO[3:0] ≠ 0000 0.5 120 min
tREFUP
(Figure3
for
example)
Reference Wake-Up Time. Added to
tCYCLE Time When Starting from the
STANDBY State. tREFUP = 0 When
Starting from Other States.
tREFUP is Independent of the Number of
Channels Measured and the ADC Mode
l2.7 3.5 4.4 ms
fSADC Clock Frequency 3.3 MHz
SPI Interface DC Specifications
VIH(SPI) SPI Pin Digital Input Voltage High Pins CSB, SCK, SDI l2.3 V
VIL(SPI) SPI Pin Digital Input Voltage Low Pins CSB, SCK, SDI l0.8 V
VIH(CFG) Configuration Pin Digital Input Voltage High Pins ISOMD, DTEN, GPIO1 to GPIO9 l2.7 V
VIL(CFG) Configuration Pin Digital Input Voltage Low Pins ISOMD, DTEN, GPIO1 to GPIO9 l1.2 V
ILEAK(DIG) Digital Input Current Pins CSB, SCK, SDI, ISOMD, DTEN l±1 μA
VOL(SDO) Digital Output Low Pin SDO Sinking 1mA l0.3 V
isoSPI DC Specifications (See Figure17)
VBIAS Voltage on IBIAS Pin READY/ACTIVE State
IDLE State
l1.9 2.0
02.1 V
V
IBIsolated Interface Bias Current RBIAS = 2k to 20k l0.1 1.0 mA
AIB Isolated Interface Current Gain VA = ≤ 1.6V IB = 1mA
IB = 0.1mA
l
l
18
18 20
20 22
24.5 mA/mA
mA/mA
VATransmitter Pulse Amplitude VA = |VIP – VIM|l1.6 V
VICMP Threshold-Setting Voltage on ICMP Pin VTCMP = ATCMP • VICMP l0.2 1.5 V
ILEAK(ICMP) Input Leakage Current on ICMP Pin VICMP = 0V to VREG l±1 µA
ILEAK(IP/IM) Leakage Current on IP and IM Pins IDLE State, VIP or VIM, 0V to VREG l±1 µA
ATCMP Receiver Comparator Threshold
VoltageGain VCM = VREG/2 to VREG – 0.2V, VICMP = 0.2V to
1.5V
l0.4 0.5 0.6 V/V
VCM Receiver Common Mode Bias IP/IM Not Driving (VREG – VICMP/3 – 167mV) V
RIN Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB l26 35 45 kΩ
isoSPI Idle/Wake-Up Specifications (See Figure26)
VWAKE Differential Wake-Up Voltage tDWELL = 240ns l200 mV
tDWELL Dwell Time at VWAKE Before Wake
Detection VWAKE = 200mV l240 ns
tREADY Start-Up Time After Wake Detection l10 µs
tIDLE Idle Timeout Duration l4.3 5.5 6.7 ms
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
LTC6812-1
8
Rev. A
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
isoSPI Pulse Timing Specifications (See Figure22)
t1/2PW(CS) Chip-Select Half-Pulse Width Transmitter l120 150 180 ns
tFILT(CS) Chip-Select Signal Filter Receiver l70 90 110 ns
tINV(CS) Chip-Select Pulse Inversion Delay Transmitter l120 155 190 ns
tWNDW(CS) Chip-Select Valid Pulse Window Receiver l220 270 330 ns
t1/2PW(D) Data Half-Pulse Width Transmitter l40 50 60 ns
tFILT(D) Data Signal Filter Receiver l10 25 35 ns
tINV(D) Data Pulse Inversion Delay Transmitter l40 55 65 ns
tWNDW(D) Data Valid Pulse Window Receiver l70 90 110 ns
SPI Timing Requirements (See Figure16 and Figure25)
tCLK SCK Period (Note 4) l1 µs
t1SDI Setup Time before SCK Rising Edge l25 ns
t2SDI Hold Time after SCK Rising Edge l25 ns
t3SCK Low tCLK = t3 + t4 ≥ 1µs l200 ns
t4SCK High tCLK = t3 + t4 ≥ 1µs l200 ns
t5CSB Rising Edge to CSB Falling Edge l0.65 µs
t6SCK Rising Edge to CSB Rising Edge (Note 4) l0.8 µs
t7CSB Falling Edge to SCK Rising Edge (Note 4) l1 µs
isoSPI Timing Specifications (See Figure25)
t8SCK Falling Edge to SDO Valid (Note 5) l60 ns
t9SCK Rising Edge to Short ±1 Transmit l50 ns
t10 CSB Transition to Long ±1 Transmit l60 ns
t11 CSB Rising Edge to SDO Rising (Note 5) l200 ns
tRTN Data Return Delay l325 375 425 ns
tDSY(CS) Chip-Select Daisy-Chain Delay l120 180 ns
tDSY(D) Data Daisy-Chain Delay l200 250 300 ns
tLAG Data Daisy-Chain Lag (vs Chip-Select) = [tDSY(D) + t1/2PW(D)] – [tDSY(CS) + t1/2PW(CS)]l0 35 70 ns
t5(GOV) Chip-Select High-to-Low Pulse
Governor
l0.6 0.82 µs
t6(GOV) Data to Chip-Select Pulse Governor l0.8 1.05 µs
tBLOCK isoSPI Port Reversal Blocking Window l2 10 µs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The ADC specifications are guaranteed by the Total Measurement
Error specification.
Note 3: The ACTIVE state current is calculated from DC measurements.
The ACTIVE state current is the additional average supply current into
VREG when there is continuous 1MHz communications on the isoSPI ports
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply
current. See Applications Information section for additional details.
Note 4: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 5: These specifications do not include rise or fall time of SDO. While
fall time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time tRISE is dependent on the pull-up
resistance and load capacitance on the SDO pin. The time constant must
be chosen such that SDO meets the setup time requirements of the MCU.
LTC6812-1
9
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Measurement Error vs
Temperature
TA = 25°C, unless otherwise noted.
Measurement Error
vs Input, Normal Mode
Measurement Error
vs Input, Filtered Mode
Measurement Error vs Input,
Fast Mode
Measurement Noise
vs Input, Normal Mode
Measurement Noise
vs Input, Filtered Mode
Measurement Noise
vs Input, Fast Mode
Measurement Gain Error
Thermal Hysteresis, Hot
Measurement Gain Error
Thermal Hysteresis, Cold
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS, CELL 1
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
MEASUREMENT ERROR (mV)
68121 G01
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
INPUT (V)
0
1
2
3
4
5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
MEASUREMENT ERROR (mV)
68121 G02
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
INPUT (V)
0
1
2
3
4
5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
MEASUREMENT ERROR (mV)
68121 G03
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
INPUT (V)
0
1
2
3
4
5
–10
–8
–6
–4
–2
0
2
4
6
8
10
MEASUREMENT ERROR (mV)
68121 G04
INPUT (V)
0
1
2
3
4
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PEAK NOISE (mV)
68121 G05
INPUT (V)
0
1
2
3
4
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PEAK NOISE (mV)
68121 G06
INPUT (V)
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
PEAK NOISE (mV)
68121 G07
T
A
= 85°C to 25°C
CHANGE IN GAIN ERROR (ppm)
–50
–30
–10
10
30
50
0
5
10
15
20
25
NUMBER OF PARTS
68121 G8
T
A
= –40°C to 25°C
CHANGE IN GAIN ERROR (ppm)
–75
–50
–25
0
25
50
75
0
5
10
15
20
25
NUMBER OF PARTS
68121 G9
LTC6812-1
10
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Noise Filter Response Measurement Error vs VREG
Measurement Error vs V+Top Cell Measurement Error vs V+Measurement Error
vs Common Mode Voltage
Measurement Error Due to a
VREG AC Disturbance
Measurement Error Due to a
V+ AC Disturbance
Measurement Error CMRR
vs Frequency
Measurement Error Due to
IR Reflow
CHANGE IN GAIN ERROR (ppm)
–50
–25
0
25
50
75
100
125
150
175
200
0
1
2
3
4
5
6
7
NUMBER OF PARTS
68121 G10
INPUT FREQUENCY (Hz)
10
100
1k
10k
100k
1M
–70
–60
–50
–40
–30
–20
–10
0
NOISE REJECTION (dB)
68121 G11
26Hz
422Hz
1kHz
2kHz
3kHz
7kHz
14kHz
27kHz
V
IN
= 2V
V
IN
= 3.3V
V
IN
= 4.2 V
V
REG
(V)
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
MEASUREMENT ERROR (mV)
68121 G12
MEASUREMENT ERROR OF
CELL1 WITH 3.3V INPUT
V
REG
GENERATED FROM
DRIVE PIN, FIGURE 32
V
+
(V)
0
10
20
30
40
50
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
MEASUREMENT ERROR (mV)
68121 G13
C15–C14 = 3.3V
C15 = 49.5V
V
+
(V)
46.5
47.5
48.5
49.5
50.5
51.5
52.5
53.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
TOP CELL MEASUREMENT ERROR (mV)
68121 G14
C15 – C14 = 3.3V
V
+
= 53.3V
C14 VOLTAGE (V)
20
25
30
35
40
45
50
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
CELL15 MEASUREMENT ERROR (mV)
68121 G15
V
REG(DC)
= 5V
V
REG(AC)
= 0.5V
p–p
1BIT CHANGE
< –70dB
FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
68121 G16
V
+
DC
= 49.5V
V
+
AC
= 5V
p–p
1BIT CHANGE
< –90dB
V
REG
GENERATED FROM
DRIVE PIN, FIGURE 32
FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
68121 G17
V
CM(IN)
= 5V
p–p
NORMAL MODE CONVERSIONS
FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
REJECTION (dB)
68121 G18
LTC6812-1
11
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Cell Measurement Error Range
vs Input RC Values
GPIO Measurement Error
vs Input RC Values
Measurement Time
vs Temperature
Sleep Supply Current vs V+Standby Supply Current vs V+REFUP Supply Current vs V+
Measure Supply Current vs V+VREF1 vs Temperature VREF2 vs Temperature
68121 G19
100nF
10nF
1µF
INPUT RESISTANCE, R (Ω)
100
1k
10k
–15
–10
–5
0
5
CELL MEASUREMENT ERROR (mV)
TIME BETWEEN MEASUREMENTS > 3RC
C = 1nF
C = 10nF
C = 100nF
C = 1µF
C = 10µF
INPUT RESISTANCE, R (Ω)
1
10
100
1k
10k
–20
–16
–12
–8
–4
0
4
8
12
16
20
GPIO MEASUREMENT ERROR (mV)
68121 G20
15 CELL NORMAL MODE CONVERSIONS
V
REG
=4.5V
V
REG
=5V
V
REG
=5.5V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
MEASUREMENT TIME (ms)
68121 G21
SLEEP SUPPLY CURRENT =
V
+
CURRENT + V
REG
CURRENT
125°C
85°C
25°C
0°C
–40°C
V
+
(V)
5
15
25
35
45
55
65
75
3
4
5
6
7
8
9
10
SLEEP SUPPLY CURRENT (µA)
68121 G22
STANDBY SUPPLY CURRENT =
V
+
CURRENT + V
REG
CURRENT
125°C
85°C
25°C
0°C
–40°C
V
+
(V)
5
15
25
35
45
55
65
75
20
30
40
50
60
70
80
STANDBY SUPPLY CURRENT (µA)
68121 G23
REFUP SUPPLY CURRENT =
V
+
CURRENT + V
REG
CURRENT
125°C
85°C
25°C
0°C
–40°C
V
+
(V)
5
15
25
35
45
55
65
75
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
REFUP SUPPLY CURRENT (mA)
68121 G24
MEASURE SUPPLY CURRENT =
V
+
CURRENT + V
REG
CURRENT
125°C
85°C
25°C
0°C
–40°C
V
+
(V)
5
15
25
35
45
55
65
75
14.5
15.0
15.5
16.0
16.5
17.0
17.5
MEASURE SUPPLY CURRENT (mA)
68121 G25
5 TYPICAL UNITS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
3.130
3.135
3.140
3.145
3.150
3.155
3.160
3.165
3.170
V
REF1
(V)
68121 G26
5 TYPICAL UNITS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
2.995
2.996
2.997
2.998
2.999
3.000
3.001
3.002
3.003
3.004
3.005
V
REF2
(V)
68121 G27
LTC6812-1
12
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
VREF2 VREG Line Regulation VREF2 V+ Line Regulation VREF2 Load Regulation
VREF2 Thermal Hysteresis, Hot VREF2 Thermal Hysteresis, Cold VREF2 Change Due to IR Reflow
VDRIVE vs Temperature VDRIVE V+ Line Regulation VDRIVE Load Regulation
I
L
= 0.6mA
125°C
85°C
25°C
–40°C
V
REG
(V)
4.5
4.75
5
5.25
5.5
–400
–320
–240
–160
–80
0
80
160
240
320
400
CHANGE IN V
REF2
(ppm)
68121 G28
V
REG
GENERATED FROM
DRIVE PIN, FIGURE 32
125°C
85°C
25°C
–40°C
V
+
(V)
15
25
35
45
55
65
75
85
95
–100
–80
–60
–40
–20
0
20
40
60
80
100
CHANGE IN V
REF2
(ppm)
68121 G29
V
+
= 49.5V
V
REG
= 5V
125°C
85°C
25°C
–40°C
I
OUT
(mA)
0.01
0.1
1
10
–1000
–800
–600
–400
–200
0
200
CHANGE IN V
REF2
(ppm)
68121 G30
T
A
= 85°C to 25°C
CHANGE IN V
REF2
(ppm)
–125
–100
–75
–50
–25
0
25
50
75
100
125
0
5
10
15
NUMBER OF PARTS
68121 G31
T
A
= –40°C to 25°C
CHANGE IN V
REF2
(ppm)
–75
–50
–25
0
25
50
75
100
0
5
10
15
NUMBER OF PARTS
68121 G32
CHANGE IN V
REF2
(ppm)
–300
–200
–100
0
100
200
300
0
1
2
3
4
5
NUMBER OF PARTS
68121 G33
5 TYPICAL UNITS
NO LOAD
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
5.4
5.5
5.6
5.7
5.8
5.9
V
DRIVE
(V)
68121 G34
125°C
85°C
25°C
0°C
–40°C
V
+
(V)
15
30
45
60
75
–10
–5
0
5
10
15
20
25
CHANGE IN V
DRIVE
(mV)
68121 G35
V
+
= 49.5V
125°C
85°C
25°C
0°C
–40°C
I
OUT
(mA)
0.01
0.1
1
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
CHANGE IN V
DRIVE
(mV)
68121 G36
LTC6812-1
13
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Discharge Switch On-Resistance
vs Cell Voltage
Internal Die Temperature
Increase vs Discharge Current
Internal Die Temperature
Measurement Error vs
Temperature
VREF1 and VREF2 Power-Up VREG and VDRIVE Power-Up
isoSPI Current (READY)
vs Temperature
isoSPI Current (ACTIVE)
vs isoSPI Clock Frequency IBIAS Voltage vs Temperature IBIAS Voltage Load Regulation
ON–RESISTANCE OF INTERNAL
DISCHARGE SWITCH MEASURED
BETWEEN S(n) AND C(n–1)
125°C
85°C
25°C
–40°C
CELL VOLTAGE (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
2
4
6
8
10
12
14
16
18
20
DISCHARGE SWITCH ON–RESISTANCE (Ω)
68121 G37
1 CELL DISCHARGING
6 CELL DISCHARGING
12 CELL DISCHARGING
15 CELL DISCHARGING
INTERNAL DISCHARGE CURRENT (mA/CELL)
0
25
50
75
100
125
150
175
200
0
5
10
15
20
25
30
35
40
45
50
INCREASE IN DIE TEMPERATURE (°C)
68121 G38
5 TYPICAL UNITS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–10
–8
–6
–4
–2
0
2
4
6
8
10
TEMPERATURE MEASUREMENT ERROR (°C)
68121 G39
V
REF1
: C
L
= 1µF
V
REF2
: C
L
= 1µF, R
L
= 5kΩ
V
REF1
V
REF2
CS
500µs/DIV
V
REF1
1V/DIV
V
REF2
1V/DIV
CS
5V/DIV
68121 G40
V
REG
: C
L
= 1µF
V
REG
GENERATED FROM
DRIVE PIN
V
REG
V
DRIVE
CS
50µs/DIV
V
DRIVE
2V/DIV
V
REG
2V/DIV
CS
5V/DIV
68121 G41
I
B
= 1mA
ISOMD = V –
ISOMD = VREG
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
3.5
4.0
4.5
5.0
5.5
6.0
isoSPI CURRENT (mA)
68121 G42
ISOMD = V
REG
I
B
= 1mA
WRITE
READ
isoSPI CLOCK FREQUENCY (kHz)
0
200
400
600
800
1000
2
3
4
5
6
7
8
9
isoSPI CURRENT (mA)
68121 G43
I
B
= 1mA
3 PARTS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1.98
1.99
2.00
2.01
2.02
IBIAS PIN VOLTAGE (V)
68121 G44
IBIAS CURRENT, I
B
(µA)
0
200
400
600
800
1000
1.990
1.995
2.000
2.005
2.010
IBIAS PIN VOLTAGE (V)
68121 G45
LTC6812-1
14
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
isoSPI Driver Current Gain
(Port A/Port B) vs IBIAS Current
isoSPI Driver Current Gain
(Port A/Port B) vs Temperature
isoSPI Comparator Threshold
Gain (Port A/Port B)
vs ICMP Voltage
isoSPI Driver Common Mode
Voltage (Port A/Port B)
vs Pulse Amplitude
isoSPI Comparator Threshold
Gain (Port A/Port B)
vs Temperature
isoSPI Comparator Threshold
Gain (Port A/Port B) vs Receiver
Common Mode
Typical Wake-Up Pulse Amplitude
(Port A/Port B) vs Dwell Time
V
A
= 1.6V
V
A
= 1V
V
A
= 0.5V
IBIAS CURRENT, I
B
(µA)
0
200
400
600
800
1000
18
19
20
21
22
23
CURRENT GAIN, A
IB
(mA)
68121 G46
I
B
= 100uA
I
B
= 1mA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
18
19
20
21
22
23
CURRENT GAIN, A
IB
(mA/mA)
68121 G47
I
B
= 100uA
I
B
= 1mA
PULSE AMPLITUDE, V
A
(V)
0
0.5
1
1.5
2
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DRIVER COMMON MODE (V)
68121 G48
V
ICMP
= 0.2V
V
ICMP
= 1V
RECEIVER COMMON MODE, V
CM
(V)
2.5
3
3.5
4
4.5
5
5.5
0.44
0.46
0.48
0.50
0.52
0.54
0.56
COMPARATOR THRESHOLD GAIN, A
TCMP
(V/V)
68121 G49
3 PARTS
ICMP VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0.44
0.46
0.48
0.50
0.52
0.54
0.56
COMPARATOR THRESHOLD GAIN, A
TCMP
(V/V)
68121 G50
V
ICMP
= 0.2V
V
ICMP
= 1V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.44
0.46
0.48
0.50
0.52
0.54
0.56
COMPARATOR THRESHOLD GAIN, A
TCMP
(V/V)
68121 G51
GUARANTEED
WAKE–UP REGION
WAKE–UP DWELL TIME, T
DWELL
(ns)
0
100
200
300
400
500
600
0
50
100
150
200
250
300
WAKE–UP PULSE AMPLITUDE, V
WAKE
(mV)
68121 G52
LTC6812-1
15
Rev. A
For more information www.analog.com
PIN FUNCTIONS
C0 to C15: Cell Inputs.
S1 to S15: Balance Inputs/Outputs. 15 internal N-MOSFETs
are connected between S(n) and C(n–1) for discharging
cells.
V+: Positive Supply Pin.
V–: Negative Supply Pins. The V– pins must be shorted
together, external to the IC.
VREF2: Buffered 2nd Reference Voltage for Driving Multiple
10k Thermistors. Bypass with an external 1μF capacitor.
VREF1: ADC Reference Voltage. Bypass with an external
1μF capacitor. No DC loads allowed.
GPIO[1:9]: General Purpose I/O. Can be used as digital
inputs or digital outputs, or as analog inputs with a mea-
surement range from V– to 5V. GPIO[3:5] can be used as
an I2C or SPI port.
DTEN: Discharge Timer Enable. Connect this pin to VREG
to enable the Discharge Timer.
DRIVE: Connect the base of an NPN to this pin. Connect
the collector to V+ and the emitter to VREG.
VREG: 5V Regulator Input. Bypass with an external 1μF
capacitor.
ISOMD: Serial Interface Mode. Connecting ISOMD to VREG
configures pins 53, 54, 61 and 62 of the LTC6812-1 for
2-wire isolated interface (isoSPI) mode. Connecting ISOMD
to V– configures the LTC6812-1 for 4-wire SPI mode.
WDT: Watchdog Timer Output Pin. This is an open drain
NMOS digital output. It can be left unconnected or con-
nected with a 1M resistor to VREG. If the LTC6812-1
does not receive a valid command within 2 seconds, the
watchdog timer circuit will reset the LTC6812-1 and the
WDT pin will go high impedance.
Serial Port Pins
ISOMD = VREG ISOMD = V–
PORT B
(Pins 57, 58, 63 and 64) IPB IPB
IMB IMB
ICMP ICMP
IBIAS IBIAS
PORT A
(Pins 53, 54, 61 and 62) (NC) SDO
(NC) SDI
IPA SCK
IMA CSB
CSB, SCK, SDI, SDO: 4-Wire Serial Peripheral Inter-
face (SPI). Active low chip select (CSB), serial clock
(SCK) and serial data in (SDI) are digital inputs. Serial
data out(SDO) is an open drain NMOS output pin. SDO
requires a 5k pull-up resistor.
IPA, IMA: Isolated 2-Wire Serial Interface Port A. IPA(plus)
and IMA (minus) are a differential input/output pair.
IPB, IMB: Isolated 2-Wire Serial Interface Port B. IPB(plus)
and IMB (minus) are a differential input/output pair.
IBIAS: Isolated Interface Current Bias. Tie IBIAS toV–
through a resistor divider to set the interface output
current level. When the isoSPI interface is enabled, the
IBIAS pin voltage is 2V. The IPA/IMA or IPB/IMB output
current drive is set to 20 times the current, IB, sourced
from the IBIAS pin.
ICMP: Isolated Interface Comparator Voltage Threshold
Set. Tie this pin to the resistor divider between IBIAS
and V– to set the voltage threshold of the isoSPI receiver
comparators. The comparator thresholds are set to half
the voltage on the ICMP pin.
NC: All pins identified with “NC” must be left unconnected.
Exposed Pad: V–. The Exposed Pad must be soldered to
PCB.
LTC6812-1
16
Rev. A
For more information www.analog.com
BLOCK DIAGRAM
VREG
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
C0
S1
C1
S2
C2
S3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IMBIPB SCK
(IPA)
CSB
(IMA)
V–V–ICMP
VREF1 VREGD POR VREG
IBIAS WDT ISOMD SDO
(NC) SDI
(NC) DTEN VREF1 VREF2 DRIVE
V+
NC
NC
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
NC
NC
C10
C9S10 S9 C8 S8 C7 S7 C6 S6 NC NC C5 S5 C4 S4 C3
C15
C14
C13
C12
C11
C6
C10
C9
C8
C7
–
+
P
M
DIGITAL
FILTERS
SERIAL
PORT B
5-CELL
MUX
P
M
AUX
MUX
P
M
6-CELL
MUX
IPB
IMB
ICMP
IBIAS
SCK (IPA)
CSB (IMA)
SDO (NC)
SDI (NC)
SERIAL
PORT A
GPIO AND
I2C
DIE
TEMPERATURE
WATCH DOG
TIMER
DISCHARGE
TIMER
2ND
REFERENCE
ADC3
C5
C4
C3
C2
C1
C0
–
+
P
M
6-CELL
MUX
ADC1
–
+
ADC2
16
16
16
15 BALANCE FETs
S(n)
C(n–1)
GPIO[9:1]
VREF2
REGULATORS
DRIVE
V+
VREGD
V+
POR
LDO2
LDO1
VREF2
WDT ISOMD
SC
TEMP
VREG
VREGD
SC
C15
C0
TEMP
DTEN
WDT
LOGIC
AND
MEMORY
1ST
REFERENCE VREF1
68121 BD
LTC6812-1
17
Rev. A
For more information www.analog.com
The LTC6812-1 is an evolution of the LTC6811-1 design. The following table summarizes the feature changes and
additions in the LTC6812-1.
ADDITIONAL LTC6812-1 FEATURES BENEFITS RELEVANT DATA SHEET SECTION(S)
The LTC6812-1 Has 3 ADCs Operating
Simultaneously vs 2 ADCs on LTC6811-1 3 Cells Can Be Measured During Each
ConversionCycle
ADC Operation
In Addition to the 3 ADC Digital Filters, There Is a
4th Filter Which Is Used for Redundancy Checks That All Digital Filters are Free of Faults ADC Conversion with Digital Redundancy for a
description and PS[1:0] bits in Table 10
Measure Cell 6 with ADC1 and ADC2
Simultaneously and then Measure Cell 11 with
ADC2 and ADC3 Simultaneously Using the
ADOLCommand
Checks That ADC2 Is as Accurate as ADC1 and
Also Checks That ADC3 Is as Accurate as ADC2
Overlap Cell Measurement (ADOL Command)
A Monitoring Feature Can Be Enabled During
the Discharge Timer. The Cell Balancing Can Be
Automatically Terminated When Cell Voltages
Reach a Programmable Undervoltage Threshold
Improved Cell Balancing Discharge Timer Monitor
The Internal Discharge MOSFETs Can Provide
200mA of Balancing Current (80mA if the die
temperature is over 95°C). The Balancing Current
Is Independent of Cell Voltage
Faster Cell Balancing, Especially for Low Cell
Voltages
Cell Balancing with Internal MOSFETs
The C0 Pin Voltage Is Allowed to Range Between
0V and 1V Without Affecting Total Measurement
Error (TME)
C0 Does Not Have to Connect Directly to V–Input Range in Electrical Characteristics
The MUTE and UNMUTE Commands Allow the
Host to Turn Off/On the Discharge Pins (S Pins)
Without Overwriting Register Values
Greater Control of Timing Between S Pins
Turning Off and Cell Measurements
S Pin Muting
Auxiliary Measurements Have an Open-Wire
Diagnostic Feature Improved Fault Detection Auxiliary Open Wire Check (AXOW Command)
Four Additional GPIO Pins Have Been Added for a
Total of Nine Increased Number of Temperature or Other
Sensors That Can Be Measured
Auxiliary (GPIO) Measurements (ADAX
Command) and Auxiliary Open Wire Check
(AXOW Command)
A Daisy Chain of LTC6812-1s Can Operate in Both
Directions (Both Ports Can Be Master or Slave) Redundant Communication Path Reversible isoSPI
IMPROVEMENTS FROM THE LTC6811-1
LTC6812-1
18
Rev. A
For more information www.analog.com
OPERATION
STATE DIAGRAM
The operation of the LTC6812-1 is divided into two sepa-
rate sections: the Core circuit and the isoSPI circuit. Both
sections have an independent set of operating states, as
well as a shutdown timeout.
CORE LTC6812-1 STATE DESCRIPTIONS
SLEEP State
The references and ADCs are powered down. The watch-
dog timer (see Watchdog and Discharge Timer) has timed
out. The discharge timer is either disabled or timed out.
The supply currents are reduced to minimum levels. The
isoSPI ports will be in the IDLE state. The DRIVE pin is
0V. All state machines are reset to their default states.
If a WAKEUP signal is received (see Waking Up the Serial
Interface), the LTC6812-1 will enter the STANDBY state.
STANDBY State
The references and the ADCs are off. The watchdog timer
and/or the discharge timer is running. The DRIVE pin
powers the VREG pin to 5V through an external transistor.
(Alternatively, VREG can be powered by an external supply).
When a valid ADC command is received or the REFON bit
is set to 1 in Configuration Register Group A, the IC pauses
for tREFUP to allow for the references to power up and then
enters either the REFUP or MEASURE state. Otherwise, if
no valid commands are received for tSLEEP, the IC returns
to the SLEEP state if DTEN = 0 or enters the EXTENDED
BALANCING state if DTEN = 1.
REFUP State
To reach this state, the REFON bit in Configuration Register
Group A must be set to 1 (using the WRCFGA command,
see Table 36). The ADCs are off. The references are powered
up so that the LTC6812-1 can initiate ADC conversions
more quickly than from the STANDBY state.
When a valid ADC command is received, the IC goes to
the MEASURE state to begin the conversion. Otherwise,
the LTC6812-1 will return to the STANDBY state when
the REFON bit is set to 0 (using WRCFGA command). If
no valid commands are received for tSLEEP, the IC returns
to the SLEEP state if DTEN = 0 or enters the EXTENDED
BALANCING state if DTEN = 1.
MEASURE State
The LTC6812-1 performs ADC conversions in this state.
The references and ADCs are powered up.
After ADC conversions are complete, the LTC6812-1 will
transition to either the REFUP or STANDBY state, depending
on the REFON bit. Additional ADC conversions can be initi-
ated more quickly by setting REFON = 1 to take advantage
of the REFUP state.
68121 F01
isoSPI PORT
WAKEUP SIGNAL
(CORE = STANDBY)
(tREADY)
WAKEUP SIGNAL
(CORE = SLEEP)
(tWAKE)
TRANSMIT/RECEIVE
NOTE: STATE TRANSITION
DELAYS DENOTED BY (tX)
NO ACTIVITY ON
isoSPI PORT
IDLE TIMEOUT
(tIDLE)
ACTIVE
READY
IDLE
CORE LTC6812-1
CONV DONE
(REFON = 1)
CONV DONE
(REFON = 0)
ADC
COMMAND
WAKEUP
SIGNAL
(tWAKE)
ADC
COMM
(tREFUP)
REFON = 1
(tREFUP)
REFON = 0 WAKEUP SIGNAL
(tWAKE)
WAKEUP
SIGNAL
(tWAKE)CONV
DONE
DCTO REACHES 0
WD TIMEOUT
AND DTEN=0
(tSLEEP)
WD TIMEOUT
AND DTEN=1
EVERY 30s
AND DTM=1
WD TIMEOUT
AND DTEN=1
WD TIMEOUT
AND DTEN=0
(tSLEEP)STANDBY
REFUP
EXTENDED
BALANCING
MEASURE DTM
MEASURE
SLEEP
Figure1. LTC6812-1 Operation State Diagram
LTC6812-1
19
Rev. A
For more information www.analog.com
Note: Non-ADC commands do not cause a Core state tran-
sition. Only an ADC Conversion or diagnostic commands
will place the Core in the MEASURE state.
EXTENDED BALANCING State
The watchdog timer has timed out, but the discharge timer
has not yet timed out (DTEN = 1). Discharge by PWM may
be in progress. If the Discharge Timer Monitor is enabled
then the LTC6812-1 will transition to the DTM MEASURE
state every 30 seconds to measure the cell voltages. If a
WAKEUP signal is received, the LTC6812-1 will transition
from EXTENDED BALANCING state to STANDBY state.
Discharge Timer Monitor MEASURE State
The watchdog timer has timed out but background monitor-
ing has been enabled (DTMEN =1 in Configuration Reg-
ister Group B). The LTC6812-1 enters this state from the
EXTENDED BALANCING state once every 30 seconds to
measure the cell voltages. The LTC6812-1 is in the highest
core power state and an A/D conversion is in progress. If a
WAKEUP signal is received, the LTC6812-1 will transition
from DTM MEASURE state to STANDBY state.
isoSPI STATE DESCRIPTIONS
Note: The LTC6812-1 has two isoSPI ports (A and B), for
daisy-chain communication.
IDLE State
The isoSPI ports are powered down.
When isoSPI Port A or Port B receives a WAKEUP signal
(see Waking Up the Serial Interface), the isoSPI enters
the READY state. This transition happens quickly (within
tREADY) if the Core is in the STANDBY state. If the Core is
in the SLEEP state when the isoSPI receives a WAKEUP
signal, then it transitions to the READY state within tWAKE.
READY State
The isoSPI port(s) are ready for communication. The serial
interface current in this state depends on the status of the
ISOMD pin and RBIAS = RB1 + RB2 (the external resistors
tied to the IBIAS pin).
OPERATION
If there is no activity (i.e., no WAKEUP signal) on Port A
or Port B for greater than tIDLE, the LTC6812-1 goes to
the IDLE state. When the serial interface is transmitting or
receiving data, the LTC6812-1 goes to the ACTIVE state.
ACTIVE State
The LTC6812-1 is transmitting/receiving data using one
or both of the isoSPI ports. The serial interface con-
sumes maximum power in this state. The supply current
increases with clock frequency as the density of isoSPI
pulses increases.
POWER CONSUMPTION
The LTC6812-1 is powered via two pins: V+ and VREG.
The V+ input requires voltage greater than or equal to
the top cell voltage minus 0.3V, and it provides power to
the high voltage elements of the Core circuits. The VREG
input requires 5V and provides power to the remaining
Core circuits and the isoSPI circuitry. The VREG input can
be powered through an external transistor, driven by the
regulated DRIVE output pin. Alternatively, VREG can be
powered by an external supply.
The power consumption varies according to the operational
states. Table 1 and Table 2 provide equations to approximate
the supply pin currents in each state. The V+ pin current
depends only on the Core state. However, the VREG pin
current depends on both the Core state and isoSPI state,
and can, therefore, be divided into two components. The
isoSPI interface draws current only from the VREG pin.
IREG = IREG(CORE) + IREG(isoSPI)
In the SLEEP state, the VREG pin will draw approximately
3.1μA if powered by an external supply. Otherwise, the
V+ pin will supply the necessary current.
Table 1. Core Supply Current
STATE IVP IREG(CORE)
SLEEP VREG = 0V 6.1µA 0µA
VREG = 5V 3µA 3.1µA
STANDBY 14µA 35µA
REFUP 550µA 900µA
MEASURE 950µA 15mA
LTC6812-1
20
Rev. A
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Table 2. isoSPI Supply Current Equations
isoSPI
STATE
ISOMD
CONNECTION IREG(isoSPI)
IDLE N/A 0mA
READY VREG 2.2mA + 3 • IB
V–1.5mA + 3 • IB
ACTIVE
VREG
Write: 2.5mA +3+20 • 100ns
tCLK
⎛
⎝
⎜⎞
⎠
⎟•IB
Read: 2.5mA +3+20 • 100ns • 1.5
tCLK
⎛
⎝
⎜⎞
⎠
⎟•IB
V–
1.8mA +3+20 • 100ns
t
CLK
⎛
⎝
⎜⎞
⎠
⎟•IB
ADC OPERATION
There are three ADCs inside the LTC6812-1. The three ADCs
operate simultaneously when measuring fifteen cells. Only
one ADC is used to measure the general purpose inputs.
The following discussion uses the term ADC to refer to one
or all ADCs, depending on the operation being performed.
The following discussion will refer to ADC1, ADC2 and
ADC3 when it is necessary to distinguish between the
three circuits, in timing diagrams, for example.
ADC Modes
The ADCOPT bit (CFGAR0[0]) in Configuration Register
Group A and the mode selection bits MD[1:0] in the conver-
sion command together provide eight modes of operation
for the ADC which correspond to different oversampling
ratios (OSR). The accuracy and timing of these modes
are summarized in Table 3. In each mode, the ADC first
measures the inputs, and then performs a calibration of
each channel. The names of the modes are based on the
–3dB bandwidth of the ADC measurement.
Mode 7kHz (Normal): In this mode, the ADC has high
resolution and low TME (Total Measurement Error). This
is considered the normal operating mode because of the
optimum combination of speed and accuracy.
Mode 27kHz (Fast): In this mode, the ADC has maximum
throughput but has some increase in TME (Total Measure-
ment Error). So this mode is also referred to as the fast
OPERATION
mode. The increase in speed comes from a reduction in
the oversampling ratio. This results in an increase in noise
and average measurement error.
Mode 26Hz (Filtered): In this mode, the ADC digital filter
–3dB frequency is lowered to 26Hz by increasing the OSR.
This mode is also referred to as the filtered mode due to
its low –3dB frequency. The accuracy is similar to the 7kHz
(Normal) mode with lower noise.
Modes 14kHz, 3kHz, 2kHz, 1kHz and 422Hz: Modes 14kHz,
3kHz, 2kHz, 1kHz and 422Hz provide additional options to
set the ADC digital filter –3dB at 13.5kHz, 3.4kHz, 1.7kHz,
845Hz and 422Hz, respectively. The accuracy of the 14kHz
mode is similar to the 27kHz (Fast) mode. The accuracy
of 3kHz, 2kHz, 1kHz and 422Hz modes is similar to the
7kHz (Normal) mode.
The filter bandwidths and the conversion times for these
modes are provided in Table 3 and Table 5. If the Core is
in STANDBY state, an additional tREFUP time is required to
power up the reference before beginning the ADC conver-
sions. The reference can remain powered up between ADC
conversions if the REFON bit in Configuration Register
Group A is set to 1 so the Core is in REFUP state after a
delay tREFUP. Then, the subsequent ADC commands will not
have the tREFUP delay before beginning ADC conversions.
Table 3. ADC Filter Bandwidth and Accuracy
MODE
–3dB
FILTER
BW
–40dB
FILTER
BW
TME SPEC
AT 3.3V,
25°C
TME SPEC
AT 3.3V,
–40°C, 125°C
27kHz
(Fast Mode) 27kHz 84kHz ±6mV ±6mV
14kHz 13.5kHz 42kHz ±6mV ±6mV
7kHz
(Normal Mode) 6.8kHz 21kHz ±2.2mV ±3.3mV
3kHz 3.4kHz 10.5kHz ±2.2mV ±3.3mV
2kHz 1.7kHz 5.3kHz ±2.2mV ±3.3mV
1kHz 845Hz 2.6kHz ±2.2mV ±3.3mV
422Hz 422Hz 1.3kHz ±2.2mV ±3.3mV
26Hz
(Filtered Mode) 26Hz 82Hz ±2.2mV ±3.3mV
Note: TME is the Total Measurement Error.
LTC6812-1
21
Rev. A
For more information www.analog.com
ADC Range and Resolution
The C inputs and GPIO inputs have the same range and
resolution. The ADC inside the LTC6812-1 has an approxi-
mate range from –0.82V to +5.73V. Negative readings are
rounded to 0V. The format of the data is a 16-bit unsigned
integer where the LSB represents 100μV. Therefore, a
reading of 0x80E8 (33,000 decimal) indicates a measure-
ment of 3.3V.
OPERATION
For example, the total measurement noise versus input
voltage in normal and filtered modes is shown in Figure2.
The specified range of the ADC is 0V to 5V. In Table 4,
the precision range of the ADC is arbitrarily defined as
0.5V to 4.5V. This is the range where the quantization
noise is relatively constant even in the lower OSR modes
(see Figure2). Table 4 summarizes the total noise in this
range for all eight ADC operating modes. Also shown is
the noise free resolution. For example, 14-bit noise free
resolution in normal mode implies that the top 14 bits will
be noise free with a DC input, but that the 15th and 16th
Least Significant Bits (LSB) will flicker.
ADC Range vs Voltage Reference Value
Typical ADCs have a range which is exactly twice the
value of the voltage reference, and the ADC measure-
ment error is directly proportional to the error in the
voltage reference. The LTC6812-1 ADC is not typical.
The absolute value of VREF1 is trimmed up or down to
compensate for gain errors in the ADC. Therefore, the
ADC Total Measurement Error (TME) specifications are
superior to the VREF1 specifications. For example, the
25°C specification of the Total Measurement Error when
measuring 3.300V in 7kHz(Normal) mode is ±2.2mV
and the 25°C specification for VREF1 is 3.150V ± 150mV.
Measuring Cell Voltages (ADCV Command)
The ADCV command initiates the measurement of the
battery cell inputs, pins C0 through C15. This command
has options to select the number of channels to measure
Table 4. ADC Range and Resolution
MODE
FULL
RANGE1SPECIFIED
RANGE
PRECISION
RANGE2LSB FORMAT MAX NOISE
NOISE FREE
RESOLUTION3
27kHz (Fast)
–0.8192V to
5.7344V
0V to 5V 0.5V to 4.5V 100μV Unsigned
16Bits
±4mVP-P 10 Bits
14kHz ±1mVP-P 12 Bits
7kHz (Normal) ±250μVP-P 14 Bits
3kHz ±150μVP-P 14 Bits
2kHz ±100μVP-P 15 Bits
1kHz ±100μVP-P 15 Bits
422Hz ±100μVP-P 15 Bits
26Hz (Filtered) ±50μVP-P 16 Bits
1. Negative readings are rounded to 0V.
2. PRECISION RANGE is the range over which the noise is less than MAX NOISE.
3. NOISE FREE RESOLUTION is a measure of the noise level within the PRECISION RANGE.
Figure2. Measurement Noise vs Input Voltage
Delta-Sigma ADCs have quantization noise which depends
on the input voltage, especially at low oversampling ra-
tios(OSR), such as in FAST mode. In some of the ADC
modes, the quantization noise increases as the input voltage
approaches the upper and lower limits of the ADC range.
NORMAL MODE
FILTERED MODE
INPUT (V)
0
1
2
3
4
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PEAK NOISE (mV)
68121 F02
LTC6812-1
22
Rev. A
For more information www.analog.com
OPERATION
CALIBRATE
MEASURE
C10 TO C9
MEASURE
C7 TO C6
MEASURE
C6 TO C5
ADC2
SERIAL
INTERFACE
tCYCLE
tSKEW2
ADCV + PEC
CALIBRATE
MEASURE
C15 TO C14
MEASURE
C12 TO C11
MEASURE
C11 TO C10
ADC3
CALIBRATE
MEASURE
C5 TO C4
MEASURE
C2 TO C1
MEASURE
C1 TO C0
ADC1
t0t1M t2M t5M
t4M t
5C
68121 F03
tREFUP
Figure3. Timing for ADCV Command Measuring All 15 Cells
Table 5. Conversion and Synchronization Times for ADCV Command Measuring All 15 Cells in Different Modes
MODE
CONVERSION TIMES (IN μs) SYNCHRONIZATION TIME (IN μs)
t0t1M t2M t4M t5M t5C tSKEW2
27kHz 0 58 104 198 244 937 187
14kHz 0 87 163 314 390 1,083 303
7kHz 0 145 279 547 681 1,956 536
3kHz 0 261 512 1,012 1,263 2,537 1,001
2kHz 0 494 977 1,943 2,426 3,701 1,932
1kHz 0 960 1,908 3,805 4,753 6,028 3,794
422Hz 0 1,890 3,770 7,529 9,408 10,683 7,518
26Hz 0 29,818 59,624 119,238 149,044 167,774 119,227
CALIBRATE
MEASURE
C9 TO C8
ADC2
SERIAL
INTERFACE
ADCV + PEC
CALIBRATE
MEASURE
C14 TO C13
ADC3
CALIBRATE
MEASURE
C4 TO C3
ADC1
t0t1M t1C
68121 F04
tREFUP
Figure4. Timing for ADCV Command Measuring 3 Cells
LTC6812-1
23
Rev. A
For more information www.analog.com
OPERATION
and the ADC mode. See the section on Commands for the
ADCV command format.
Figure 3 illustrates the timing of the ADCV command
which measures all fifteen cells. After the receipt of the
ADCV command to measure all 15 cells, ADC1 sequentially
measures the bottom 5 cells. ADC2 measures the middle
5 cells and ADC3 measures the top 5 cells. After the cell
measurements are complete, each channel is calibrated
to remove any offset errors.
Table 5 shows the conversion times for the ADCV com-
mand measuring all 15 cells. The total conversion time is
given by t5C which indicates the end of the calibration step.
Figure4 illustrates the timing of the ADCV command
that measures only three cells.
Table 6 shows the conversion time for the ADCV command
measuring only 3 cells. t1C indicates the total conversion
time for this command.
Table 6. Conversion Times for ADCV Command Measuring
3Cells in Different Modes
MODE
CONVERSION TIMES (IN μs)
t0t1M t1C
27kHz 0 58 203
14kHz 0 87 232
7kHz 0 145 407
3kHz 0 261 523
2kHz 0 494 756
1kHz 0 960 1,221
422Hz 0 1,890 2,152
26Hz 0 29,818 33,570
Under/Overvoltage Monitoring
Whenever the C inputs are measured, the results are com-
pared to undervoltage and overvoltage thresholds stored
in memory. If the reading of a cell is above the overvoltage
limit, a bit in memory is set as a flag. Similarly, measure-
ment results below the undervoltage limit cause a flag to
be set. The overvoltage and undervoltage thresholds are
stored in Configuration Register Group A. The flags are
stored in Status Register Group B and Auxiliary Register
Group D.
Auxiliary (GPIO) Measurements (ADAX Command)
The ADAX command initiates the measurement of the
GPIO inputs. This command has options to select which
GPIO input to measure (GPIO1–9) and which ADC mode
to use. The ADAX command also measures the 2nd refer-
ence. There are options in the ADAX command to measure
subsets of the GPIOs and the 2nd reference separately
or to measure all nine GPIOs and the 2nd reference in a
single command. See the section on Commands for the
ADAX command format. All auxiliary measurements are
relative to the V– pin voltage. This command can be used
to read external temperatures by connecting temperature
sensors to the GPIOs. These sensors can be powered from
the 2nd reference which is also measured by the ADAX
command, resulting in precise ratiometric measurements.
Figure 5 illustrates the timing of the ADAX command
measuring all GPIOs and the 2nd reference. All 10 measure-
ments are carried out on ADC1 alone. The 2nd reference
is measured after GPIO5 and before GPIO6.
ADC2
SERIAL
INTERFACE
tCYCLE
tSKEW
ADAX + PEC
ADC3
MEASURE
GPIO6
MEASURE
GPIO9
MEASURE
2ND REF
MEASURE
GPIO5
MEASURE
GPIO2
MEASURE
GPIO1
ADC1
t0t1M t2M t4M t5M t6M t7M t9M t10M t
10C
68121 F05
tREFUP
CALIBRATE
Figure5. Timing for ADAX Command Measuring All GPIOs and 2nd Reference
LTC6812-1
24
Rev. A
For more information www.analog.com
OPERATION
Table 7 shows the conversion time for the ADAX command
measuring all of the GPIOs and the 2nd reference. t10C
indicates the total conversion time.
Auxiliary (GPIO) Measurements with Digital
Redundancy (ADAXD Command)
The ADAXD command operates similarly to the ADAX
command except that an additional diagnostic is per-
formed using digital redundancy. PS[1:0] in Configuration
Register Group B must be set to 0 or 1 during ADAXD to
enable redundancy. See the ADC Conversion with Digital
Redundancy section.
The execution time of ADAX and ADAXD is the same.
Table 7. Conversion and Synchronization Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
MODE
CONVERSION TIMES (IN μs) SYNCHRONIZATION TIME (IN μs)
t0t1M t2M t9M t10M t10C tSKEW
27kHz 0 58 104 431 478 1,825 420
14kHz 0 87 163 693 769 2,116 682
7kHz 0 145 279 1,217 1,350 3,862 1,205
3kHz 0 261 512 2,264 2,514 5,025 2,253
2kHz 0 494 977 4,358 4,841 7,353 4,347
1kHz 0 960 1,908 8,547 9,496 12,007 8,536
422Hz 0 1,890 3,770 16,926 18,805 21,316 16,915
26Hz 0 29,818 59,624 268,271 298,078 335,498 268,260
CALIBRATE
MEASURE
C10 TO C9
MEASURE
C9 TO C8
MEASURE
C8 TO C7
MEASURE
C7 TO C6
MEASURE
C6 TO C5
ADC2
SERIAL
INTERFACE
tCYCLE
tSKEW3
tSKEW1
ADCVAX + PEC
CALIBRATE
MEASURE
C15 TO C14
MEASURE
C14 TO C13
MEASURE
C13 TO C12
MEASURE
C12 TO C11
MEASURE
C11 TO C10
ADC3
CALIBRATE
MEASURE
C5 TO C4
MEASURE
C4 TO C3
MEASURE
GPIO2
MEASURE
GPIO1
MEASURE
C3 TO C2
MEASURE
C2 TO C1
MEASURE
C1 TO C0
ADC1
t0t1M t2M t3M t4M t5M t6M t7M t
7C
tREFUP
68121 F06
Measuring Cell Voltages and GPIOs (ADCVAX
Command)
The ADCVAX command combines fifteen cell measure-
ments with two GPIO measurements (GPIO1 and GPIO2).
This command simplifies the synchronization of battery
cell voltage and current measurements when current sen-
sors are connected to GPIO1 or GPIO2 inputs. Figure6
illustrates the timing of the ADCVAX command. See the
section on Commands for the ADCVAX command format.
The synchronization of the current and voltage measure-
ments, tSKEW1 and tSKEW3, in Fast mode is within 194μs
and 147µs, respectively.
Table 8 shows the conversion and synchronization time
for the ADCVAX command in different modes. The total
conversion time for the command is given by t7C.
Figure6. Timing of ADCVAX Command
LTC6812-1
25
Rev. A
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OPERATION
DATA ACQUISITION SYSTEM DIAGNOSTICS
The battery monitoring data acquisition system is com-
prised of the multiplexers, ADCs, 1st reference, digital filters
and memory. To ensure long term reliable performance
there are several diagnostic commands which can be used
to verify the proper operation of these circuits.
Measuring Internal Device Parameters (ADSTAT
Command)
The ADSTAT command is a diagnostic command that
measures the following internal device parameters: Sum
of All Cells (SC), Internal Die Temperature (ITMP), Analog
Table 8. Conversion and Synchronization Times for ADCVAX Command in Different Modes
MODE
CONVERSION TIMES (IN μs) SYNCHRONIZATION TIMES (IN μs)
t0t1M t2M t3M t4M t5M t6M t7M t7C tSKEW1 tSKEW3
27kHz 0 58 104 151 205 252 306 352 1,328 194 147
14kHz 0 87 163 238 321 397 480 556 1,531 310 235
7kHz 0 145 279 413 554 688 829 963 2,753 543 409
3kHz 0 261 512 762 1,020 1,270 1,527 1,778 3,568 1,008 758
2kHz 0 494 977 1,460 1,950 2,433 2,924 3,407 5,197 1,939 1,456
1kHz 0 960 1,908 2,857 3,812 4,761 5,717 6,665 8,455 3,801 2,853
422Hz 0 1,890 3,770 5,649 7,536 9,415 11,302 13,181 14,971 7,525 5,645
26Hz 0 29,818 59,624 89,431 119,245 149,052 178,866 208,672 234,899 119,234 89,427
Figure7. Timing for ADSTAT Command Measuring SC, ITMP, VA, VD
ADC2
SERIAL
INTERFACE
t
CYCLE
tSKEW
ADSTAT + PEC
ADC3
CALIBRATE
ITMP
CALIBRATE
VD
CALIBRATE
SC
MEASURE
VD
MEASURE
ITMP
MEASURE
SC
ADC1
t0t1M t2M t4M
t3M t1C t2C t3C t
4C
68121 F07
tREFUP
Power Supply (VA) and the Digital Power Supply (VD).
These parameters are described in the section below.
All the 8 ADC modes described earlier are available for
these conversions. See the section on Commands for the
ADSTAT command format. Figure7 illustrates the timing
of the ADSTAT command measuring all 4 internal device
parameters.
Table 9 shows the conversion time of the ADSTAT com-
mand measuring all 4 internal parameters. t4C indicates
the total conversion time for the ADSTAT command.
LTC6812-1
26
Rev. A
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OPERATION
Sum of All Cells Measurement: The Sum of All Cells
measurement is the voltage between C15 and C0 with a
30:1 attenuation. The 16-bit ADC value of Sum of All Cells
measurement (SC) is stored in Status Register Group
A. Any potential difference between the C0 and V– pins
results in an error in the SC measurement equal to this
difference. From the SC value, the sum of all cell voltage
measurements is given by:
Sum of All Cells = SC • 30 • 100 µV
Internal Die Temperature: The ADSTAT command can
measure the internal die temperature. The 16-bit ADC
value of the die temperature measurement (ITMP) is
stored in Status Register Group A. From ITMP, the actual
die temperature is calculated using the expression:
Internal Die Temperature (°C) =
ITMP • 100 µV
7.6mV
⎛
⎝
⎜⎞
⎠
⎟°C – 276°C
Power Supply Measurements: The ADSTAT command is
also used to measure the Analog Power Supply (VREG)
and Digital Power Supply (VREGD). The 16-bit ADC value
of the analog power supply measurement (VA) is stored
in Status Register Group A. The 16-bit ADC value of the
digital power supply measurement (VD) is stored in Status
Register Group B. From VA and VD, the power supply
measurements are given by:
Analog Power Supply Measurement (VREG) =
VA • 100 µV
Table 9. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, VD in Different Modes
MODE
CONVERSION TIMES (IN μs) SYNCHRONIZATION TIME (IN μs)
t0t1M t2M t3M t4M t4C tSKEW
27kHz 0 58 104 151 198 742 140
14kHz 0 87 163 238 314 858 227
7kHz 0 145 279 413 547 1,556 402
3kHz 0 261 512 762 1,012 2,022 751
2kHz 0 494 977 1,460 1,943 2,953 1,449
1kHz 0 960 1,908 2,857 3,805 4,814 2,845
422Hz 0 1,890 3,770 5,649 7,529 8,538 5,638
26Hz 0 29,818 59,624 89,431 119,238 134,211 89,420
Digital Power Supply Measurement (VREGD) =
VD • 100 µV
The value of VREG is determined by external components.
VREG should be between 4.5V and 5.5V to maintain ac-
curacy. The value of VREGD is determined by internal
components. The normal range of VREGD is 2.7V to 3.6V.
Measuring Internal Device Parameters with Digital
Redundancy (ADSTATD Command)
The ADSTATD command operates similarly to the ADSTAT
command except that an additional diagnostic is performed
using digital redundancy. PS[1:0] in Configuration Reg-
ister Group B must be set to 0 or 1 during ADSTATD to
enable redundancy. See the ADC Conversion with Digital
Redundancy section.
The execution time of ADSTAT and ADSTATD is the same.
ADC Conversion with Digital Redundancy
Each of the three internal ADCs contains its own digital
integration and differentiation machine. The LTC6812-1
also contains a fourth digital integration and differentiation
machine that is used for redundancy and error checking.
All of the ADC and self test commands, except ADAX and
ADSTAT, can operate with digital redundancy. This includes
ADCV, ADOW, CVST, ADOL, ADAXD, AXOW, AXST, ADSTATD,
STATST, ADCVAX and ADCVSC. When performing an ADC
conversion with redundancy, the analog modulator sends
its bit stream to both the primary digital machine and the
redundant digital machine. At the end of the conversion
LTC6812-1
27
Rev. A
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OPERATION
the results from the two machines are compared. If any
result bit mismatch is detected then a digital redundancy
fault code is stored in place of the ADC result. The digital
redundancy fault code is a value of 0xFF0X. This is detect-
able because it falls outside the normal result range of
0x0000 to 0xDFFF. The last four bits are used to indicate
which nibble(s) of the result values did not match.
Indication of Digital Redundancy Fault Codes
DIGITAL REDUNDANCY FAULT
CODE 4 LSBs
INDICATION
0b0XXX No fault detected in bits 15–12
0b1XXX Fault detected in bits 15–12
0bX0XX No fault detected in bits 11–8
0bX1XX Fault detected in bits 11–8
0bXX0X No fault detected in bits 7–4
0bXX1X Fault detected in bits 7–4
0bXXX0 No fault detected in bits 3–0
0bXXX1 Fault detected in bits 3–0
0b0000 The digital redundancy feature will
not write this value of all zeros in the
last 4 bits
Since there is a single redundant digital machine, it can
apply redundancy to only one ADC at a time. By default, the
LTC6812-1 will automatically select ADC path redundancy.
However, the user can choose an ADC redundancy path
selection by writing to the PS[1:0] bits in Configuration
Register Group B.
Table 10 shows all possible ADC path redundancy
selections.
When the FDRF bit in Configuration Register Group B is
written to 1 it will force the digital redundancy comparison
to fail during subsequent ADC conversions.
Measuring Cell Voltages and Sum of All Cells
(ADCVSC Command)
The ADCVSC command combines fifteen cell measure-
ments and the measurement of Sum of All Cells. This
command simplifies the synchronization of the individual
battery cell voltage and the total Sum of All Cells mea-
surements. Figure8 illustrates the timing of the ADCVSC
command. See the section on Commands for the ADCVSC
command format. The synchronization of the cell voltage
and Sum of All Cells measurements, tSKEW4 and tSKEW5, in
Fast mode is within 147μs and 101µs, respectively.
Table 11 shows the conversion and synchronization time
for the ADCVSC command in different modes. The total
conversion time for the command is given by t6C.
Table 10. ADC Path Redundancy Selection
MEASURE
PS[1:0] = 00 PS[1:0] = 01 PS[1:0] = 10 PS[1:0] = 11
PATH SELECT
REDUNDANT
MEASURE PATH SELECT
REDUNDANT
MEASURE PATH SELECT
REDUNDANT
MEASURE PATH SELECT
REDUNDANT
MEASURE
Cells 1, 6, 11 ADC1 Cell 1 ADC1 Cell 1 ADC2 Cell 6 ADC3 Cell 11
Cells 2, 7, 12 ADC2 Cell 7 ADC1 Cell 2 ADC2 Cell 7 ADC3 Cell 12
Cells 3, 8, 13 ADC3 Cell 13 ADC1 Cell 3 ADC2 Cell 8 ADC3 Cell 13
Cells 4, 9, 14 ADC1 Cell 4 ADC1 Cell 4 ADC2 Cell 9 ADC3 Cell 14
Cells 5, 10, 15 ADC2 Cell 10 ADC1 Cell 5 ADC2 Cell 10 ADC3 Cell 15
Cell 6 (ADOL) ADC2 Cell 6 ADC1 Cell 6 ADC2 Cell 6 ADC3 N/A
Cell 11 (ADOL) ADC2 Cell 11 ADC1 N/A ADC2 Cell 11 ADC3 Cell 11
GPIO[n]* ADC1 GPIO[n] ADC1 GPIO[n] ADC2 N/A ADC3 N/A
2nd Reference* ADC1 2nd Ref ADC1 2nd Ref ADC2 N/A ADC3 N/A
SC* ADC1 SC ADC1 SC ADC2 N/A ADC3 N/A
ITMP* ADC1 ITMP ADC1 ITMP ADC2 N/A ADC3 N/A
VA* ADC1 VA ADC1 VA ADC2 N/A ADC3 N/A
VD* ADC1 VD ADC1 VD ADC2 N/A ADC3 N/A
*Note that the ADAX and ADSTAT commands are identical to the ADAXD and ADSTATD commands except that ADAX and ADSTAT will not apply any
digital redundancy.
LTC6812-1
28
Rev. A
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OPERATION
Figure8. Timing for ADCVSC Command Measuring All 15 Cells, SC
CALIBRATE
MEASURE
C10 TO C9
MEASURE
C9 TO C8
MEASURE
C8 TO C7
MEASURE
C7 TO C6
MEASURE
C6 TO C5
ADC2
SERIAL
INTERFACE
tCYCLE
tSKEW4 tSKEW5
ADCVSC + PEC
CALIBRATE
MEASURE
C15 TO C14
MEASURE
C14 TO C13
MEASURE
C13 TO C12
MEASURE
C12 TO C11
MEASURE
C11 TO C10
ADC3
CALIBRATE
MEASURE
C5 TO C4
MEASURE
C4 TO C3
MEASURE
SC
MEASURE
C3 TO C2
MEASURE
C2 TO C1
MEASURE
C1 TO C0
ADC1
t0t1M t2M t3M t4M t5M t6M t6C
tREFUP
68121 F08
Table 11. Conversion and Synchronization Times for ADCVSC Command in Different Modes
MODE
CONVERSION TIMES (IN μs) SYNCHRONIZATION TIMES (IN μs)
t0t1M t2M t3M t4M t5M t6M t6C tSKEW4 tSKEW5
27kHz 0 58 104 151 205 259 306 1,147 147 101
14kHz 0 87 163 238 321 404 480 1,322 235 159
7kHz 0 145 279 413 554 695 829 2,369 409 275
3kHz 0 261 512 762 1,020 1,277 1,527 3,067 758 508
2kHz 0 494 977 1,460 1,950 2,441 2,924 4,463 1,456 973
1kHz 0 960 1,908 2,857 3,812 4,768 5,717 7,256 2,853 1,904
422Hz 0 1,890 3,770 5,649 7,536 9,423 11,302 12,842 5,645 3,766
26Hz 0 29,818 59,624 89,431 119,245 149,059 178,866 201,351 89,427 59,621
LTC6812-1
29
Rev. A
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Overlap Cell Measurement (ADOL Command)
The ADOL command first simultaneously measures Cell6
with ADC1 and ADC2. Then it simultaneously measures
Cell 11 with both ADC2 and ADC3. The host can compare
the results against each other to look for inconsistencies
which may indicate a fault. The result of the Cell 6 mea-
surement from ADC2 is placed in Cell Voltage Register
GroupC where the Cell 7 result normally resides. The
result from ADC1 is placed in Cell Voltage Register Group
C where the Cell 8 result normally resides. The result of
the Cell11 measurement from ADC3 is placed in Cell Volt-
age Register Group E where the Cell 13 result normally
resides. The result from ADC2 is placed in Cell Voltage
Register Group E where the Cell 14 result normally resides.
Figure9 illustrates the timing of the ADOL command. See
the section on Commands for the ADOL command format.
Table 12 shows the conversion time for the ADOL command.
t2C indicates the total conversion time for this command.
Accuracy Check
Measuring an independent voltage reference is the best
means to verify the accuracy of a data acquisition system.
The LTC6812-1 contains a 2nd reference for this purpose.
The ADAX command will initiate the measurement of the
2nd reference. The results are placed in Auxiliary Register
Group B. The range of the result depends on the ADC1
measurement accuracy and the accuracy of the 2nd ref-
erence, including thermal hysteresis and long term drift.
Readings outside the range 2.990V to 3.014V (2.992V
to 3.012V for LTC6812I) indicate the system is out of
its specified tolerance. ADC2 is verified by comparing it
to ADC1 using the ADOL command. ADC3 is verified by
comparing it to ADC2 using the ADOL command.
OPERATION
Table 12. Conversion Times for ADOL Command
MODE
CONVERSION TIMES (IN μs)
t0t1M t2M t2C
27kHz 0 58 106 384
14kHz 0 87 164 442
7kHz 0 146 281 791
3kHz 0 262 513 1,024
2kHz 0 495 979 1,490
1kHz 0 960 1,910 2,420
422Hz 0 1,891 3,772 4,282
26Hz 0 29,818 59,626 67,119
Figure9. Timing for ADOL Command
CALIBRATE
C11 TO C10
CALIBRATE
C6 TO C5
MEASURE
C11 TO C10
MEASURE
C6 TO C5
ADC2
SERIAL
INTERFACE
ADOL + PEC
CALIBRATE
C11 TO C10
MEASURE
C11 TO C10
ADC3
CALIBRATE
C6 TO C5
MEASURE
C6 TO C5
ADC1
t0t1M t2M t1C t
2C
68121 F09
t
REFUP
LTC6812-1
30
Rev. A
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MUX Decoder Check
The diagnostic command DIAGN ensures the proper op-
eration of each multiplexer channel. The command cycles
through all channels and sets the MUXFAIL bit to1 in
Status Register Group B if any channel decoder fails. The
MUXFAIL bit is set to 0 if the channel decoder passes the
test. The MUXFAIL is also set to 1 on power-up (POR) or
after a CLRSTAT command.
The DIAGN command takes about 400μs to complete if the
Core is in REFUP state and about 4.5ms to complete if the
Core is in STANDBY state. The polling methods described
in the section Polling Methods can be used to determine
the completion of the DIAGN command.
Digital Filter Check
The delta-sigma ADC is composed of a 1-bit pulse den-
sity modulator followed by a digital filter. A pulse density
modulated bit stream has a higher percentage of 1s for
higher analog input voltages. The digital filter converts
this high frequency 1-bit stream into a single 16-bit word.
This is why a delta-sigma ADC is often referred to as an
oversampling converter.
The self test commands verify the operation of the digital
filters and memory. Figure 10 illustrates the operation
of the ADC during self test. The output of the 1-bit pulse
density modulator is replaced by a 1-bit test signal. The
test signal passes through the digital filter and is converted
to a 16-bit value. The 1-bit test signal undergoes the same
digital conversion as the regular 1-bit signal from the
modulator, so the conversion time for any self test com-
mand is exactly the same as the corresponding regular
ADC conversion command. The 16-bit ADC value is stored
in the same register groups as the corresponding regular
ADC conversion command. The test signals are designed
to place alternating one-zero patterns in the registers.
Table 13 provides a list of the self test commands. If the
digital filters and memory are working properly, then the
registers will contain the values shown in Table 13. For
more details see the Commands section.
OPERATION
Figure10. Operation of LTC6812-1 ADC Self Test
68121 F10
RESULTS
REGISTER
DIGITAL
FILTER
ANALOG
INPUT
MUX
TEST SIGNAL
PULSE DENSITY
MODULATED
BIT STREAM
1
SELF TEST
PATTERN
GENERATOR
16
1-BIT
MODULATOR
Table 13. Self Test Command Summary
COMMAND SELF TEST OPTION
OUTPUT PATTERN IN DIFFERENT ADC MODES
RESULTS REGISTER GROUPS27kHz 14kHz
7kHz, 3kHz, 2kHz,
1kHz, 422Hz, 26Hz
CVST ST[1:0] = 01 0x9565 0x9553 0x9555 C1V to C15V
(CVA, CVB, CVC, CVD, CVE)
ST[1:0] = 10 0x6A9A 0x6AAC 0x6AAA
AXST ST[1:0] = 01 0x9565 0x9553 0x9555 G1V to G9V, REF
(AUXA, AUXB, AUXC, AUXD)
ST[1:0] = 10 0x6A9A 0x6AAC 0x6AAA
STATST ST[1:0] = 01 0x9565 0x9553 0x9555 SC, ITMP, VA, VD
(STATA, STATB)
ST[1:0] = 10 0x6A9A 0x6AAC 0x6AAA
LTC6812-1
31
Rev. A
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ADC Clear Commands
LTC6812-1 has 3 clear ADC commands: CLRCELL, CLRAUX
and CLRSTAT. These commands clear the registers that
store all ADC conversion results.
The CLRCELL command clears Cell Voltage Register
Groups A, B, C, D and E. All bytes in these registers are
set to 0xFF by CLRCELL command.
The CLRAUX command clears Auxiliary Register GroupsA,
B, C and D. All bytes in these registers, except the last four
registers of Group D, are set to 0xFF by CLRAUX command.
The CLRSTAT command clears Status Register Groups A
and B except the REV and RSVD bits in Status Register
Group B. A read back of REV will return the revision code
of the part. RSVD bits always read back 0s. All OV and
UV flags, MUXFAIL bit, and THSD bit in Status Register
Group B and also in Auxiliary Register Group D are set
to1 by CLRSTAT command. The THSD bit is set to 0 after
RDSTATB command. The registers storing SC, ITMP, VA
and VD are all set to 0xFF by CLRSTAT command.
Open Wire Check (ADOW Command)
The ADOW command is used to check for any open wires
between the ADCs of the LTC6812-1 and the external cells.
This command performs ADC conversions on the Cpin
inputs identically to the ADCV command, except two in-
ternal current sources sink or source current into the two
C pins while they are being measured. The pull-up(PUP)
bit of the ADOW command determines whether the current
sources are sinking or sourcing 100μA.
The following simple algorithm can be used to check for
an open wire on any of the 16 C pins:
1. Run the 15-cell command ADOW with PUP = 1 at least
twice. Read the cell voltages for cells 1 through 15
once at the end and store them in array CELLPU(n).
2. Run the 15-cell command ADOW with PUP = 0 at least
twice. Read the cell voltages for cells 1 through 15
once at the end and store them in array CELLPD(n).
3. Take the difference between the pull-up and pull-down
measurements made in above steps for cells 2 to 15:
CELL∆(n) = CELLPU(n) – CELLPD(n).
OPERATION
4. For all values of n from 1 to 14: If CELL∆(n+1)
<–400mV, then C(n) is open. If CELLPU(1) = 0.0000,
then C(0) is open. If CELLPD(15) = 0.0000, then C(15)
is open.
The above algorithm detects open wires using normal mode
conversions with as much as 10nF of capacitance remaining
on the LTC6812-1 side of the open wire. However, if more
external capacitance is on the open C pin, then the length
of time that the open wire conversions are ran in steps 1
and 2 must be increased to give the 100μA current sources
time to create a large enough difference for the algorithm
to detect an open connection. This can be accomplished
by running more than two ADOW commands in steps 1
and 2, or by using filtered mode conversions instead of
normal mode conversions. Use Table 14 to determine how
many conversions are necessary:
Table 14
EXTERNAL C PIN
CAPACITANCE
NUMBER OF ADOW COMMANDS
REQUIRED IN STEPS 1 AND 2
NORMAL MODE FIL
TERED MODE
≤10nF 2 2
100nF 10 2
1μF 100 2
C 1 + ROUNDUP (C/10nF) 2
Auxiliary Open Wire Check (AXOW Command)
The AXOW command is used to check for any open wires
between the GPIO pins of the LTC6812-1 and the external
circuit. This command performs ADC conversions on the
GPIO pin inputs identically to the ADAX command, except
internal current sources sink or source current into each
GPIO pin while it is being measured. The pull-up (PUP) bit
of the AXOW command determines whether the current
sources are sinking or sourcing 100μA.
Thermal Shutdown
To protect the LTC6812-1 from overheating, there is a
thermal shutdown circuit included inside the IC. If the
temperature detected on the die goes above approximately
150°C, the thermal shutdown circuit trips and resets the
Configuration Register Groups (except the MUTE bit) and
turns off all discharge switches. When a thermal shutdown
event has occurred, the THSD bit in Status Register Group
LTC6812-1
32
Rev. A
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B will go high. The CLRSTAT command can also set the
THSD bit high for diagnostic purposes. This bit is cleared
when a read operation is performed on Status Register
Group B (RDSTATB command). The CLRSTAT command
sets the THSD bit high for diagnostic purposes but does
not reset the Configuration Register Groups.
Revision Code
The Status Register Group B contains a 4-bit revision code
(REV). If software detection of device revision is neces-
sary, then contact the factory for details. Otherwise, the
code can be ignored. In all cases, however
, the values of
all bits must be used when calculating the Packet Error
Code (PEC) on data reads.
WATCHDOG AND DISCHARGE TIMER
When there is no valid command for more than 2 seconds,
the watchdog timer expires. This resets Configuration
Register bytes CFGAR0, CFGAR1-3 (if DTMEN = 0) and the
GPIO bits in Configuration Register Group B in all cases.
CFGAR4, CFGAR5, the S Control Register Group (includ-
ing S control bits in PWM/S Control Register Group B)
and the remainder of Configuration Register Group B are
reset by the watchdog timer when the discharge timer is
disabled. The WDT pin is pulled high by the external pull-
up when the watchdog time elapses. The watchdog timer
is always enabled and it resets after every valid command
with matching command PEC.
The discharge timer is used to keep the discharge switches
turned ON for programmable time duration. If the discharge
timer is being used, the discharge switches are not turned
OFF when the watchdog timer is activated.
To enable the discharge timer, connect the DTEN pin to VREG
(Figure11). In this configuration, the discharge switches
will remain ON for the programmed time duration that is
determined by the DCTO value written in Configuration
Register Group A. Table 15 shows the various time settings
and the corresponding DCTO value. Table 16 summarizes
the status of the Configuration Register Groups after a
watchdog timer or discharge timer event.
OPERATION
Figure11. Watchdog and Discharge Timer
68121 F11
V
REG
DTEN
LTC6812-1
DCTO ≠ 0
2
DISCHARGE
TIMER
TIMEOUT
DCTEN
EN
RSTCLK
1
RST
(POR OR WRCFGA DONE OR TIMEOUT)
(POR OR VALID COMMAND)
CLK
OSC 16Hz
OSC 16Hz
WDT
WDTPD
WDTRST && ~DCTEN
RST1
(RESETS DCTO, DCC)
RST2
(RESETS REFUP, GPIO, VUV, VOV)
WDTRST
WATCHDOG
TIMER
LTC6812-1
33
Rev. A
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Table 15. DCTO Settings
DCTO 0 1 2 3 4 5 6 7 8 9 A B C D E F
TIME (MIN) Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120
Table 16
WATCHDOG TIMER DISCHARGE TIMER
DTEN = 0, DCTO = XXXX Resets CFGAR0-5, CFGBR0-1 and SCTRL When It Fires Disabled
DTEN = 1, DCTO = 0000 Resets CFGAR0-5, CFGBR0-1 and SCTRL When It Fires Disabled
DTEN = 1, DCTO != 0000 Resets CFGAR0, CFGAR1-3 (if DTMEN = 0) and GPIO Bits
in CFGBR0 When It Fires Resets CFGAR1-3 (if DTMEN = 1), CFGAR4-5, SCTRL and
Remainder of CFGBR0-1 (except MUTE Bit) When it Fires
The status of the discharge timer can be determined by
reading Configuration Register Group A using the RDCFGA
command. The DCTO value indicates the time left before
the discharge timer expires as shown in Table 17.
Table 17
DCTO (READ VALUE) DISCHARGE TIME LEFT (MIN)
0 Disabled (or) Timer Has Timed Out
1 0 < Timer ≤ 0.5
2 0.5 < Timer ≤ 1
3 1 < Timer ≤ 2
4 2 < Timer ≤ 3
5 3 < Timer ≤ 4
6 4 < Timer ≤ 5
7 5 < Timer ≤ 10
8 10 < Timer ≤ 15
9 15 < Timer ≤ 20
A 20 < Timer ≤ 30
B 30 < Timer ≤ 40
C 40 < Timer ≤ 60
D 60 < Timer ≤ 75
E 75 < Timer ≤ 90
F 90 < Timer ≤ 120
OPERATION
Unlike the watchdog timer, the discharge timer does not
reset when there is a valid command. The discharge timer
can only be reset after a valid WRCFGA (Write Configura-
tion Register Group A) command. There is a possibility
that the discharge timer will expire in the middle of some
commands.
If the discharge timer activates in the middle of a WRCFGA
command, the Configuration Register Groups and S Control
Register Group (including S control bits in PWM/S Control
Register Group B) will reset as per Table 16. However, at
the end of the valid WRCFGA command, the new data
is copied to Configuration Register Group A. The new
configuration data is not lost when the discharge timer
is activated.
If the discharge timer activates in the middle of a RDCFGA
or RDCFGB command, the Configuration Register Groups
reset as per Table 16. As a result, the read back data from
bytes CFGAR4 and CFGAR5 and CFGBR0 and CFGBR1
could be corrupted. If the discharge timer activates in the
middle of a RDSCTRL or RDPSB command, the S Control
Register Group (including S control bits in PWM/S Control
Register Group B) resets as per Table 16. As a result, the
read back data could be corrupted.
LTC6812-1
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Rev. A
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RESET EVENT DEVICE BEHAVIOR
Power Cycle
(V+ and VREG both
power cycled)
Transition to STANDBY state.
All registers and state machines are reset to default values.
Cell discharge is disabled.
Thermal Shutdown Cell discharge is disabled, but S Control Register Group is not reset.
All of Configuration Register Group A is reset.
All of Configuration Register Group B is reset except the MUTE bit.
The COMM Register Group is reset.
Watchdog Timeout
(while Discharge Timer
is Running)
Transition to EXTENDED BALANCING state.
CFGAR0 of Configuration Register Group A is reset.
If DTMEN (in Configuration Register Group B) = 0
then CFGAR1, CFGAR2 and CFGAR3 of Configuration Register Group A are reset.
Bits [3:0] of CFGBR0 (the GPIO bits) of Configuration Register Group B are reset.
Bit [7] of CFGBR1 (the MUTE bit) of Configuration Register Group B is reset.
The COMM Register Group is reset.
Watchdog Timeout
(no Discharge Timer
Running)
Transition to SLEEP state.
Cell discharge is disabled.
All state machines are reset.
All of Configuration Register Group A is reset.
All of Configuration Register Group B is reset.
The PWM Register Group is reset.
The S Control Register Group is reset.
The PWM/S Control Register Group is reset.
The COMM Register Group is reset.
Discharge Timeout
(while Watchdog Time-
out has Elapsed)
T
ransition to SLEEP state.
Same behavior as the previous case above.
Discharge Timeout
(while Watchdog Time-
out is not Elapsed)
Cell discharge is disabled.
The PWM Register Group is reset.
The S Control Register Group is reset.
The PWM/S Control Register Group is reset.
If DTMEN (in Configuration Register Group B) = 1
then CFGAR1, CFGAR2 and CFGAR3 of Configuration Register Group A are reset.
CFGAR4 and CFGAR5 of Configuration Register Group A are reset.
Bits [7:4] of CFGBR0 of Configuration Register Group B are reset.
All of CFGBR1 of Configuration Register Group B is reset except the MUTE bit.
RESET BEHAVIORS
Power cycling, thermal shutdown, watchdog timeout and
discharge timeout can cause various registers and circuitry
to reset when they occur. The following summarizes the
behaviors when these events occur:
OPERATION
LTC6812-1
35
Rev. A
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S PIN PULSE-WIDTH MODULATION FOR CELL
BALANCING
For additional control of cell discharging, the host may
configure the S pins to operate using pulse-width modula-
tion. While the watchdog timer is not expired, the DCC bits
in the Configuration Register Groups control the S pins
directly. After the watchdog timer expires, PWM operation
begins and continues for the remainder of the selected
discharge time or until a wake-up event occurs (and the
watchdog timer is reset). During PWM operation, the
DCC bits must be set to 1 for the PWM feature to operate.
Once PWM operation begins, the configurations in the
PWM register may cause some or all S pins to be pe-
riodically de-asserted to achieve the desired duty cycle
as shown in Table 18. Each PWM signal operates on a
30 second period. For each cycle, the duty cycle can be
programmed from 0% to 100% in increments of 1/15 =
6.67% (2 seconds).
Each S pin PWM signal is sequenced at different inter-
vals to ensure that no two pins switch on or off at the
same time. The switching interval between channels is
62.5ms, and 0.9375 seconds is required for all fifteen
pins to switch (15• 62.5ms).
The default values of the PWM control settings (located
in PWM Register Group and PWM/S Control Register
GroupB) are all 1s. Upon entering sleep mode, the PWM
control settings will be initialized to their default values.
OPERATION
DISCHARGE TIMER MONITOR
The LTC6812-1 has the ability to periodically monitor
cell voltages while the discharge timer is active. The host
should write the DTMEN bit in Configuration Register
Group B to1 to enable this feature.
When the discharge timer monitor is enabled and the
watchdog timer has expired, the LTC6812-1 will perform
a conversion of all cell voltages in 7kHz (Normal) mode
every 30 seconds. The overvoltage and undervoltage
comparisons will be performed and flags will be set if
cells have crossed a threshold. For any undervoltage cells
the discharge timer monitor will automatically clear the
associated DCC bit in Configuration Register Group A or
Configuration Register Group B so that the cell will no
longer be discharged. Clearing the DCC bit will also dis-
able PWM discharge. With this feature, the host can write
the undervoltage threshold to the desired discharge level
and use the discharge timer monitor to discharge all, or
selected, cells (using either constant discharge or PWM
discharge) down to that level.
During discharge timer monitoring, digital redundancy
checking will be performed on the cell voltage measure-
ments. If a digital redundancy failure occurs, all DCC bits
will be cleared.
LTC6812-1
36
Rev. A
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OPERATION
Table 18. S Pin Pulse-Width Modulation Settings
DCC BIT (CONFIG
REGISTER GROUPS) PWMC SETTING ON TIME (SECONDS) OFF TIME (SECONDS) DUTY CYCLE (%)
0 4’bXXXX 0 Continuously Off 0
1 4’b1111 Continuously On 0 100.0
1 4’b1110 28 2 93.3
1 4’b1101 26 4 86.7
1 4’b1100 24 6 80.0
1 4’b1011 22 8 73.3
1 4’b1010 20 10 66.7
1 4’b1001 18 12 60.0
1 4’b1000 16 14 53.3
1 4’b0111 14 16 46.7
1 4’b0110 12 18 40.0
1 4’b0101 10 20 33.3
1 4’b0100 8 22 26.7
1 4’b0011 6 24 20.0
1 4’b0010 4 26 13.3
1 4’b0001 2 28 6.7
1 4’b0000 0 Continuously Off 0
I2C/SPI MASTER ON LTC6812-1 USING GPIOs
The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6812-1 can
be used as an I2C or SPI master port to communicate to an
I2C or SPI slave. In the case of an I2C master, GPIO4 and
GPIO5 form the SDA and SCL ports of the I2C interface,
respectively. In the case of a SPI master, GPIO3, GPIO4 and
GPIO5 become the CSBM, SDIOM and SCKM ports of the
SPI interface respectively. The SPI master on LTC6812-1
supports SPI mode 3 (CHPA = 1, CPOL = 1).
The GPIOs are open-drain outputs, so an external pull-
up is required on these ports to operate as an I2C or SPI
master. It is also important to write the GPIO bits to 1 in
the Configuration Register Groups so these ports are not
pulled low internally by the device.
COMM Register
LTC6812-1 has a 6-byte COMM register as shown in
Table 19. This register stores all data and control bits
required for I2C or SPI communication to a slave. The
COMM register contains three bytes of data Dn[7:0]
to be transmitted to or received from the slave device.
ICOMn[3:0] specify control actions before transmitting/
receiving each data byte. FCOMn[3:0] specify control ac-
tions after transmitting/receiving each data byte.
If the bit ICOMn[3] in the COMM register is set to 1, the
part becomes a SPI master and if the bit is set to 0, the
part becomes an I2C master.
Table 20 describes the valid write codes for ICOMn[3:0]
and FCOMn[3:0] and their behavior when using the part
as an I2C master.
Table 21 describes the valid write codes for ICOMn[3:0]
and FCOMn[3:0] and their behavior when using the part
as a SPI master.
Note that only the codes listed in Table 20 and Table 21
are valid for ICOMn[3:0] and FCOMn[3:0]. Writing any
other code that is not listed in Table 20 and Table 21 to
ICOMn[3:0] and FCOMn[3:0] may result in unexpected
behavior on the I2C or SPI port.
LTC6812-1
37
Rev. A
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OPERATION
COMM Commands
Three commands help accomplish I2C or SPI commu-
nication to the slave device: WRCOMM, STCOMM and
RDCOMM.
WRCOMM Command: This command is used to write data
to the COMM register. This command writes 6 bytes of
data to the COMM register. The PEC needs to be written at
the end of the data. If the PEC does not match, all data in
the COMM register is cleared to 1s when CSB goes high.
See the section Bus Protocols for more details on a write
command format.
STCOMM Command: This command initiates I2C/SPI com-
munication on the GPIO ports. The COMM register contains
3 bytes of data to be transmitted to the slave. During this
command, the data bytes stored in the COMM register are
transmitted to the slave I2C or SPI device and the data
received from the I2C or SPI device is stored in the COMM
register. This command uses GPIO4 (SDA) and GPIO5
(SCL) for I2C communication or GPIO3 (CSBM), GPIO4
(SDIOM) and GPIO5 (SCKM) for SPI communication.
The STCOMM command is to be followed by 24 clock
cycles for each byte of data to be transmitted to the slave
device while holding CSB low. For example, to transmit
Table 19. COMM Register Memory Map
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4]
COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0]
COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4]
COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0]
COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4]
COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0]
Table 20. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master
CONTROL BITS CODE ACTION DESCRIPTION
ICOMn[3:0]
0110 START Generate a START Signal on I2C Port Followed by Data Transmission
0001 STOP Generate a STOP Signal on I2C Port
0000 BLANK Proceed Directly to Data Transmission on I2C Port
0111 No Transmit Release SDA and SCL and Ignore the Rest of the Data
FCOMn[3:0]
0000 Master ACK Master Generates an ACK Signal on Ninth Clock Cycle
1000 Master NACK Master Generates a NACK Signal on Ninth Clock Cycle
1001 Master NACK + STOP Master Generates a NACK Signal Followed by STOP Signal
Table 21. Write Codes for ICOMn[3:0] and FCOMn[3:0] on SPI Master
CONTROL BITS CODE ACTION DESCRIPTION
ICOMn[3:0]
1000 CSBM Low Generates a CSBM Low Signal on SPI Port (GPIO3)
1010 CSBM Falling Edge Drives CSBM (GPIO3) High, then Low
1001 CSBM High Generates a CSBM High Signal on SPI Port (GPIO3)
1111 No Transmit Releases the SPI Port and Ignores the Rest of the Data
FCOMn[3:0] X000 CSBM Low Holds CSBM Low at the End of Byte Transmission
1001 CSBM High Transitions CSBM High at the End of Byte Transmission
LTC6812-1
38
Rev. A
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OPERATION
three bytes of data to the slave, send STCOMM command
and its PEC followed by 72 clock cycles. Pull CSB high
at the end of the 72 clock cycles of STCOMM command.
During I2C or SPI communication, the data received from
the slave device is updated in the COMM register.
RDCOMM Command: The data received from the slave
device can be read back from the COMM register using
the RDCOMM command. The command reads back six
bytes of data followed by the PEC. See the section Bus
Protocols for more details on a read command format.
Table 22 describes the possible read back codes for
ICOMn[3:0] and FCOMn[3:0] when using the part as an
I2C master. Dn[7:0] contains the data byte transmitted by
the I2C slave.
Table 22. Read Codes for ICOMn[3:0] and FCOMn[3:0]
on I2C Master
CONTROL BITS CODE DESCRIPTION
ICOMn[3:0]
0110 Master Generated a START Signal
0001 Master Generated a STOP Signal
0000 Blank, SDA Was Held Low Between Bytes
0111 Blank, SDA Was Held High Between Bytes
FCOMn[3:0]
0000 Master Generated an ACK Signal
0111 Slave Generated an ACK Signal
1111 Slave Generated a NACK Signal
0001 Slave Generated an ACK Signal, Master
Generated a STOP Signal
1001 Slave Generated a NACK Signal, Master
Generated a STOP Signal
In case of the SPI master, the read back codes for
ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111,
respectively. Dn[7:0] contains the data byte transmitted
by the SPI slave.
Figure12 illustrates the operation of LTC6812-1 as an I2C
or SPI master using the GPIOs.
Any number of bytes can be transmitted to the slave in
groups of 3 bytes using these commands. The GPIO ports
will not get reset between different STCOMM commands.
However, if the wait time between the commands is greater
than 2s, the watchdog will time out and reset the ports to
their default values.
To transmit several bytes of data using an I2C master, a
START signal is only required at the beginning of the entire
data stream. A STOP signal is only required at the end of
the data stream. All intermediate data groups can use a
BLANK code before the data byte and an ACK/NACK signal
as appropriate after the data byte. SDA and SCL will not
get reset between different STCOMM commands.
To transmit several bytes of data using SPI master, a
CSBM low signal is sent at the beginning of the 1st data
byte. CSBM can be held low or taken high for intermediate
data groups using the appropriate code on FCOMn[3:0].
A CSBM high signal is sent at the end of the last byte of
data. CSBM, SDIOM and SCKM will not get reset between
different STCOMM commands.
Figure13 shows the 24 clock cycles following STCOMM
command for an I2C master in different cases. Note that
if ICOMn[3:0] specified a STOP condition, after the STOP
signal is sent, the SDA and SCL lines are held high and
all data in the rest of the word is ignored. If ICOMn[3:0]
is a NO TRANSMIT, both SDA and SCL lines are released,
and the rest of the data in the word is ignored. This is
used when a particular device in the stack does not have
to communicate to a slave.
Figure14 shows the 24 clock cycles following STCOMM
command for a SPI master. Similar to the I2C master, if
ICOMn[3:0] specified a CSBM HIGH or a NO TRANSMIT
condition, the CSBM, SCKM and SDIOM lines of the SPI
master are released and the rest of the data in the word
is ignored.
68121 F12
COMM
REGISTER
GPIO
PORT
I2C/SPI
SLAVE
PORT A
RDCOMM
WRCOMM
STCOMM
LTC6812-1
Figure12. LTC6812-1 I2C/SPI Master Using GPIOs
LTC6812-1
39
Rev. A
For more information www.analog.com
OPERATION
Timing Specifications of I2C and SPI Master
The timing of the LTC6812-1 I2C or SPI master will be
controlled by the timing of the communication at the
LTC6812-1’s primary SPI interface. Table 23 shows the
I2C master timing relationship to the primary SPI clock.
Table 24 shows the SPI master timing specifications.
S PIN PULSING USING THE S PIN CONTROL SETTINGS
The S pins of the LTC6812-1 can be used as a simple
serial interface. This is particularly useful for control-
ling Analog Devices LT8584, a monolithic flyback DC/
DC converter
, designed to actively balance large battery
stacks. The LT8584 has several operating modes which
are controlled through a serial interface. The LTC6812-1
can communicate to an LT8584 by sending a sequence
of pulses on each S pin to select a specific LT8584 mode.
The S pin control settings (located in S Control Register
Group and PWM/S Control Register Group B) are used
to specify the behavior for each of the 15 S pins, where
each nibble specifies whether the S pin should drive high,
drive low, or send a pulse sequence of between 1 and 7
SDA (GPIO4)
68121 F13
SCL (GPIO5)
NO TRANSMIT
SDA (GPIO4)
SCL (GPIO5)
STOP
SDA (GPIO4)
SCL (GPIO5)
START ACK
SDA (GPIO4)
SCL (GPIO5)
START NACK + STOP
SDA (GPIO4)
SCL (GPIO5)
BLANK NACK
(SCK)
t
CLK
t
4
t
3
Figure13. STCOMM Timing Diagram for an I2C Master
SDIOM (GPIO4) 68121 F14
SCKM (GPIO5)
CSBM HIGH/NO TRANSMIT
CSBM (GPIO3)
SDIOM (GPIO4)
SCKM (GPIO5)
CSBM (GPIO3)
CSBM LOW
CSBM LOW ≥ HIGH
SDIOM (GPIO4)
SCKM (GPIO5)
CSBM (GPIO3)
CSBM HIGH ≥ LOW
CSBM LOW
(SCK)
t
CLK
t
4
t
3
Figure14. STCOMM Timing Diagram for a SPI Master
LTC6812-1
40
Rev. A
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OPERATION
Table 23. I2C Master Timing
I2C MASTER PARAMETER
TIMING RELATIONSHIP TO
PRIMARY SPI INTERFACE
TIMING SPECIFICATIONS
AT t CLK = 1μs
SCL Clock Frequency 1/(2 • tCLK) Max 500kHz
tHD;STA t3Min 200ns
tLOW tCLK Min 1μs
tHIGH tCLK Min 1μs
tSU;STA tCLK + t4* Min 1.03μs
tHD;DAT t4* Min 30ns
tSU;DAT t3Min 200ns
tSU;STO tCLK + t4* Min 1.03μs
tBUF 3 • tCLK Min 3μs
*Note: When using isoSPI, t4 is generated internally and is a minimum of 30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times
of the SCK input, each with a specified minimum of 200ns.
Table 24. SPI Master Timing
SPI MASTER PARAMETER
TIMING RELATIONSHIP TO
PRIMARY SPI INTERFACE
TIMING SPECIFICATIONS
AT t CLK = 1μs
SDIOM Valid to SCKM Rising Setup t3Min 200ns
SDIO Valid from SCKM Rising Hold tCLK + t4* Min 1.03μs
SCKM Low tCLK Min 1μs
SCKM High tCLK Min 1μs
SCKM Period (SCKM_Low + SCKM_High) 2 • tCLK Min 2μs
CSBM Pulse Width 3 • tCLK Min 3μs
SCKM Rising to CSBM Rising 5 • tCLK + t4* Min 5.03μs
CSBM Falling to SCKM Falling t3Min 200ns
CSBM Falling to SCKM Rising tCLK + t3Min 1.2μs
SCKM Falling to SDIOM Valid Master Requires < tCLK
*Note: When using isoSPI, t4 is generated internally and is a minimum of 30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times
of the SCK input, each with a specified minimum of 200ns.
pulses. Table 25 shows the possible S pin behaviors that
can be sent to the LT8584.
The S pin pulses occur at a pulse rate of 6.44kHz (155μs
period). The pulse width will be 77.6μs. The S pin pulsing
begins when the STSCTRL command is sent, after the last
command PEC clock, provided that the command PEC
LTC6812-1
41
Rev. A
For more information www.analog.com
OPERATION
matches. The host may then continue to clock SCK in
order to poll the status of the pulsing. This polling works
similarly to the ADC polling feature. The data out will remain
logic low until the S pin pulsing sequence has completed.
While the S pin pulsing is in progress, new STSCTRL,
WRSCTRL or WRPSB commands are ignored. The PLADC
command may be used to determine when the S pin puls-
ing has completed.
If the WRSCTRL (or WRPSB) command and command PEC
are received correctly but the data PEC does not match,
then the S pin control settings will be cleared.
If a DCC bit in Configuration Register Group A or Con-
figuration Register Group B is asserted, the LTC6812-1
will drive the selected S pin low, regardless of the S pin
control settings. The host should leave the DCC bits set
to 0 when using the S pin control settings.
The CLRSCTRL command can be used to quickly reset
the S pin control settings to all 0s and force the pulsing
machine to release control of the S pins. This command
may be helpful in reducing the diagnostic control loop
time in an automotive application.
S PIN MUTING
The S pins may be disabled by sending the MUTE com-
mand and re-enabled by sending the UNMUTE command.
The MUTE and UNMUTE commands do not require any
subsequent data and thus the commands will propagate
quickly through a stack of LTC6812-1 devices. This al-
lows the host to quickly (<100µs) disable and re-enable
discharging without disturbing register contents. This
can be useful, for instance, to allow for a specific settling
time before taking cell measurements. The mute status
is reported in the read-only MUTE bit in Configuration
Register Group B.
SERIAL INTERFACE OVERVIEW
There are two types of serial ports on the LTC6812-1: a
standard 4-wire serial peripheral interface (SPI) and a
2-wire isolated interface (isoSPI). The state of the ISOMD
Table 25. S Pin Pulsing Behavior
NIBBLE VALUE S PIN BEHAVIOR
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
LTC6812-1
42
Rev. A
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OPERATION
pin determines whether pins 53, 54, 61 and 62 are a 2-wire
or 4-wire serial port.
The LTC6812-1 is used in a daisy-chain configuration.
A second isoSPI interface uses pins 57, 58, 63 and 64.
4-WIRE SERIAL PERIPHERAL INTERFACE (SPI)
PHYSICAL LAYER
External Connections
Connecting ISOMD to V– configures serial Port A for
4-wire SPI. The SDO pin is an open drain output which
requires a pull-up resistor tied to the appropriate supply
voltage (Figure15).
Timing
The 4-wire serial port is configured to operate in a SPI
system using CPHA = 1 and CPOL = 1. Consequently, data
on SDI must be stable during the rising edge of SCK. The
timing is depicted in Figure16. The maximum data rate
is 1Mbps; however the device is tested at a higher data
rate in production in order to guarantee operation at the
maximum specified data rate.
2-WIRE ISOLATED INTERFACE (isoSPI) PHYSICAL
LAYER
The 2-wire interface provides a means to interconnect
LTC6812-1 devices using simple twisted pair cabling. The
interface is designed for low packet error rates when the
cabling is subjected to high RF fields. Isolation is achieved
through an external transformer.
Standard SPI signals are encoded into differential pulses.
The strength of the transmission pulse and the threshold
level of the receiver are set by two external resistors. The
values of the resistors allow the user to trade-off power
dissipation for noise immunity.
Figure17 illustrates how the isoSPI circuit operates. A 2V
reference drives the IBIAS pin. External resistors RB1 and
RB2 create the reference current IB. This current sets the
drive strength of the transmitter. RB1 and RB2 also form
a voltage divider to supply a fraction of the 2V reference
for the ICMP pin. The receiver circuit threshold is half of
the voltage at the ICMP pin.
Figure15. 4-Wire SPI Configuration
External Connections
The LTC6812-1 has 2 serial ports which are called PortB
and Port A. Port B is always configured as a 2-wire interface.
Port A is either a 2-wire or 4-wire interface, depending on
the connection of the ISOMD pin.
When Port A is configured as a 4-wire interface, Port A
is always the SLAVE port and Port B is the MASTER port.
Communication is always initiated on Port A of the first
device in the daisy-chain configuration. The final device
in the daisy chain does not use Port B, and it should be
terminated into RM. Figure18 shows the simplest port
connections possible when the microprocessor and
the LTC6812-1s are located on the same PCB. In this
figure capacitors are used to couple signals between the
LTC6812-1s.
When Port A is configured as a 2-wire interface, com-
munication can be initiated on either Port A or Port B. If
communication is initiated on Port A, LTC6812-1 configures
Port A as slave and Port B as master. Likewise, if commu-
nication is initiated on Port B, LTC6812-1 configures PortB
as slave and Port A as master. See the section Reversible
isoSPI for a detailed description of reversible isoSPI.
Figure19 is an example of a robust interconnection of
multiple identical PCBs, each containing one LTC6812-1
configured for operation in a daisy chain. The micropro-
5k
DAISY-
CHAIN
SUPPORT
DAISY-CHAIN
SUPPORT
68121 F15
LTC6812-1
MPU
CLK
CS
VDD
MOSI
MISO
IMBIPB SCK CSB V–V–ICMP IBIAS ISOMD SDO SDI
LTC6812-1
43
Rev. A
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OPERATION
Figure16. Timing Diagram of 4-Wire Serial Peripheral Interface
68121 F16
SDI
SCK
D3 D2 D1 D0 D7…D4 D3
CURRENT COMMANDPREVIOUS COMMAND
t
7
t8
t
6
t5
SDO
CSB
D3D4 D2 D1 D0 D7…D4 D3
t
1t2
t
3
t
4
Figure17. isoSPI Interface
68121 F17
IM RM
IBIAS
IB
RB1
ICMP
2V
IP
LOGIC
AND
MEMORY
Tx = +1 Tx • 20 • IB
Tx = –1
SDO Tx = 0
PULSE
ENCODER/
DECODER
SDI
SCK
CSB
WAKEUP
CIRCUIT
(ON PORT A/B)
LTC6812-1
+
–
–
+
Rx = +1
Rx = –1
Rx = 0
RB2
COMPARATOR THRESHOLD = RB1 + RB2
1V • RB2
0.5X
••
LTC6812-1
44
Rev. A
For more information www.analog.com
OPERATION
cessor is located on a separate PCB. To achieve 2-wire
isolation between the microprocessor PCB and the 1st
LTC6812-1 PCB, use the LTC6820 support IC. The LTC6820
is functionally equivalent to the diagram in Figure17. In
this example, communication is initiated on Port A. So the
LTC6812-1 configures Port A as slave and Port B as master.
Using a Single LTC6812-1
When only one LTC6812-1 is needed, it can be used as
a single (non daisy-chained) device if the second isoSPI
port (Port B) is properly biased and terminated, as shown
in Figure20 and Figure21. ICMP should not be tied to
GND, but can be tied directly to IBIAS. A bias resistance
(2k to 20k) is required for IBIAS. Do not tie IBIAS directly
to VREG orV–. Finally, IPB and IMB should be terminated
into a 100Ω resistor (not tied to VREG or V–).
Selecting Bias Resistors
The adjustable signal amplitude allows the system to trade
power consumption for communication robustness, and
the adjustable comparator threshold allows the system to
account for signal losses.
The isoSPI transmitter drive current and comparator
voltage threshold are set by a resistor divider (RBIAS =
RB1 + RB2) between IBIAS and V–. The divided voltage
is connected to the ICMP pin, which sets the compara-
tor threshold to half of this voltage (VICMP). When either
isoSPI interface is enabled (not IDLE) IBIAS is held at 2V,
causing a current IB to flow out of the IBIAS pin. The IP
and IM pin drive currents are 20 • IB.
As an example, if divider resistor RB1 is 2.8k and resistor
RB2 is 1.21k (so that RBIAS = 4k), then:
IB=2V
R
B1
+R
B2
= 0.5mA
IDRV = IIP = IIM = 20 • IB = 10mA
Figure18. Capacitive-Coupled Daisy-Chain Configuration
GNDA
GNDA
V
DDA
MPU
CS
MISO
68121 F18
CLK
MOSI VDD
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
NC
NC
ISOMD
VREG
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
NC
NC
ISOMD
VREG
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
NC
NC
ISOMD
VREG
LTC6812-1
IMB
IPB
SCK
CSB
V–
V–
ICMP
IBIAS
SDO
SDI
ISOMD
VREG
GNDD
GNDD
GNDC
GNDC
GNDB
GNDB
LTC6812-1
45
Rev. A
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OPERATION
Figure19. Transformer-Isolated Daisy-Chain Configuration
••
GNDA
GNDA
MSTR
IBIAS
ICMP
GND
POL
PHA
IP
IM
MOSI
MISO
SCK
CSB
VCCO
EN
SLOW
VCC
LTC6820
MOSI
MISO
CLK
CS VDD
MPU
VDDA
68121 F19
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
GNDD
GNDC
GNDB
•
•
••
••
••
••
••
GNDD
GNDC
GNDB
LTC6812-1
46
Rev. A
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OPERATION
Figure20. Single Device Using 2-Wire Port A
Figure21. Single Device Using 4-Wire Port A
5k
68121 F21
LTC6812-1
MPU
CLK
CS
VDD
MOSI
MISO
IMBIPB SCK CSB V–V–ICMP IBIAS WDT ISOMD SDO SDI
V
DDA
GNDA
GNDA
20k
100Ω
TERMINATED
UNUSED
PORT REQUIRED
BIAS
••
GNDA
GNDA
100Ω
MSTR
IBIAS
ICMP
GND
POL
PHA
IP
IM
MOSI
MISO
SCK
CSB
VCCO
EN
SLOW
VCC
LTC6820
MOSI
MISO
CLK
CS VDD
MPU
VDDA
TERMINATED
UNUSED
PORT
68121 F20
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
GNDB
••
GNDB
LTC6812-1
47
Rev. A
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VICMP =2V • RB2
R
B1
+R
B2
=IB• RB2 = 603mV
VTCMP = 0.5 • VICMP = 302mV
In this example, the pulse drive current IDRV will be 10mA,
and the receiver comparators will detect pulses with IP–IM
amplitudes greater than ±302mV.
If the isolation barrier uses 1:1 transformers connected
by a twisted pair and terminated with 120Ω resistors on
each end, then the transmitted differential signal amplitude
(±) will be:
VA=IDRV •RM
2
= 0.6V
(This result ignores transformer and cable losses, which
may reduce the amplitude).
isoSPI Pulse Detail
Two LTC6812-1 devices can communicate by transmitting
and receiving differential pulses back and forth through an
isolation barrier. The transmitter can output three voltage
levels: +VA, 0V and –VA. A positive output results from
IP sourcing current and IM sinking current across load
resistor RM. A negative voltage is developed by IP sink-
ing and IM sourcing. When both outputs are off, the load
resistance forces the differential output to 0V.
To eliminate the DC signal component and enhance reli-
ability, the isoSPI uses two different pulse lengths. This
allows four types of pulses to be transmitted, as shown in
Table 26. A +1 pulse will be transmitted as a positive pulse
followed by a negative pulse. A –1 pulse will be transmit-
ted as a negative pulse followed by a positive pulse. The
duration of each pulse is defined as t1/2PW, since each is
half of the required symmetric pair. (The total isoSPI pulse
duration is 2 • t1/2PW).
Table 26. isoSPI Pulse Types
PULSE TYPE
FIRST LEVEL
(t1/2PW)
SECOND LEVEL
(t1/2PW) ENDING LEVEL
Long +1 +VA (150ns) –VA (150ns) 0V
Long –1 –VA (150ns) +VA (150ns) 0V
Short +1 +VA (50ns) –VA (50ns) 0V
Short –1 –VA (50ns) +VA (50ns) 0V
OPERATION
The receiver is designed to detect each of these isoSPI pulse
types. For successful detection, the incoming isoSPI pulses
(CSB or data) should meet the following requirements:
1. t1/2PW of incoming pulse > tFILT of the receiver and
2. tINV of incoming pulse < tWNDW of the receiver
The worst-case margin (margin 1) for the first condition
is the difference between minimum t1/2PW of the incom-
ing pulse and maximum tFILT of the receiver. Likewise, the
worst-case margin (margin 2) for the second condition is
the difference between minimum tWNDW of the receiver
and maximum tINV of the incoming pulse. These timing
relations are illustrated in Figure22.
A host microcontroller does not have to generate isoSPI
pulses to use this 2-wire interface. The first LTC6812-1 in
the system can communicate to the microcontroller using
the 4-wire SPI interface on its Port A, then daisy chain to
other LTC6812-1s using the 2-wire isoSPI interface on its
Port B. Alternatively, the LTC6820 can be used to translate
the SPI signals into isoSPI pulses.
Operation with Port A Configured for SPI
When the LTC6812-1 is operating with Port A as a SPI
(ISOMD = V–), the SPI detects one of four communica-
tion events: CSB falling, CSB rising, SCK rising with SDI
= 0 and SCK rising with SDI = 1. Each event is converted
into one of the four pulse types for transmission through
the daisy chain. Long pulses are used to transmit CSB
changes and short pulses are used to transmit data, as
explained in Table 27.
Table 27. Port B (Master) isoSPI Port Function
COMMUNICATION EVENT
(PORT A SPI)
TRANSMITTED PULSE
(PORT B isoSPI)
CSB Rising Long +1
CSB Falling Long –1
SCK Rising Edge, SDI = 1 Short +1
SCK Rising Edge, SDI = 0 Short –1
Operation with Port A Configured for isoSPI
On the other side of the isolation barrier (i.e., at the other
end of the cable), the 2nd LTC6812-1 will have ISOMD =
VREG so that its Port A is configured for isoSPI. The slave
isoSPI port (Port A or B) receives each transmitted pulse
LTC6812-1
48
Rev. A
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OPERATION
and reconstructs the SPI signals internally, as shown in
Table 28. In addition, during a READ command this port
may transmit return data pulses.
Table 28. Port A (Slave) isoSPI Port Function
RECEIVED PULSE
(PORT A isoSPI)
INTERNAL SPI
PORT ACTION RETURN PULSE
Long +1 Drive CSB High None
Long –1 Drive CSB Low
Short +1 1. Set SDI = 1
2. Pulse SCK Short –1 Pulse
if Reading a 0 Bit
(No Return Pulse if not in READ
Mode or if Reading a 1 Bit)
Short –1 1. Set SDI = 0
2. Pulse SCK
The slave isoSPI port never transmits long (CSB) pulses.
Furthermore, a slave isoSPI port will only transmit short
–1 pulses, never a +1 pulse. The master port recognizes
a null response as a logic 1.
Reversible isoSPI
When the LTC6812-1 is operating with Port A configured
for isoSPI, communication can be initiated from either
Port A or Port B. In other words, LTC6812-1 can configure
either Port A or Port B as slave or master, depending on
the direction of communication. The reversible isoSPI
feature permits communication from both directions in
a stack of daisy-chained devices. See Figure23 for an
example schematic. Figure24 illustrates the operation of
reversible isoSPI.
When LTC6812-1 is in SLEEP state, it will respond to a
valid WAKEUP signal on either Port A or Port B. This is
true for either configuration of the ISOMD pin.
If the WAKEUP signal was sent on Port A, LTC6812-1
transmits a long +1 isoSPI pulse (CSB rising) on Port B
after the isoSPI is powered up. If the WAKEUP signal was
sent on Port B, LTC6812-1 powers up the isoSPI but does
not transmit a long +1 isoSPI pulse on Port A.
When LTC6812-1 is in READY state, communication can
be initiated by sending a long –1 isoSPI pulse (CSB falling)
on either Port A or Port B. The LTC6812-1 automatically
configures the port that receives the long –1 isoSPI pulse
as the slave and the other port is configured as the master.
The isoSPI pulses are transmitted through the master port
to the rest of the devices in the daisy chain.
In ACTIVE state, the LTC6812-1 is in the middle of com-
munication and CSB of the internal SPI port is low. At
the end of communication a long +1 pulse (CSB rising)
on the SLAVE port returns the part to the READY state.
Although it is not part of a normal communication routine,
the LTC6812-1 allows ports A and B to be swapped inside
Figure22. isoSPI Pulse Detail
+VTCMP
–VTCMP
VIP – VIM
+VTCMP
–VTCMP
VIP – VIM
+1 PULSE
–1 PULSE
t
WNDW
t1/2PW
68121 F22
tFILT MARGIN 1
MARGIN 2
t1/2PW
tFILT
tINV
MARGIN 1
tWNDW
t1/2PW
tFILT MARGIN 1
MARGIN 2
t1/2PW
tFILT
tINV
MARGIN 1
LTC6812-1
49
Rev. A
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••
GNDA
GNDA
GNDA
GNDA
MSTR
IBIAS
ICMP
GND
POL
PHA
IP
IM
MOSI
MISO
SCK
CSB
VCCO
EN
SLOW
VCC
LTC6820
MSTR
IBIAS
ICMP
GND
POL
PHA
IP
IM
MOSI
MISO
SCK
CSB
VCCO
EN
SLOW
VCC
LTC6820
CS2
MOSI
MISO
CLK
CS1 VDD
MPU
VDDA
68121 F23
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
LTC6812-1
IMB
IPB
IPA
IMA
V–
V–
ICMP
IBIAS
ISOMD
VREG
GNDD
GNDC
GNDB
•
•
••
••
••
••
••
GNDD
GNDC
GNDB
••
OPERATION
Figure23. Reversible isoSPI Daisy Chain
LTC6812-1
50
Rev. A
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68121 F24
AFTER WAKEUP,
TRANSMIT CSB HIGH
PULSE ON PORT B
SLEEP STATE
AFTER WAKEUP,
DO NOT TRANSMIT
CSB PULSE
CONFIGURE PORTS:
PORT A → SLAVE
PORT B → MASTER
CONFIGURE PORTS:
PORT B → SLAVE
PORT A → MASTER
READY STATE
INTERNAL CSB IS HIGH
PART IS READY TO
ACCEPT CSB LOW PULSES
CSB LOW PULSE
ON PORT A
WAKEUP SIGNAL
ON PORT A
CSB HIGH PULSE
ON MASTER
CSB LOW PULSE
ON SLAVE
CSB LOW PULSE
ON MASTER (INSIDE tBLOCK)
CSB LOW PULSE
ON PORT B
WAKEUP SIGNAL
ON PORT B
CSB LOW PULSE
ON MASTER (OUTSIDE tBLOCK)
ACTIVE STATE
INTERNAL CSB IS LOW
PART IS IN THE MIDDLE OF
ACTIVE COMMUNICATION
SWAP PORTS
A ↔ B
NO ACTION
CSB HIGH PULSE
ON SLAVE
OPERATION
Figure24. Reversible isoSPI State Diagram
the ACTIVE state. This feature is useful for the master
controller to reclaim control of the slave port of LTC6812-1
irrespective of the current state of the ports. This can be
done by sending a long –1 isoSPI pulse on the master port
after a time delay of tBLOCK from the last isoSPI signal that
was transmitted by the part. Any long isoSPI pulse sent to
the master port inside tBLOCK is rejected by the part. This
ensures the LTC6812-1 cannot switch ports because of
signal reflections from poorly terminated cables (<100m
cable length).
Timing Diagrams
Figure25 shows the isoSPI timing diagram for a READ
command to daisy-chained LTC6812-1 parts. The ISOMD
pin is tied to V– on the bottom part so its Port A is config-
ured as a SPI port (CSB, SCK, SDI and SDO). The isoSPI
signals of three stacked devices are shown labeled with
the port (A or B) and part number
. Note that ISO B1 and
ISO A2 is actually the same signal, but shown on each
end of the transmission cable that connects Parts 1 and 2.
Likewise, ISO B2 and ISO A3 is the same signal, but with
the cable delay shown between Parts 2 and 3.
Bits WN–W0 refer to the 16-bit command code and the
16-bit PEC of a READ command. At the end of Bit W0,
the three parts decode the READ command and begin
shifting out data, which is valid on the next rising edge
of clock SCK. Bits XN–X0 refer to the data shifted out by
Part 1. Bits YN–Y0 refer to the data shifted out by Part 2
and bits ZN–Z0 refer to the data shifted out by Part 3. All
this data is read back from the SDO port on Part 1 in a
daisy-chained fashion.
Waking Up the Serial Interface
The serial ports (SPI or isoSPI) will enter the low power
IDLE state if there is no activity on Port A or Port B for
a time of tIDLE. The WAKEUP circuit monitors activity on
pins 61 through 64.
If ISOMD = V–, Port A is in SPI mode. Activity on the
CSB or SCK pin will wake up the SPI interface. If ISOMD
= VREG, Port A is in isoSPI mode. Differential activity on
IPA–IMA (or IPB–IMB) wakes up the isoSPI interface. The
LTC6812-1 will be ready to communicate when the isoSPI
state changes to READY within tWAKE or tREADY, depend-
ing on the Core state (see Figure1 and state descriptions
for details).
Figure 26 illustrates the timing and the functionally
equivalent circuit (only Port A shown). Common mode
LTC6812-1
51
Rev. A
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OPERATION
68121 F25
SDI
SCK
SDO
CSB
ISO A2
ISO B2
ISO A3
ISO B1
READ DATACOMMAND
6000500040003000200010000
t7t6t5
tRTN
t11
t10
t2
t1
tCLK
t4t3
tRISE
tDSY(CS)
t8
t9
tDSY(CS)
Zn-1
Zn-1
Zn
Zn
W0
W0
Wn
Wn
Yn-1
Yn-1
Yn
Yn
W0
W0
Xn-1
XnZ0
Wn
Wn
tDSY(D)
t10
Figure25. isoSPI Timing Diagram
68121 F26
CSB OR IMA
SCK OR IPA
|SCK(IPA) - CSB(IMA)|
WAKEUP
STATE
REJECTS COMMON
MODE NOISE
WAKEUP
CSB OR IMA
SCK OR IPA
LOW POWER MODE
tIDLE > 4.5ms
tREADY < 10µs
tDWELL= 240ns
VWAKE = 200mV
LOW POWER MODE OK TO COMMUNICATE
tDWELL = 240ns
DELAY
RETRIGGERABLE
tIDLE = 5.5ms
ONE-SHOT
Figure26. Wake-Up Detection and IDLE Timer
LTC6812-1
52
Rev. A
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OPERATION
signals will not wake up the serial interface. The inter-
face is designed to wake up after receiving a large signal
single-ended pulse, or a low-amplitude symmetric pulse.
The differential signal |SCK(IPA) – CSB(IMA)|, must be at
least VWAKE = 200mV for a minimum duration of tDWELL
= 240ns to qualify as a WAKEUP signal that powers up
the serial interface.
Waking a Daisy Chain—Method 1
The LTC6812-1 sends a long +1 pulse on Port B after it is
ready to communicate. In a daisy-chained configuration,
this pulse wakes up the next device in the stack which will,
in turn, wake up the next device. If there are ‘N’ devices in
the stack, all the devices are powered up within the time
N • tWAKE or N • tREADY, depending on the Core state. For
large stacks, the time N • tWAKE may be equal to or larger
than tIDLE. In this case, after waiting longer than the time
of N • tWAKE, the host may send another dummy byte and
wait for the time N • tREADY, in order to ensure that all
devices are in the READY state.
Method 1 can be used when all devices on the daisy chain
are in the IDLE state. This guarantees that they propagate
the WAKEUP signal up the daisy chain. However, this
method will fail to wake up all devices when a device in
the middle of the chain is in the READY state instead of
IDLE. When this happens, the device in READY state will
not propagate the wake-up pulse, so the devices above it
will remain IDLE. This situation can occur when attempt-
ing to wake up the daisy chain after only tIDLE of idle time
(some devices may be IDLE, some may not).
Waking a Daisy Chain—Method 2
A more robust wake-up method does not rely on the built-
in wake-up pulse, but manually sends isoSPI traffic for
enough time to wake the entire daisy chain. At minimum,
a pair of long isoSPI pulses (–1 and +1) is needed for each
device, separated by more than tREADY or tWAKE (if the Core
state is STANDBY or SLEEP, respectively), but less than
tIDLE. This allows each device to wake up and propagate
the next pulse to the following device. This method works
even if some devices in the chain are not in the IDLE state.
In practice, implementing method 2 requires toggling
the CSB pin (of the LTC6820, or bottom LTC6812-1 with
ISOMD= 0) to generate the long isoSPI pulses. Alternatively,
dummy commands (such as RDCFGA) can be executed
to generate the long isoSPI pulses.
DATA LINK LAYER
All data transfers on LTC6812-1 occur in byte groups.
Every byte consists of 8 bits. Bytes are transferred with
the most significant bit (MSB) first. CSB must remain low
for the entire duration of a command sequence, including
between a command byte and subsequent data. On a write
command, data is latched in on the rising edge of CSB.
NETWORK LAYER
Packet Error Code
The Packet Error Code (PEC) is a 15-bit cyclic redundancy
check (CRC) value calculated for all of the bits in a register
group in the order they are passed, using the initial PEC
value of 000000000010000 and the following character-
istic polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 +1.
To calculate the 15-bit PEC value, a simple procedure can
be established:
1. Initialize the PEC to 000000000010000 (PEC is a 15-bit
register group).
2. For each bit DIN coming into the PEC register group, set:
IN0 = DIN XOR PEC[14]
IN3 = IN0 XOR PEC[2]
IN4 = IN0 XOR PEC[3]
IN7 = IN0 XOR PEC[6]
IN8 = IN0 XOR PEC[7]
IN10 = IN0 XOR PEC[9]
IN14 = IN0 XOR PEC[13]
LTC6812-1
53
Rev. A
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OPERATION
3. Update the 15-bit PEC as follows:
PEC[14] = IN14
PEC[13] = PEC[12]
PEC[12] = PEC[11]
PEC[11] = PEC[10]
PEC[10] = IN10
PEC[9] = PEC[8]
PEC[8] = IN8
PEC[7] = IN7
PEC[6] = PEC[5]
PEC[5] = PEC[4]
PEC[4] = IN4
PEC[3] = IN3
PEC[2] = PEC[1]
PEC[1] = PEC[0]
PEC[0] = IN0
4. Go back to step 2 until all the data is shifted. The final
PEC (16 bits) is the 15-bit value in the PEC register
with a 0 bit appended to its LSB.
Figure27 illustrates the algorithm described above. An
example to calculate the PEC for a 16-bit word (0x0001)
is listed in Table 29. The PEC for 0x0001 is computed as
0x3D6E after stuffing a 0 bit at the LSB. For longer data
streams, the PEC is valid at the end of the last bit of data
sent to the PEC register.
LTC6812-1 calculates PEC for any command or data re-
ceived and compares it with the PEC following the command
or data. The command or data is regarded as valid only if
the PEC matches. LTC6812-1 also attaches the calculated
PEC at the end of the data it shifts out. Table 30 shows the
format of PEC while writing to or reading from LTC6812-1.
While writing any command to LTC6812-1, the command
bytes CMD0 and CMD1 (see Table 37 and Table 38) and
the PEC bytes PEC0 and PEC1 are sent on Port A in the
following order:
CMD0, CMD1, PEC0, PEC1
After a write command to daisy-chained LTC6812-1
devices, data is sent to each device followed by the PEC.
For example, when writing Configuration Register GroupA
to two daisy-chained devices (primary device P, stacked
device S), the data will be sent to the primary device on
Port A in the following order:
CFGAR0(S), … , CFGAR5(S), PEC0(S), PEC1(S),
CFGAR0(P), … , CFGAR5(P), PEC0(P), PEC1(P)
After a read command for daisy-chained devices, each
device shifts out its data and the PEC that it computed for
its data on Port A followed by the data received on PortB.
For example, when reading Status Register Group B from
two daisy-chained devices (primary device P, stacked
device S), the primary device sends out data on port A in
the following order:
STBR0(P), … , STBR5(P), PEC0(P), PEC1(P),
STBR0(S), … , STBR5(S), PEC0(S), PEC1(S)
See Bus Protocols for command format.
All devices in a daisy-chained configuration receive the
command bytes simultaneously. For example, to initiate
ADC conversions in a stack of devices, a single ADCV
command is sent, and all devices will start conversions
at the same time. For read and write commands, a single
command is sent, and then the stacked devices effectively
turn into a cascaded shift register, in which data is shifted
through each device to the next higher (on a write) or the
next lower (on a read) device in the stack. See the Serial
Interface Overview section.
Polling Methods
The simplest method to determine ADC completion is for
the controller to start an ADC conversion and wait for the
specified conversion time to pass before reading the results.
If using a single LTC6812-1 that communicates in SPI
mode (ISOMD pin tied low), there are two methods of
polling. The first method is to hold CSB low after an ADC
conversion command is sent. After entering a conversion
command, the SDO line is driven low when the device is
busy performing conversions. SDO is pulled high when
LTC6812-1
54
Rev. A
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OPERATION
Figure27. 15-Bit PEC Computation Circuit
Table 29. PEC Calculation for 0x0001
PEC[14]00000000001111100 0
PEC[13]00000000010000110 0
PEC[12]00000000100001101 1
PEC[11]00000001000011011 1
PEC[10]00000010000110111 1
PEC[9] 00000100000010001 1
PEC[8] 00001000000100010 0
PEC[7] 00010000000111011 1
PEC[6] 00100000000001000 0
PEC[5] 01000000000010001 1
PEC[4] 10000000000100011 1
PEC[3] 00000000000111000 0
PEC[2] 00000000000001111 1
PEC[1] 00000000000011111 1
PEC[0] 00000000000111111 1
IN14 0000000001111100 0
IN10 0000010000110111 PEC Word
IN8 0001000000100010
IN7 0010000000111011
IN4 0000000000100011
IN3 0000000000111000
IN0 0000000000111111
DIN 0000000000000001
Clock Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
68121 F27
DIN
I/P
O/P I/P
PEC REGISTER BIT X
XOR GATE
X
012345678914 10111213
Table 30. Write/Read PEC Format
NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PEC0 RD/WR PEC[14] PEC[13] PEC[12] PEC[11] PEC[10] PEC[9] PEC[8] PEC[7]
PEC1 RD/WR PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] 0
LTC6812-1
55
Rev. A
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Table 30. Write/Read PEC Format
NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PEC0 RD/WR PEC[14] PEC[13] PEC[12] PEC[11] PEC[10] PEC[9] PEC[8] PEC[7]
PEC1 RD/WR PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] 0
OPERATION
the device completes conversions. However, SDO will also
go back high when CSB goes high even if the device has
not completed the conversion (Figure28). A problem with
this method is that the controller is not free to do other
serial communication while waiting for ADC conversions
to complete.
The next method overcomes this limitation. The controller
can send an ADC start command, perform other tasks, and
then send a poll ADC converter status (PLADC) command
to determine the status of the ADC conversions (Figure29).
After entering the PLADC command, SDO will go low if
the device is busy performing conversions. SDO is pulled
high at the end of conversions. However, SDO will also
go high when CSB goes high even if the device has not
completed the conversion.
If using a single LTC6812-1 that communicates in isoSPI
mode, the low side port transmits a data pulse only in
response to a master isoSPI pulse received by it. So,
after entering the command in either method of polling
described above, isoSPI data pulses are sent to the part
to update the conversion status. These pulses can be
sent using LTC6820 by simply clocking its SCK pin. In
response to this pulse, the LTC6812-1 sends back a low
isoSPI pulse if it is still busy performing conversions or
a high data pulse if it has completed the conversions. If
a CSB high isoSPI pulse is sent to the device, it exits the
polling command.
In a daisy-chained configuration of N stacked devices,
the same two polling methods can be used. If the bottom
device communicates in SPI mode, the SDO of the bot-
tom device indicates the conversion status of the entire
stack. i.e., SDO will remain low until all the devices in
the stack have completed the conversions. In the first
method of polling, after an ADC conversion command
is sent, clock pulses are sent on SCK while keeping CSB
low. The SDO status becomes valid only at the end of N
clock pulses on SCK. During the first N clock pulses, the
bottom LTC6812-1 in the daisy chain will output a 0 or a
low data pulse. After N clock pulses, the output data from
the bottom LTC6812-1 gets updated for every clock pulse
that follows (Figure30). In the second method, the PLADC
command is sent followed by clock pulses on SCK while
keeping CSB low. Similar to the first method, the SDO
status is valid only after N clock cycles on SCK and gets
updated after every clock cycle that follows (Figure31).
If the bottom device communicates in isoSPI mode, isoSPI
data pulses are sent to the device to update the conversion
status. Using LTC6820, this can be achieved by just clocking
its SCK pin. The conversion status is valid only after the
bottom LTC6812-1 device receives N isoSPI data pulses
and the status gets updated for every isoSPI data pulse
that follows. The device returns a low data pulse if any of
the devices in the stack is busy performing conversions
and returns a high data pulse if all the devices are free.
LTC6812-1
56
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OPERATION
Figure28. SDO Polling After an ADC Conversion Command (Single LTC6812-1)
68121 F28
SDI
SCK
tCYCLE
SDO
CSB
MSB(CMD) LSB(PEC)BIT 14(CMD)
68121 F29
SDI
SCK
SDO
CSB
MSB(CMD) LSB(PEC)
CONVERSION DONE
BIT 14(CMD)
Figure29. SDO Polling Using PLADC Command (Single LTC6812-1)
LTC6812-1
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OPERATION
68121 F30
SDI
SCK
tCYCLE (ALL DEVICES)
SDO
CSB
MSB(CMD) LSB(PEC)
1 2 N
68121 F31
SDI
SCK
SDO
CSB
MSB(CMD) LSB(PEC)
1 2 N
CONVERSION DONE
Figure30. SDO Polling After an ADC Conversion Command (Daisy-Chain Configuration)
Figure31. SDO Polling Using PLADC Command (Daisy-Chain Configuration)
LTC6812-1
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OPERATION
Bus Protocols
Protocol Format: The protocol formats for commands are depicted in Table 32 through 34. Table 31 is the key for
reading the protocol diagrams.
Table 31. Protocol Key
CMD0 Command Byte 0 (See Table 35)
CMD1 Command Byte 1 (See Table 35)
PEC0 Packet Error Code Byte 0 (See Table 30)
PEC1 Packet Error Code Byte 1 (See Table 30)
n
Number of Bytes
… Continuation of Protocol
Master to Slave
Slave to Master
Table 32. Poll Command
8888
CMD0 CMD1 PEC0 PEC1 Poll Data
Table 33. Write Command
88888 8888 8
CMD0 CMD1 PEC0 PEC1 Data Byte
Low … Data Byte
High PEC0 PEC1 Shift
Byte 1 … Shift
Byte n
Table 34. Read Command
88888 8888 8
CMD0 CMD1 PEC0 PEC1 Data Byte
Low … Data Byte
High PEC0 PEC1 Shift
Byte 1 … Shift
Byte n
Command Format: The format for the commands is shown in Table 35. CC[10:0] is the 11-bit command code. A list of
all the command codes is shown in Table 36. All commands have a value 0 for CMD0[7] through CMD0[3]. The PEC
must be computed on the entire 16-bit command (CMD0 and CMD1).
Table 35. Command Format
NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CMD0 WR 0 0 0 0 0 CC[10] CC[9] CC[8]
CMD1 WR CC[7] CC[6] CC[5] CC[4] CC[3] CC[2] CC[1] CC[0]
LTC6812-1
59
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OPERATION
Commands
Table 36 lists all the commands and their options.
Table 36. Command Codes
COMMAND
DESCRIPTION NAME
CC[10:0] – COMMAND CODE
10 9 8 7 6 5 4 3 2 1 0
Write Configuration
Register Group A WRCFGA 0 0 0 0 0 0 0 0 0 0 1
Write Configuration
Register Group B WRCFGB 0 0 0 0 0 1 0 0 1 0 0
Read Configuration
Register Group A RDCFGA 0 0 0 0 0 0 0 0 0 1 0
Read Configuration
Register Group B RDCFGB 0 0 0 0 0 1 0 0 1 1 0
Read Cell Voltage
Register Group A RDCVA 0 0 0 0 0 0 0 0 1 0 0
Read Cell Voltage
Register Group B RDCVB 0 0 0 0 0 0 0 0 1 1 0
Read Cell Voltage
Register Group C RDCVC 0 0 0 0 0 0 0 1 0 0 0
Read Cell Voltage
Register Group D RDCVD 0 0 0 0 0 0 0 1 0 1 0
Read Cell Voltage
Register Group E RDCVE 0 0 0 0 0 0 0 1 0 0 1
Read Auxiliary
Register Group A RDAUXA 0 0 0 0 0 0 0 1 1 0 0
Read Auxiliary
Register Group B RDAUXB 0 0 0 0 0 0 0 1 1 1 0
Read Auxiliary
Register Group C RDAUXC 0 0 0 0 0 0 0 1 1 0 1
Read Auxiliary
Register Group D RDAUXD 0 0 0 0 0 0 0 1 1 1 1
Read Status
Register Group A RDSTATA 0 0 0 0 0 0 1 0 0 0 0
Read Status
Register Group B RDSTATB 0 0 0 0 0 0 1 0 0 1 0
Write S Control Register Group WRSCTRL 0 0 0 0 0 0 1 0 1 0 0
Write PWM Register Group WRPWM 0 0 0 0 0 1 0 0 0 0 0
Write PWM/S Control Register Group B WRPSB 0 0 0 0 0 0 1 1 1 0 0
Read S Control Register Group RDSCTRL 0 0 0 0 0 0 1 0 1 1 0
Read PWM Register Group RDPWM 0 0 0 0 0 1 0 0 0 1 0
Read PWM/S Control Register Group B RDPSB 0 0 0 0 0 0 1 1 1 1 0
Start S Control Pulsing and
Poll Status STSCTRL 0 0 0 0 0 0 1 1 0 0 1
Clear S Control Register Group CLRSCTRL 0 0 0 0 0 0 1 1 0 0 0
LTC6812-1
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OPERATION
COMMAND
DESCRIPTION NAME
CC[10:0] – COMMAND CODE
10 9 8 7 6 5 4 3 2 1 0
Start Cell Voltage ADC Conversion
and Poll Status ADCV 0 1 MD[1] MD[0] 1 1 DCP 0 CH[2] CH[1] CH[0]
Start Open Wire ADC Conversion
and Poll Status ADOW 0 1 MD[1] MD[0] PUP 1 DCP 1 CH[2] CH[1] CH[0]
Start Self Test Cell Voltage
Conversion and Poll Status CVST 0 1 MD[1] MD[0] ST[1] ST[0] 0 0 1 1 1
Start Overlap Measurements of Cell 6
and Cell 11 Voltages ADOL 0 1 MD[1] MD[0] 0 0 DCP 0 0 0 1
Start GPIOs ADC Conversion and
Poll Status ADAX 1 0 MD[1] MD[0] 1 1 0 0 CHG[2] CHG[1] CHG[0]
Start GPIOs ADC Conversion with
Digital Redundancy and Poll Status ADAXD 1 0 MD[1] MD[0] 0 0 0 0 CHG[2] CHG[1] CHG[0]
Start GPIOs Open Wire ADC
Conversion and Poll Status AXOW 1 0 MD[1] MD[0] PUP 0 1 0 CHG[2] CHG[1] CHG[0]
Start Self Test GPIOs Conversion and
Poll Status AXST 1 0 MD[1] MD[0] ST[1] ST[0] 0 0 1 1 1
Start Status Group ADC Conversion
and Poll Status ADSTAT 1 0 MD[1] MD[0] 1 1 0 1 CHST[2] CHST[1] CHST[0]
Start Status Group ADC Conversion
with Digital Redundancy and
Poll Status
ADSTATD 1 0 MD[1] MD[0] 0 0 0 1 CHST[2] CHST[1] CHST[0]
Start Self Test Status Group
Conversion and Poll Status STATST 1 0 MD[1] MD[0] ST[1] ST[0] 0 1 1 1 1
Start Combined Cell Voltage and
GPIO1, GPIO2 Conversion and
Poll Status
ADCVAX 1 0 MD[1] MD[0] 1 1 DCP 1 1 1 1
Start Combined Cell Voltage and SC
Conversion and Poll Status ADCVSC 1 0 MD[1] MD[0] 1 1 DCP 0 1 1 1
Clear Cell Voltage Register Groups CLRCELL 1 1 1 0 0 0 1 0 0 0 1
Clear Auxiliary Register Groups CLRAUX 1 1 1 0 0 0 1 0 0 1 0
Clear Status Register Groups CLRSTAT 1 1 1 0 0 0 1 0 0 1 1
Poll ADC Conversion Status PLADC 1 1 1 0 0 0 1 0 1 0 0
Diagnose MUX and Poll Status DIAGN 1 1 1 0 0 0 1 0 1 0 1
Write COMM Register Group WRCOMM 1 1 1 0 0 1 0 0 0 0 1
Read COMM Register Group RDCOMM 1 1 1 0 0 1 0 0 0 1 0
Start I2C/SPI Communication STCOMM 1 1 1 0 0 1 0 0 0 1 1
Mute Discharge MUTE 0 0 0 0 0 1 0 1 0 0 0
Unmute Discharge UNMUTE 0 0 0 0 0 1 0 1 0 0 1
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Table 37. Command Bit Descriptions
NAME DESCRIPTION VALUES
MD[1:0] ADC Mode
MD ADCOPT(CFGAR0[0]) = 0 ADCOPT(CFGAR0[0]) = 1
00 422Hz Mode 1kHz Mode
01 27kHz Mode (Fast) 14kHz Mode
10 7kHz Mode (Normal) 3kHz Mode
11 26Hz Mode (Filtered) 2kHz Mode
DCP Discharge
Permitted
DCP
0 Discharge Not Permitted
1 Discharge Permitted
CH[2:0] Cell Selection
for ADC
Conversion
Total Conversion Time in the 8 ADC Modes
CH 27kHz 14kHz 7kHz 3kHz 2kHz 1kHz 422Hz 26Hz
000 All Cells 0.9ms 1.1ms 2.0ms 2.5ms 3.7ms 6.0ms 10.7ms 168ms
001 Cells 1, 6, 11
203μs 232μs 407μs 523μs 756μs 1.2ms 2.2ms 34ms
010 Cells 2, 7, 12
011 Cells 3, 8, 13
100 Cells 4, 9, 14
101 Cells 5, 10, 15
PUP
Pull-Up/Pull-
Down Current
for Open Wire
Conversions
PUP
0 Pull-Down Current
1 Pull-Up Current
ST[1:0] Self Test Mode
Selection
Self Test Conversion Result
ST 27kHz 14kHz 7kHz 3kHz 2kHz 1kHz 422Hz 26Hz
01 Self Test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 0x9555 0x9555
10 Self test 2 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA
CHG[2:0] GPIO Selection
for ADC
Conversion
Total Conversion Time in the 8 ADC Modes
CHG 27kHz 14kHz 7kHz 3kHz 2kHz 1kHz 422Hz 26Hz
000 GPIO 1–5, 2nd
Reference, GPIO 6–9 1.8ms 2.1ms 3.9ms 5.0ms 7.4ms 12.0ms 21.3ms 335ms
001 GPIO 1 and GPIO 6
380μs 439μs 788μs 1.0ms 1.5ms 2.4ms 4.3ms 67.1ms
010 GPIO 2 and GPIO 7
011 GPIO 3 and GPIO 8
100 GPIO 4 and GPIO 9
101 GPIO 5 200μs 229μs 403μs 520μs 753μs 1.2ms 2.1ms 34ms
110 2nd Reference
CHST[2:0]* Status Group
Selection
Total Conversion Time in the 8 ADC Modes
CHST 27kHz 14kHz 7kHz 3kHz 2kHz 1kHz 422Hz 26Hz
000 SC, ITMP, VA, VD 742μs 858μs 1.6ms 2.0ms 3.0ms 4.8ms 8.5ms 134ms
001 SC
200μs 229μs 403μs 520μs 753μs 1.2ms 2.1ms 34ms
010 ITMP
011 VA
100 VD
*Note: Valid options for CHST in ADSTAT command are 0–4. If CHST is set to 5/6 in ADSTAT command, the LTC6812-1 ignores the command.
OPERATION
LTC6812-1
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Memory Map
Table 38. Configuration Register Group A
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CFGAR0 RD/WR GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 REFON DTEN ADCOPT
CFGAR1 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[0]
CFGAR2 RD/WR VOV[3] VOV[2] VOV[1] VOV[0] VUV[11] VUV[10] VUV[9] VUV[8]
CFGAR3 RD/WR VOV[11] VOV[10] VOV[9] VOV[8] VOV[7] VOV[6] VOV[5] VOV[4]
CFGAR4 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1
CFGAR5 RD/WR DCTO[3] DCTO[2] DCTO[1] DCTO[0] DCC12 DCC11 DCC10 DCC9
Table 39. Configuration Register Group B
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CFGBR0 RD/WR RSVD DCC15 DCC14 DCC13 GPIO9 GPIO8 GPIO7 GPIO6
CFGBR1 RD/WR MUTE FDRF PS[1] PS[0] DTMEN DCC0 RSVD RSVD
CFGBR2 RD/WR RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
CFGBR3 RD/WR RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
CFGBR4 RD/WR RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
CFGBR5 RD/WR RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0
Table 40. Cell Voltage Register Group A
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVAR0 RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0]
CVAR1 RD C1V[15] C1V[14] C1V[13] C1V[12] C1V[11] C1V[10] C1V[9] C1V[8]
CVAR2 RD C2V[7] C2V[6] C2V[5] C2V[4] C2V[3] C2V[2] C2V[1] C2V[0]
CVAR3 RD C2V[15] C2V[14] C2V[13] C2V[12] C2V[11] C2V[10] C2V[9] C2V[8]
CVAR4 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0]
CVAR5 RD C3V[15] C3V[14] C3V[13] C3V[12] C3V[11] C3V[10] C3V[9] C3V[8]
Table 41. Cell Voltage Register Group B
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVBR0 RD C4V[7] C4V[6] C4V[5] C4V[4] C4V[3] C4V[2] C4V[1] C4V[0]
CVBR1 RD C4V[15] C4V[14] C4V[13] C4V[12] C4V[11] C4V[10] C4V[9] C4V[8]
CVBR2 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0]
CVBR3 RD C5V[15] C5V[14] C5V[13] C5V[12] C5V[11] C5V[10] C5V[9] C5V[8]
CVBR4 RD C6V[7] C6V[6] C6V[5] C6V[4] C6V[3] C6V[2] C6V[1] C6V[0]
CVBR5 RD C6V[15] C6V[14] C6V[13] C6V[12] C6V[11] C6V[10] C6V[9] C6V[8]
OPERATION
LTC6812-1
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OPERATION
Table 42. Cell Voltage Register Group C
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVCR0* RD C7V[7]* C7V[6]* C7V[5]* C7V[4]* C7V[3]* C7V[2]* C7V[1]* C7V[0]*
CVCR1* RD C7V[15]* C7V[14]* C7V[13]* C7V[12]* C7V[11]* C7V[10]* C7V[9]* C7V[8]*
CVCR2** RD C8V[7]** C8V[6]** C8V[5]** C8V[4]** C8V[3]** C8V[2]** C8V[1]** C8V[0]**
CVCR3** RD C8V[15]** C8V[14]** C8V[13]** C8V[12]** C8V[11]** C8V[10]** C8V[9]** C8V[8]**
CVCR4 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0]
CVCR5 RD C9V[15] C9V[14] C9V[13] C9V[12] C9V[11] C9V[10] C9V[9] C9V[8]
*After performing the ADOL command, CVCR0 and CVCR1 of Cell Voltage Register Group C will contain the result of measuring Cell 6 from ADC2.
**After performing the ADOL command, CVCR2 and CVCR3 of Cell Voltage Register Group C will contain the result of measuring Cell 6 from ADC1.
Table 43. Cell Voltage Register Group D
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVDR0 RD C10V[7] C10V[6] C10V[5] C10V[4] C10V[3] C10V[2] C10V[1] C10V[0]
CVDR1 RD C10V[15] C10V[14] C10V[13] C10V[12] C10V[11] C10V[10] C10V[9] C10V[8]
CVDR2 RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0]
CVDR3 RD C11V[15] C11V[14] C11V[13] C11V[12] C11V[11] C11V[10] C11V[9] C11V[8]
CVDR4 RD C12V[7] C12V[6] C12V[5] C12V[4] C12V[3] C12V[2] C12V[1] C12V[0]
CVDR5 RD C12V[15] C12V[14] C12V[13] C12V[12] C12V[11] C12V[10] C12V[9] C12V[8]
Table 44. Cell Voltage Register Group E
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CVER0* RD C13V[7]* C13V[6]* C13V[5]* C13V[4]* C13V[3]* C13V[2]* C13V[1]* C13V[0]*
CVER1* RD C13V[15]* C13V[14]* C13V[13]* C13V[12]* C13V[11]* C13V[10]* C13V[9]* C13V[8]*
CVER2** RD C14V[7]** C14V[6]** C14V[5]** C14V[4]** C14V[3]** C14V[2]** C14V[1]** C14V[0]**
CVER3** RD C14V[15]** C14V[14]** C14V[13]** C14V[12]** C14V[11]** C14V[10]** C14V[9]** C14V[8]**
CVER4 RD C15V[7] C15V[6] C15V[5] C15V[4] C15V[3] C15V[2] C15V[1] C15V[0]
CVER5 RD C15V[15] C15V[14] C15V[13] C15V[12] C15V[11] C15V[10] C15V[9] C15V[8]
*After performing the ADOL command, CVER0 and CVER1 of Cell Voltage Register Group E will contain the result of measuring Cell 11 from ADC3.
**After performing the ADOL command, CVER2 and CVER3 of Cell Voltage Register Group E will contain the result of measuring Cell 11 from ADC2
Table 45. Auxiliary Register Group A
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AVAR0 RD G1V[7] G1V[6] G1V[5] G1V[4] G1V[3] G1V[2] G1V[1] G1V[0]
AVAR1 RD G1V[15] G1V[14] G1V[13] G1V[12] G1V[11] G1V[10] G1V[9] G1V[8]
AVAR2 RD G2V[7] G2V[6] G2V[5] G2V[4] G2V[3] G2V[2] G2V[1] G2V[0]
AVAR3 RD G2V[15] G2V[14] G2V[13] G2V[12] G2V[11] G2V[10] G2V[9] G2V[8]
AVAR4 RD G3V[7] G3V[6] G3V[5] G3V[4] G3V[3] G3V[2] G3V[1] G3V[0]
AVAR5 RD G3V[15] G3V[14] G3V[13] G3V[12] G3V[11] G3V[10] G3V[9] G3V[8]
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OPERATION
Table 46. Auxiliary Register Group B
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AVBR0 RD G4V[7] G4V[6] G4V[5] G4V[4] G4V[3] G4V[2] G4V[1] G4V[0]
AVBR1 RD G4V[15] G4V[14] G4V[13] G4V[12] G4V[11] G4V[10] G4V[9] G4V[8]
AVBR2 RD G5V[7] G5V[6] G5V[5] G5V[4] G5V[3] G5V[2] G5V[1] G5V[0]
AVBR3 RD G5V[15] G5V[14] G5V[13] G5V[12] G5V[11] G5V[10] G5V[9] G5V[8]
AVBR4 RD REF[7] REF[6] REF[5] REF[4] REF[3] REF[2] REF[1] REF[0]
AVBR5 RD REF[15] REF[14] REF[13] REF[12] REF[11] REF[10] REF[9] REF[8]
Table 47. Auxiliary Register Group C
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AVCR0 RD G6V[7] G6V[6] G6V[5] G6V[4] G6V[3] G6V[2] G6V[1] G6V[0]
AVCR1 RD G6V[15] G6V[14] G6V[13] G6V[12] G6V[11] G6V[10] G6V[9] G6V[8]
AVCR2 RD G7V[7] G7V[6] G7V[5] G7V[4] G7V[3] G7V[2] G7V[1] G7V[0]
AVCR3 RD G7V[15] G7V[14] G7V[13] G7V[12] G7V[11] G7V[10] G7V[9] G7V[8]
AVCR4 RD G8V[7] G8V[6] G8V[5] G8V[4] G8V[3] G8V[2] G8V[1] G8V[0]
AVCR5 RD G8V[15] G8V[14] G8V[13] G8V[12] G8V[11] G8V[10] G8V[9] G8V[8]
Table 48. Auxiliary Register Group D
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AVDR0 RD G9V[7] G9V[6] G9V[5] G9V[4] G9V[3] G9V[2] G9V[1] G9V[0]
AVDR1 RD G9V[15] G9V[14] G9V[13] G9V[12] G9V[11] G9V[10] G9V[9] G9V[8]
AVDR2 RD RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1
AVDR3 RD RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1 RSVD1
AVDR4 RD RSVD RSVD C15OV C15UV C14OV C14UV C13OV C13UV
AVDR5 RD RSVD1 RSVD1 RSVD1 RSVD1 RSVD RSVD RSVD RSVD
Table 49. Status Register Group A
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STAR0 RD SC[7] SC[6] SC[5] SC[4] SC[3] SC[2] SC[1] SC[0]
STAR1 RD SC[15] SC[14] SC[13] SC[12] SC[11] SC[10] SC[9] SC[8]
STAR2 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0]
STAR3 RD ITMP[15] ITMP[14] ITMP[13] ITMP[12] ITMP[11] ITMP[10] ITMP[9] ITMP[8]
STAR4 RD VA[7] VA[6] VA[5] VA[4] VA[3] VA[2] VA[1] VA[0]
STAR5 RD VA[15] VA[14] VA[13] VA[12] VA[11] VA[10] VA[9] VA[8]
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OPERATION
Table 50. Status Register Group B
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STBR0 RD VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0]
STBR1 RD VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8]
STBR2 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV
STBR3 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV
STBR4 RD C12OV C12UV C11OV C11UV C10OV C10UV C9OV C9UV
STBR5 RD REV[3] REV[2] REV[1] REV[0] RSVD RSVD MUXFAIL THSD
Table 51. COMM Register Group
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4]
COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0]
COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4]
COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0]
COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4]
COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0]
Table 52. S Control Register Group
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SCTRL0 RD/WR SCTL2[3] SCTL2[2] SCTL2[1] SCTL2[0] SCTL1[3] SCTL1[2] SCTL1[1] SCTL1[0]
SCTRL1 RD/WR SCTL4[3] SCTL4[2] SCTL4[1] SCTL4[0] SCTL3[3] SCTL3[2] SCTL3[1] SCTL3[0]
SCTRL2 RD/WR SCTL6[3] SCTL6[2] SCTL6[1] SCTL6[0] SCTL5[3] SCTL5[2] SCTL5[1] SCTL5[0]
SCTRL3 RD/WR SCTL8[3] SCTL8[2] SCTL8[1] SCTL8[0] SCTL7[3] SCTL7[2] SCTL7[1] SCTL7[0]
SCTRL4 RD/WR SCTL10[3] SCTL10[2] SCTL10[1] SCTL10[0] SCTL9[3] SCTL9[2] SCTL9[1] SCTL9[0]
SCTRL5 RD/WR SCTL12[3] SCTL12[2] SCTL12[1] SCTL12[0] SCTL11[3] SCTL11[2] SCTL11[1] SCTL11[0]
Table 53. PWM Register Group
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PWMR0 RD/WR PWM2[3] PWM2[2] PWM2[1] PWM2[0] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
PWMR1 RD/WR PWM4[3] PWM4[2] PWM4[1] PWM4[0] PWM3[3] PWM3[2] PWM3[1] PWM3[0]
PWMR2 RD/WR PWM6[3] PWM6[2] PWM6[1] PWM6[0] PWM5[3] PWM5[2] PWM5[1] PWM5[0]
PWMR3 RD/WR PWM8[3] PWM8[2] PWM8[1] PWM8[0] PWM7[3] PWM7[2] PWM7[1] PWM7[0]
PWMR4 RD/WR PWM10[3] PWM10[2] PWM10[1] PWM10[0] PWM9[3] PWM9[2] PWM9[1] PWM9[0]
PWMR5 RD/WR PWM12[3] PWM12[2] PWM12[1] PWM12[0] PWM11[3] PWM11[2] PWM11[1] PWM11[0]
LTC6812-1
66
Rev. A
For more information www.analog.com
OPERATION
Table 54. PWM/S Control Register Group B
REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PSR0 RD/WR PWM14[3] PWM14[2] PWM14[1] PWM14[0] PWM13[3] PWM13[2] PWM13[1] PWM13[0]
PSR1 RD/WR RSVD RSVD RSVD RSVD PWM15[3] PWM15[2] PWM15[1] PWM15[0]
PSR2 RD/WR RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
PSR3 RD/WR SCTL14[3] SCTL14[2] SCTL14[1] SCTL14[0] SCTL13[3] SCTL13[2] SCTL13[1] SCTL13[0]
PSR4 RD/WR RSVD RSVD RSVD RSVD SCTL15[3] SCTL15[2] SCTL15[1] SCTL15[0]
PSR5 RD/WR RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Table 55. Memory Bit Descriptions
NAME DESCRIPTION VALUES
GPIOx GPIOx Pin
Control
Write: 0 GPIOx Pin Pull-Down ON; 1 GPIOx Pin Pull-Down OFF (Default)
Read: 0 GPIOx Pin at Logic 0; 1 GPIOx Pin at Logic 1
REFON References
Powered Up
1 References Remain Powered Up Until Watchdog Timeout
0 References Shut Down After Conversions (Default)
DTEN Discharge Timer
Enable (READ
ONLY)
1 Enables the Discharge Timer for Discharge Switches
0 Disables Discharge Timer
ADCOPT ADC Mode
Option Bit
ADCOPT: 0 Selects Modes 27kHz, 7kHz, 422Hz or 26Hz with MD[1:0] Bits in ADC Conversion Commands (Default)
1 Selects Modes 14kHz, 3kHz, 1kHz or 2kHz with MD[1:0] Bits in ADC Conversion Commands
VUV Undervoltage
Comparison
Voltage*
Comparison Voltage = (VUV + 1) • 16 • 100μV
Default: VUV = 0x000
VOV Overvoltage
Comparison
Voltage*
Comparison Voltage = VOV • 16 • 100μV
Default: VOV = 0x000
DCC[x] Discharge
Cell x
x = 1 to 15: 1 Turn ON Shorting Switch for Cell x
0 Turn OFF Shorting Switch for Cell x (Default)
x = 0: 1 Turn ON GPIO9 Pull-Down
0 Turn OFF GPIO9 Pull-Down (Default)
DCTO Discharge Time
Out Value
DCTO
(Write) 0 1 2 3 4 5 6 7 8 9 A B C D E F
Time (Min) Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120
DCTO (Read) 0 1 2 3 4 5 6 7 8 9 A B C D E F
Time Left (Min)
Disabled
or
Timeout
0–0.5 0.5–1 1–2 2–3 3–4 4–5 5–10 10–15 15–20 20–30 30–40 40–60 60–75 75–90 90–120
MUTE Mute Status
(READ ONLY)
1 Mute is Activated and Discharging is Disabled
0 Mute is Deactivated
FDRF Force Digital
Redundancy
Failure
1 Forces the Digital Redundancy Comparison for ADC Conversions to Fail
0 Enables the Normal Redundancy Comparison
PS[1:0] Digital
Redundancy
Path Selection
11 Redundancy is Applied Only to ADC3 Digital Path
10 Redundancy is Applied Only to ADC2 Digital Path
01 Redundancy is Applied Only to ADC1 Digital Path
00 Redundancy is Applied Sequentially to ADC1, ADC2 and ADC3 Digital Paths During Cell Conversions
and Applied to ADC1 During AUX and STATUS Conversions
LTC6812-1
67
Rev. A
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OPERATION
NAME DESCRIPTION VALUES
DTMEN Enable
Discharge Timer
Monitor
1 Enables the Discharge Timer Monitor Function if the DTEN Pin is Asserted
0 Disables the Discharge Timer Monitor Function. The Normal Discharge Timer Function
Will Be Enabled if the DTEN Pin is Asserted
CxV Cell x Voltage* x = 1 to 15 16-Bit ADC Measurement Value for Cell x
Cell Voltage for Cell x = CxV • 100μV
CxV is Reset to 0xFFFF on Power-Up and After Clear Command
GxV GPIO x Voltage* x = 1 to 9 16-Bit ADC Measurement Value for GPIOx
Voltage for GPIOx = GxV • 100μV
GxV is Reset to 0xFFFF on Power-Up and After Clear Command
REF 2nd Reference
Voltage*
16-Bit ADC Measurement Value for 2nd Reference
Voltage for 2nd Reference = REF • 100μV
Normal Range is within 2.990V to 3.014V (2.992V to 3.012V for LTC6812I), Allowing for Variations of VREF2 Voltage and ADC
TME as well as Additional Margin to Prevent a False Fault from Being Reported
SC Sum of All Cells
Measurement*
16-Bit ADC Measurement Value of the Sum of All Cell Voltages
Sum of All Cells Voltage = SC • 100μV • 30
ITMP Internal Die
Temperature*
16-Bit ADC Measurement Value of Internal Die Temperature
Temperature Measurement Voltage = ITMP • 100μV/7.6mV/°C – 276°C
VA Analog Power
Supply Voltage*
16-Bit ADC Measurement Value of Analog Power Supply Voltage
Analog Power Supply Voltage = VA • 100μV
The Value of VA is Set by External Components and Should Be in the Range 4.5V to 5.5V for Normal Operation
VD Digital Power
Supply Voltage*
16-Bit ADC Measurement Value of Digital Power Supply Voltage
Digital Power Supply Voltage = VD • 100μV
Normal Range is within 2.7V to 3.6V
CxOV Cell x Over-
voltage Flag
x = 1 to 15 Cell Voltage Compared to VOV Comparison Voltage
0 Cell x Not Flagged for Overvoltage Condition; 1 Cell x Flagged
CxUV Cell x Under-
voltage Flag
x = 1 to 15 Cell Voltage Compared to VUV Comparison Voltage
0 Cell x Not Flagged for Undervoltage Condition; 1 Cell x Flagged
REV Revision Code Device Revision Code
RSVD Reserved Bits Read: Read Back Value Can Be 1 or 0
RSVD0 Reserved Bits Read: Read Back Value is Always 0
RSVD1 Reserved Bits Read: Read Back Value is Always 1
MUXFAIL Multiplexer Self
Test Result
Read: 0 Multiplexer Passed Self Test; 1 Multiplexer Failed Self Test
THSD Thermal
Shutdown
Status
Read: 0 Thermal Shutdown Has Not Occurred; 1 Thermal Shutdown Has Occurred
THSD Bit Cleared to 0 on Read of Status Register Group B
SCTLx[x] S Pin Control
Bits
0000 – Drive S Pin High (De-Asserted)
0001 – Send 1 High Pulse on S Pin
0010 – Send 2 High Pulses on S Pin
0011 – Send 3 High Pulses on S Pin
0100 – Send 4 High Pulses on S Pin
0101 – Send 5 High Pulses on S Pin
0110 – Send 6 High Pulses on S Pin
0111 – Send 7 High Pulses on S Pin
1XXX – Drive S Pin Low (Asserted)
Table 55 (Continued). Memory Bit Descriptions
LTC6812-1
68
Rev. A
For more information www.analog.com
OPERATION
NAME DESCRIPTION VALUES
PWMx[x] PWM Discharge
Control
0000 - Selects 0% Discharge Duty Cycle if DCCx = 1 and Watchdog Timer Has Expired
0001 - Selects 6.7% Discharge Duty Cycle if DCCx = 1 and Watchdog Timer Has Expired
0010 - Selects 13.3% Discharge Duty Cycle if DCCx = 1 and Watchdog Timer Has Expired
...
1110 - Selects 93.3% Discharge Duty Cycle if DCCx = 1 and Watchdog Timer Has Expired
1111 - Selects 100% Discharge Duty Cycle if DCCx = 1 and Watchdog Timer Has Expired
ICOMn Initial
Communication
Control Bits
Write I2C 0110 0001 0000 0111
START STOP BLANK NO TRANSMIT
SPI 1000 1010 1001 1111
CSB Low CSB Falling Edge CSB High NO TRANSMIT
Read I2C 0110 0001 0000 0111
START from Master STOP from Master SDA Low Between Bytes SDA High Between Bytes
SPI 0111
Dn I2C/SPI
Communication
Data Byte
Data Transmitted (Received) to (from) I2C/SPI Slave Device
FCOMn Final
Communication
Control Bits
Write I2C 0000 1000 1001
Master ACK Master NACK Master NACK + STOP
SPI X000 1001
CSB Low CSB High
Read I2C 0000 0111 1111 0001 1001
ACK from Master ACK from Slave NACK from Slave ACK from Slave +
STOP from Master
NACK from Slave +
STOP from Master
SPI 1111
*Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.
Table 55 (Continued). Memory Bit Descriptions
LTC6812-1
69
Rev. A
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APPLICATIONS INFORMATION
PROVIDING DC POWER
Simple Linear Regulator
The primary supply pin for the LTC6812-1 is the 5V (±0.5V)
VREG input pin. To generate the required 5V supply for VREG,
the DRIVE pin can be used to form a discrete regulator with
the addition of a few external components, as shown in
Figure32. The DRIVE pin provides a 5.7V output, capable of
sourcing 1mA. When buffered with an NPN transistor, this
provides a stable 5V over temperature. The NPN transistor
should be chosen to have a sufficient Beta over temperature
(> 40) to supply the necessary supply current. The peak
VREG current requirement of the LTC6812-1 approaches
35mA when simultaneously communicating over isoSPI
and making ADC conversions. If the VREG pin is required
to support any additional load, a transistor with an even
higher Beta may be required.
bypassed with a 1µF capacitor. Larger capacitance should
be avoided since this will increase the wake-up time of the
LTC6812-1. Some attention should be given to the ther-
mal characteristic of the NPN, as there can be significant
heating with a high collector voltage.
Improved Regulator Power Efficiency
For improved efficiency when powering the LTC6812-1
from the cell stack, VREG may be powered from a DC/DC
converter, rather than the NPN pass transistor. An ideal
circuit is based on Analog Devices LT8631 step-down
regulator, as shown in Figure 33. A 100Ω resistor is
recommended between the battery stack and the LT8631
input; this will prevent in-rush current when connecting to
the stack and it will reduce conducted EMI. The EN/UVLO
pin should be connected to the DRIVE pin, which will put
the LT8631 into a low power state when the LTC6812-1
is in the SLEEP state.
Figure32. Simple VREG Power Source Using NPN
Pass Transistor
The NPN collector can be powered from any voltage
source that is a minimum 6V above V–. This includes the
cells that are being monitored, or an unregulated power
supply. A 100Ω/100nF RC decoupling network is recom-
mended for the collector power connection to protect the
NPN from transients. The emitter of the NPN should be
Figure33. VREG Powered From Cell Stack with High
Efficiency Regulator
1µF
0.1µF
100Ω
68121 F32
WDT
DRIVE
VREG
DTEN
VREF1
VREF2
V–
V–
1µF
1µF
LTC6812-1
DZT5551
VIN INTVCC
LT8631
BST
SW
IND
EN/UV
MODE
PG
RT
2.2µF
4.7pF
25.5k
22µF
2.2µF
V
IN
18V TO
100V
V
REG
1M
191k
100Ω
22µH
VOUT
FB
GND
68121 F33
TR/SS
100pF
5V
0.1µF
LTC6812-1
70
Rev. A
For more information www.analog.com
INTERNAL PROTECTION AND FILTERING
Internal Protection Features
The LTC6812-1 incorporates various ESD safeguards to
ensure robust performance. An equivalent circuit showing
the specific protection structures is shown in Figure34.
Zener-like suppressors are shown with their nominal
clamp voltage, and the unmarked diodes exhibit standard
PN junction behavior.
Filtering of Cell and GPIO Inputs
The LTC6812-1 uses a delta-sigma ADC, which includes a
delta-sigma modulator followed by a SINC3 finite impulse
response (FIR) digital filter. This greatly relaxes input
filtering requirements. Furthermore, the programmable
oversampling ratio allows the user to determine the best
trade-off between measurement speed and filter cutoff
frequency. Even with this high order low pass filter, fast
APPLICATIONS INFORMATION
Figure34. Internal ESD Protection Structures of the LTC6812-1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IMBIPB SCK CSB V–V–ICMP IBIAS WDT ISOMD SDO SDI DTEN VREF1 VREF2 DRIVE
V+
NC
NC
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
NC
NC
C10
VREG
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
C0
S1
C1
S2
C2
S3
120V
C9S10 S9 C8 S8 C7 S7 C6 S6 NC NC C5 S5 C4 S4 C3
NOTE: ZENER VOLTAGE IS 8V UNLESS MARKED OTHERWISE.
68121 F34
LTC6812-1
24V
24V
24V 24V 24V
24V
LTC6812-1
71
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
transient noise can still induce some residual noise in mea-
surements, especially in the faster conversion modes. This
can be minimized by adding an RC low pass decoupling to
each ADC input, which also helps reject potentially damag-
ing high energy transients. Adding more than about 100Ω
to the ADC inputs begins to introduce a systematic error
in the measurement, which can be improved by raising
the filter capacitance or mathematically compensating in
software with a calibration procedure. For situations that
demand the highest level of battery voltage ripple rejec-
tion, grounded capacitor filtering is recommended. This
configuration has a series resistance and capacitors that
decouple HF noise to V–. In systems where noise is less
periodic or higher oversample rates are in use, a differential
capacitor filter structure is adequate. In this configuration
Figure35. Input Filter Structure Configurations
there are series resistors to each input, but the capacitors
connect between the adjacent C pins. However, the dif-
ferential capacitor sections interact. As a result, the filter
response is less consistent and results in less attenuation
than predicted by the RC, by approximately a decade. Note
that the capacitors only see one cell of applied voltage (thus
smaller and lower cost) and tend to distribute transient
energy uniformly across the IC (reducing stress events
on the internal protection structure). Figure35 shows the
two methods schematically. ADC accuracy varies with R, C
as shown in the Typical Performance curves, but error is
minimized if R = 100Ω and C = 10nF. The GPIO pins will
always use a grounded capacitor configuration because
the measurements are all with respect to V–.
68121 F35
CELL2
V–
C2
10nF
BATTERY V–
100Ω
(a) Differential Capacitor Filter
BSS308PE
33Ω
3.3k
CELL1 C1
S2
S1
LTC6812-1
LTC6812-1
S2
S1
10nF
10nF
100Ω
BSS308PE
33Ω
100Ω C0
3.3k
CELL2
V–
C2
BATTERY V
–
100Ω
(b) Grounded Capacitor Filter
BSS308PE
33Ω
3.3k
*
CELL1 C1
100Ω
BSS308PE
*6.8V ZENERS RECOMMENDED IF C ≥ 100nF
33Ω
C0
C
C
C
3.3k
*
*
100Ω
LTC6812-1
72
Rev. A
For more information www.analog.com
Using Nonstandard Cell Input Filters
A cell pin filter of 100Ω and 10nF is recommended for all
applications. This filter provides the best combination of
noise rejection and Total Measurement Error (TME) per-
formance. In applications that use C pin RC filters larger
than 100Ω/10nF there may be additional measurement
error. Figure36a shows how both total TME and TME
variation increase as the RC time constant increases. The
increased error is related to the MUX settling. It is possible
to reduce TME levels to near data sheet specifications by
implementing an extra single channel conversion before
issuing a standard all channel ADCV command. Figure37a
APPLICATIONS INFORMATION
shows the standard ADCV command sequence. Figure37b
and 37c show the recommended command sequence
andtiming that will allow the MUX to settle. The purpose
of the modified procedure is to allow the MUX to settle
at C1/C6/C11 before the start of the measurement cycle.
The delay between the C1/C6/C11 ADCV command and
the All Channel ADCV command is dependent on the time
constant of the RC being used. The general guidance is to
wait 6τ between the C1/C6/C11 ADCV command and the All
Channel ADCV command. Figure36b shows the expected
TME when using the recommended command sequence.
Figure36. Cell Measurement TME
(a)
ADCV (all cells) Delay RDCVA-E
(b)
ADCV (C1/C6/C11) Delay 6τADCV (all cells) CNV Time RDCVA-E
(c) ADCV (all cells) CNV Time RDCVA-E ADCV (C1/C6/C11) Delay 6τ
68121 F37
(a) Cell Measurement Error Range vs Input RC Values (b) Cell Measurement Error vs Input RC Values
(Extra Conversion and Delay Before Measurement)
68121 F36a
100nF
10nF
1µF
INPUT RESISTANCE, R (Ω)
100
1k
10k
–15
–10
–5
0
5
CELL MEASUREMENT ERROR (mV)
100nF
10nF
1µF
INPUT RESISTANCE, R (Ω)
100
1k
10k
–15
–10
–5
0
5
CELL MEASUREMENT ERROR (mV)
68121 F36b
Figure37. ADC Command Order
LTC6812-1
73
Rev. A
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CELL BALANCING
Cell Balancing with Internal MOSFETs
With passive balancing, if one cell in a series stack becomes
overcharged, an S output can slowly discharge this cell
by connecting it to a resistor. Each S output is connected
to an internal N-channel MOSFET with a maximum on
resistance of 10Ω. An external resistor should be con-
nected in series with these MOSFETs to allow most of the
heat to be dissipated outside of the LTC6812-1 package,
as illustrated in Figure38a.
The internal discharge switches (MOSFETs) S1 through
S15 can be used to passively balance cells as shown in
Figure38a with balancing current of 200mA or less (80mA
or less if the die temperature is over 95°C). Balancing
current larger than 200mA is not recommended for the
internal switches due to excessive die heating. When
discharging cells with the internal discharge switches, the
die temperature should be monitored. See the Thermal
Shutdown section.
Note that the anti-aliasing filter resistor is part of the dis-
charge path, so it should be removed or reduced. Use of
an RC for added cell voltage measurement filtering is OK
APPLICATIONS INFORMATION
but the filter resistor must remain small, typically around
10Ω to reduce the effect on the balance current.
Cell Balancing with External Transistors
For applications that require balancing currents above
200mA or large cell filters, the S outputs can be used to
control external transistors. The LTC6812-1 includes an
internal pull-up PMOS transistor with a 1k series resistor.
The S pins can act as digital outputs suitable for driving
the gate of an external MOSFET as illustrated in Figure38b.
Figure35 shows external MOSFET circuits that include RC
filtering. For applications with very low cell voltages the
PMOS in Figure38b can be replaced with a PNP. When a
PNP is used, the resistor in series with the base should
be reduced.
Choosing a Discharge Resistor
When sizing the balancing resistor, it is important to know
the typical battery imbalance and the allowable time for cell
balancing. In most small battery applications, it is reason-
able for the balancing circuitry to be able to correct for a
5% SOC (State of Charge) error with 5 hours of balancing.
For example a 5AHr battery with a 5% SOC imbalance
will have approximately 250mA Hrs of imbalance. Using
a 50mA balancing current this could be corrected in 5
hours. With a 100mA balancing current, the error would
be corrected in 2.5 hours. In systems with very large
batteries, it becomes difficult to use passive balancing to
correct large SOC imbalances in short periods of time.
The excessive heat created during balancing generally
limits the balancing current. In large capacity battery ap-
plications, if short balancing times are required, an active
balancing solution should be considered. When choosing
a balance resistor
, the following equations can be used to
help determine a resistor value:
Balance Current =
%SOC_Imbalance • Battery Capacity
Number of Hours to Balance
Balance Resistor =
Nominal Cell Voltage
Balance Current
Figure38. Internal/External Discharge Circuits
LTC6812-1
68121 F38
R
FILTER
RFILTER
CFILTER
RDISCHARGE
C(n)
S(n)
C(n – 1)
+
RDISCHARGE
BSS308PE
3.3k
C(n)
S(n)
C(n – 1)
+
1k
(a) Internal Discharge Circuit
(b) External Discharge Circuit
LTC6812-1
LTC6812-1
74
Rev. A
For more information www.analog.com
Figure39. 15-Cell Battery Stack Module with Active Balancing
APPLICATIONS INFORMATION
Active Cell Balancing
Applications that require 1A or greater of cell balancing
current should consider implementing an active balancing
system. Active balancing allows for much higher balancing
currents without the generation of excessive heat. Active
balancing also allows for energy recovery since most
of the balance current will be redistributed back to the
battery pack. Figure39 shows a simple active balancing
implementation using Analog Devices LT8584. The LT8584
also has advanced features which can be controlled via
the LTC6812-1. See S Pin Pulsing Using the S Pin Control
Settings in this data sheet and the LT8584 data sheet for
more details.
DISCHARGE CONTROL DURING CELL
MEASUREMENTS
If the discharge permitted (DCP) bit is high at the time of
a cell measurement command, the S pin discharge states
do not change during cell measurements. If the DCP bit
is low, S pin discharge states will be disabled while the
corresponding cell or adjacent cells are being measured.
If using an external discharge transistor, the relatively low
1kΩ impedance of the internal LTC6812-1 PMOS transis-
tors should allow the discharge currents to fully turn off
before the cell measurement. Table 56 illustrates the ADCV
command with DCP = 0. In this table, OFF indicates that
the S pin discharge is forced off irrespective of the state
of the corresponding DCC[x] bit. ON indicates that the
S pin discharge will remain on during the measurement
period if it was ON prior to the measurement command.
In some cases, it is not possible for the automatic dis-
charge control to eliminate all measurement error caused
by running the discharges. This is due to the discharge
transistor not turning off fast enough for the cell voltage
to completely settle before the measurement starts. For
the best measurement accuracy when running discharge,
the MUTE and UNMUTE commands should be used. The
MUTE command can be issued to temporarily disable all
discharge transistors before the ADCV command is issued.
After the cell conversion completes, an UNMUTE can be
sent to re-enable all discharge transistors that were previ-
ously ON. Using this method maximizes the measurement
accuracy with a very small time penalty.
Method to Verify Discharge Circuits
When using the internal discharge feature, the ability
to verify discharge functionality can be implemented in
software. In applications using an external discharge
MOSFET, an additional resistor can be added between
the battery cell and the source of the discharge MOSFET.
This will allow the system to test discharge functionality.
OFF
ON
OFF
ON
LT8584
LTC6812-1
BATTERY STACK
MONITOR
2.5A AVERAGE
DISCHARGE MODULE+
MODULE+
MODULE–
V+
V–/C0
BAT 15
+MODULE–
•
•
68121 F39
2.5A AVERAGE
DISCHARGE MODULE+
BAT 2
+
MODULE–
•
•
2.5A AVERAGE
DISCHARGE MODULE+
S15
LT8584 S2
LT8584 S1
BAT 1
+MODULE–
•
•
OFF
ON
LTC6812-1
75
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table 56. Discharge Control During an ADCV Command with DCP = 0
CELL MEASUREMENT PERIODS CELL CALIBRATION PERIODS
CELL
1/6/11
CELL
2/7/12
CELL
3/8/13
CELL
4/9/14
CELL
5/10/15
CELL
1/6/11
CELL
2/7/12
CELL
3/8/13
CELL
4/9/14
CELL
5/10/15
DISCHARGE PIN t0 – t1M t1M – t2M t2M – t3M t3M – t4M t4M – t5M t5M – t1C t1C – t2C t2C – t3C t3C – t4C t4C – t5C
S1 OFF OFF ON ON OFF OFF OFF ON ON OFF
S2 OFF OFF OFF ON ON OFF OFF OFF ON ON
S3 ON OFF OFF OFF ON ON OFF OFF OFF ON
S4 ON ON OFF OFF OFF ON ON OFF OFF OFF
S5 OFF ON ON OFF OFF OFF ON ON OFF OFF
S6 OFF OFF ON ON OFF OFF OFF ON ON OFF
S7 OFF OFF OFF ON ON OFF OFF OFF ON ON
S8 ON OFF OFF OFF ON ON OFF OFF OFF ON
S9 ON ON OFF OFF OFF ON ON OFF OFF OFF
S10 OFF ON ON OFF OFF OFF ON ON OFF OFF
S11 OFF OFF ON ON OFF OFF OFF ON ON OFF
S12 OFF OFF OFF ON ON OFF OFF OFF ON ON
S13 ON OFF OFF OFF ON ON OFF OFF OFF ON
S14 ON ON OFF OFF OFF ON ON OFF OFF OFF
S15 OFF ON ON OFF OFF OFF ON ON OFF OFF
LTC6812-1
76
Rev. A
For more information www.analog.com
Figure40. Balancing Self Test Circuit
Both circuits are shown in Figure40. The functionality of
the discharge circuits can be verified by conducting cell
measurements and comparing measurements when the
discharge is off to measurements when the discharge is
on. The measurement taken when the discharge is on
requires that the discharge permit bit (DCP) be set. The
change in the measurement when the discharge is turned
on is calculable based on the resistor values. The following
algorithm can be used in conjunction with Figure40 to
verify each discharge circuit:
1. Measure all cells with no discharging (all S outputs
off) and read and store the results.
2. Turn on S1, S6 and S11.
3. Measure C1–C0, C6–C5, C11–C10.
4. Turn off S1, S6 and S11.
5. Turn on S2, S7 and S12.
APPLICATIONS INFORMATION
6. Measure C2–C1, C7–C6, C12–C11.
7. Turn off S2, S7 and S12.
…
14. Turn on S5, S10 and S15.
15. Measure C5–C4, C10–C9, C15–C14.
16. Turn off S5, S10 and S15.
17. Read the Cell Voltage Register Groups to get the results
of Steps 2 thru 16.
18. Compare new readings with old readings. Each cell volt-
age reading should have decreased by a fixed percentage
set by RDISCHARGE and RFILTER for internal designs and
RDISCHARGE1 and RDISCHARGE2 for external MOSFET
designs. The exact amount of decrease depends on
the resistor values and MOSFET characteristics.
LTC6812-1
68121 F40
RFILTER
RFILTER
CFILTER
RDISCHARGE
C(n)
S(n)
C(n–1)
+
RDISCHARGE2
3.3k
C(n)
S(n)
C(n–1)
+
1k
(a) Internal Discharge Circuit
(b) External Discharge Circuit
LTC6812-1
RDISCHARGE1
RFILTER
RFILTER
LTC6812-1
77
Rev. A
For more information www.analog.com
DIGITAL COMMUNICATIONS
PEC Calculation
The Packet Error Code (PEC) can be used to ensure that
the serial data read from the LTC6812-1 is valid and has
not been corrupted. This is a critical feature for reliable
communication, particularly in environments of high noise.
The LTC6812-1 requires that a PEC be calculated for all
data being read from, and written to, the LTC6812-1. For
this reason it is important to have an efficient method for
calculating the PEC.
APPLICATIONS INFORMATION
The C code below provides a simple implementation of a
lookup-table-derived PEC calculation method. There are
two functions. The first function init_PEC15_Table() should
only be called once when the microcontroller starts and
will initialize a PEC15 table array called pec15Table[]. This
table will be used in all future PEC calculations. The PEC15
table can also be hard coded into the microcontroller rather
than running the init_PEC15_Table() function at startup.
The pec15() function calculates the PEC and will return
the correct 15-bit PEC for byte arrays of any given length.
/************************************
Copyright 2012 Analog Devices, Inc. (ADI)
Permission to freely use, copy, modify, and distribute this software for any purpose with or
without fee is hereby granted, provided that the above copyright notice and this permission
notice appear in all copies: THIS SOFTWARE IS PROVIDED “AS IS” AND ADI DISCLAIMS ALL WARRANTIES IN-
CLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL ADI BE LIABLE FOR ANY
SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE
OF SAME, INCLUDING ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
***************************************/
int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
{
remainder = i << 7;
for (int bit = 8; bit > 0; --bit)
{
if (remainder & 0x4000)
{
remainder = ((remainder << 1));
remainder = (remainder ^ CRC15_POLY)
}
else
{
remainder = ((remainder << 1));
}
}
pec15Table[i] = remainder&0xFFFF;
}
}
unsigned int16 pec15 (char *data , int len)
{
int16 remainder,address;
remainder = 16;//PEC seed
for (int i = 0; i < len; i++)
{
address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address
remainder = (remainder << 8 ) ^ pec15Table[address];
}
return (remainder*2);//The CRC15 has a 0 in the LSB so the final value must be multiplied by 2
}
LTC6812-1
78
Rev. A
For more information www.analog.com
Figure41. isoSPI Circuit
APPLICATIONS INFORMATION
isoSPI IBIAS and ICMP Setup
The LTC6812-1 allows the isoSPI links of each applica-
tion to be optimized for power consumption or for noise
immunity. The power and noise immunity of an isoSPI
system is determined by the programmed IB current,
which controls the isoSPI signaling currents. Bias current
IB can range from 100μA to 1mA. Internal circuitry scales
up this bias current to create the isoSPI signal currents
equal to be 20 • IB. A low IB reduces the isoSPI power
consumption in the READY and ACTIVE states, while a
high IB increases the amplitude of the differential signal
voltage VA across the matching termination resistor, RM.
The IB current is programmed by the sum of the RB1 and
RB2 resistors connected between the 2V IBIAS pin and
GND as shown in Figure41. The receiver input threshold
is set by the ICMP voltage that is programmed with the
resistor divider created by the RB1 and RB2 resistors. The
receiver threshold will be half of the voltage present on
the ICMP pin.
The following guidelines should be used when setting the
bias current (100μA to 1mA) IB and the receiver compara-
tor threshold voltage VICMP/2:
RM = Transmission Line Characteristic Impedance Z0
Signal Amplitude VA = (20 • IB) • (RM/2)
VTCMP (Receiver Comparator Threshold) = K • VA
VICMP (voltage on ICMP pin) = 2 • VTCMP
RB2 = VICMP/IB
RB1 = (2/IB) – RB2
Select IB and K (Signal Amplitude VA to Receiver Compara-
tor Threshold ratio) according to the application:
For lower power links: IB = 0.5mA and K = 0.5
For full power links: IB = 1mA and K = 0.5
For long links (>50m): IB = 1mA and K = 0.25
For applications with little system noise, setting IB to 0.5mA
is a good compromise between power consumption and
noise immunity. Using this IB setting with a 1:1 transformer
and RM = 100Ω, RB1 should be set to 3.01k and RB2 set
to 1k. With typical CAT5 twisted pair, these settings will
allow for communication up to 50m. For applications in
very noisy environments or that require cables longer than
50m it is recommended to increase IB to 1mA. Higher drive
current compensates for the increased insertion loss in
the cable and provides high noise immunity. When using
cables over 50m and a transformer with a 1:1 turns ratio
and RM = 100Ω, RB1 would be 1.5k and RB2 would be 499Ω.
The maximum clock rate of an isoSPI link is determined
by the length of the isoSPI cable. For cables 10m or less,
the maximum 1MHz SPI clock frequency is possible. As
the length of the cable increases, the maximum possible
SPI clock rate decreases. This dependence is a result of
the increased propagation delays that can create possible
timing violations. Figure42 shows how the maximum data
rate reduces as the cable length increases when using a
CAT5 twisted pair.
Cable delay affects three timing specifications: tCLK, t6
and t7. In the Electrical Characteristics table, each of these
specifications is derated by 100ns to allow for 50ns of cable
RM
IPA ISOMD V
REG
IMA
+
–
+
–
IBIAS
ICMP
68121 F41
LTC6812-1
RM
RB1
RB2
RB1
RB2
IPBISOMD
IMB
IBIAS
ICMP
SDI
SDO
SCK
CSB
SDO
SDI
SCK
CS
LTC6812-1
TWISTED-PAIR CABLE
WITH CHARACTERISTIC IMPEDANCE RM
ISOLATION BARRIER
(MAY USE ONE OR TWO TRANFORMERS)
MASTER •• ••
2V
VA
2V
VA
LTC6812-1
79
Rev. A
For more information www.analog.com
delay. For longer cables, the minimum timing parameters
may be calculated as shown below:
tCLK, t6 and t7 > 0.9μs + 2 • tCABLE (0.2m per ns)
Implementing a Modular isoSPI Daisy Chain
The hardware design of a daisy-chain isoSPI bus is identi-
cal for each device in the network due to the daisy-chain
point-to-point architecture. The simple design as shown in
Figure41 is functional, but inadequate for most designs. The
termination resistor RM should be split and bypassed with
a capacitor as shown in Figure43. This change provides
both a differential and a common mode termination, and
as such, increases the system noise immunity.
Figure42. Data Rate vs Cable Length
Figure43. Daisy Chain Interface Components
APPLICATIONS INFORMATION
The use of cables between battery modules, particularly
in automotive applications, can lead to increased noise
susceptibility in the communication lines. For high levels
of electromagnetic interference (EMC), additional filtering
is recommended. The circuit example in Figure43 shows
the use of common mode chokes (CMC) to add common
mode noise rejection from transients on the battery lines.
The use of a center tapped transformer will also provide
additional noise performance. A bypass capacitor con-
nected to the center tap creates a low impedance for
common mode noise (Figure43b). Since transformers
without a center tap can be less expensive, they may be
preferred. In this case, the addition of a split termination
resistor and a bypass capacitor (Figure43a) can enhance
the isoSPI performance. Large center tap capacitors
greater than 10nF should be avoided as they may prevent
the isoSPI common mode voltage from settling. Common
mode chokes similar to those used in Ethernet or CANbus
applications are recommended. Specific examples are
provided in Table 58.
An important daisy chain design consideration is the
number of devices in the isoSPI network. Both the number
of devices in a daisy chain and the length of wire between
devices determines the serial timing and affects data
latency and throughput.
For a daisy chain, it is necessary to extend minimum
required t5, the time from a rising chip select to the next
falling chip select (between commands), from 0.65μs to
2μs (see Figure25).
This timing for t5 is set by the MCU on the SPI interface
of LTC6820 or the SPI interface of the bottom LTC6812-1
device if it is configured to operate in SPI mode. If neces-
sary, LTC6812-1 will internally adjust the timing for t6 and
t5 while transmitting on the Master isoSPI port such that
t6 (Master port) > t6(GOV) and t5 (Master port) > t5(GOV).
This satisfies the timing requirement for the Slave port
of the next device.
CABLE LENGTH (METERS)
1
DATA RATE (Mbps)
1.2
0.8
0.4
0.2
1.0
0.6
010
68121 F42
100
CAT5 ASSUMED
isoSPI LINK
XFMR
isoSPI LINK
CT XFMR
LTC6812-1
LTC6812-1
IP
IM
V–
10nF
100pF
100pF
100µH CMC
••
49.9Ω
49.9Ω
••
a)
IP
IM
V–
10nF
100µH CMC
10nF
••
51Ω
51Ω
••
b)
68121 F43
LTC6812-1
80
Rev. A
For more information www.analog.com
Figure44. Daisy Chain Interface Components on Single Board
APPLICATIONS INFORMATION
10nF
GNDD
10nF
GNDD
GNDD
GNDD
10nF
GNDC
10nF
GNDC
GNDC
GNDC
10nF
GNDB
10nF
GNDB
GNDB
10nF
GNDA
GNDB
GNDA
10nF*10nF*
1k 1k
•
•
GNDC
1k 1k
•
•
GNDB
1k 1k
1k 1k
•
•
GNDA
GNDD
GNDB GNDA
10nF*
GNDC 10nF*
10nF*
10nF*
49.9Ω
49.9Ω
IPA
IBIAS
ICMP
LTC6812-1
IMA
49.9Ω
49.9Ω
IPB
IMB
49.9Ω
49.9Ω
IPA
IBIAS
ICMP
LTC6812-1
IMA
49.9Ω
49.9Ω
IPB
IMB
49.9Ω
49.9Ω
IPA
IBIAS
ICMP
IBIAS
ICMP
LTC6812-1
V–
V–
V–
IMA
49.9Ω
49.9Ω
IP
IM V–
49.9Ω
49.9Ω
IPB
IMB
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP
68121 F44
LTC6820
LTC6812-1
81
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
If the t5 requirement of 2μs is satisfied on the SPI interface,
there is no strict limitation on the maximum number of
devices in the daisy chain.
However, it is important to note that the serial read back
time, and the increased current consumption, might dictate
a practical limitation in the size of the network.
Connecting Multiple LTC6812-1s on the Same PCB
When connecting multiple LTC6812-1 devices on the same
PCB, only a single transformer is required between the
LTC6812-1 isoSPI ports. The absence of the cable also
reduces the noise levels on the communication lines and
often only a split termination is required. Figure44 shows
an example application that has multiple LTC6812-1s
on the same PCB, communicating to the bottom MCU
through an LTC6820 isoSPI driver. If a transformer with
a center tap is used, a capacitor can be added for better
noise rejection. Additional noise filtering can be provided
with discrete common mode chokes (not shown) placed
to both sides of the single transformer.
On single board designs with low noise requirements,
it is possible for a simplified capacitor-isolated coupling
as shown in Figure45 to replace the transformer. In this
circuit, the transformer is directly replaced by two 10nF
capacitors. An optional common mode choke (CMC) pro-
vides noise rejection similar to application circuits using
transformers. The circuit is designed to use IBIAS/ICMP
settings identical to the transformer circuit.
Connecting an MCU to an LTC6812-1 with an isoSPI
Data Link
The LTC6820 will convert standard 4-wire SPI into a
2-wire isoSPI link that can communicate directly with
the LTC6812-1. An example is shown in Figure46. The
LTC6820 can be used in applications to provide isolation
between the microcontroller and the stack of LTC6812-1s.
The LTC6820 also enables system configurations that
have the BMS controller at a remote location relative to
the LTC6812-1 devices and the battery pack.
LTC6812-1
82
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure45. Capacitive Isolation Coupling for LTC6812-1s on the Same PCB
10nF
GNDB
GNDB
GNDB
10nF
GNDB
10nF
10nF
10nF
GNDA
GNDA
GNDA
10nF
GNDA
68121 F45
10nF
10nF
1k 1k
1k 1k
IPA
IBIAS
ICMP
LTC6812-1
IMA
49.9Ω
49.9Ω
49.9Ω
49.9Ω
IPB
IMB
V–
IPA
IBIAS
ICMP
LTC6812-1
IMA
49.9Ω
49.9Ω
49.9Ω
49.9Ω
IPB
IMB
V–
•
•
ACT45B-101-2P-TL003
ACT45B-101-2P-TL003
•
•
LTC6812-1
83
Rev. A
For more information www.analog.com
Transformer Selection Guide
As shown in Figure41, a transformer or pair of transform-
ers isolates the isoSPI signals between two isoSPI ports.
The isoSPI signals have programmable pulse amplitudes
up to 1.6VP-P and pulse widths of 50ns and 150ns. To be
able to transmit these pulses with the necessary fidelity,
the system requires that the transformers have primary
inductances above 60μH and a 1:1 turns ratio. It is also
necessary to use a transformer with less than 2.5μH of
leakage inductance. In terms of pulse shape the primary
inductance will mostly affect the pulse droop of the 50ns
and 150ns pulses. If the primary inductance is too low,
the pulse amplitude will begin to droop and decay over
the pulse period. When the pulse droop is severe enough,
the effective pulse width seen by the receiver will drop
substantially, reducing noise margin. Some droop is ac-
ceptable as long as it is a relatively small percentage of
the total pulse amplitude. The leakage inductance primarily
affects the rise and fall times of the pulses. Slower rise
and fall times will effectively reduce the pulse width. Pulse
width is determined by the receiver as the time the signal
is above the threshold set at the ICMP pin. Slow rise and
fall times cut into the timing margins. Generally it is best
to keep pulse edges as fast as possible. When evaluating
transformers, it is also worth noting the parallel winding
capacitance. While transformers have very good CMRR at
low frequency, this rejection will degrade at higher frequen-
cies, largely due to the winding to winding capacitance.
APPLICATIONS INFORMATION
When choosing a transformer, it is best to pick one with
less parallel winding capacitance when possible.
When choosing a transformer, it is equally important to
pick a part that has an adequate isolation rating for the
application. The working voltage rating of a transformer
is a key spec when selecting a part for an application.
Interconnecting daisy-chain links between LTC6812-1
devices see <60V stress in typical applications; ordinary
pulse and LAN type transformers will suffice. Connections
to the LTC6820, in general, may need much higher work-
ing voltage ratings for good long-term reliability. Usually,
matching the working voltage to the voltage of the entire
battery stack is conservative. Unfortunately, transformer
vendors will often only specify one-second HV testing,
and this is not equal to the long-term (“permanent”)
rating of the part. For example, according to most safety
standards a 1.5kV rated transformer is expected to handle
230V continuously, and a 3kV device is capable of 1100V
long-term, though manufacturers may not always certify
to those levels (refer to actual vendor data for specif-
ics). Usually, the higher voltage transformers are called
“high-isolation” or “reinforced insulation” types by the
suppliers. Table 57 shows a list of transformers that have
been evaluated in isoSPI links.
In most applications a common mode choke is also
necessary for noise rejection. Table 58 includes a list of
suitable CMCs if the CMC is not already integrated into
the transformer being used.
Figure46. Interfacing an LTC6812-1 with a μC Using an LTC6820 for Isolated SPI Control
10nF
GNDB
GNDB
10nF
GNDA
GNDA
10nF*
10nF*
10nF
GNDB
10nF*
1k 1k
1k 1k
•
•
GNDA
GNDB
•
•
GNDB
GNDA
49.9Ω
49.9Ω
49.9Ω
49.9Ω
IPA
IBIAS
ICMP
IBIAS
ICMP
LTC6812-1
IMA
49.9Ω
49.9Ω
IP
IM V–
IPB
IMB
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP 68121 F46
LTC6820
V–
LTC6812-1
84
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table 58. Recommended Common Mode Chokes
MANUFACTURER PART NUMBER
TDK ACT45B-101-2P
Murata DLW43SH101XK2
Table 57. Recommended Transformers
SUPPLIER PART NUMBER TEMP RANGE VWORKING VHIPOT/60S CT CMC H L
W
(W/ LEADS) PINS
AEC–
Q200
Recommended Dual Transformers
Bourns SM91501AL –40°C to 125°C 1000V 4.3kVdc l l 5.0mm 15.0mm 14.7mm 12SMT l
Bourns SM13105L (AS4562) –40°C to 125°C 1600V 4.3kVrms l l 5.0mm 15.0mm 27.9mm 12SMT –
Bourns US4374 –40°C to 125°C 950V 4.3kVdc l l 4.9mm 15.6mm 24.0mm 12SMT l
Jingweida S12502BA –40°C to 125°C 1000V 4.3kVdc l l 5.0mm 14.8mm 14.8mm 12SMT l
Halo TG110–AE050N5LF –40°C to 85/125°C 60V (est) 1.5kVrms l l 6.4mm 12.7mm 9.5mm 16SMT l
Sumida CLP178–C20114 –40°C to 125°C 1000V (est) 3.75kVrms l l 9mm 17.5mm 15.1mm 12SMT –
Sumida CLP0612–C20115 600Vrms 3.75kVrms l– 5.7mm 12.7mm 9.4mm 16SMT –
Pulse HM2100NL –40°C to 105°C 1000V 4.3kVdc – l3.5mm 14.7mm 15.0mm 10SMT l
Pulse HM2112ZNL –40°C to 125°C 1600V 4.3kVdc l l 3.5mm 14.7mm 15.5mm 12SMT l
Pulse HX1188FNL –40°C to 85°C 60V (est) 1.5kVrms l l 6.0mm 12.7mm 9.7mm 16SMT –
Pulse HX0068ANL –40°C to 85°C 60V (est) 1.5kVrms l l 2.1mm 12.7mm 9.7mm 16SMT –
Wurth 7490140110 –40°C to 85°C 250Vrms 4kVrms l l 10.9mm 24.6mm 17.0mm 16SMT –
Wurth 7490140111 0°C to 70°C 1000V (est) 4.5kVrms l– 8.4mm 17.1mm 15.2mm 12SMT –
Wurth 749014018 0°C to 70°C 250Vrms 4kVrms l l 8.4mm 17.1mm 15.2mm 12SMT –
Recommended Single Transformers
Bourns SM91502AL –40°C to 125°C 1000V 4.3kVdc l l 6.5mm 8.5mm 8.9mm 6SMT l
Bourns SM13102AL (US4195) –40°C to 125°C 800V 4kVrms l l 3.8mm 11.6mm 21.1mm 6SMT –
Halo TD04–QXLTAW –40°C to 85°C 1000V (est) 5kVrms l– 8.6mm 8.9mm 16.6mm 6TH –
Halo TGR04–6506V6LF –40°C to 125°C 300V 3kVrms l– 10mm 9.5mm 12.1mm 6SMT –
Halo TGR04–A6506NA6NL –40°C to 125°C 300V 3kVrms l– 9.4mm 8.9mm 12.1mm 6SMT l
Halo TDR04–A550ALLF –40°C to 105°C 1000V 5kVrms l– 6.4mm 8.9mm 16.6mm 6TH l
Jingweida S06107BA –40°C to 125°C 1000V (est) 4.3kVdc l l 6.3mm 7.6mm 9.9mm 6SMT –
Pulse HM2101NL –40°C to 105°C 1000V 4.3kVdc – l5.7mm 7.6mm 9.3mm 6SMT l
Pulse HM2113ZNL –40°C to 125°C 1600V 4.3kVdc l l 3.5mm 9mm 15.5mm 6SMT l
Sumida CEEH96BNP–LTC6804/11 –40°C to 125°C 600V 2.5kVrms – – 7mm 9.2mm 12.0mm 4SMT
Sumida CEP99NP–LTC6804 –40°C to 125°C 600V 2.5kVrms l– 10mm 9.2mm 12.0mm 8SMT –
Sumida ESMIT–4180/A –40°C to 105°C 250Vrms 3kVrms – – 3.5mm 5.2mm 9.1mm 4SMT l
Sumida ESMIT–4187 –40°C to 105°C >400Vrms
(est) 2.5kVrms – – 3.5mm 7.5mm 12.8mm 4SMT l
TDK VMT40DR–201S2P4 –40°C to 125°C 600V (est) 3.4kVdc l– 4.0mm 8.5mm 13.8mm 6SMT l
TDK ALT4532V–201–T001 –40°C to 105°C 80V ~1kV l– 2.9mm 3.2mm 4.5mm 6SMT l
TDK VGT10/9EE–204S2P4 –40°C to 125°C 700V 2.8kVrms l– 10.6mm 10.4mm 12.6mm 8SMT l
Sunlord ALTW0806C–C03 –40°C to 125°C 300V (est) 3kVrms l– 8.8mm 6.3mm 8.9mm 6SMT l
Wurth 750340848 –40°C to 105°C 250V 3kVrms – – 2.2mm 4.4mm 9.1mm 4SMT –
XFMRS XFBMC29–BA09 –40°C to 85°C 1600V (est) 2.9kVrms l l 5.0mm 10.0mm 19.5mm 6SMT l
LTC6812-1
85
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
isoSPI Layout Guidelines
Layout of the isoSPI signal lines also plays a significant
role in maximizing the noise immunity of a data link. The
following layout guidelines are recommended:
1. The transformer should be placed as close to the
isoSPI cable connector as possible. The distance
should be kept less than 2cm. The LTC6812-1 should
be placed close to but at least 1cm to 2cm away from
the transformer to help isolate the IC from magnetic
field coupling.
2. A V– ground plane should not extend under the
transformer, the isoSPI connector or in between the
transformer and the connector.
3. The isoSPI signal traces should be as direct as pos-
sible while isolated from adjacent circuitry by ground
metal or space. No traces should cross the isoSPI
signal lines, unless separated by a ground plane on
an inner layer.
System Supply Current
The LTC6812-1 has various supply current specifications
for the different states of operation. The average supply
current depends on the control loop in the system. It is
necessary to know which commands are being executed
each control loop cycle, and the duration of the control
loop cycle. From this information it is possible to determine
the percentage of time the LTC6812-1 is in the MEASURE
state versus the low power SLEEP state. The amount of
isoSPI or SPI communication will also affect the average
supply current.
Calculating Serial Throughput
For any given LTC6812-1 the calculation to determine
communication time is simple: it is the number of bits in
the transmission multiplied by the SPI clock period being
used. The control protocol of the LTC6812-1 is very uniform
so almost all commands can be categorized as a write,
read or an operation. Table 59 can be used to determine
the number of bits in a given LTC6812-1 command.
ENHANCED APPLICATIONS
Using the LTC6812-1 with Fewer than 15 Cells
Cells can be connected in a conventional bottom (C1) to
top (C15) sequence with all unused C inputs either shorted
to the highest connected cell or left open. The unused S
pins can simply be left unconnected.
Alternatively, to optimize measurement synchronization
in applications with fewer than fifteen cells, the unused
C pins may be equally distributed between the top of the
third MUX (C15), the top of the second MUX (C10) and
the top of the first MUX (C5). See Figure47. If the number
of cells being measured is not a multiple of three, the top
MUX(es) should have fewer cells connected. The unused
cell inputs should be tied to the other unused inputs on
the same MUX and then connected to the battery stack
through a 100Ω resistor. The unused inputs will result in
a reading of 0.0V for those cells.
Current Measurement with a Hall-Effect Sensor
The LTC6812-1 auxiliary ADC inputs (GPIO pins) may
be used for any analog signal, including active sensors
with 0V to 5V analog outputs. For battery current mea-
surements, Hall-effect sensors provide an isolated, low
power solution. Figure48 shows schematically a typical
Hall-effect sensor that produces two outputs that propor-
tion to the VCC provided. The sensor in Figure48 has two
bidirectional outputs centered at half of VCC. CH1 is a 0A
to 50A low range and CH2 is a 0A to 200A high range. The
sensor is powered from a 5V source and produces analog
outputs that are connected to GPIO pins or inputs of the
Table 59. Daisy Chain Serial Time Equations
COMMAND TYPE
CMD BYTES
+ CMD PEC
DATA BYTES
+ DATA PEC PER IC TOTAL BITS COMMUNICATION TIME
Read 4 8 (4 + (8 • #ICs)) • 8 Total Bits • Clock Period
Write 4 8 (4 + (8 • #ICs)) • 8 Total Bits • Clock Period
Operation 4 0 4 • 8 = 32 32 • Clock Period
LTC6812-1
86
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure47. Cell Connection Schemes for 12 Cells
V+
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V–
LTC6812-112-CELL
MODULE
NEXT HIGHER GROUP
OF 12 CELLS
NEXT LOWER GROUP
OF 12 CELLS
V+
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V–
LTC6812-112-CELL
MODULE
NEXT HIGHER GROUP
OF 12 CELLS
NEXT LOWER GROUP
OF 12 CELLS
68121 F47
Figure48. Interfacing a Typical Hall-Effect Battery Current Sensor to Auxiliary ADC Inputs
68121 F48
LEM DHAB
CH2 ANALOG → GPIO2
VCC 5V
GND ANALOG_COM → V
–
CH1 ANALOG0 → GPIO1
A
B
C
D
LTC6812-1
87
Rev. A
For more information www.analog.com
MUX application shown in Figure50. The use of GPIO1
and GPIO2 as the ADC inputs has the possibility of being
digitized within the same conversion sequence as the cell
inputs (using the ADCVAX command), thus synchronizing
cell voltage and cell current measurements.
READING EXTERNAL TEMPERATURE PROBES
Figure49 shows the typical biasing circuit for a negative
temperature coefficient (NTC) thermistor. The 10k at 25°C
is the most popular sensor value and the VREF2 output
stage is designed to provide the current required to bias
several of these probes. The biasing resistor is selected
to correspond to the NTC value so the circuit will provide
1.5V at 25°C (VREF2 is 3V nominal). The overall circuit
response is approximately –1%/°C in the range of typical
cell temperatures, as shown in the chart of Figure49.
Expanding the Number of Auxiliary Measurements
The LTC6812-1 has nine GPIO pins that can be used as ADC
inputs. In applications that need to measure more than nine
signals, a multiplexer (MUX) circuit can be implemented
APPLICATIONS INFORMATION
Figure49. Typical Temperature Probe Circuit and
Relative Output
to expand the analog measurements to sixteen different
signals (Figure 50). The GPIO1 ADC input is used for
measurement and MUX control is provided by the I2C port
on GPIO 4 and 5. The buffer amplifier was selected for
fast settling and will increase the usable throughput rate.
Figure50. MUX Circuit Supports Sixteen Additional Analog Measurements
TEMPERATURE (°C)
–40 0
VTEMPx (% VREF2)
100
80
60
40
20
90
70
50
30
10
0–20 20 6040 80
68121 F49
10k
NTC
10k AT 25°C
V–
VREF2
VTEMP
S1
S2
S3
S4
S5
S6
S7
S8
VDD
GND
A0
A1
SCL
SDA
D
RESET
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
ADG728
S1
S2
S3
S4
S5
S6
S7
S8
VDD
GND
A0
A1
SCL
SDA
D
RESET
ANALOG9
ANALOG10
ANALOG11
ANALOG12
ANALOG13
ANALOG14
ANALOG15
ANALOG16
ADG728
1µF
10nF
68121 F50
VREG
GPIO5
GPIO4
V–
GPIO1
LTC6812-1
20k
20k
–
+
LTC6255 100Ω
ANALOG INPUTS: 0.04V TO 4.5V
LTC6812-1
88
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
LWE64 LQFP 0416 REV A
0° – 7°
11° – 13°
0.45 – 0.75
1.00 REF
11° – 13°
1
64
1.60
MAX
1.35 – 1.45
0.05 – 0.150.09 – 0.20 0.50
BSC 0.17 – 0.27
GAUGE PLANE
0.25
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND
MAX 0.50mm (20 MILS) ON ANY SIDE OF THE EXPOSED PAD, MAX 0.77mm
(30 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
R0.08 – 0.20
10.15 – 10.25
7.50 REF
7.50 REF
10.15 – 10.25
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
SIDE VIEW
SECTION A – A
0.50 BSC
1.30 MIN
0.20 – 0.30
12.00 BSC
10.00 BSC
5.74 ±0.10
5.74 ±0.05
5.74 ±0.05
5.74 ±0.10
49
1732
48
3316
481
3217
4964
33
33
48
4964
3217
1
16
C0.30 – 0.50
LWE Package
64-Lead Plastic Exposed Pad LQFP (10mm × 10mm)
(Reference LTC DWG #05-08-1982 Rev A)
16
SEE NOTE: 3
10.00 BSC
12.00 BSC
PACKAGE OUTLINE
A A
LTC6812-1
89
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/19 Added AEC-Qualification Indicator
Order Information Updated Format
Renamed Sum of Cells to “Sum of All Cells”
Updated isoSPI related typical performance characteristics
Note added regarding pin functions denoted as “NC”
Rewrite to section entitled “CORE LTC6812-1 STATE DESCRIPTIONS”
Rewrite to section entitled “ADC Conversion with Digital Redundancy”
Rewrite to section entitled “Thermal Shutdown”
Rewrite to section entitled “WATCHDOG AND DISCHARGE TIMER”
Added new section entitled “RESET BEHAVIORS”
Correction to Table 37, section CH[2:0], conversion times for All Cells
Rewrite to section entitled “Implementing a Modular isoSPI Daisy Chain”
Update to Table 57. Recommended Transformers
Rewrite to section entitled “Related Parts”
1
3
4, 5, 25-27, 65
13
15
18–19
27
31
32
33
59
77
81
86
LTC6812-1
90
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2018–2019
10/19
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC6810-1/
LTC6810-2 4th Generation 6-Cell Battery Stack
Monitor and Balancing IC Measures Cell Voltages for Up to 6 Series Battery Cells. Daisy-Chain Capability Allows
Multiple Devices to Be Connected to Measure Many Battery Cells Simultaneously. The isoSPI
Bus Can Operate Up to 1MHz and Can Be Operated Bidirectionally for Fault Conditions, Such
As a Broken Wire or Connector. Includes Internal Passive Cell Balancing of up to 150mA.
LTC6811-1/
LTC6811-2 4th Generation 12-Cell Battery Stack
Monitor and Balancing IC Measures Cell Voltages for Up to 12 Series Battery Cells. Daisy-Chain Capability Allows
Multiple Devices to Be Connected to Measure Many Battery Cells Simultaneously Via the
Built-In 1MHz, 2-Wire Isolated Communication (isoSPI). Includes Capability for Passive Cell
Balancing.
LTC6813-1 4th Generation 18-Cell Battery Stack
Monitor and Balancing IC Measures Cell Voltages for Up to 18 Series Battery Cells. The isoSPI Daisy-Chain
Capability Allows Multiple Devices to be Interconnected for Measuring Many Battery Cells
Simultaneously. The isoSPI Bus can Operate Up to 1MHz and can be Operated Bidirectionally
for Fault Conditions, such as a Broken Wire or Connector. Includes Internal Passive Cell
Balancing Capability of Up to 200mA.
LTC6820 isoSPI Isolated Communications
Interface Provides an Isolated Interface for SPI Communication Up to 100 Meters, Using a Twisted
Pair. Companion to the LTC6804, LTC6806, LTC6811, LTC6812 and LTC6813.
68121 TA02
+
+
+
+
•
•
V+
C15
S15
C14
S14
C2
S2
C1
S1
C0
V–
DRIVE
VREG
VREF1
VREF2
IPB
IMB
IPA
IMA
IBIAS
ICMP
ISOMD
LTC6812-1
1k 1k
•
•
100Ω
100Ω
1μF
1μF
1μF
NPN
100Ω
100Ω
100nF
10Ω
33Ω
100nF
10Ω
33Ω
100nF
10Ω
33Ω
100nF
10Ω
33Ω
100nF
C15
3.7V
C14
3.7V
C2
3.7V
C1
3.7V
10Ω
CELL3
TO CELL13
CIRCUITS
10nF
VREG