SL74HC132 Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High-Performance Silicon-Gate CMOS The SL74HC132 is identical in pinout to the LS/ALS132. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC132 can be used to enhance noise immunity or to square up slowly changing waveforms. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC132N Plastic SL74HC132D SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor Output A B Y L L H L H H H L H H H L SL74HC132 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin 20 mA DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 C 260 C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 C - no limit* ns When VIN 0.5VCC, ICC> > quiescent current. * This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC132 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 C to -55C 85 C 125 C Unit VT+max Maximum PositiveGoing Input Threshold Voltage VOUT=0.1 V IOUT 20 A 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VT+min Minimum PositiveGoing Input Threshold Voltage VOUT=0.1 V IOUT 20 A 2.0 4.5 6.0 1.0 2.3 3.0 0.95 2.25 2.95 0.95 2.25 2.95 V VT-max Maximum NegativeGoing Input Threshold Voltage VOUT=VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 0.9 2.0 2.6 0.95 2.05 2.65 0.95 2.05 2.65 V VT-min Minimum NegativeGoing Input Threshold Voltage VOUT=VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VHmax Note Maximum Hysteresis Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 1.2 2.25 3.0 1.2 2.25 3.0 1.2 2.25 3.0 V VHmin Note Minimum Hysteresis Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 0.2 0.4 0.5 0.2 0.4 0.5 0.2 0.4 0.5 V VOH Minimum High-Level Output Voltage VINVT-min or VT+max Iout 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN VT+max IOUT 4.0 mA IOUT 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VINVT-min or VT+max IOUT 4.0 mA IOUT 5.2 mA VOL Maximum Low-Level Output Voltage VIN VT+max IOUT 20 A V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0A 6.0 1.0 10 40 A Note. VHmin>(VT+min)-(VT-max); VHmax=(VT+max)+(VT-min). SLS System Logic Semiconductor SL74HC132 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 C to -55C 85C 125C Unit tPLH, t PHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF CIN Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) CPD Typical @25C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC * Figure 1. Switching Waveforms 24 pF Includes all probe and jig capacitance. Figure 2. Test Circuit SLS System Logic Semiconductor