54ABT16500
18-Bit Universal Bus Transceivers with TRI-STATE®
Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the high-to-low transition of
CLKAB. Output-enable OEAB is active-high. When OEAB is
high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The output enables are complementary
(OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
nCombines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
nFlow-through architecture optimizes PCB layout
nGuaranteed latch-up protection
nHigh impedance glitch free bus loading during entire
power up and power down cycle
nNon-destructive hot insertion capability
nStandard Microcircuit Drawing (SMD) 5962-9687001
Ordering Code
Military Package Package Description
Number
54ABT16500W-QML WA56A 56-Lead Cerpack
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
July 1998
54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs
© 2004 National Semiconductor Corporation DS100225 www.national.com
Connection Diagram
Function Table (Note 1)
Inputs Output
B
OEAB LEAB CLKAB A
LX X X Z
HH X L L
HH X H H
HL ↓LL
HL ↓HH
HL H XB
0
(Note 2)
HL L XB
0
(Note 3)
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions were established.
Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
Pin Assignment for Cerpack
DS100225-1
54ABT16500
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Logic Diagram
DS100225-2
54ABT16500
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Absolute Maximum Ratings (Note 4)
Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias
Ceramic −55˚C to +175˚C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 4) −0.5V to +7.0V
Input Current (Note 4) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-off State −0.5V to 5.5V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military −55˚C to +125˚C
Supply Voltage
Military +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Note 4: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol Parameter ABT16500 Units VCC Conditions
Min Typ Max
VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized LOW Signal
VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
VOH Output HIGH Voltage 54ABT 2.5 V Min IOH =−3mA
54ABT 2.0 V Min IOH = −24 mA
VOL Output LOW Voltage 54ABT 0.55 V Min IOL =48mA
IIH Input HIGH Current 5 µA Max VIN = 2.7V (Note 6)
5V
IN =V
CC
IBVI Input HIGH Current Breakdown Test 7 µA Max VIN = 7.0V
IIL Input LOW Current −5 µA Max VIN = 0.5V (Note 6)
−5 VIN = 0.0V
VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA
All Other Pins Grounded
IIH + Output Leakage Current 50 µA 0 − 5.5V VOUT = 2.7V; OE, OE = 2.0V
IOZH
IIL + Output Leakage Current −50 µA 0 − 5.5V VOUT = 0.5V; OE, OE = 2.0V
IOZL
IOS Output Short-Circuit Current −100 −275 mA Max VOUT =0V
ICEX Output High Leakage Current 50 µA Max VOUT =V
CC
IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND
ICCH Power Supply Current 1.0 mA Max All Outputs HIGH
ICCL Power Supply Current 68 µA Max An or Bn Outputs Low
ICCZ Power Supply Current 1.0 mA Max OEn=V
CC,
All Others at VCC or GND
ICCT Additional ICC/Input 2.5 mA Max VI=V
CC − 2.1V
All Others at VCC or GND
ICCD Dynamic ICC No Load mA/ Max Outputs Open
(Note 6) 0.23 MHz Transparent Mode
One Bit Toggling, 50% Duty Cycle
Note 6: Guaranteed, but not tested.
DC Electrical Characteristics
Symbol Parameter Min Max Units V
CC
Conditions
C
L
= 50 pF; R
L
=
500Ω
V
OLP
Quiet Output Maximum Dynamic V
OL
1.1 V 5.0 T
A
= 25˚C (Note 7)
54ABT16500
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DC Electrical Characteristics (Continued)
Symbol Parameter Min Max Units V
CC
Conditions
C
L
= 50 pF; R
L
=
500Ω
V
OLV
Quiet Output Minimum Dynamic V
OL
-1.7 V 5.0 T
A
= 25˚C (Note 7)
Note 7: Max number of outputs defined as (n).n−1data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
AC Electrical Characteristics
Symbol Parameter 54ABT Units Fig.
No.
T
A
= −55˚C to +125˚C
V
CC
= 4.5V–5.5V
C
L
=50pF
Min Max
f
max
Maximum Clock Frequency 150 MHz
t
PLH
Propagation Delay 1.0 6.5 ns Figure 4
t
PHL
AorBtoBorA 1.0 7.0
t
PLH
Propagation Delay 1.0 7.0 ns Figure 4
t
PHL
LEAB or LEBA to B or A 1.0 7.8
t
PLH
Propagation Delay 1.0 7.5 ns Figure 4
t
PHL
CLKAB or CLKBA to B or A 1.0 8.0
t
PZH
Propagation Delay 1.0 6.3 ns Figure 6
t
PZL
OEAB or OEBA to B or A 1.0 6.5
t
PHZ
Propagation Delay 1.0 7.2 ns Figure 6
t
PLZ
OEAB or OEBA to B or A 1.0 6.8
AC Operating Requirements
Symbol Parameter 54ABT Units Fig.
No.
T
A
= −55˚C to +125˚C
V
CC
= 4.5V–5.5V
C
L
=50pF
Min Max
t
s
(H) Setup Time, 4.5 ns Figure 7
t
s
(L) A to CLKAB 4.5
t
h
(H) Hold Time, 0 ns Figure 7
t
h
(L) A to CLKAB 0
t
s
(H) Setup Time, 4.0 ns Figure 7
t
s
(L) B to CLKBA 4.0
t
h
(H) Hold Time, 0 ns Figure 7
t
h
(L) B to CLKBA 0
t
s
(H) Setup Time, A to LEAB 1.5 ns Figure 7
t
s
(L) or B to LEBA, CLK High 1.5
t
h
(H) Hold Time, A to LEAB 1.5 ns Figure 7
t
h
(L) or B to LEBA, CLK High 1.5
t
s
(H) Setup Time, A to LEAB 4.5 ns Figure 7
t
s
(L) or B to LEBA, CLK Low 4.5
t
h
(H) Hold Time, A to LEAB 1.5 ns Figure 7
t
h
(L) or B to LEBA, CLK Low 1.5
t
w
(H) Pulse Width, 3.3 ns Figure 5
t
w
(L) LEAB or LEBA, High 3.3
54ABT16500
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AC Operating Requirements (Continued)
Symbol Parameter 54ABT Units Fig.
No.
T
A
= −55˚C to +125˚C
V
CC
= 4.5V–5.5V
C
L
=50pF
Min Max
t
w
(H) Pulse Width, CLKAB 3.3 ns Figure 5
t
w
(L) or CLKBA, High or Low 3.3
Capacitance
Symbol Parameter Typ Units Conditions, T
A
= 25˚C
C
IN
Input Capacitance 5.0 pF V
CC
= 0.0V
C
I/O
(Note 8) Output Capacitance 11.0 pF V
CC
= 5.0V
Note 8: CI/O is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012.
54ABT16500
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AC Loading
DS100225-3
*Includes jig and probe capacitance.
FIGURE 1. Standard AC Test Load
DS100225-5
FIGURE 2. V
M
= 1.5V
Input Pulse Requirements
Amplitude Rep. Rate t
W
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100225-7
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
DS100225-4
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100225-6
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100225-8
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
54ABT16500
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Physical Dimensions inches (millimeters) unless otherwise noted
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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56-Lead Cerpack
NS Package Number WA56A
54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
