NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 32Mx8 SDRAM
Features
• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
• Performance :
PC1600
PC2100
Speed Sort - 8B - 75B
- 7K
DIMM CAS Latency 2 2.5 2 Unit
f CK
Clock Frequency 100 133 133 MHz
t CK
Clock Cycle 10 7.5 7.5 ns
f DQ
DQ Burst Frequency 200 266 266 MHz
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/2 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
Description
NT256D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number Speed Organization Leads Power
143MHz (7ns @ CL = 2.5 )
NT256D64S88A0G-7K 133MHz (7.5ns @ CL= 2 ) PC2100
133MHz (7.5ns @ CL= 2.5 )
NT256D64S88A0G –75B
100MHz (10ns @ CL = 2 ) PC2100
125MHz (8ns @ CL = 2.5 )
NT256D64S88A0G –8B 100MHz (10ns @ CL = 2 ) PC1600
32Mx64 Gold 2.5V
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 2
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Description
CK0, CK1, CK2
CK0 ,CK1,CK2
Differential Clock Inputs DQ0-DQ63 Data input/output
CKE0 Clock Enable
RAS Row Address Strobe DQS0-DQS7,
DQS9-DQS16 Bidirectional data strobes
CAS Column Address Strobe VDD Power (2.5V)
WE Write Enable VDDQ Supply voltage for DQs(2.5V)
S0 Chip Selects VSS Ground
A0-A9, A11,A12 Address Inputs NC No Connect
A10/AP Address Input/Autoprecharge SCL Serial Presence Detect Clock Input
BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output
VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs
VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply(2.5V)
Pinout
Pin
Front Pin
Back Pin
Front Pin
Back Pin
Front Pin
Back
1 VREF 93 VSS 32 A5 124
VSS 62 VDDQ 154
RAS
2 DQ0 94 DQ4 33 DQ24 125
A6 63 WE 155
DQ45
3 VSS 95 DQ5 34 VSS 126
DQ28 64 DQ41 156
VDDQ
4 DQ1 96 VDDQ 35 DQ25 127
DQ29 65 CAS 157
S0
5 DQS0 97 DQS9 36 DQS3 128
VDDQ 66 VSS 158
NC
6 DQ2 98 DQ6 37 A4 129
DQS12 67 DQS5 159
DQS14
7 VDD 99 DQ7 38 VDD 130
A3 68 DQ42 160
VSS
8 DQ3 100
VSS 39 DQ26 131
DQ30 69 DQ43 161
DQ46
9 NC 101
NC 40 DQ27 132
VSS 70 VDD 162
DQ47
10 NC 102
NC 41 A2 133
DQ31 71 NC 163
NC
11 VSS 103
NC 42 VSS 134
NC 72 DQ48 164
VDDQ
12 DQ8 104
VDDQ 43 A1 135
NC 73 DQ49 165
DQ52
13 DQ9 105
DQ12 44 NC 136
VDDQ 74 VSS 166
DQ53
14 DQS1 106
DQ13 45 NC 137
CK0 75 CK2 167
NC
15 VDDQ 107
DQS10 46 VDD 138
CK0 76 CK2 168
VDD
16 CK1 108
VDD 47 NC 139
VSS 77 VDDQ 169
DQS15
17 CK1 109
DQ14 48 A0 140
NC 78 DQS6 170
DQ54
18 VSS 110
DQ15 49 NC 141
A10 79 DQ50 171
DQ55
19 DQ10 111
NC 50 VSS 142
NC 80 DQ51 172
VDDQ
20 DQ11 112
VDDQ 51 NC 143
VDDQ 81 VSS 173
NC
21 CKE0 113
NC 52 BA1 144
NC 82 VDDID 174
DQ60
22 VDDQ 114
DQ20 KEY KEY 83 DQ56 175
DQ61
23 DQ16 115
A12 53 DQ32 145
VSS 84 DQ57 176
VSS
24 DQ17 116
VSS 54 VDDQ 146
DQ36 85 VDD 177
DQS16
25 DQS2 117
DQ21 55 DQ33 147
DQ37 86 DQS7 178
DQ62
26 VSS 118
A11 56 DQS4 148
VDD 87 DQ58 179
DQ63
27 A9 119
DQS11 57 DQ34 149
DQS13 88 DQ59 180
VDDQ
28 DQ18 120
VDD 58 VSS 150
DQ38 89 VSS 181
SA0
29 A7 121
DQ22 59 BA0 151
DQ39 90 NC 182
SA1
30 VDDQ 122
A8 60 DQ35 152
VSS 91 SDA 183
SA2
31 DQ19 123
DQ23 61 DQ40 153
DQ44 92 SCL 184
VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Input/Output Functional Description
Symbol Type Polarity
Function
CK0 , CK1, CK2 (SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inp
uts are sampled on the rising
edge of their associated clocks.
CK0 ,CK1,CK2 (SSTL)
Negative
Edge
The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.
CKE0 (SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating
the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
S0 (SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
RAS ,CAS ,WE (SSTL)
Active
Low When sampled at the positive rising edge of the clock, RAS ,CAS ,WE
define the
operation to be executed by the SDRAM.
VREF Supply
Reference voltage for SSTL-2 inputs
VDDQ Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
BA0, BA1 (SSTL)
- Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11,A12 (SSTL)
-
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12
)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9
)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation
at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to contro
l
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63, (SSTL)
- Data and Check Bit input/output pins operate in the
same manner as on conventional
DRAMs.
DQS0 - DQS7
DQS9 - DQS16 (SSTL)
Active
High
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
VDD , VSS Supply
Power and ground for the DDR SDRAM input buffers and core logic
SA0 – SA2 - Address inputs. Connected to either VDD or VSS
on the system board to configure the
Serial Presence Detect EEPROM address.
SDA - This bidirectional pin is used to transfer data into or out
of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pullup.
SCL -
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pullup.
V DDSPD Supply
Serial EEPROM positive power supply.
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Functional Block Diagram ( 1 Bank, 32Mx8 DDR SDRAMs )
S0
DQS9
DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11
S0
A0-A12
RAS
BA0-BA1
CS : SDRAMs D0 -D7
BA0 - BA1 : SDRAMs D0 -D7
A0 - A12: SDRAMs D0 -D7
RAS : SDRAMs D0 -D7
DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D3
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D2
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D4
VDDQ
VSS
D0 - D7
Serial PD
A0 A2A1
SCL
WP SDA
SA0 SA2SA1
DQS0 DQS13
DQS4
DQS
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D0
DQS
DQS10
DQS1
DQS
DQS11
DQS2
DQS12
DQS3
DQS
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35
DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D1
DQS I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D5
DQS
DQS5
DQS14
DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D6
DQS
DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM CS
D7
DQS
DQS6
DQS15
DQS7
DQS16
CKE0
WE
CAS CAS : SDRAMs D0 -D7
CKE0 : SDRAMs D0 -D7
WE : SDRAMs D0 -D7
120 ohm SDRAM x 2
CK0
CK0
120 ohm SDRAM x 3
CK1
CK1
120 ohm SDRAM x 3
CK2
CK2
D0 - D7
D0 - D7
D0 - D7
VDD
VREF
VDDID
Notes :1. DQ-to-I/O wring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
Strap: see Note 4
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value Serial PD Data Entry (Hexadecimal)
Note
Byte Description DDR266A
-7K DDR266B
-75B DDR200
-8B DDR266A
-7K DDR266B
-75 DDR200
-8B
0 Number of Serial PD Bytes Written during
Production 128 80
1 Total Number of Bytes in Serial PD device 256 08
2 Fundamental Memory Type SDRAM DDR 07
3 Number of Row Addresses on Assembly 13 0D
4 Number of Column Addresses on Assembly 10 0A
5 Number of DIMM Bank 1 01
6. Data Width of Assembly X64 40
7 Data Width of Assembly (cont’) X64 00
8 Voltage Interface Level of this Assembly SSTL 2.5V 04
9 DDR SDRAM Device Cycle Time at CL=2.5 7ns 7.5ns 8ns 70 75 80
10 DDR SDRAM Device Access Time from
Clock at CL=2.5 0.75ns 0.75ns 0.8ns 75 75 80
11 DIMM Configuration Type Non-Parity 00
12 Refresh Rate/Type SR/1x(7.8us) 82
13 Primary DDR SDRAM Width X8 08
14 Error Checking DDR SDRAM Device Width N/A 00
15 DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access 1 Clock 01
16 DDR SDRAM Device Attributes:
Burst Length Supported 2,4,8 0E
17 DDR SDRAM Device Attributes: Number of
Device Banks 4 04
18 DDR SDRAM Device Attributes: CAS
Latencies Supported 2/2.5 2/2.5 2/2.5 0C 0C 0C
19 DDR SDRAM Device Attributes: CS Latency
0 01
20 DDR SDRAM Device Attributes: WE Latency
1 02
21 DDR SDRAM Device Attributes: Differential Clock 20
22 DDR SDRAM Device Attributes: General +/-0.2V Voltage Tolerance 00
23 Minimum Clock Cycle at CL=2 7.5ns 10ns 10ns 75 A0 A0
24 Maximum Data Access Time from Clock at
CL=2 0.75ns 0.75ns 0.8ns 75 75 80
25 Minimum Clock Cycle Time at CL=1 N/A 00
26 Maximum Data Access Time from Clock at
CL=1 N/A 00
27 Minimum Row Precharge Time(tRP) 20ns 20ns 20ns 50 50 50
28 Minimum Row Active to Row Active delay
(tRRD) 15ns 15ns 15ns 3C 3C 3C
29 Minimum RAS to CAS delay (tRCD) 20ns 20ns 20ns 50 50 50
30 Minimum RAS Pulse Width (tRAS) 45ns 45ns 50ns 2D 2D 32
31 Module Bank Density 256MB 40
32 Address and Command Setup Time Before
Clock 0.9ns 0.9ns 1.1ns 90 90 B0
33 Address and Command Hold Time After
Clock 0.9ns 0.9ns 1.1ns 90 90 B0
34 Data Input Setup Time Before Clock 0.5ns 0.5ns 0.6ns 50 50 60
35 Data Input Hold Time After Clock 0.5ns 0.5ns 0.6ns 50 50 60
36-61
Reserved Undefined 00
62 SPD Revision Initial Initial Initial 00 00 00
63 Checksum Data 8F BF 45
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 2 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value Serial PD Data Entry (Hexadecimal)
Byte Description DDR266A
-7K DDR266B
-75B DDR200
-8B DDR266A
-7K DDR266B
-75 DDR200
-8B Note
64-71
Manufacturer’s JEDED ID Code 0B 7F7F7F0B00000000
72 Module Manufacturing Location N/A 00
73-90
Module Part number N/A N/A N/A 00 00 00
91-92
Module Revision Code N/A 00
93-94
Module Manufacturing Data Year/Week Code yy/ww 1,2
95-98
Module Serial Number Serial Number 00
99-255
Reserved Undefined 00
1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 7
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Absolute Maximum Ratings
Symbol Parameter Rating Units
VIN, VOUT Voltage on I/O pins relative to Vss -0.5 to VDDQ+0.5 V
VIN Voltage on Input relative to Vss -0.5 to +3.6 V
VDD Voltage on VDD supply relative to Vss -0.5 to +3.6 V
VDDQ Voltage on VDDQ supply relative to Vss -0.5 to +3.6 V
TA Operating Temperature (Ambient) 0 to+70 °C
TSTG Storage Temperature (Plastic) -55 to +150 °C
PD Power Dissipation 8 W
IOUT Short Circuit Output Current 50 mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter Symbol Max. Units Notes
Input Capacitance: CK0, CK0 , CK1, CK1, CK2,CK2 CI1 12 pF 1
Input Capacitance: A0-A11, BA0, BA1, WE,RAS ,CAS , CKE0, S0 CI2 30 pF 1
Input Capacitance: SA0-SA2, SCL CI4 9 pF 1
Input/Output Capacitance DQ0-63; DQS0-7, 9-16 CIO1 7 pF 1,2
Input/Output Capacitance: SDA CIO3 11 pF
1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V.
2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at
the board level.
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 8
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DC Electrical Characteristics and Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol Parameter Min Max Units Notes
VDD Supply Voltage 2.3 2.7 V 1
VDDQ I/O Supply Voltage 2.3 2.7 V 1
VSS , VSSQ
Supply Voltage, I/O Supply Voltage 0 0 V
VREF /O Reference Voltage 0.49 x VDDQ
0.51 x VDDQ
V 1,2
VTT I/O Termination Voltage (System) VREF – 0.04
VREF + 0.04
V 1,3
VIH(DC) Input High (Logic1) Voltage VREF + 0.15
VDDQ + 0.3
V 1
VIL(DC) Input Low (Logic0) Voltage -0.3 VREF- 0.15
V 1
VIN(DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3
V 1
VID(DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6
V 1,4
II Input Leakage Current
Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) -5 5 uA 1
IOZ Output Leakage Current
(DQs are disabled; 0V ≤ Vout ≤ VDDQ -5 5 uA 1
IOH Output High Current
(VOUT = VDDQ -0.373V, min VREF , min VTT ) -16.8 - mA 1
IOL Output Low Current
(VOUT = 0.373, max VREF , max VTT ) 16.8 - mA 1
1. Inputs are not recognized as valid until V REF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,
and must track variations in the DC level of V REF .
4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V SS .
2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I DD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC) unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.
AC Output Load Circuits
Timing Reference Point
V
TT
50 ohms
30 pF
Output
V
OUT
AC Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition Min Max Unit Notes
VIH(AC)
Input High (Logic 1) Voltage. V REF + 0.31 V 1, 2
VIL(AC)
Input Low (Logic 0) Voltage. V REF ?- 0.31 V 1, 2
VID(AC)
Input Differential Voltage, CK and CK Inputs 0.62 V DDQ + 0.6 V 1, 2, 3
VIX(AC)
Input Differential Pair Cross Point Voltage, CK andCK Inputs (0.5*VDDQ ) - 0.2
(0.5*VDDQ ) +? 0.2
V 1, 2, 4
1. Input slew rate = 1V/ ns .
2. Inputs are not recognized as valid until V REF stabilizes.
3. V ID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 10
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition PC1600 PC2100 Unit Notes
I DD0 Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;
tCK = tCK (MIN)
; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle 600 680 mA 1,2
I DD1 Operating Current : one bank; active / read / precharge; Burst = 2;
tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;
address and control inputs changing once per clock cycle 720 880 mA 1,2
I DD2P
Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN) 120 120 mA 1,2
I DD2N
Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE ≥ VIH(MIN) ;
tCK = tCK (MIN) ; address and control inputs changing once per clock cycle 240 280 mA 1,2
I DD3P
Active Power-Down Standby Current : one bank active;
power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN) 120 120 mA 1,2
I DD3N
Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;
CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS
inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
400 480 mA 1,2
I DD4R
Operating Current : one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
tCK = tCK (MIN) ; IOUT = 0mA
1040 1320 mA 1,2
I DD4W
Operating Current : one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
tCK = tCK (MIN)
920 1200 mA 1,2
t RC = t RFC (MIN) 1280 1360 mA 1,2
I DD5 Auto-Refresh Current : t RC = 7.8 µs 132 132 mA 1,2,4
I DD6 Self-Refresh Current : CKE ≤ ?0.2V 16 16 mA 1,2,3
1. I DD specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns .
3. Enables on-chip refresh and address counters.
4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
-7K -75B -8B
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
Notes
tAC DQ output access time from CK/ CK -0.75 +0.75
-0.75 +0.75
-0.8 +0.8 ns 1,2,3,4
tDQSCK DQS output access time from CK/CK -0.75 +0.75
-0.75 +0.75
-0.8 +0.8 ns 1,2,3,4
tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1,2,3,4
tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1,2,3,4
tCK CL=2.5 7 12 7.5 12 8 12 ns 1,2,3,4
tCK Clock cycle time CL=2 7.5 12 10 12 10 12 ns 1,2,3,4
tDH DQ and DM input hold time 0.5 0.5 0.6 ns 1,2,3,4
,15,16
tDS DQ and DM input setup time 0.5 0.5 0.6 ns 1,2,3,4
,15,16
tDIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1,2,3,4
tHZ Data-out high-impedance time from
CK/ CK -0.75 +0.75
-0.75 +0.75
-0.8 +0.8 ns 1, 2, 3,
4, 5
tLZ Data-out low-impedance time from
CK/CK -0.75 +0.75
-0.75 +0.75
-0.8 +0.8 ns 1, 2, 3,
4, 5
tDQSQ DQS-DQ skew (DQS & associated DQ
signals) 0.5 0.5 0.6 ns 1,2,3,4
tDQSQA DQS-DQ skew (DQS & all DQ signals) 0.5 0.5 0.6 ns 1,2,3,4
tHP Minimum half clk period for any given
cycle; defined by clk high(tCH )
or clk low (tCL ) time
tCH
or
tCL tCH
or
tCL tCH
or
tCL tCK 1,2,3,4
tQH Data output hold time from DQS tHP -
0.75ns
tHP -
0.75ns
tHP -
1.0ns
tCK 1,2,3,4
tDQSS Write command to 1st DQS latching
transition 0.75 1.25 0.75 1.25 0.75 1.25 tCK 1,2,3,4
tDQSL,H DQS input low (high) pulse width
(write cycle) 0.35 0.35 0.35 tCK 1,2,3,4
tDSS DQS falling edge to CK setup time
(write cycle) 0.2 0.2 0.2 tCK 1,2,3,4
tDSH DQS falling edge hold time from CK
(write cycle) 0.2 0.2 0.2 tCK 1,2,3,4
tMRD Mode register set command cycle time 14 15 16 ns 1,2,3,4
tWPRES Write preamble setup time 0 0 0 ns 1, 2, 3,
4, 7
tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1, 2, 3,
4, 6
tWPRE Write preamble 0.25 0.25 0.25 tCK 1,2,3,4
tIH Address and control input hold time
(fast slew rate) 0.9 1.1 1.1 ns 2, 3, 4,
9, 11,
12
tIS Address and control input setup time
(fast slew rate) 0.9 1.1 1.1 ns 2, 3, 4,
9, 11,
12
tIH Address and control input hold time
(slow slew rate) 1.0 1.1 1.1 ns 2, 3, 4,
10, 11,
12, 14
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 12
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
-7K -75B -8B
Symbol
Parameter Min. Max. Min. Max. Min. Max. Unit
Notes
tIS Address and control input setup time
(slow slewrate) 1.0 1.0 1.1 ns 2, 3, 4,
10, 11,
12, 14
tIPW Input pulse width 2.2 2.2 - ns 2, 3, 4,
12
tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1,2,3,4
tRPST Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1,2,3,4
tRAS Active to Precharge command 45 120,000
45 120,000
50 120,000
ns 1,2,3,4
tRC Active to Active/Auto-refresh
command period 65 65 70 ns 1,2,3,4
tRFC Auto-refresh to Active/Auto-refresh
command period 75 75 80 ns 1,2,3,4
tRCD Active to Read or Write delay 20 20 20 ns 1,2,3,4
tRAP Active to Read Command with
Autoprecharge 20 20 20 ns 1,2,3,4
tRP Precharge command period 20 20 20 ns 1,2,3,4
tRRD Active bank A to Active bank B
command 15 15 15 ns 1,2,3,4
tWR Write recovery time 15 15 15 ns 1,2,3,4
tDAL Auto precharge write recovery +
precharge time
(tWR/
tCK )
+
(tRP/
tCK )
(tWR/
tCK )
+
(tRP /
tCK )
(tWR/
tCK )
+
(tRP /
tCK )
tCK 1, 2, 3,
4, 13
tWTR Internal write to read command delay 1 1 1 tCK 1,2,3,4
tXSNR Exit self-refresh to non-read
command 75 75 80 ns 1,2,3,4
tXSRD Exit self-refresh to read command 200 200 200 tCK 1,2,3,4
tREFI Average Periodic Refresh Interval 7.8 7.8 7.8 µs 1, 2, 3,
4, 8
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 13
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/ CK input reference level (for timing reference to CK/CK ) is the point at which CK and CK cross: the input reference level for
signals other than CK/ CK , is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS .
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
11. CK/ CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system
clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate ?Delta ( tIS ) Delta ( tIH ) Unit Note
0.5 V/ns 0 0 ps 1,2
0.4 V/ns +50 0 ps 1,2
0.3 V/ns +100 0 ps 1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly
for rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate Delta ( tDS ) Delta ( tDH ) Unit Note
0.5 V/ns 0 0 ps 1,2
0.4 V/ns +75 +75 ps 1,2
0.3 V/ns +150 +150 ps 1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for
rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate Delta ( tDS ) Delta ( tDH ) Unit Note
0.0 ns/V 0 0 ps 1,2,3,4
0.25 ns/V +50 +50 ps 1,2,3,4
0.5 ns/V +100 +100 ps 1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly
for rising transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Preliminary 08 / 2001 14
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Package Dimensions
Note : All dimensions are typical unless otherwise stated.
133.35
128.95
1.250
0.157
0.700
FRONT
Side
0.394
1.27+/- 0.10
Detail A
1.27 Pitch
Detail B
1.00 Width
2.59
Detail A Detail B
0.118
θ 2.50
3.80
1.80
6.35
5.25
5.077
3.0 (2x)4.00
17.80
31.75
10.0
0.098
0.102 max.
0.050 +/- 0.004
0.05
0.039
0.071
0.250
0.150
4.00
0.157
BACK
Unit :
Inches
Millimeters
