SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 * * * * SN54ALS996 . . . JT PACKAGE SN74ALS996 . . . DW OR NT PACKAGE (TOP VIEW) 3-State I/O-Type Read-Back Inputs Bus-Structured Pinout T/C Determines True or Complementary Data at Q Outputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs 1D 2D 3D 4D 5D 6D 7D 8D EN RD CLK GND description These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability. The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable (EN) input is low. Data can be read back onto the data inputs by taking the read (RD) input low, in addition to having EN low. When EN is high, both the read-back and write modes are disabled. Transitions on EN should only be made with CLK high to prevent false clocking. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE T/C CLR 3D 2D 1D NC VCC 1Q 2Q SN54ALS996 . . . FK PACKAGE (TOP VIEW) 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 4 4D 5D 6D NC 7D 8D EN 19 11 12 13 14 15 16 17 18 RD CLK GND NC CLR T/C OE The polarity of the Q outputs can be controlled by the polarity (T/C) input. When T/C is high, Q is the same as is stored in the flip-flops. When T/C is low, the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable (OE) input high. OE does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off. 3Q 4Q 5Q NC 6Q 7Q 8Q NC - No internal connection A low level at the clear (CLR) input resets the internal registers low. The clear function is asynchronous and overrides all other register functions. The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996. The SN54ALS996 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ALS996 is characterized for operation from 0C to 70C. Copyright 1995, Texas Instruments Incorporated !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. * DALLAS, TEXAS 75265 * HOUSTON, TEXAS 77251-1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2-1 SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 logic symbol 15 OE 14 T/C 13 CLR EN4 N3 R 10 & RD EN2 9 EN CLK 1D 1 11 1 C1 1D 3,4 2 2D 3D 4D 5D 6D 7D 8D 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. logic diagram (positive logic) OE T/C CLR RD EN CLK 1D 15 14 13 10 9 11 1 1D 23 C1 R To Seven Other Channels Pin numbers shown are for the DW, JT, and NT packages. 2-2 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1Q SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 timing diagram (T/C = H) CLR D II II II Input Data tsu Read-Back Data th tw CLK tdis ten tsu EN th tdis ten RD tp Q Output Output Data tdis ten OE Async Clear Write Read Back This hold time ensures that the read-back circuit will not create a conflict on the input data bus. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (OE, RD, EN, CLK, CLR, and T/C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C SN74ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 2-3 SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 recommended operating conditions SN54ALS996 VCC Supply voltage SN74ALS996 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 All inputs VIH High-level input voltage IOH All inputs except OE, RD 2 IOL Low-level output current 0.8 0.8 Q -1 -2.6 D -0.4 -0.4 12 24 48 8 8 Q D fclock Clock frequency tw Pulse duration tsu th Setup time Hold time 0 35 0 CLR low 10 10 CLK low 14.5 14.5 CLK high 14.5 14.5 Data before CLK 15 15 EN low before CLK 10 10 CLK high before EN 15 15 CLR high (inactive) before CLK 10 10 Data after CLK 1 0 EN low after CLK 5 5 RD high after CLK 5 5 TA Operating free-air temperature -55 Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V This setup time ensures that EN will not false clock the data register. This hold time ensures that there will be no conflict on the input data bus. 2-4 V 2.2 Low-level input voltage High-level output current V 2 OE, RD VIL UNIT MIN * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 125 0 35 V mA mA MHZ ns ns ns 70 C SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK SN54ALS996 TYP MAX TEST CONDITIONS MIN All outputs VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = - 18 mA IOH = - 0.4 mA Q VCC = 4.5 V IOH = - 1 mA IOH = - 2.6 mA VCC = 4.5 V IOL = 4 mA IOL = 8 mA 0.25 D VCC = 4.5 V IOL = 12 mA IOL = 24 mA IOL = 48 mA 0.25 Q Q VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V VCC = 5.5 V VI = 5.5 V VI = 7 V VCC = 5.5 V, VI = 2.7 V VCC = 5.5 V, VI = 0.4 V IO VCC = 5.5 V, CLR = 2.5 V VO = 2.25 V ICC VCC = 5.5 V, EN, RD low VOH VOL IOZH IOZL Q D inputs II IIH IIL All others D inputs All others D inputs All others SN74ALS996 TYP MAX MIN -1.2 VCC - 2 2.4 -1.2 UNIT V VCC - 2 3.2 V 2.4 -20 3.2 0.4 0.4 0.35 0.5 0.25 0.4 0.35 0.5 0.35 0.5 V 20 20 A -20 -20 A 0.1 0.1 0.1 0.1 20 20 20 20 -0.1 -0.1 -0.1 -0.1 -112 -30 -112 Outputs high 35 55 35 55 Outputs low 55 85 55 85 mA A A mA mA mA Outputs disabled 42 65 42 65 All typical values are at VCC = 5 V, TA = 25C. Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 2-5 SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, TA = MIN to MAX SN54ALS996 SN74ALS996 MIN fmax tPLH tPHL tPLH tPHL tPLH CLK (T/C = H or L) Q CLR (T/C = L) Q CLR (T/C = H) T/C Q CLR D RD D ten tdis EN D ten tdis OE Q tPHL tPHL ten tdis MAX 35 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * MAX 35 MHz 5 30 5 28 5 24 5 28 5 27 7 27 5 23 7 23 4 23 5 23 5 23 5 23 5 30 8 30 2 18 3 16 1 19 3 19 2 17 3 16 1 19 3 19 2 15 4 15 1 11 1 10 ns ns ns ns ns ns ns For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ten = tPZH or tPZL tdis = tPHZ or tPLZ 2-6 MIN UNIT SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V 7V S1 S1 500 1 k Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 LOAD CIRCUIT FOR Q OUTPUTS 1 k LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 3.5 V High-Level Pulse 1.3 V 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.3 V 1.3 V 0.3 V 3.5 V Output Control (low-level enabling) 1.3 V tPHL tPLH 1.3 V 1.3 V VOL tPLH tPHL Out-of-Phase Output (see Note B) Waveform 1 S1 Closed (see Note C) VOH tPLZ 1.3 V tPHZ Waveform 2 S1 Open (see Note C) 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES [3.5 V 1.3 V tPZH VOH 1.3 V 0.3 V tPZL 1.3 V 0.3 V In-Phase Output 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Input 3.5 V Low-Level Pulse 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. When measuring propagation delay times of 3-state outputs, switch S1 is open. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. Figure 1. Load Circuits and Voltage Waveforms * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 2-7 SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995 2-8 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) 5962-89945013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596289945013A SNJ54ALS 996FK 5962-8994501LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8994501LA SNJ54ALS996JT SN74ALS996-1DWR OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70 SN74ALS996-1NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996-1NT SN74ALS996-1NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996-1NT SN74ALS996DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996 SN74ALS996DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996 SN74ALS996DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996 SN74ALS996DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996 SN74ALS996DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996 SN74ALS996NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996NT SN74ALS996NT3 OBSOLETE PDIP NT 24 TBD Call TI Call TI 0 to 70 SN74ALS996NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SNJ54ALS996FK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596289945013A SNJ54ALS 996FK SNJ54ALS996JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8994501LA SNJ54ALS996JT SNJ54ALS996W OBSOLETE CFP W 24 TBD A42 N / A for Pkg Type -55 to 125 5962-8994501KA SNJ54ALS996W Addendum-Page 1 SN74ALS996NT Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF SN54ALS996, SN74ALS996 : * Catalog: SN74ALS996 * Military: SN54ALS996 NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS996DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS996DWR SOIC DW 24 2000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MCER004A - JANUARY 1995 - REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCFP007 - OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30 TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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