SN54ALS996 . . . JT PACKAGE
SN74ALS996 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54ALS996 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1D
2D
3D
4D
5D
6D
7D
8D
EN
RD
CLK
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE
T/C
CLR
NC − No internal connection
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3Q
4Q
5Q
NC
6Q
7Q
8Q
4D
5D
6D
NC
7D
8D
EN
426
14 15 16 17 18
RD
CLK
GND
NC
CLR
T/C
OE
3D
2D
1D
NC
1Q
2Q
VCC
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
•3-State I/O-Type Read-Back Inputs
•Bus-Structured Pinout
•T/C Determines True or Complementary
Data at Q Outputs
•Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These 8-bit latches are designed specifically for
storing the contents of the input data bus and
providing the capability of reading back the stored
data onto the input data bus. The Q outputs are
designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the
low-to-high transition of the clock (CLK) input
when the enable (EN) input is low. Data can be
read back onto the data inputs by taking the read
(RD) input low , in addition to having EN low. When
EN is high, both the read-back and write modes
are disabled. Transitions on EN should only be
made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by
the polarity (T/C) input. When T/C is high, Q is the
same as i s s t o red in the flip-flops. When T/C is low,
the output data is inverted. The Q outputs can be
placed in the high-impedance state by taking the
output-enable (O E ) input high. OE does not a ffect
the internal operation of the register. Old data can
be retained or new data can be entered while the
outputs are off.
A low level at the clear (CLR) input resets the
internal registers low. The clear function is
asynchronous and overrides all other register
functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum
IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS996 is characterized for operation from 0°C to 70°C.
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic symbol†
11
CLK
2D 2
3D 3
4D 4
5D 5
6D 6
7D 7
8D 8
5Q
19
6Q
18
7Q
17
8Q
16
2Q
22
3Q
21
4Q
20
1Q
23
1D
1
1D
9
EN
2
10
RD
R
13
CLR
N3
14
T/C
EN4
15
OE
3,4
&EN2
C1
≥1
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
logic diagram (positive logic)
To Seven Other Channels
15
23
OE
1Q
14
T/C
13
CLR
10
RD
1D
C1
R
9
EN
11
CLK
1
1D
Pin numbers shown are for the DW, JT, and NT packages.
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
timing diagram
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
(T/C = H)
CLR
D
EN
RD
Q
OE
Async
Clear Write
Input Data
Output
CLK
Read-Back Data
Output Data
Read
Back
tsu th
tw
tsu
tdis
tdis
tdis
tp
th†
ten
ten
ten
†This hold time ensures that the read-back circuit will not create a conflict on the input data bus.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (OE, RD, EN, CLK, CLR, and T/C) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to D inputs and to disabled 3-state outputs 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS996 −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS996 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
SN54ALS996 SN74ALS996
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
All inputs 2
V
IH
High-level input voltage All inputs except OE, RD 2V
VIH
High-level input voltage
OE, RD 2.2
V
VIL Low-level input voltage 0.8 0.8 V
IOH
High-level output current
Q−1 −2.6
mA
IOH High-level output current D−0.4 −0.4 mA
Q
12 24
I
OL
Low-level output current Q48†mA
IOL
Low-level output current
D 8 8
mA
fclock Clock frequency 0 35 0 35 MHZ
CLR low 10 10
t
w
Pulse duration CLK low 14.5 14.5 ns
tw
Pulse duration
CLK high 14.5 14.5
ns
Data before CLK↑15 15
tsu
Setup time
EN low before CLK↑10 10
ns
tsu Setup time CLK high before EN↑‡15 15 ns
CLR high (inactive) before CLK↑10 10
Data after CLK↑1 0
t
h
Hold time EN low after CLK↑5 5 ns
th
Hold time
RD high after CLK↑§5 5
ns
TAOperating free-air temperature −55 125 0 70 °C
†Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V
‡This setup time ensures that EN will not false clock the data register.
§This hold time ensures that there will be no conflict on the input data bus.
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS996 SN74ALS996
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V
All outputs VCC = 4.5 V to 5.5 V, IOH = − 0.4 mA VCC −2 VCC −2
V
OH
Q
VCC = 4.5 V
IOH = − 1 mA 2.4 3.2 V
VOH
QVCC = 4.5 V IOH = − 2.6 mA 2.4 3.2
V
D
VCC = 4.5 V
IOL = 4 mA 0.25 0.4
D VCC = 4.5 V IOL = 8 mA 0.35 0.5
V
OL
IOL = 12 mA 0.25 0.4 0.25 0.4 V
VOL
QV
CC
= 4.5 V IOL = 24 mA 0.35 0.5
V
Q
VCC = 4.5 V
IOL = 48 mA‡0.35 0.5
IOZH Q VCC = 5.5 V, VO = 2.7 V 20 20 µA
IOZL Q VCC = 5.5 V, VO = 0.4 V −20 −20 µA
II
D inputs
VCC = 5.5 V
VI = 5.5 V 0.1 0.1
mA
IIAll others VCC = 5.5 V VI = 7 V 0.1 0.1 mA
IIH
D inputs§
VCC = 5.5 V,
VI = 2.7 V
20 20
A
I
IH All others VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL
D inputs§
VCC = 5.5 V,
VI = 0.4 V
−0.1 −0.1
mA
I
IL All others VCC = 5.5 V, VI = 0.4 V −0.1 −0.1 mA
IO¶VCC = 5.5 V, VO = 2.25 V
CLR = 2.5 V −20 −112 −30 −112 mA
VCC = 5.5 V,
Outputs high 35 55 35 55
I
CC
VCC = 5.5 V,
EN, RD low
Outputs low 55 85 55 85 mA
ICC
EN, RD low
Outputs disabled 42 65 42 65
mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V
§For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
¶The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
TA = MIN to MAX†
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) SN54ALS996 SN74ALS996
UNIT
MIN MAX MIN MAX
fmax 35 35 MHz
tPLH
CLK
Q
5 30 5 28
ns
tPHL
CLK
(T/C = H or L) Q5 24 5 28 ns
tPLH CLR (T/C = L)
Q
5 27 7 27
ns
tPHL CLR (T/C = H) Q5 23 7 23 ns
tPLH
T/C
Q
4 23 5 23
ns
tPHL T/C Q 5 23 5 23 ns
tPHL CLR D5 30 8 30 ns
ten‡
RD
D
2 18 3 16
ns
tdis§RD D 1 19 3 19 ns
ten‡
EN
D
2 17 3 16
ns
tdis§EN D 1 19 3 19 ns
ten‡
OE
Q
2 15 4 15
ns
tdis§
OE
Q
111 1 10
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ten = tPZH or tPZL
§tdis = tPHZ or tPLZ
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR Q OUTPUTS
From Output
Under Test Test
Point
500 Ω
S1
CL
(see Note A)
7 V
500 Ω
LOAD CIRCUIT FOR D OUTPUTS
From Output
Under Test Test
Point
1 kΩ
S1
CL
(see Note A)
7 V
1 kΩ
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
tPHZ
tPLZ
0.3 V
tPZL
tPZH
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C) [0 V
VOH
VOL
[3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
tPHL tPLH
tPLH tPHL
Input
Out-of-Phase
Output
(see Note B)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
VOL
VOH
VOH
VOL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
Figure 1. Load Circuits and Voltage Waveforms
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-89945013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89945013A
SNJ54ALS
996FK
5962-8994501LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8994501LA
SNJ54ALS996JT
SN74ALS996-1DWR OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70
SN74ALS996-1NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996-1NT
SN74ALS996-1NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996-1NT
SN74ALS996DW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996
SN74ALS996DWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996
SN74ALS996DWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996
SN74ALS996DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996
SN74ALS996DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS996
SN74ALS996NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996NT
SN74ALS996NT3 OBSOLETE PDIP NT 24 TBD Call TI Call TI 0 to 70
SN74ALS996NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS996NT
SNJ54ALS996FK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89945013A
SNJ54ALS
996FK
SNJ54ALS996JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8994501LA
SNJ54ALS996JT
SNJ54ALS996W OBSOLETE CFP W 24 TBD A42 N / A for Pkg Type -55 to 125 5962-8994501KA
SNJ54ALS996W
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS996, SN74ALS996 :
•Catalog: SN74ALS996
•Military: SN54ALS996
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS996DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS996DWR SOIC DW 24 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
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