SiP32101, SiP32102, SiP32103
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6.5 mΩ, Bi-Directional Battery Switch in Compact WCSP
DESCRIPTION
The SiP32101, SiP32102, and SiP32103 bidirectional
switches feature reverse blocking capability to isolate the
battery from the system. The internal switch has an ultra-low
6.5 mΩ (typ at 3.3 V) on-resistance and operates from a
+2.3 V to +5.5 V input voltage range, making the devices
ideal battery-disconnect switches for high-capacity battery
applications.
The SiP32101, SiP32102, and SiP32103 have slew rate
control, making them ideal in large load capacitor as well as
high-current load switching applications. These devices are
also highly efficient, consuming a mere 10 pA (typ.) current
in shutdown and 15 pA while operating.
The SiP32101 and SiP32103 have an active low enable and
the SiP32102 has an active high enable. They can interface
directly with a low voltage control signal.
The SiP32101, SiP32102, and SiP32103 are available in an
ultra compact 12-Bump, 1.3 mm x 1.7 mm, 0.4 mm pitch
WCSP package with top side lamination. The device
operates over the temperature of -40 °C to +85 °C.
FEATURES
• Bi-directional ON and OFF
• 7 A continuous current capability
• Ultra low Ron, 6.5 mΩ (typ.) at 3.3 V
• Wide input voltage, 2.3 V to 5.5 V
• Slew rate controlled turn on
• Ultra-low quiescent current: 15 pA (SiP32101, SiP32102)
• EN pin with integrated pull up or pull down resistor
• Available in both logic high and logic low enable options
• Compact 12-Bump, 1.3 mm x 1.7 mm x 0.55 mm
WCSP package
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Smartphones and tablets
• Digital still / video cameras
• Portable meters and test instruments
• Communication devices with embedded batteries
• Portable medical and healthcare systems
• Data storage
• Battery bank
TYPICAL APPLICATION CIRCUIT
Fig. 1 - Typical Application Circuit
Note
• GE1 denotes halogen-free and RoHS-compliant
MARKING
ORDERING INFORMATION
PART NUMBER MARKING ENABLE ENABLE PULL RESISTOR PACKAGE TEMPERATURE
SiP32101DB-T1-GE1 32101 Low enable Pull Low
12-Bump, 1.3 mm x 1.7 mm,
0.4 mm pitch
WCSP package
-40 °C to +85 °C
SiP32102DB-T1-GE1 32102 High enable Pull Low
SiP32102DB-T5-GE1 32102 High enable Pull Low
SiP32103DB-T1-GE1 32103 Low enable Pull High
SiP32101EVB - - -
Evaluation Board
-
SiP32102EVB - - - -
SiP32103EVB - - - -
Port A
Port B
To Battery Pack
System Power Input
Charger Output
System Charging Block
Charging
Control
and
Regulator
System Connector
Power Input
Slew Rate Gate
Drive Logic
LevelShift
GND
EN, EN
SiP32101,
SiP32102
1234
A
B
C
FYWL
32101
SiP32101, SiP32102, SiP32103
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Notes
a. Negative current injection up to 300 mA.
b. All bumps soldered to 1 inch x 1 inch, 2 oz. copper, 4 layers PC board.
c. Derate 13.7 mW/°C above TA = 70 °C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. For VIN outside this range consult typical EN, EN threshold curve.
ABSOLUTE MAXIMUM RATINGS
PARAMETER CONDITIONS LIMIT UNIT
VPA, VPB
Reference to GND -0.3 to +6
VPulse at 1 ms reference to GND a -1.6
VEN Reference to GND -0.3 to +6
Maximum Continuous Switch Current 7 A
Maximum Pulse Current 100 μs pulse 15
ESD (HBM) 8000 V
Operating Temperature -40 to +85
°COperating Junction Temperature 125
Storage Temperature -65 to +150
Thermal Resistance (θJA) b 73 °C/W
Power Dissipation (PD) b, c TA = 70 °C 1096 mW
SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS UNLESS SPECIFIED LIMITS
UNIT
V
IN
= V
PA
/V
PB
= 2.3 V to 5.5 V, T
A
= -40 °C to 85 °C
(Typical values are at V
PA
, V
PB
= 4.2 V,
C
PA
, C
PB
= 0.1 μF, T
A
= 25 °C)
MIN.a TYP.b MAX.a
Power Supply
Operating Voltage c VPA/PB 2.3 - 5.5 V
Quiescent Current IQ
VEN = 0 V (for SiP32101),
VEN = VIN (for SiP32102),
no load
- 0.015 300 nA
VEN = 0 V (for SiP32103),
no load - 8.2 15 μA
Shutdown Current ISHDN
VEN = VIN (for SiP32101),
VEN = 0 V (for SiP32102),
no load
- 0.010 300 nA
Internal FET
On-Resistance RDS(on)
VPA/VPB = 2.3 V, IL = 500 mA, TA = 25 °C - 8 13 mΩ
VPA/VPB = 3.3 V, IL = 500 mA, TA = 25 °C - 6.5 10
Control
EN / EN Input Logic-Low Voltage c VIL --0.4
V
EN / EN Input Logic-High Voltage c VIH 1.4 - -
EN / EN Pull Resistor REN VPA/VPB = 5.5 V, VEN (or VEN) = 2.3 V - 500 700 kΩ
Timing
Output Turn-On Delay Time td(on)
VIN = 4.2 V, RL = 100 Ω, CL = 0.1 μF, TA = 25 °C
-0.5-
ms
Output Turn-On Rise Time tr-1-
Output Turn-Off Delay Time td(off) -2.4-
Output Turn-Off Fall Time tf-1-
SiP32101, SiP32102, SiP32103
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BUMP CONFIGURATION
Fig. 2 - WCSP12, 1.3 mm x 1.7 mm
FUNCTIONAL BLOCK DIAGRAM
BUMP DESCRIPTION
BUMP NUMBER NAME FUNCTION
A1, B1, A3, B3, C3 PB Power port B
C1 GND Ground
A2, B2, C2, B4, C4 PA Power port A
A4 EN / EN Switch enable input,
active low for SiP32101 and SiP32103, active high for SiP32102
Top view (solder bumps on bottom)
A1
C3
B3
A3
C2
B2
A2
C1
B1
/EN
Port A
1234
A
C
B
C4
B4
A4
GND Port A
Port A
Port A
Port A
Port B
Port B
Port B
Port B
Port B
Internal Bias
Circuit
Slew Rate Gate
Drive
Logic Level Shift
GND
EN, SiP32101
EN, SiP32102
Port B
SiP32101,
SiP32102
Port A
Internal Bias
Circuit
Slew Rate Gate
Drive
Logic Level Shift
GND
EN, SiP32101
Port B
SiP32103
Port A
SiP32101, SiP32102, SiP32103
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S15-0598-Rev. G, 30-Mar-15 4Document Number: 62617
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TYPICAL CHARACTERISTICS (internally regulated 25 °C, unless otherwise noted)
Fig. 3 - Quiescent vs. Input Voltage
Fig. 4 - Quiescent vs. Input Voltage
Fig. 5 - Shutdown Current vs. Input Voltage
Fig. 6 - Quiescent vs. Temperature
Fig. 7 - Quiescent vs. Temperature
Fig. 8 - On Resistance vs. Temperature
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
- Quiescent Current (nA)
VPA /VPB (V)
IQPA/IQPB
SiP32101, SiP32102
0
2
4
6
8
10
12
14
16
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
QPA
/
IQPB
-Quiescent Current (μA)
V
PA
/V
PB
(V)
V = 0 V (SiP32103)
EN
0.00
0.02
0.04
0.06
0.08
0.10
0.12
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
ISHDN-PA/ISHDN-PB - Shutdown Current (nA)
VPA /VPB (V)
VV=
PA/VPB (SiP32101, SiP32102)
EN
0.01
0.10
1.00
10.00
- 40 - 15 10 35 60 85
IQPA/IQPB - Quiescent Current (nA)
Temperature (°C)
VPA/VPB = 5.0 V
V
PA
/V
PB
= 2.7 V
VPA/VPB = 4.2 V
SiP32101, SiP32102
0
2
4
6
8
10
12
14
16
- 40 - 15 10 35 60 85
IQPA/IQPB -Quiescent Current (μA)
Temperature (°C)
VPA/VPB = 5.0 V
VPA/VPB = 2.7 V
VPA/VPB = 4.2 V
V = 0 V (SiP32103)
EN
2
3
4
5
6
7
8
9
10
- 40 - 15 10 35 60 85
RDS - On-Resistance (mΩ)
Temperature (°C)
IL = 0.5 A
VPA/VPB = 4.2 V
SiP32101, SiP32102, SiP32103
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TYPICAL CHARACTERISTICS (internally regulated 25 °C, unless otherwise noted)
Fig. 9 - Shutdown Current vs.Temperature
Fig. 10 - On Resistance vs. Input Voltage
Fig. 11 - EN Pull down Resistance vs. Temperature
Fig. 12 - Normalized On Resistance vs. Load Current
Fig. 13 - Reverse Blocking Current (IRB) vs. Output Voltage
Fig. 14 - Rise Time vs. Temperature
0.001
0.01
0.1
1
10
- 40 - 15 10 35 60 85
ISHDN-PA/ISHDN-PB - Shutdown Current (nA)
Temperature (°C)
VPA/VPB = 2.7 V
VPA/VPB = 5 V
V
PA
/V
PB
= 4.2
4
5
6
7
8
9
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
RDS - On-Resistance (mΩ)
VPA/VPB (V)
IL = 0.5 A
400
420
440
460
480
500
520
540
560
580
600
- 40 - 15 10 35 60 85
R/EN - /EN Pull down / Pull up Resistance (kΩ)
Temperature (°C)
V = 2.3 V
VPA/VPB = 5.5 V
EN
0.95
1
1.05
1.1
1.15
1234567
RDS(norm) -Normalized On -Resistance
IOUT (A)
TA = 25 °C VPA/VPB = 2.7 V
VPA/VPB = 3.3 V
VPA/VPB = 4.35 V
VPA/VPB = 5 V
- 16
- 14
- 12
- 10
- 8
- 6
- 4
- 2
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
IPB/IPA - Input Current (nA)
VPA/VPB (V)
VPB/VPA = 2.3 V
0.80
0.90
1.00
1.10
1.20
1.30
- 40 - 15 10 35 60 85
tr - Rise Time (ms)
Temperature (°C)
VPA/VPB = 4.2 V
CL = 0.1 μF
RL = 10 Ω
SiP32101, SiP32102, SiP32103
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TYPICAL CHARACTERISTICS (internally regulated 25 °C, unless otherwise noted)
Fig. 15 - EN, EN Threshold Voltage vs. Input Voltage
Fig. 16 - Turn-on Delay Time vs. Temperature
Fig. 17 - Turn-off Delay Time vs. Temperature
Fig. 18 - Fall Time vs. Temperature
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
2.0 3.0 4.0 5.0 6.0
EN, EN - Threshold Voltage (V)
VPA / V
PB
(V)
V
IH
V
IL
0.4
0.45
0.5
0.55
0.6
0.65
0.7
- 40 - 15 10 35 60 85
td(on) - Turn-On Delay Time (ms)
Temperature (°C)
VPA/VPB = 4.2 V
CL = 0.1 μF
1.8
2.0
2.2
2.4
2.6
2.8
3.0
- 40 - 15 10 35 60 85
td(off) - Turn-Off Delay Time (ms)
Temperature (°C)
VPA/VPB = 4.2 V
CL = 0.1 μF
RL = 10 Ω
0.6
0.7
0.8
0.9
1.0
1.1
1.2
- 40 - 15 10 35 60 85
t
f
- Fall Time (ms)
Temperature (°C)
V
PA
/V
PB
= 4.2 V
C
L
= 0.1 μF
R
L
= 10 Ω
SiP32101, SiP32102, SiP32103
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DETAILED DESCRIPTION
The SiP32101, SiP32102, and SiP32103 bidirectional
switches feature reverse blocking capability to isolate the
battery from the system. The internal switch has an ultra-low
6.5 mΩ (typ. at 3.3 V) on-resistance and operates from a
+2.3 V to +5.5 V input voltage range, making the device ideal
battery-disconnect switch for high-capacity battery
applications. The parts can handle 7 A continuous current at
both directions.
The SiP32101, SiP32102, and SiP32103 have slew rate
control, making them ideal in large load capacitor as well as
high-current load switching applications.
The SiP32101, SiP32102, and SiP32103 are available in an
ultra compact 12-Bump, 1.3 mm x 1.7 mm, 0.4 mm pitch
WCSP package with top side lamination. The device
operates over the temperature of -40 °C to +85 °C.
REVERSE CURRENT BLOCKING
The SiP32101, SiP32102, and SiP32103 are bidirectional
switches that prevent current flowing from either port to the
other when the device is disabled.
EN, EN INPUT
SiP32101 and SiP32103 have an active-low enable pin
which can interface with low voltage GPIO directly. The
switch is on when EN is low and off when EN is high. The
SiP32102 has an active-high enable pin that turns the switch
on when high and off when low. The SiP32101 and
SiP32102 have an integrated pull down resistor at EN pin.
The SiP32103 EN pin integrates a pull up resistor that will
automatically connected to either port A or port whichever
is of higher voltage.
SWITCH ON AND OFF PERFORMANCE
The SiP32101, SiP32102, and SiP32103 have slew rate
control. This minimizes the inrush current and provides a
soft turn on.
Fig. 19 - Port B Turn-On Time
(VPA = 4.2 V, RL = 10 Ω, CL = 0.1 μF)
Fig. 20 - Port B Turn-Off Time
(VPA = 4.2 V, RL = 10 Ω, CL = 0.1 μF)
DEVICE PIN OUT
Device pin out is designed for ease of layout.
Fig. 21 - Proposed Layout
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62617.
)
/EN
GND
A1
C3
B3
A3
C2
B2
A2
C1
B1
/EN
Port A
C4
B4
A4
GND Port A
Port A
Port A
Port A
Port B
Port B
Port B
Port B
Port B
Port A
Port B
Current
Package Information
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Revision: 16-Dec-13 1Document Number: 62592
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WCSP12: 12 Bumps
(3 x 4, 0.4 mm pitch, 208 μm bump height, 1.71 mm x 1.31 mm die size)
Notes (unless otherwise specified)
(1) Laser mark on the silicon die back coated with an epoxy film.
(2) Bumps are SAC396.
(3) 0.050 max. co-planarity.
(4) Laminate tape thickness is 0.022 mm.
(5) Use millimeters as the primary measurement.
MILLIMETERS (5) INCHES
DIMENSION MIN. NOM. MAX. MIN. NOM. MAX.
A 0.515 0.530 0.545 0.0203 0.0209 0.0215
A1 0.183 0.208 0.233 0.0072 0.0082 0.0092
b 0.234 0.260 0.312 0.0092 0.0102 0.0123
e 0.400 0.0157
s 0.235 0.255 0.275 0.0093 0.0100 0.0108
D 1.270 1.310 1.350 0.0500 0.0516 0.0531
E 1.670 1.710 1.750 0.0657 0.0673 0.0689
ECN: S13-2510-Rev. B, 16-Dec-13
DWG: 6017
es e s
se se e
b
D
E
FYWL
ABCDE
Index Bump A1
A1
B1
C1
A2
A3
A4
B2
B3
B4
C2C3C4
Top View Bottom View
A
A1
Side View
Note 3
Bump Note 2
Note 4
RECOMMENDED
LAND PATTERN
(NSMD)
e
ee
A1
e
e
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