HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Features * 8-bit High Speed Single/ Dual/ Quad ADC Single Channel Mode: FSmax = 1000 MSPS Dual Channel Mode: FSmax = 500 MSPS Quad Channel Mode: FSmax = 250 MSPS * Internal Offset Correction * Integrated Cross Point Switches (Mux Array) * Serial LVDS/RSDS Output * 1X to 50X Digital Gain No Missing Codes up to 32X * 7x7 mm QFN 48 (LP7D) Package * 1X Gain: 49.8 dB SNR. 10X Gain: 48 dB SNR * Internal Low Jitter Programmable Clock Divider A / D Converters - SMT 0 * 1.8V Supply Voltage * 1.7 - 3.6V CMOS Logic on Control Interface Pins Typical Applications * USB Powered Oscilloscopes * Ultra Low Power Dissipation 710 mW including I/O at 1000 MSPS * Digital Oscilloscopes * 0.5 s Start-up Time from Sleep, 15 s from Power Down Pin compatible parts * Internal Reference Circuitry with no External Components Required * HMCAD1511 is pin compatible with HMCAD1520 * Coarse and Fine Gain Control * Digital Fine Gain Adjustment for each ADC * Satellite Receivers * HMCAD1511 is pin compatible and can be configured to operate as HMCAD1510, with functionality and performance as described in HMCAD1510 datasheet Functional Diagram Figure 1. Functional Block Diagram 0-1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter General Description The HMCAD1511 is a versatile high performance low power analog-to-digital converter (ADC), utilizing time-interleaving to increase sampling rate. Integrated Cross Point Switches activate the input selected by the user. In single channel mode, one of the four inputs can be selected as a valid input to the single ADC channel. In dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode, any input can be assigned to any ADC channel. An internal, low jitter and programmable clock divider makes it possible to use a single clock source for all operational modes. The HMCAD1511 is based on a proprietary structure, and employs internal reference circuitry, a serial control interface and serial LVDS/RSDS output data. Data and frame synchronization clocks are supplied for data capture at the receiver. Internal 1 to 50X digital coarse gain with ENOB > 7.5 up to 16X gain, allows digital implementation of oscilloscope gain settings. Internal digital fine gain can be set separately for each ADC to calibrate for gain errors. HMCAD1511 is designed to easily interface with Field Programmable Gate Arrays (FPGAs) from several vendors. Electrical Specifications DC Specifications AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, FS = 125 MSPS, Quad Channel Mode, 50% clock duty cycle, -1 dBFS 70 MHz input signal, 1x/0 dB digital gain (fine and coarse), unless otherwise noted Parameter Description Min Typ Max Unit 6 %FS DC accuracy No missing codes Offset Guaranteed Offset error after internal digital offset correction 0.05 LSB Gabs Gain error Grel Gain matching between channels. 3 sigma value at worst case conditions 0.5 DNL Differential non linearity 0.2 LSB INL Integral non linearity 0.5 LSB Common mode voltage output VAVDD/2 VCM,out %FS Analog Input VCM,in Analog input common mode voltage FSR Differential input voltage full scale range VCM -0.1 2 VCM +0.2 Vpp V Cin,Q Differential input capacitance, Quad channel mode 5 pF Cin,D Differential input capacitance, Dual channel mode 7 pF Cin,S Differential input capacitance, Single channel mode 11 pF 0 A / D Converters - SMT Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determine the exact function of this pin. Power Supply VAVDD Analog Supply Voltage 1.7 1.8 2 VDVDD Digital and output driver supply voltage 1.7 1.8 2 V V VOVDD Digital CMOS Input Supply Voltage 1.7 1.8 3.6 V Operating free-air temperature -40 85 C Temperature TA For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0-2 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter AC Specifications AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50% clock duty cycle, -1 dBFS 71 MHz input signal, Gain = 1X, RSDS output data levels unless otherwise noted Parameter Description Min Typ 48.5 49.8 Max Unit Performance SNR Signal to Noise Ratio, excluding interleaving spurs Single Ch Mode, FS = 1000 MSPS 49.7 dBFS Single Ch Mode, FS = 1000 MSPS, Gain = 10X 48.1 dBFS 49.8 dBFS Single Ch Mode, FS = 500 MSPS 48.5 Single Ch Mode, FS = 500 MSPS, Gain = 10X A / D Converters - SMT 0 SINADincl 49.8 dBFS Quad Ch Mode, FS = 250 MSPS 48.5 49.9 dBFS Signal to Noise and Distortion Ratio, including interleaving spurs 45.7 dBFS Dual Ch Mode, FS = 500 MSPS 44 dBFS Quad Ch Mode, FS = 250 MSPS 49.2 dBFS 49.3 dBFS Signal to Noise and Distortion Ratio, excluding interleaving spurs 48 Single Ch Mode, FS = 1000 MSPS, FIN = 170 MHz 46.5 dBFS Single Ch Mode, FS = 1000 MSPS, Gain = 10X 47.5 dBFS Single Ch Mode, FS = 500 MSPS 48 Single Ch Mode, FS = 500 MSPS, Gain = 10X SFDRexcl dBFS 48 49 dBFS 48 49.3 dBFS Spurious Free Dynamic Range, including interleaving spurs Single Ch Mode, FS = 1000 MSPS 49 dBc Dual Ch Mode, FS = 500 MSPS 44 dBc Quad Ch Mode, FS = 250 MSPS 57 dBc 64 dBc Spurious Free Dynamic Range, excluding interleaving spurs 55 Single Ch Mode, FS = 1000 MSPS, FIN = 170 MHz 63 dBc Single Ch Mode, FS = 1000 MSPS, Gain = 10X 62 dBc 65 dBc 65 dBc Single Ch Mode, FS = 500 MSPS 56 Dual Ch Mode, FS = 500 MSPS 55 63 dBc Quad Ch Mode, FS = 250 MSPS 58 70 dBc 60 65 dBc Worst of HD2/HD3 Single Ch Mode, FS = 1000 MSPS Single Ch Mode, FS = 1000 MSPS, FIN = 170 MHz 65 dBc Single Ch Mode, FS = 1000 MSPS, Gain = 10X 63 dBc 65 dBc 65 dBc Single Ch Mode, FS = 500 MSPS 60 Single Ch Mode, FS = 500 MSPS, Gain = 10X 0-3 dBFS 47.7 Quad Ch Mode, FS = 250 MSPS Single Ch Mode, FS = 500 MSPS, Gain = 10X ENOBexcl 49.4 Dual Ch Mode, FS = 500 MSPS Single Ch Mode, FS = 1000 MSPS HD2/3 dBFS 48.5 Single Ch Mode, FS = 1000 MSPS SFDRincl 48.2 Dual Ch Mode, FS = 500 MSPS Single Ch Mode, FS = 1000 MSPS SINADexcl dBFS Single Ch Mode, FS = 1000 MSPS, FIN = 170 MHz Dual Ch Mode, FS = 500 MSPS 57 63 dBc Quad Ch Mode, FS = 250 MSPS 50 70 dBc Effective number of Bits, excluding interleaving spurs Single Ch Mode, FS = 1000 MSPS 7.9 bits Single Ch Mode, FS = 1000 MSPS, FIN = 170 MHz 7.4 bits Single Ch Mode, FS = 1000 MSPS, Gain = 10X 7.6 bits Single Ch Mode, FS = 500 MSPS 7.9 bits Single Ch Mode, FS = 500 MSPS, Gain = 10X 7.6 bits Dual Ch Mode, FS = 500 MSPS 7.8 bits Quad Ch Mode, FS = 250 MSPS 7.9 bits For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter AC Specifications AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50% clock duty cycle, -1 dBFS 71 MHz input signal, Gain = 1X, RSDS output data levels unless otherwise noted Description Min Typ Max Unit Xtlk,2 CrossTalk Dual Ch Mode. Signal applied to 1 channel (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 71 MHz, FIN0 = 70 MHz 65 dBc Xtlk,4 CrossTalk Quad Ch Mode. Signal applied to 1 channel (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 71 MHz, FIN0 = 70 MHz 70 dBc Power Supply Single Ch: FS = 1 GSPS, Dual Ch: FS = 500 MSPS, Quad Ch: FS = 250 MSPS. mA IAVDD Analog Supply Current 270 IDVDD Digital and output driver Supply Current 125 mA PAVDD Analog Power 486 mW PDVDD Digital Power 224 mW PTOT Total Power Dissipation 710 mW PPD Power Down Mode dissipation 15 W PSLP Deep sleep Mode power dissipation 72 mW PSLPCH Power dissipation with all channels in sleep channel mode (Light sleep) 153 mW PSLPCH_SAV Power dissipation savings per channel off (Quad Channel mode) 139 mW Full Power Bandwidth 650 MHz Analog Input FPBW Clock Inputs Max. Conversion Rate in Modes: Single Ch FSmax Dual Ch / Quad Ch 1000 / MSPS 500 / 250 Min. Conversion Rate in Modes: Single Ch Fsmin 120 / Dual Ch / Quad Ch 60 / 30 MSPS Digital and Switching Specifications AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted Parameter Description Min Typ Max Unit 55 % high Clock Inputs DC Duty Cycle Compliance LVDS supported up to 700 MHz VCK,sine Differential input voltage swing, sine wave clock input VCK,CMOS VCM,CK 45 LVPECL, Sine wave, CMOS, LVDS 1500 Voltage input range CMOS (CLKN connected to ground) Input common mode voltage. Keep voltages within ground and voltage of OVDD CCK mVpp 0 A / D Converters - SMT Parameter VOVDD VOVDD -0.3 0.3 Differential Input capacitance 3 V pF Logic inputs (CMOS) VHI High Level Input Voltage. VOVDD 3.0V 2 VHI High Level Input Voltage. VOVDD = 1.7V - 3.0V 0.8 *VOVDD V VLI Low Level Input Voltage. VOVDD 3.0V 0 0.8 V VLI Low Level Input Voltage. VOVDD = 1.7V - 3.0V 0 0.2 *VOVDD V V IHI High Level Input leakage Current +/-10 A ILI Low Level Input leakage Current +/-10 A CI Input Capacitance 3 pF Data Outputs Compliance LVDS / RSDS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0-4 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Digital and Switching Specifications AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted Parameter Description Min Typ Max Unit VOUT Differential output voltage, LVDS 350 mV VOUT Differential output voltage, RSDS 150 mV VCM Output common mode voltage 1.2 V Default/optional Offset Binary/ 2's complement Output coding Timing Characteristics A / D Converters - SMT 0 tA Aperture delay 1.5 ns tj Aperture jitter, One bit set to `1' in jitter_ctrl<7:0> 160 fsrms Tskew Timing skew between ADC channels 2.5 psrms TSU Start up time from Power Down Mode and Deep Sleep Mode to Active Mode in s. See section "Clock Frequency" for details. 15 s 1 clock cycles TSLPCH Start up time from Sleep Channel Mode to Active Mode TOVR TLATHSMQ Pipeline delay, Quad Channel Mode 32 clock cycles TLATHSMD Pipeline delay, Dual Channel Mode 64 clock cycles TLATHSMS Pipeline delay, Single Channel Mode 128 clock cycles LVDS Output Timing Characteristics tdata LCLK to data delay time (excluding programmable phase shift) TPROP 50 Clock propagation delay. 6*TLVDS +2.2 LVDS bit-clock duty-cycle 45 7*TLVDS +3.5 Frame clock cycle-to-cycle jitter ps 7*TLVDS +5.0 ns 55 % LCLK cycle 2.5 % LCLK cycle TEDGE Data rise- and fall time 20% to 80% 0.7 ns TCLKEDGE Clock rise- and fall time 20% to 80% 0.7 ns Table 1: Maximum Voltage Ratings Pin Reference pin Rating AVDD AVSS -0.3V to +2.3V Table 2: Maximum Temperature Ratings Operating Temperature -40 to +85 C Storage Temperature -60 to +150 C DVDD DVSS -0.3V to +2.3V Maximum Junction Temperature OVDD AVSS -0.3V to +3.9V Thermal Resistance (Rth) AVSS / DVSS DVSS / AVSS -0.3V to +0.3V Soldering Profile Qualification ESD Sensivity HBM Class 1C ESD Sensivity CDM Class III Analog inputs and outputs AVSS -0.3V to +2.3V CLKx AVSS -0.3V to +3.9V LVDS outputs DVSS -0.3V to +2.3V Digital inputs DVSS -0.3V to +3.9V Applying voltages to the pins beyond those specified in Table 1 could cause permanent damage to the circuit. 0-5 s Out of range recovery time 110 C 29 C/W J-STD-020 ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Pin Configuration and Description Figure 2: Package diagram Table 3: Pin Descriptions Pin Name Description Pin Number # Of Pins AVDD Analog power supply, 1.8V 1, 36 2 CSN Chip select enable. Active low 2 1 SDATA Serial data input 3 1 SCLK Serial clock input 4 1 RESETN Reset SPI interface. Active low 5 1 PD Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature 6 1 DVDD Digital and I/O power supply, 1.8V 7, 30 2 DVSS Digital ground 8, 29 2 DP1A LVDS channel 1A, positive output 9 1 DN1A LVDS channel 1A, negative output 10 1 DP1B LVDS channel 1B, positive output 11 1 1 DN1B LVDS channel 1B, negative output 12 DP2A LVDS channel 2A, positive output 13 1 DN2A LVDS channel 2A, negative output 14 1 DP2B LVDS channel 2B, positive output 15 1 DN2B LVDS channel 2B, negative output 16 1 LCLKP LVDS bit clock, positive output 17 1 LCLKN LVDS bit clock, negative output 18 1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com A / D Converters - SMT 0 0-6 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 3: Pin Descriptions A / D Converters - SMT 0 0-7 Pin Name Description Pin Number # Of Pins FCLKP LVDS frame clock (1X), positive output 19 1 FCLKN LVDS frame clock (1X), negative output 20 1 DP3A LVDS channel 3A, positive output 21 1 DN3A LVDS channel 3A, negative output 22 1 DP3B LVDS channel 3B, positive output 23 1 DN3B LVDS channel 3B, negative output 24 1 DP4A LVDS channel 4A, positive output 25 1 DN4A LVDS channel 4A, negative output 26 1 DP4B LVDS channel 4B, positive output 27 1 DN4B LVDS channel 4B, negative output 28 1 1 AVSS2 Analog ground domain 2 31 AVDD2 Analog power supply domain 2, 1.8V 32 1 OVDD Digital CMOS Inputs supply voltage 33 1 CLKN Negative differential input clock. 34 1 CLKP Positive differential input clock 35 1 IN4 Negative differential input signal, channel 4 37 1 IP4 Positive differential input signal, channel 4 38 1 AVSS Analog ground 39, 42, 45 3 IN3 Negative differential input signal, channel 3 40 1 IP3 Positive differential input signal, channel 3 41 1 IN2 Negative differential input signal, channel 2 43 1 IP2 Positive differential input signal, channel 2 44 1 IN1 Negative differential input signal, channel 1 46 1 IP1 Positive differential input signal, channel 1 47 1 VCM Common mode output pin, 0.5*AVDD 48 1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Start up Initialization As part of the HMCAD1511 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. Make sure that the supply voltages are properly settled before the start up initialization is being performed. Reset can be done in one of two ways: 1. By applying a low-going pulse (minimum 20 ns) on the RESETN pin (asynchronous). 2. By using the serial interface to set the `rst' bit high. Internal registers are reset to default values when this bit is set. The `rst' bit is self-reset to zero. When using this method, do not apply any low-going pulse on the RESETN pin. Power down cycling can be done in one of two ways: 1. By applying a high-going pulse (minimum 20 ns) on the PD pin (asynchronous). Serial Interface The HMCAD1511 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set low: * Serial data are shifted into the chip * At every rising edge of SCLK, the value present at SDATA is latched * SDATA is loaded into the register every 24th rising edge of SCLK Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is divided into two parts: * The first eight bits form the register address * The remaining 16 bits form the register data Acceptable SCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled. Timing Diagram Figure 4 shows the timing of the serial port interface. Table 4 explains the timing variables used in figure 4. thi tlo tcs CSN tck ts tchi tch th 0 A / D Converters - SMT 2. By cycling the `pd' bit in register 0Fhex to high (reg value `0200'hex) and then low (reg value `0000'hex). SCLK SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 3: Serial Port Interface timing Table 4: Serial Port Interface Timing Definitions Parameter Description Minimum value Unit tcs Setup time between CSN and SCLK 8 ns tch Hold time between CSN and SCLK 8 ns thi SCLK high time 20 ns tlo SCLK low time 20 ns tck SCLK period 50 ns ts Data setup time 5 ns th Data hold time 5 ns For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0-8 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Timing Diagrams N+31 N+32 N+33 Analog input N+35 N+34 Input clock LCLKP LCLKN FCLKP FCLKN A / D Converters - SMT 0 TLVDS DxnA D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-4 N-4 N-4 N-4 N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N D1 N D2 N D3 N D4 N D5 N D6 N DxnB D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-3 N-3 N-3 N-3 N-3 N-3 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 TPROP Figure 4: Quad channel - LVDS timing 8-bit output N+62 N+63 N+64 N+65 N+66 Analog input N+67 N+70 N+68 N+69 Input clock LCLKP LCLKN FCLKP FCLKN TLVDS Dx1A / Dx3A D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-8 N-8 N-8 N-8 N-8 N-8 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N D1 N D2 N D3 N D4 N D5 N D6 N Dx1B / Dx3B D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-7 N-7 N-7 N-7 N-7 N-7 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+1 N+1 N+1 N+1 N+1 N+1 N+1 Dx2A / Dx4A D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-6 N-6 N-6 N-6 N-6 N-6 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 Dx2B / Dx4B D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-5 N-5 N-5 N-5 N-5 N-5 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+3 N+3 N+3 N+3 N+3 N+3 N+3 TPROP Figure 5: Dual channel - LVDS timing 8-bit output 0-9 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter N+124 N+126 N+128 N+130 N+132 Analog input N+134 N+136 N+138 N+140 Input clock TLVDS Dx1A D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-16 N-16 N-16 N-16 N-16 N-16 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N D1 N D2 N D3 N D4 N D5 N D6 N Dx1B D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-15 N-15 N-15 N-15 N-15 N-15 N-7 N-7 N-7 N-7 N-7 N-7 N-7 N-7 N+1 N+1 N+1 N+1 N+1 N+1 N+1 Dx2A D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-14 N-14 N-14 N-14 N-14 N-14 N-6 N-6 N-6 N-6 N-6 N-6 N-6 N-6 N+2 N+2 N+2 N+2 N+2 N+2 N+2 Dx2B D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-13 N-13 N-13 N-13 N-13 N-13 N-5 N-5 N-5 N-5 N-5 N-5 N-5 N-5 N+3 N+3 N+3 N+3 N+3 N+3 N+3 Dx3A D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-12 N-12 N-12 N-12 N-12 N-12 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N+4 N+4 N+4 N+4 N+4 N+4 N+4 Dx3B D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-11 N-11 N-11 N-11 N-11 N-11 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+5 N+5 N+5 N+5 N+5 N+5 N+5 Dx4A D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-10 N-10 N-10 N-10 N-10 N-10 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+6 N+6 N+6 N+6 N+6 N+6 N+6 Dx4B D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-9 N-9 N-9 N-9 N-9 N-9 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+7 N+7 N+7 N+7 N+7 N+7 N+7 TPROP Figure 6: Single channel - LVDS timing 8-bit output TLVDS LCLKP LCLKN Dxxx 0 A / D Converters - SMT LCLKP LCLKN FCLKP FCLKN TLVDS /2 tdata Figure 7: LVDS data timing For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 10 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Register Map Summary Table 5: Register Map Name rst * A / D Converters - SMT 0 0 - 11 Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 Self-clearing software reset. Inactive sleep4_ch <4:1> Channel-specific sleep mode for a Quad Channel setup. Inactive sleep2_ch <2:1> Channel-specific sleep mode for a Dual Channel setup. Inactive sleep1_ch1 Channel-specific sleep mode for a Single Channel setup. Inactive sleep Go to sleep-mode. Inactive pd Go to power-down. Inactive Configures the PD pin function. PD pin configured for power-down mode ilvds_lclk <2:0> LVDS current drive programmability for LCLKP and LCLKN pins. 3.5 mA drive ilvds_frame <2:0> LVDS current drive programmability for FCLKP and FCLKN pins. 3.5 mA drive ilvds_dat <2:0> LVDS current drive programmability for output data pins. 3.5 mA drive en_lvds_ term Enables internal termination for LVDS buffers. Termination disabled X term_lclk <2:0> Programmable termination for LCLKN and LCLKP buffers. Termination disabled 1 term_frame <2:0> Programmable termination for FCLKN and FCLKP buffers. Termination disabled 1 term_dat <2:0> Programmable termination for output data buffers. Termination disabled 1 invert4_ch <4:1> Channel specific swapping of the analog input signal for a Quad Channel setup. IPx is positive input invert2_ch <2:1> Channel specific swapping of the analog input signal for a Dual Channel setup. IPx is positive input invert1_ch1 Channel specific swapping of the analog input signal for a Single Channel setup. IPx is positive input X en_ramp Enables a repeating full-scale ramp pattern on the outputs. Inactive dual_ custom_pat Enable the mode wherein the output toggles between two defined codes. single_ custom_pat pd_pin_cfg <1:0> D2 D1 D0 X X X X X Hex Address 0x00 X X X 0x0F X X X X X X X X X X X 0x11 X X X X X 0x12 X X X X X X X X X X 0x24 X X X 0 0 Inactive 0 X 0 Enables the mode wherein the output is a constant specified code. Inactive 0 0 X bits_custom1 <7:0> Bits for the single custom pattern and for the first code of the dual custom pattern. 0x00 X X X X X X X X 0x26 bits_custom2 <7:0> Bits for the second code of the dual custom pattern. 0x00 X X X X X X X X 0x27 cgain4_ch1 <3:0> Programmable coarse gain channel 1 in a Quad Channel setup. 1x gain cgain4_ch2 <3:0> Programmable coarse gain channel 2 in a Quad Channel setup. 1x gain cgain4_ch3 <3:0> Programmable coarse gain channel 3 in a Quad Channel setup. 1x gain cgain4_ch4 <3:0> Programmable coarse gain channel 4 in a Quad Channel setup. 1x gain 0x25 X X X X X X X X 0x2A X X X X X X X X For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 5: Register Map Description Default cgain2_ch1 <3:0> Programmable coarse gain channel 1 in a Dual Channel setup. 1x gain cgain2_ch2 <3:0> Programmable coarse gain channel 2 in a Dual Channel setup. 1x gain cgain1_ch1 <3:0> Programmable coarse gain channel 1 in a Single Channel setup. 1x gain Clock jitter adjustment. 160 fsrms Set number of channels: 1, 2 or 4 channels. 4 channels Define clock divider factor: 1, 2, 4 or 8 Divide by 1 Configures the coarse gain setting x-gain enabled Enable use of fine gain. Disabled fgain_ branch1 <6:0> Programmable fine gain for branch1. 0dB gain fgain_ branch2 <6:0> Programmable fine gain for branch 2. 0dB gain fgain_ branch3 <6:0> Programmable fine gain for branch 3. 0dB gain fgain_ branch4 <6:0> Programmable fine gain for branch 4. 0dB gain fgain_ branch5 <6:0> Programmable fine gain for branch 5. 0dB gain fgain_ branch6 <6:0> Programmable fine gain for branch 6. 0dB gain fgain_ branch7 <6:0> Programmable fine gain for branch 7. 0dB gain fgain_ branch8 <6:0> Programmable fine gain for branch 8. 0dB gain inp_sel_adc1 <4:0> Input select for adc 1. Signal input: IP1/IN1 inp_sel_adc2 <4:0> Input select for adc 2. Signal input: IP2/ IN2 inp_sel_adc3 <4:0> Input select for adc 3. Signal input: IP3/ IN3 inp_sel_ adc4<4:0> Input select for adc 4. Signal input: IP4/ IN4 phase_ddr <1:0> Controls the phase of the LCLK output relative to data. 90 degrees jitter_ctrl <7:0> channel_ num <2:0> * clk_divide <1:0>* coarse_ gain_cfg fine_gain_en pat_deskew D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X X X X X X X X X X X X D2 D1 D0 X X Hex Address X 0x2B X X X X X X X X 0x30 0x31 X X X 0x33 X X X X X X X 0x34 X X X X X X X X X X X X X X 0x35 X X X X X X X X X X X X X X 0x36 X X X X X X X X X X X X X X 0x37 X X X X X X X X X X X 0 0x3A X X X X 0 X X X X 0 X 0 A / D Converters - SMT Name 0x3B X X X X 0 X X 0x42 Enable deskew pattern mode. Inactive 0 X pat_sync Enable sync pattern mode. Inactive X 0 btc_mode Binary two's complement format for ADC output data. Straight offset binary msb_first Serialized ADC output data comes out with MSB first. LSB first adc_curr <2:0> ADC current scaling. Nominal VCM buffer driving strength control. Nominal Controls LVDS power down mode High z-mode 0x45 ext_vcm_bc <1:0> lvds_pd_ mode X 0x46 X X X X 0x50 X X X 0x52 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 12 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 5: Register Map Name Description Default low_clk_ freq * Low clock frequency used. Inactive lvds_ advance Advance LVDS data bits and frame clock by one clock cycle Inactive 0 Delay LVDS data bits and frame clock by one clock cycle Inactive Fine adjust ADC full scale range 0% change Controls start-up time. `000' lvds_delay fs_cntrl <5:0> startup_ctrl <2:0> * D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Hex Address 0 0 0 X 0 0 0 X 0 0 0 0 X X X X X 0x55 X X X 0x56 X 0x53 Undefined register addresses must not be written to; incorrect behavior may be the result. 0 Unused register bits (blank table cells) must be set to `0' when programming the registers. All registers can be written to while the chip is in power down mode. A / D Converters - SMT * These registers require a power down cycle when written to (See Start up Initialization). Register Description Software Reset Name rst Description Default Self-clearing software reset. Inactive D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address X 0x00 Setting the rst register bit to `1', restores the default value of all the internal registers including the rst register bit itself. Modes of Operation and Clock Divide Factor Name Description Default channel_ num <2:0> Set number of channels: 1, 2 or 4 channels. 4 channels clk_divide <1:0> Define clock divider factor: 1, 2, 4 or 8 Divide by 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X Hex Address X 0x31 X X The HMCAD1511 has three main operating modes controlled by the register bits channel_num<2:0> as defined in table 6. Power down mode, as described in section `Startup Initialization', must be activated after or during a change of operating mode to ensure correct operation. All active operating modes utilize interleaving to achieve high sampling speed. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while single channel mode interleave all 8 ADC branches. Table 6: Modes of operation channel_num <2:0> Mode of operation Description 0 0 1 Single channel Single channel by interleaving ADC1 to ADC4 0 1 0 Dual channel Dual channel where channel 1 is made by interleaving ADC1 and ADC2, channel 2 by interleaving ADC3 and ADC4 1 0 0 Quad channel Quad channel where channel 1 corresponds to ADC1, channel2 to ADC2, channel3 to ADC3 and channel 4 to ADC4 Only one of the 3bits should be activated at the same time. 0 - 13 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. The clock divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, defined by the clk_divide<1:0> register. By setting the clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all settings on number of channels. e.g: When increasing the number of channels from 1 to 4, the maximum sampling rate is reduced by a factor of 4. By letting clk_divide<1:0> follow the channel_num<2:0> value, and change it from 1 to 4, the internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency. Table 7: Clock Divider Factor Clock Divider Factor Sampling rate (FS) 00 (default) 1 Input clock frequency / 1 01 2 Input clock frequency / 2 10 4 Input clock frequency / 4 11 8 Input clock frequency / 8 Input Select Name Description Default inp_sel_adc1 <4:0> Input select for adc 1. Signal input: IP1/IN1 inp_sel_adc2 <4:0> Input select for adc 2. Signal input: IP2/IN2 inp_sel_adc3 <4:0> Input select for adc 3. Signal input: IP3/IN3 Input select for adc 4. Signal input: IP4/IN4 inp_sel_adc4 <4:0> D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 0 Hex Address 0x3A X X X X 0 X X X X 0 0x3B X X X X 0 Each ADC is connected to the four input signals via a full flexible cross point switch, set up by inp_sel_adcx. In single channel mode, any one of the four inputs can be selected as valid input to the single ADC channel. In dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode any input can be assigned to any ADC channel. The switching of inputs can be done during normal operation, and no additional actions are needed. The switching will occur instantaneously at the end of each SPI command. Table 8: Select inp_sel_adcx<4:0> Selected Input 0001 0 IP1/IN1 0010 0 IP2/IN2 0100 0 IP3/IN3 1000 0 IP4/IN4 other Do not use For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 A / D Converters - SMT clk_divide<1:0> 0 - 14 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter inp_sel_adc1<4:1> <4:1> IP1 / IN1 inp_sel_adc2<4:1> ADC 1 <4:1> IP2 / IN2 inp_sel_adc3<4:1> ADC 2 <4:1> IP3 / IN3 inp_sel_adc4<4:1> IP4 / IN4 A / D Converters - SMT 0 <4:1> ADC 4 Cross Point Switch (Analog Mux) Figure 8: ADC input signals through Cross Point Switch Full-Scale Control Name Description Default fs_cntrl <5:0> Fine adjust ADC full scale range 0% change D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X X X D2 D1 D0 X X X Hex Address 0x55 The full-scale voltage range of HMCAD1511 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register. Changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. This leads to a maximum range of 10% adjustment. Table 9 shows how the register settings correspond to the full-scale range. Note that the values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous. The full-scale control and the programmable gain features differ in two major ways: 1.The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2.The programmable gain feature has much coarser gain steps and larger range than the full-scale control. Table 9: Register Values with Corresponding Change in Full-Scale Range fs_cntrl<5:0> 0 - 15 ADC 3 Full-Scale Range Adjustment 111111 9.70% 111110 9.40% 100001 0.30% 100000 0% 011111 -0.3% 000001 -9.7% 000000 -10% For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Current Control Name Description Default adc_curr<2:0> ADC current scaling. Nominal ext_vcm_bc<1:0> VCM buffer driving strength control. Nominal D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 X X D3 D2 D1 D0 X X X Hex Address 0x50 There are two registers that impact performance and power dissipation. The adc_curr register scales the current consumption in the ADC core. The performance is guaranteed at the nominal setting. Lower power consumption can be achieved by reducing the adc_curr value, see table 10. The impact on performance is low for settings down to minimum, but will depend on the ADC sampling rate. Table 10: ADC Current Control Settings ADC Core Current 100 -40% (lower performance) 101 -30% 110 -20% 111 -10% 000 (default) Nominal 001 Do not use 010 Do not use 011 Do not use 0 The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is not in use, the buffer can be switched off. If current is drawn from the VCM pin, the driving strength can be increased to keep the voltage on this pin at the correct level. Table 11: External Common Mode Voltage Buffer Driving Strength ext_vcm_bc<1:0> VCM buffer driving strength (A) Max current sinked/sourced from VCM pin with < 20 mV voltage change. 00 Off (VCM floating) 01 (default) 20 10 400 11 700 A / D Converters - SMT adc_curr<2:0> Start-up and Clock Jitter Control Name Description Default startup_ctrl<2:0> Controls start-up time. '000' jitter_ctrl<7:0> Clock jitter adjustment. 160 fsrms D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X X X X X Hex Address D2 D1 D0 X X X 0x56 X X X 0x30 To optimize start up time, a register is provided where the start-up time in number of clock cycles can be set. Some internal circuitry have start up times that are clock frequency independent. Default counter values are set to accommodate these start up times at the maximum clock frequency (sampling rate). This will lead to increased start up times at low clock frequencies. Setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced. The start up times from power down and sleep modes are changed by this register setting. If the clock divider is used (set to other than 1), the input clock frequency must be divided by the divider factor to find the correct clock frequency range (see table 7). For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 16 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 12: Start-Up Time Control Settings Quad Channel Dual Channel startup_ctrl <2:0> Clock Frequency Range (MSPS) Startup Delay (clock cycles) Startup Delay (s) startup_ctrl <2:0> Clock Frequency Range (MSPS) Startup Delay (clock cycles) Startup Delay (s) 100 160 - 250 3072 12.3 - 19.2 100 320 - 500 6144 12.3 - 19.2 000 100 - 160 1984 12.4 - 19.8 000 200 - 320 3968 12.4 - 19.8 001 65 - 100 1280 12.8 - 19.7 001 130 - 200 2560 12.8 - 19.7 101 40 - 65 840 12.9 - 21 101 80 - 130 1680 12.9 - 21 011 30 - 40 520 13 - 17.3 011 60 - 80 1040 13 - 17.3 other Do not use - - other Do not use - - startup_ctrl <2:0> Clock frequency range (MSPS) Startup Delay (clock cycles) Startup delay (s) Single Channel A / D Converters - SMT 0 0 - 17 100 640 - 1000 12288 12.3 - 19.2 000 400 - 640 7936 12.4 - 19.8 001 260 - 400 5120 12.8 - 19.7 101 160 - 260 3360 12.9 - 21 011 120 - 160 2080 13 - 17.3 other Do not use - - jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. If all bits in the register is set low, the clock signal is stopped. The clock jitter depends on the number of bits set to `1' in the jitter_ctrl<7:0> register. Which bits are set high does not affect the result. Table 13: Clock Jitter Performance Number of bits to '1' in jitter_ctrl<7:0> Clock Jitter Performance (fsrms) Module Current Consumption (mA) 1 160 1 2 150 2 3 136 3 4 130 4 5 126 5 6 124 6 7 122 7 8 120 8 0 Clock stopped For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter LVDS Output Configuration and Control Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 low_clk_freq Low clock frequency used. Inactive lvds_advance Advance LVDS data bits and frame clock by one clock cycle Inactive 0 lvds_delay Delay LVDS data bits and frame clock by one clock cycle Inactive X phase_ddr<1:0> Controls the phase of the LCLK output relative to data. 90 degrees btc_mode Binary two's complement format for ADC output data. Straight offset binary msb_first Serialized ADC output data comes out with MSB first. LSB first X D5 D4 D3 D2 D1 D0 X 0 0 0 X 0 0 0 0 0 0 0 X Hex Address 0x53 0x42 X 0x46 X The HMCAD1511 uses an 8-bit serial LVDS output interface as shown in the Timing Diagrams section. The different selection of number of channels uses the LVDS outputs as defined by table 14. Table 14: Use of LVDS Outputs Channel Set-Up LVDS Outputs Used Single channel D1A, D1B, D2A, D2B, D3A, D3B, D4A, D4B Dual channel, channel 1 D1A, D1B, D2A, D2B Dual channel, channel 2 D3A, D3B, D4A, D4B Quad channel, channel 1 D1A, D1B Quad channel, channel 2 D2A, D2B Quad channel, channel 3 D3A, D3B Quad channel, channel 4 D4A, D4B Maximum data output bit-rate for HMCAD1511 is 1 Gb/s. The maximum sampling rate for the different configurations is given by table 15. The sampling rate is set by the frequency of the input clock (FS). The frame-rate, i.e. the frequency of the FCLK signal on the LVDS outputs, depends on the selected mode and the sampling frequency (FS) as defined in table 16. Table 15: Maximum Sampling Rate for Different HMCAD1511 Configurations Product Single Channel (MSPS) Dual Channel (MSPS) Quad Channel (MSPS) HMCAD1511 1000 500 250 0 A / D Converters - SMT Name Table 16: Output Data Frame Rate Mode of Operation Frame-Rate (FCLK Frequency) Single channel FS / 8 Dual channel FS / 4 Quad channel FS / 2 If the HMCAD1511 device is used at a low sampling rate the register bit low_clk_freq has to be set to `1'. See table 17 for when to use this register bit for the different modes of operation. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 18 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 17: Use of Register Bit low_clk_freq Mode of Operation Limit When low_clk_freq Should Be Activated Single channel FS < 240 MHz Dual channel FS < 120 MHz Quad channel FS < 60 MHz To ease timing in the receiver when using multiple HMCAD1511, the device has the option to adjust the timing of the output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. See figure 10 for details. Note that LCLK is not affected by lvds_delay or lvds_advance settings. Input clock A / D Converters - SMT 0 0 - 19 LCLKP LCLKN TLVDS TPROP default: FCLKN FCLKP Dxxx D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N TPROP lvds_delay = '1': D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 TPROP lvds_advance = '1': D2 N D3 N D4 N D5 N D6 N TLVDS FCLKP FCLKN Dxxx D1 N D0 N D1 N D2 N D3 N D4 N D5 N D2 N D3 N D4 N D5 N D6 N D7 N TLVDS FCLKP FCLKN Dxxx D0 D1 D2 D3 D4 D5 D6 D7 D0 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N D1 N Figure 9: LVDS output timing adjustment The LVDS output interface of HMCAD1511 is a DDR interface. The default setting is with the LCLK rising and falling edge transitions in the middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock and data bits using phase_ddr<1:0>. The LCLK phase modes are shown in figure 11. The default timing is identical to setting phase_ddr<1:0>='10'. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter PHASE_DDR<1:0>='00' (270 deg) FCLKN FCLKP LCLKP LCLKN Dxx<1:0> PHASE_DDR<1:0>='10' (90 deg) FCLKN FCLKP LCLKN LCLKP Dxx<1:0> PHASE_DDR<1:0>='11' (0 deg) FCLKN FCLKP LCLKP LCLKN 0 Dxx<1:0> Figure 10: Phase programmability modes for LCLK The default data output format is offset binary. Two's complement mode can be selected by setting the btc_mode bit to `1' which inverts the MSB. The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Programming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP rising edge. LVDS Drive Strength Programmability Name Description Default ilvds_lclk <2:0> LVDS current drive programmability for LCLKP and LCLKN pins. 3.5 mA drive ilvds_frame <2:0> LVDS current drive programmability for FCLKP and FCLKN pins. 3.5 mA drive ilvds_dat <2:0> LVDS current drive programmability for output data pins. 3.5 mA drive D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 X X X D5 X D4 X D3 D2 D1 D0 X X X Hex Address 0x11 X The current delivered by the LVDS output drivers can be configured as shown in table 18. The default current is 3.5mA, which is what the LVDS standard specifies. To reduce power consumption in the HMCAD1511, Reduced Swing Data Signaling (RSDS), is recommended. The output current drive setting should then be 1.5 mA. A / D Converters - SMT Dxx<1:0> PHASE_DDR<1:0>='01' (180 deg) FCLKN FCLKP LCLKN LCLKP Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and LCLKN pins. Setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the FCLKP and FCLKN pins. Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]N pins. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 20 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 18: LVDS Output Drive Strength for LCLK, FCLK & Data A / D Converters - SMT 0 0 - 21 ilvds_*<2:0> LVDS Drive Strength 000 3.5 mA (default) 001 2.5 mA 101 1.5 mA (RSDS) 011 0.5 mA 100 7.5 mA 101 6.5 mA 110 5.5 mA 111 4.5 mA LVDS Internal Termination Programmability Name Description Default D15 D14 D13 D12 D11 D10 D9 en_lvds_term Enables internal termination for LVDS buffers. Termination disabled X term_lclk <2:0> Programmable termination for LCLKN and LCLKP buffers. Termination disabled 1 term_frame <2:0> Programmable termination for FCLKN and FCLKP buffers. Termination disabled 1 term_dat <2:0> Programmable termination for output data buffers. Termination disabled 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X Hex Address X 0x12 X X X X X X The off-chip load on the LVDS buffers may represent a characteristic impedance that is not perfectly matched with the PCB traces. This may result in reflections back to the LVDS outputs and loss of signal integrity. This effect can be mitigated by enabling an internal termination between the positive and negative outputs of each LVDS buffer. Internal termination mode can be selected by setting the en_lvds_term bit to `1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table 19 shows how the internal termination of the LVDS buffers are programmed. The values are typical values and can vary by up to 20% from device to device and across temperature. Table 19: LVDS Output Internal Termination for LCLK, FCLK and Data term_*<2:0> LVDS Internal Termination 000 Termination disabled 001 260 101 150 011 94 100 125 101 80 110 66 111 55 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Power Mode Control Name Description Default sleep4_ch <4:1> Channel-specific sleep mode for a Quad Channel setup. Inactive sleep2_ch <2:1> Channel-specific sleep mode for a Dual Channel setup. Inactive sleep1_ch1 Channel-specific sleep mode for a Single Channel setup. Inactive sleep Go to sleep-mode. Inactive pd Go to power-down. Inactive Configures the PD pin function. PD pin configured for power-down mode lvds_pd_mode Controls LVDS power down mode D8 D7 D6 D5 D4 D3 X X D2 D1 D0 X X Hex Address X X X 0x0F High z-mode X X X X X 0x52 The HMCAD1511 device has several modes for power management, from sleep modes with short start up time to full power down with extremely low power dissipation. There are two sleep modes, both with the LVDS clocks (FCLK, LCLK) running, such that the synchronization with the receiver is maintained. The first is a light sleep mode (sleep*_ ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down. Setting sleep4_ch<n> = `1' sets channel <n> in a Quad Channel setup in sleep mode. Setting sleep2_ch<n> = `1' sets channel <n> in a Dual Channel setup in sleep mode. Setting sleep1_ch1 = `1' sets the ADC channel in a Single Channel setup in sleep mode. This is a light sleep mode with short start up time. Setting sleep = `1', puts all channels to sleep, but keeps FCLK and LCLK running to maintain LVDS synchronization. The start up time is the same as for complete power down. Power consumption is significantly lower than for setting all channels to sleep by using the sleep*_ch register. Setting pd = `1' completely powers down the chip, including the band-gap reference circuit. Start-up time from this mode is significantly longer than from the sleep*_ch mode. The synchronization with the LVDS receiver is lost since LCLK and FCLK outputs are put in high-Z mode. Setting pdn_pin_cfg<1:0> = `x1' configures the circuit to enter sleep channel mode (all channels off) when the PD pin is set high. This is equal to setting all channels to sleep by using sleep*_ch. The channels can not be powered down separately using the PD pin. Setting pdn_pin_cfg<1:0> = `10' configures the circuit to enter (deep) sleep mode when the PD pin is set high (equal to setting sleep='1'). When pdn_pin_cfg <1:0>= `00', which is the default, the circuit enters the power down mode when the PD pin is set high. The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or kept alive in sleep and sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and sleep channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z mode, and the driver is completely powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on during sleep and sleep channel modes. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 A / D Converters - SMT pd_pin_cfg <1:0> D15 D14 D13 D12 D11 D10 D9 0 - 22 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Programmable Gain A / D Converters - SMT 0 0 - 23 Name Description Default cgain_cfg Configures the coarse gain setting x-gain enabled fine_gain_en Enable use of fine gain. Disabled cgain4_ch1 <3:0> Programmable coarse gain channel 1 in a Quad Channel setup. 1x gain cgain4_ch2 <3:0> Programmable coarse gain channel 2 in a Quad Channel setup. 1x gain cgain4_ch3 <3:0> Programmable coarse gain channel 3 in a Quad Channel setup. 1x gain cgain4_ch4 <3:0> Programmable coarse gain channel 4 in a Quad Channel setup. 1x gain cgain2_ch1 <3:0> Programmable coarse gain channel 1 in a Dual Channel setup. 1x gain cgain2_ch2 <3:0> Programmable coarse gain channel 2 in a Dual Channel setup. 1x gain cgain1_ch1 <3:0> Programmable coarse gain channel 1 in a 1 channel setup. 1x gain fgain_branch1<6:0> Programmable fine gain for branch1. 0dB gain fgain_branch2<6:0> Programmable fine gain for branch 2. 0dB gain fgain_branch3<6:0> Programmable fine gain for branch 3. 0dB gain fgain_branch4<6:0> Programmable fine gain for branch 4. 0dB gain D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Hex Address 0x33 X X X X X X X X X 0x2A fgain_branch5<6:0> Programmable fine gain for branch 5. 0dB gain fgain_branch6<6:0> Programmable fine gain for branch 6. 0dB gain fgain_branch7<6:0> Programmable fine gain for branch 7. 0dB gain fgain_branch8<6:0> Programmable fine gain for branch 8. 0dB gain X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0x2B X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0x34 0x35 0x36 0x37 The device includes a digital programmable gain in addition to the Full-scale control. The programmable gain of each channel can be individually set using a four bit code, indicated as cgain*<3:0>. The gain is configured by the register cgain_cfg, when cgain_cfg equals `0' a gain in dB steps is enabled as defined in table 20 otherwise if cgain_cfg equals `1' the gain is defined by table 21. There will be no missing codes for gain settings lower than 32x (30dB), due to higher than 8 bit resolution internally. Table 20: Gain setting - dB Step cgain_cfg cgain*<3:0> Implemented Gain (dB) 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 1100 12 0 1101 Not used 0 1110 Not used 0 1111 Not used For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 21: Gain Setting - x Step Implemented Gain Factor (x) cgain*<3:0> 1 0000 1 1 0001 1.25 1 0010 2 1 0011 2.5 1 0100 4 1 0101 5 1 0110 8 1 0111 10 1 1000 12.5 1 1001 16 1 1010 20 0 1 1011 25 1 1100 32 1 1101 50 1 1110 Not used 1 1111 Not used There is a digital fine gain implemented for each ADC to adjust the fine gain errors between the ADCs. The gain is controlled by fgain_branch* as defined in table 22. There will be no missing codes when using digital fine gain, due to higher resolution internally. To enable the fine gain function the register bit fine_gain_en has to be activated, set to `1'. Table 22: Fine Gain Setting Arithmetic Function Implemented Gain (x) Gain (dB) 0 1 fgain_branchx<6:0> 1 1 1 1 1 OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12 + 2-13) * IN 1.0077 0.0665 0 1 1 1 1 1 0 OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12) * IN 1.0076 0.0655 0 1 1 1 1 0 1 OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-13) * IN 1.0074 0.0644 0 1 1 1 1 0 0 OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11) * IN 1.0073 0.0634 0 0 0 0 0 1 1 OUT = (1 + 2-12 + 2-13) * IN 1.0004 0.0031 0 0 0 0 0 1 0 OUT = (1 + 2-12) * IN 1.0002 0.0021 0 0 0 0 0 0 1 OUT = (1 + 2-13) * IN 1.0001 0.001 0 0 0 0 0 0 0 OUT = IN 1.0000 0.0000 1 1 1 1 1 1 1 OUT = IN 1.0000 0.0000 1 1 1 1 1 1 0 OUT = (1 - 2-13) * IN 0.9999 -0.0011 1 1 1 1 1 0 1 OUT = (1 - 2-12) * IN 0.9998 -0.0021 1 1 1 1 1 0 0 OUT = (1 - 2-12 - 2-13) * IN 0.9996 -0.0032 1 0 0 0 0 1 1 OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11) * IN 0.9927 -0.0639 1 0 0 0 0 1 0 OUT = (1 - 2 - 2 - 2 - 2 ) * IN 0.9926 -0.0649 1 0 0 0 0 0 1 OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12) * IN 0.9924 -0.0660 1 0 0 0 0 0 0 OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12 - 2-13) * IN 0.9923 -0.0670 -8 -9 -10 -2 -11 -13 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com A / D Converters - SMT cgain_cfg 0 - 24 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Analog Input Invert Name Description Default invert4_ch <4:1> Channel specific swapping of the analog input signal for a Quad Channel setup. IPx is positive input invert2_ch <2:1> Channel specific swapping of the analog input signal for a Dual Channel setup. IPx is positive input invert1_ch1 Channel specific swapping of the analog input signal for a 1 channel setup. IPx is positive input D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X Hex Address X 0x24 X X The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting the bits marked invertx_ch<n:1> (individual control for each channel) causes the inputs to be swapped. INx would then represent the positive input, and IPx the negative input. A / D Converters - SMT 0 LVDS Test Patterns D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address Name Description Default en_ramp Enables a repeating full-scale ramp pattern on the outputs. Inactive X 0 0 dual_custom_pat Enable the mode wherein the output toggles between two defined codes. Inactive 0 X 0 single_custom_ pat Enables the mode wherein the output is a constant specified code. Inactive 0 0 X bits_custom1 <7:0> Bits for the single custom pattern and for the first code of the dual custom pattern. <0> is the LSB. 0x00 X X X X X X X X 0x26 bits_custom2 <7:0> Bits for the second code of the dual custom pattern. 0x00 X X X X X X X X 0x27 pat_deskew Enable deskew pattern mode. Inactive 0 X pat_sync Enable sync pattern mode. Inactive X 0 0x25 0x45 To ease the LVDS synchronization setup of HMCAD1511, several test patterns can be set up on the outputs. Normal ADC data are replaced by the test pattern in these modes. Setting en_ramp to `1' sets up a repeating full-scale ramp pattern on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and starts the ramp again after reaching the full-scale code. A constant value can be set up on the outputs by setting single_custom_pat to `1', and programming the desired value in bits_custom1<7:0>. In this mode, bits_custom1<7:0> replaces the ADC data at the output, and is controlled by LSBfirst and MSB-first modes in the same way as normal ADC data are. The device may also be made to alternate between two codes by programming dual_custom_pat to `1'. The two codes are the contents of bits_custom1<7:0> and bits_custom2<7:0>. Two preset patterns can also be selected: 1. Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with `01010101' 2.Sync pattern: Set using pat_sync, the normal ADC word is replaced by a fixed `11110000' word Note: Only one of the above patterns should be selected at the same time. 0 - 25 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Table 23: Quad Channel Mode HMCAD1511 is a multi Mode high-speed, CMOS ADC, consisting of 8 ADC branches, configured in different channel modes, using interleaving to achieve high speed sampling. For all practical purposes, the device can be considered to contain 4 ADCs. Fine gain is adjusted for each of the eight branches separately. Channel # HMCAD1511 utilizes a LVDS output, described in `Register Description, LVDS Output Configuration and Control'. The clocks needed (FCLK, LCLK) for the LVDS interface are generated by an internal PLL. 3 The HMCAD1511 operate from one clock input, which can be differential or single ended. The sampling clocks for each of the four channels are generated from the clock input using a carefully matched clock buffer tree. Internal clock dividers are utilized to control the clock for each ADC during interleaving. The clock tree is controlled by the Mode of operations. HMCAD1511 uses internally generated references. The differential reference value is 1V. This results in a differential input of -1V to correspond to the zero code of the ADC, and a differential input of +1V to correspond to the full-scale code (code 255). 1 2 4 Sampling Order LVDS Output Fine Gain Branch 1 D1A 1 2 D1B 2 1 D2A 3 2 D2B 4 1 D3A 5 2 D3B 6 1 D4A 7 2 D4B 8 Table 24: Dual Channel Mode Channel # 1 2 Sampling Order LVDS Output Fine Gain Branch 1 D1A 1 2 D1B 3 3 D2A 2 4 D2B 4 1 D3A 5 2 D3B 7 3 D4A 6 4 D4B 8 The ADC employs a Pipeline converter architecture. Each Pipeline Stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes. Table 25: Single Channel Mode HMCAD1511 operates from two sets of supplies and grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by DVDD and DVSS. Interleaving Effects and Sampling Order Interleaving ADCs will generate interleaving artifacts caused by gain, offset and timing mismatch between the ADC branches. The design of HMCAD1511 has been optimized to minimize these effects. It is not possible, though, to eliminate mismatch completely, such that additional compensation may be needed, especially when using high digital gain settings. The internal digital fine gain control may be used to compensate for gain errors between the ADC branches. Due to the optimization of HMCAD1511 there is not a one-to-one correspondence between the sampling order, LVDS output order and the branch number. Tables 23, 24 and 25 give an overview of the corresponding branches, LVDS outputs and sampling order for the different high speed modes. Channel # 1 Sampling Order LVDS Output Fine Gain Branch 1 D1A 1 2 D1B 6 3 D2A 2 4 D2B 5 5 D3A 8 6 D3B 3 7 D4A 7 8 D4B 4 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 A / D Converters - SMT Theory of Operation 0 - 26 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Recommended Usage Analog Input The analog input to HMCAD1511 ADC is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The VCM pin provides a voltage suitable as common mode voltage reference. The internal buffer for the VCM voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_bc<1:0> register. A / D Converters - SMT 0 The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with HMCAD1511 input specifications. Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 13 must be adjusted according to the recommendations for the driver. AC-Coupling Figure 11: Input configuration Figure 12 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. DC-Coupling Figure 13 shows a recommended configuration for DC-coupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as reference to set the common mode voltage. 0 - 27 Figure 12: DC coupled input Figure 13: Transformer coupled input A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 14 shows a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. The bandwidth should preferably exceed the sampling rate of the ADC several times. It is also important to minimize phase mismatch between the differential ADC inputs for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Figure 14: AC coupled input Figure 15 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. Note that Start Up Time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. Clock Input and Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In HMCAD1511 only the rising edge of the clock is used. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, hence a wide common mode voltage range is accepted. Differential clock sources such as LVDS, LVPECL or differential sine wave can be utilized. LVDS/LVPECL clock signals must be appropriately terminated as close to the ADC clock pins as possible. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. CMOS input clock is not recommended above 200 MHz clock frequency. For differential sine wave clock input the amplitude must be at least 0.8 Vpp. No additional configuration is needed to set up the clock source format. The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. SNRjitter = 20 * log (2 * * IN * t) (1) where fIN is the signal frequency, and t is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Application Usage Example This section gives an overview on how HMCAD1511 can be used in an application utilizing all active modes with a single clock source. The example assumes that a 1 GHz clock source is applied. A differential clock should be used, and can be generated from a single ended crystal oscillator, using a transformer or balun in conjunction with ac-coupling to convert from single ended to differential signal. 0 A / D Converters - SMT If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. Start-up Initialization The start-up sequence will be as follows: * Apply power * Apply reset (RESETN low, then high, or SPI command 0x00 0x0001) * Set power down (PD pin high or SPI command 0x0F 0x0200) For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 28 HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter * Set LVDS bit clock phase (phase_ddr, register 0x42)) if other than default must be used (depends on the receiver). * Select operating mode, for instance dual channel mode, and clock divider factor (SPI command 0x31 0x0102). * Set active mode (PD pin low or SPI command 0x0F 0x0000) * Select analog inputs, for instance input 1 on channel 1 and input 3 on channel 2 (SPI commands 0x3A 0202 and 0x3B 0808) A / D Converters - SMT 0 0 - 29 Change Mode When changing operational mode, power down must be activated due to internal synchronization routines. A typical mode change will then be like this: * Set power down (PD pin high or SPI command 0x0F 0x0200) * Change mode to for example Single channel mode (SPI command 0x31 0x0001) * Set active mode (PD pin low or SPI command 0x0F 0x0000) * Select analog inputs, for instance Input 1 (SPI commands 0x3A 0202 and 0x3B 0202) Table 26 gives an overview of the operational modes in this example and the SPI commands to apply for each mode. Table 26: Overview of Operating Modes and Setup Conditions Operating Mode Sampling Speed (MSPS) Clock Divider Factor SPI command for Mode Selection and Clock Divider Single channel 1000 1 0x31 0x0001 Dual channel 500 2 0x31 0x0102 Quad channel 250 4 0x31 0x0204 Select Analog Input When an operational mode is selected, the analog inputs can be changed `on-the-fly'. To change analog input one merely have to apply the dedicated SPI commands. The change will occur instantaneously at the end of each SPI command. Table 27: Example of Some Analog Input Selections Operating Mode Signal Input Selection SPI Commands Single channel IP4/IN4 0x3A 1010, 0x3B 1010 Dual channel Ch1: IP2/IN2 Ch2: IP3/IN3 0x3A 0404, 0x3B 0808 Ch1: IP4/IN4 Quad channel Ch2: IP3/IN3 Ch3: IP2/IN2 0x3A 1008, 0x3B 0402 Ch4: IP1/IN1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter Outline Drawing Table 28: 7x7 mm QFN 48 Pin (LP7) Dimensions Symbol Millimeter Inch Min Typ Max Min Typ Max A 0.8 0.9 1 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.0008 0.002 A2 b 0.2 0.18 D 0.3 0.007 7.00 bsc D2 5.15 L 0.3 e F 0.25 0.008 0.01 0.012 A / D Converters - SMT 0 0.276 bsc 5.3 5.4 0.203 0.4 0.5 0.012 0.50 bsc 0.2 0.209 0.213 0.016 0.02 0.020 bsc 0.008 Package Information Part Number Package Body Material Lead Finish MSL [1] Package Marking [2] HMCAD1511 RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn Level 2A HAD1511 XXXX [1] MSL, Peak Temp: The moisture sensitivity level rating classified according to the JEDEC industry standard and to peak solder temperature. [2] Proprietary marking XXXX, 4-Digit lot number XXXX For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 30