GT24C08 GT24C08 2-WIRE 8K Bits Serial EEPROM Copyright (c) 2011 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. Giantec Semiconductor, Inc. A3 www.giantec-semi.com 1/21 GT24C08 Table of Contents 1. 2. 3. 4. Features ..................................................................................................................................................................... 3 General Description ............................................................................................................................................. 3 Functional Block Diagram ................................................................................................................................ 4 Pin Configuration................................................................................................................................................... 5 4.1 8-Pin SOIC, TSSOP and MSOP ............................................................................................................. 5 4.2 8-Lead UDFN .......................................................................................................................................... 5 4.3 Pin Definition ........................................................................................................................................... 5 4.4 Pin Descriptions ...................................................................................................................................... 5 5. Device Operation................................................................................................................................................... 6 5.1 2-WIRE Bus ............................................................................................................................................ 6 5.2 The Bus Protocol .................................................................................................................................... 6 5.3 Start Condition ........................................................................................................................................ 6 5.4 Stop Condition......................................................................................................................................... 6 5.5 Acknowledge ........................................................................................................................................... 6 5.6 Reset ....................................................................................................................................................... 6 5.7 Standby Mode ......................................................................................................................................... 6 5.8 Device Addressing .................................................................................................................................. 6 5.9 Write Operation ....................................................................................................................................... 7 5.10 Read Operation..................................................................................................................................... 7 5.11 Diagrams ............................................................................................................................................... 8 5.12 Timing Diagrams ................................................................................................................................. 11 6. Electrical Characteristics .............................................................................................................................. 12 6.1 Absolute Maximum Ratings .................................................................................................................. 12 6.2 Operating Range................................................................................................................................... 12 6.3 Capacitance .......................................................................................................................................... 12 6.4 DC Electrical Characteristic .................................................................................................................. 13 6.5 AC Electrical Characteristic .................................................................................................................. 14 7. Ordering Information......................................................................................................................................... 15 8. Top Markings ......................................................................................................................................................... 16 8.1 SOIC Package ...................................................................................................................................... 16 8.2 TSSOP Package ................................................................................................................................... 16 8.3 UDFN Package ..................................................................................................................................... 16 8.4 MSOP Package .................................................................................................................................... 16 9. Package Information ......................................................................................................................................... 17 9.1 SOIC ..................................................................................................................................................... 17 9.2 TSSOP .................................................................................................................................................. 18 9.3 UDFN .................................................................................................................................................... 19 9.4 MSOP.................................................................................................................................................... 20 10. Revision History ................................................................................................................................................ 21 Giantec Semiconductor, Inc. A3 www.giantec-semi.com 2/21 GT24C08 1. Features 2 - TM Two-Wire Serial Interface, I C Compatible Bi-directional data transfer protocol Page Size: 16 bytes Page write mode - Wide-voltage Operation - VCC = 1.7V to 5.5V Partial page writes allowed Self timed write cycle: 5 ms (max.) Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V) Noise immunity on inputs, besides Schmitt trigger Standby current (max.): 1 A, 1.7V High-reliability Operating current (max.): 3 mA, 5.5V Hardware Data Protection - - - Write Protect Pin Endurance: 1 million cycles Data retention: 100 years Industrial grade Sequential & Random Read Features Packages: SOIC, TSSOP, UDFN, MSOP and CSP Memory organization: 8Kb (1,024 x 8) Lead-free, RoHS, Halogen free, Green 2. General Description The GT24C08 is an industrial standard electrically erasable appropriate. The GT24C08 also has a Write Protect programmable read only memory (EEPROM) device that function via WP pin to cease from overwriting the data utilizes stored inside the memory array. the industrial standard 2-wire interface for communications. The GT24C08 contains a memory array of In order to refrain the state machine entering into a wrong 8K bits (1,024x8), which is organized in 16-byte per page. state during power-up sequence or a power toggle off-on The EEPROM operates in a wide voltage range from 1.7V condition, a power on reset circuit is embedded. During to 5.5V, which fits most application. The product provides power-up, the device does not respond to any instructions low-power operations and low standby current. The device until the supply voltage (VCC) has reached an acceptable is offered in Lead-free, RoHS, halogen free or Green stable level above the reset threshold voltage. Once VCC package. The available package types are 8-pin SOIC, passes the power on reset threshold, the device is reset TSSOP, UDFN, MSOP and CSP. and enters into the Standby mode. This would also avoid The GT24C08 is compatible to the standard 2-wire bus any inadvertent Write operations during power-up stage. protocol. The simple bus consists of Serial Clock (SCL) and During power-down process, the device will enter into Serial Data (SDA) signals. Utilizing such bus protocol, a standby mode, once VCC drops below the power on reset Master device, such as a microcontroller, can usually threshold voltage. In addition, the device will be in standby control one or more Slave devices, alike this GT24C08. The mode after receiving the Stop command, provided that no bit stream over the SDA line includes a series of bytes, internal write operation is in progress. Nevertheless, it is not which identifies a particular Slave device, an instruction, an recommended to send an command until the VCC reaches address within that Slave device, and a series of data, if its operating level. Giantec Semiconductor, Inc. A3 www.giantec-semi.com 3/21 GT24C08 3. Functional Block Diagram 8 SDA 5 SCL 6 WP 7 X DECODER VCC HIGH VOLTAGE GENERATOR TIMING & CONTROL CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR A0 1 A1 2 A2 3 WORD ADDRESS COUNTER ACK Y DECODER CLOCK DI/O GND 4 DATA REGISTER nMOS Giantec Semiconductor, Inc. A3 EEPROM ARRAY www.giantec-semi.com 4/21 GT24C08 4. Pin Configuration 4.1 8-Pin SOIC, TSSOP and MSOP 4.2 8-Lead UDFN Top View Top View A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL GND 4 5 SDA GND 4 5 SDA 4.3 Pin Definition Pin No. Pin Name I/O Definition 1 A0 I Device Address Input 2 A1 I Device Address Input 3 A2 I Device Address Input 4 GND - Ground 5 SDA I/O 6 SCL I Serial Clock Input 7 WP I Write Protect Input 8 VCC - Power Supply Serial Address and Data input and Data out put 4.4 Pin Descriptions SCL floated, it's defaulted to "zero". Thus, a total of 2 devices This input clock pin is used to synchronize the data transfer can be connected on a single bus system. to and from the device. WP SDA WP is the Write Protect pin. While the WP pin is connected The SDA is a bi-directional pin used to transfer addresses to the power supply of GT24C08, the entire array becomes and data into and out of the device. The SDA pin is an open Write Protected (i.e. the device becomes Read only). When drain output and can be wired with other open drain or open WP is tied to Ground or left floating, the normal write collector outputs. However, the SDA pin requires a pull-up operations are allowed. resistor connected to the power supply. VCC A0, A1, A2 Supply voltage The A0, A1 and A2 are the device address inputs. GND For GT24C08, only A2 pin is for hardwire address input, Ground of supply voltage while the A0 and A1 pins are no connected. Once A2 is Giantec Semiconductor, Inc. A3 www.giantec-semi.com 5/21 GT24C08 5. Device Operation The GT24C08 serial interface supports communications 2 loss), or needs to be terminated mid-stream. The reset is using industrial standard 2-wire bus protocol, such as I C. initiated when the Master device creates a Start condition. 5.1 2-WIRE Bus To do this, it may be necessary for the Master device to The two-wire bus is defined as Serial Data (SDA), and monitor the SDA line while cycling the SCL up to nine times. Serial Clock (SCL). The protocol defines any device that (For each clock signal transition to High, the Master checks sends data onto the SDA bus as a transmitter, and the for a High level on SDA.) receiving devices as receivers. The bus is controlled by 5.7 Standby Mode Master device that generates the SCL, controls the bus While in standby mode, the power consumption is minimal. access, and generates the Start and Stop conditions. The The GT24C08 enters into standby mode during one of the GT24C08 is the Slave device. following conditions: a) After Power-up, while no Op-code is 5.2 The Bus Protocol sent; b) After the completion of an operation and followed Data transfer may be initiated only when the bus is not busy. by the Stop signal, provided that the previous operation is During a data transfer, the SDA line must remain stable not Write related; or c) After the completion of any internal whenever the SCL line is high. Any changes in the SDA line write operations. while the SCL line is high will be interpreted as a Start or 5.8 Device Addressing Stop condition. The Master begins a transmission on by sending a Start The state of the SDA line represents valid data after a Start condition, then sends the address of the particular Slave condition. The SDA line must be stable for the duration of devices to be communicated. The Slave device address is 8 the High period of the clock signal. The data on the SDA line bits format as shown in Figure. 5-5. may be changed during the Low period of the clock signal. The four most significant bits of the Slave address are fixed There is one clock pulse per bit of data. Each data transfer (1010) for GT24C08. is initiated with a Start condition and terminated by a Stop The GT24C08 utilizes bits B0 and B1 to address one of the condition. four 256-byte blocks in the device. Also, bit A2 is being 5.3 Start Condition compared with the hardwired value of A2 input pin. Up to The Start condition precedes all commands to the device two GT24C08 units can be connected onto the same 2-wire and is defined as a High to Low transition of SDA when SCL bus. is High. The EEPROM monitors the SDA and SCL lines and The last bit of the Slave address specifies whether a Read will not respond until the Start condition is met. or Write operation is to be performed. When this bit is set to 5.4 Stop Condition 1, Read operation is selected. While it is set to 0, Write The Stop condition is defined as a Low to High transition of operation is selected. SDA when SCL is High. All operations must end with a Stop After the Master transmits the Start condition and Slave condition. address byte appropriately, the associated 2-wire Slave 5.5 Acknowledge device, GT24C08, will respond with ACK on the SDA line. After a successful data transfer, each receiving device is Then GT24C08 will pull down the SDA on the ninth clock required to generate an ACK. The Acknowledging device cycle, signaling that it received the eight bits of data. pulls down the SDA line. The GT24C08 then prepares for a Read or Write operation 5.6 Reset by monitoring the bus. The GT24C08 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted (e.g. a power Giantec Semiconductor, Inc. A3 www.giantec-semi.com 6/21 GT24C08 5.9 Write Operation condition followed by the Slave address for a Write 5.9.1 Byte Write operation. If the EEPROM is still busy with the Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte address that is to be written into the address pointer of the GT24C08. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The GT24C08 acknowledges once more and the Master generates the Stop condition, at which time operation, no ACK will be returned. If the GT24C08 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. 5.10 Read Operation Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to "1". There are three Read operation options: current address read, random address read and sequential read. the device begins its internal programming cycle. While this 5.10.1 Current Address Read internal cycle is in progress, the device will not respond to The GT24C08 contains an internal address counter which any request from the Master device. maintains the address of the last byte 5.9.2 Page Write incremented by one. For example, if the previous operation The GT24C08 is capable of 16-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 15 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the four lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device accessed, is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to "1"), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the GT24C08 discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 5-8. Current Address Read Diagram.) should transmit more than 16 bytes prior to issuing the Stop 5.10.2 Random Address Read condition, the address counter will "roll over," and the Selective Read operations allow the Master device to select previously written data will be overwritten. Once all 16 bytes at random any memory location for a Read operation. The are received and the Stop condition has been sent by the Master device first performs a 'dummy' Write operation by Master, the internal programming cycle begins. At this point, sending the Start condition, Slave address and byte all received data is written to the GT24C08 in a single Write address of the location it wishes to read. After the GT24C08 cycle. All inputs are disabled until completion of the internal acknowledges the byte address, the Master device resends Write cycle. the Start condition and the Slave address, this time with the 5.9.3 Acknowledge (ACK) Polling R/W bit set to one. The EEPROM then responds with its The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 5-9. Random Address Read Diagram.) GT24C08 initiates the internal Write cycle. ACK polling can 5.10.3 Sequential Read be initiated immediately. This involves issuing the Start Sequential Reads can be initiated as either a Current Giantec Semiconductor, Inc. A3 www.giantec-semi.com 7/21 GT24C08 Address Read or Random Address Read. After the with the data from address n followed by the data from GT24C08 sends the initial byte sequence, the Master address n+1,n+2 ... etc.. The address counter increments device now responds with an ACK indicating it requires by one automatically, allowing the entire memory contents additional data from the GT24C08. The EEPROM continues to be serially read during sequential Read operation. When to output data for each ACK received. The Master device the memory address boundary of the array is reached, the terminates the sequential Read operation by pulling SDA address counter "rolls over" to address 0, and the device High (no ACK) indicating the last data word to be read, continues to output data. (Refer to Figure 5-10. Sequential followed by a Stop condition. The data output is sequential, Read Diagram). 5.11 Diagrams Figure 5-1. Typical System Bus Configuration VCC SDA SCL Master Transmitter/Receiver GT24CXX Figure 5-2. Output Acknowledge SCL from Master 1 8 9 Data Output from Transmitter TAA Data Output from Receiver TAA ACK SDA Giantec Semiconductor, Inc. A3 STOP CONDITION SCL START CONDITION Figure 5-3. Start and Stop Conditions www.giantec-semi.com 8/21 GT24C08 Figure 5-4. Data Validity Protocol Data Change SCL Data Stable Data Stable SDA Figure 5-5. Slave Address Bit 7 6 5 4 3 2 1 0 1 0 1 0 A2 B1 B0 R/W Figure 5-6. Byte Write S T A R T Device Address SDA Bus Activity W R I T E Byte Address A C K M S B S T O P Data A C K A C K L S B R/W Figure 5-7. Page Write S T A R T W R I T E Byte Address(n) A A C C K K Device Address SDA Bus Activity M S B Data(n+1) A C K Data(n+15) A C K A C K L S B R/W Giantec Semiconductor, Inc. A3 Data(n) S T O P www.giantec-semi.com 9/21 GT24C08 Figure 5-8. Current Address Read S T A R T R E A D Device Address S T O P Data A C K SDA Bus Activity M S B L S B N O A C K R/W Figure 5-9. Random Address Read S T A R T Device Address SDA Bus Activity W R I T E Byte Address(n) A C K M S B S T A R T Device Address A C K R E A D S T O P Data n A C K N O L S B R/W A C K DUMMY WRITE Figure 5-10. Sequential Read Device Address SDA Bus Activity R E A D Data Byte n A C K Data Byte n+1 A C K S T O Data Byte n+x P Data Byte n+2 A C K A C K N O R/W Giantec Semiconductor, Inc. A3 A C K www.giantec-semi.com 10/21 GT24C08 5.12 Timing Diagrams Figure 5-11. Bus Timing TR TF THIGH TLOW TSU:STO SCL TSU:STA THD:STA TSU:DAT THD:DAT TBUF SDAIN TAA TDH SDAOUT TSU:WP THD:WP WP Figure 5-12. Write Cycle Timing SCL SDA ACK Word n TWR STOP Condition Giantec Semiconductor, Inc. A3 START Condition www.giantec-semi.com 11/21 GT24C08 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage -0.5 to + 6.5 V VP Voltage on Any Pin -0.5 to VCC + 0.5 V TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C IOUT Output Current 5 mA Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6.2 Operating Range Range Ambient Temperature (TA) VCC Industrial -40C to +85C 1.7V to 5.5V Note: Giantec offers Industrial grade for Commercial applications (0C to +70C). 6.3 Capacitance Symbol Parameter[1, 2] Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF CI/O Input / Output Capacitance VI/O = 0V 8 pF Notes: [1] Tested initially and after any design or process changes that may affect these parameters and not 100% tested. Test conditions: TA = 25C, f = 1 MHz, VCC = 5.0V [2] Giantec Semiconductor, Inc. A3 www.giantec-semi.com 12/21 GT24C08 6.4 DC Electrical Characteristic Industrial: TA = -40C to +85C, VCC = 1.7V ~ 5.5V Symbol Parameter [1] VCC Test Conditions Min. Max. Unit 1.7 5.5 V VCC Supply Voltage VIH Input High Voltage 0.7*VCC VCC+1 V VIL Input Low Voltage -1 0.3* VCC V ILI Input Leakage Current 5V -- 2 A ILO Output Leakage Current 5V -- 2 A VIN = VCC max VOL1 Output Low Voltage 1.7V IOL = 0.15 mA -- 0.2 V VOL2 Output Low Voltage 2.5V IOL = 2.1 mA -- 0.4 V ISB1 Standby Current 1.7V VIN = VCC or GND -- 1 A ISB2 Standby Current 2.5V VIN = VCC or GND -- 2 A ISB3 Standby Current 5V VIN = VCC or GND -- 3 A 1.7V Read at 400 KHz -- 0.8 mA 2.5V Read at 1 MHz -- 1 mA 5.5V Read at 1 MHz -- 2 mA 1.7V Write at 400 KHz -- 1 mA 2.5V Write at 1 MHz -- 2 mA 5.5V Write at 1 MHz -- 3 mA ICC1 ICC2 Read Current Write Current Note: The parameters are characterized but not 100% tested. Giantec Semiconductor, Inc. A3 www.giantec-semi.com 13/21 GT24C08 6.5 AC Electrical Characteristic Industrial: TA = -40C to +85C, Supply voltage = 1.7V to 5.5V Symbol Parameter [1] [2] 1.7VVCC<2.5V 2.5VVCC<4.5V 4.5VVCC5.5V Min. Min. Min. Max. 400 Max. FSCL SCK Clock Frequency 1000 TLOW Clock Low Period 1200 -- 600 -- THIGH Clock High Period 600 -- 400 Max. Unit 1000 KHz 600 -- ns -- 400 -- ns TR Rise Time (SCL and SDA) -- 300 -- 300 -- 300 ns TF Fall Time (SCL and SDA) -- 300 -- 100 -- 100 ns TSU:STA Start Condition Setup Time 600 -- 250 -- 250 -- ns TSU:STO Stop Condition Setup Time 600 -- 250 -- 250 -- ns THD:STA Start Condition Hold Time 600 -- 250 -- 250 -- ns TSU:DAT Data In Setup Time 100 -- 100 -- 100 -- ns THD:DAT Data In Hold Time 0 -- 0 -- 0 -- ns 100 900 50 400 50 400 ns 100 -- 50 -- 50 -- ns -- 5 -- 5 -- 5 ms 1000 -- 400 -- 400 -- ns TAA Clock to Output Access time (SCL Low to SDA Data Out Valid) TDH Data Out Hold Time (SCL Low to SDA Data Out Change) TWR Write Cycle Time TBUF Bus Free Time Before New Transmission TSU:WP WP pin Setup Time 600 -- 600 -- 600 THD:WP WP pin Hold Time 1200 -- 1200 -- 1200 -- ns -- 100 -- 50 -- 50 ns T Notes: Noise Suppression Time [1] [2] The parameters are characterized but not 100% tested. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5.0V), 10 k (1.7V) CL = 100 pF Input pulse voltages: 0.3*VCC to 0.7*VCC Input rise and fall times: 50 ns Timing reference voltages: half VCC level Giantec Semiconductor, Inc. A3 ns www.giantec-semi.com 14/21 GT24C08 7. Ordering Information Industrial Grade: -40C to +85C, Lead-free Voltage Range Part Number* Package (8-pin)* 1.7V to 5.5V GT24C08-2GLI-TR 150-mil SOIC GT24C08-2ZLI-TR 3 x 4.4 mm TSSOP GT24C08-2UDLI-TR 2 x 3 x 0.55 mm UDFN GT24C08-2SLI-TR 3 x 3 mm MSOP GT24C08-2CLI-TR CSP * 1. Contact Giantec Sales Representatives for availability and other package information. 2. The product is packed in tape and reel "-TR" (4K per reel), except UDFN is 5K per reel. 3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable. 4. Giantec offers Industrial grade for Commercial applications (0C to +70C). Giantec Semiconductor, Inc. A3 www.giantec-semi.com 15/21 GT24C08 8. Top Markings 8.1 SOIC Package G: Giantec Logo 408-2GLI: GT24C08-2GLI-TR YWW: Date Code, Y=year, WW=week 8.2 TSSOP Package GT: Giantec Logo 408-2ZLI: GT24C08-2ZLI-TR YWW: Date Code, Y=year, WW=week 8.3 UDFN Package GT: Giantec Logo 43: GT24C08-2UDLI-TR YWW: Date Code, Y=year, WW=week 8.4 MSOP Package GT: Giantec Logo 4082SLI: GT24C08-2SLI-TR YWW: Date Code, Y=year, WW=week Giantec Semiconductor, Inc. A3 www.giantec-semi.com 16/21 GT24C08 9. Package Information 9.1 SOIC 8L 150mil SOIC Package Outline Detail A D E E1 b ZD Detail A GAUGE PLANE A SEATING PLANE e SYMBOLS A1 DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES MIN NOM MAX MIN NOM MAX A 1.35 -- 1.75 0.053 -- 0.069 A1 0.10 -- 0.25 0.004 -- 0.010 b 0.33 -- 0.51 0.013 -- 0.020 D 4.80 -- 5.00 0.189 -- 0.197 Note: E 5.80 -- 6.20 0.228 -- 0.244 1. Controlling Dimension:MM E1 3.80 -- 4.00 0.150 -- 0.157 2. Dimension D and E1 do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard MS-012 5. Drawing is not to scale e L 1.27 BSC. 0.38 L1 -- 0.050 BSC. 1.27 0.015 0.25 BSC. ZD -- 0.050 0.010 BSC. 0.545 REF. 0 Giantec Semiconductor, Inc. A3 L L1 0.021 REF. 8 0 -- 8 www.giantec-semi.com 17/21 GT24C08 9.2 TSSOP 8L 3x4.4mm TSSOP Package Outline D C e 8 L E E1 1 12(4X) A2 0.10mm b A1 A SYMBOLS A A1 A2 b c D E E1 e L DIMENSIONS IN MILLIMETERS MIN -0.05 0.80 0.19 0.09 2.90 4.30 0.45 0 Giantec Semiconductor, Inc. A3 Note: 1. Controlling Dimension:MM 2. Dimension D and E do not include Mold protrusion 3. Dimension b does not include dambar protrusion/intrusion. 4. Refer to Jedec standard MO-153 AA 5. Drawing is not to scale 6. Package may have exposed tie bar. NOM --1.00 --3.00 4.40 6.4 BSC 0.65 BSC 0.60 -- DIMENSIONS IN INCHES MAX 1.20 0.15 1.05 0.30 0.20 3.10 4.50 MIN -0.002 0.031 0.007 0.004 0.114 0.169 0.75 8 0.018 0 NOM --0.039 --0.118 0.173 0.252 BSC 0.026 BSC 0.024 -- MAX 0.047 0.006 0.041 0.012 0.008 0.122 0.177 0.030 8 www.giantec-semi.com 18/21 GT24C08 9.3 UDFN 8L 2x3mm UDFN Package Outline D2 D e K E2 E PIN#1 IDENTIFICATION CHAMFER L b PIN#1 DOT BY MARKING BOTTOM VIEW TOP VIEW A A1 A2 SIDE VIEW SYMBOLS DIMENSIONS IN MILLIMETERS A A1 b A2 D D2 E E2 e K L MIN 0.50 0.00 0.18 1.25 1.15 0.40 0.20 NOM 0.55 -0.25 0.152 REF 2.00 BSC 1.40 3.00 BSC 1.30 0.50 BSC. -0.30 DIMENSIONS IN INCHES MAX 0.60 0.05 0.30 MIN 0.020 0.000 0.007 1.50 0.049 1.40 0.045 -0.40 0.016 0.008 NOM 0.022 -0.010 0.006 REF 0.079 BSC 0.055 0.118 BSC 0.051 0.020 BSC. -0.012 MAX 0.024 0.002 0.012 0.059 0.055 -0.016 Note: 1. Controlling Dimension:MM 2. Drawing is not to scale Giantec Semiconductor, Inc. A3 www.giantec-semi.com 19/21 GT24C08 9.4 MSOP 8L 120mil MSOP package Outline D C e L E 12(4X) E1 A2 A A1 b SYMBOLS DIMENSIONS IN MILLIMETERS A A1 A2 b C D E E1 e L DIMENSIONS IN INCHES MIN NOM MAX MIN NOM MAX -0.05 0.75 0.25 0.13 2.90 2.90 --0.85 --3.00 3.00 4.90 BSC 0.65 BSC --- 1.10 0.15 0.95 0.40 0.23 3.10 3.10 -0.002 0.030 0.010 0.005 0.114 0.114 0.043 0.006 0.037 0.016 0.009 0.122 0.122 0.55 7 -0 --0.033 --0.118 0.118 0.193 BSC 0.026 BSC --- -0 0.022 7 Note: 1. Controlling Dimension:MM 2. Dimension D and E do not include Mold protrusion 3. Refer to Jedec standard MO187 4. Drawing is not to scale Giantec Semiconductor, Inc. A3 www.giantec-semi.com 20/21 GT24C08 10. Revision History Revision Date Descriptions A0 Jan. 2010 Initial version A1 Jun. 2011 New datasheet format A2 Jan. 2012 Change VCC from 1.8V to 1.7V A3 Oct. 2013 Revise SOIC/SOP to SOIC Giantec Semiconductor, Inc. A3 www.giantec-semi.com 21/21