CY7C1324H 2-Mbit (128 K x 18) Flow-Through Sync SRAM 2-Mbit (128 K x 18) flow-through Sync SRAM Features Functional Description 128 K x 18 common I/O 3.3 V core power supply 3.3- / 2.5-V I/O supply Fast clock-to-output times 6.5 ns (133 MHz version) Provide high-performance 2-1-1-1 access rate User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable Offered in JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP) package "ZZ" sleep mode option The CY7C1324H[1] is a 128 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1324H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1324H operates from a +3.3 V core power supply while all outputs may operate with either a +3.3 V or +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 133 MHz Unit Maximum access time 6.5 ns Maximum operating current 225 mA Maximum standby current 40 mA Note 1. Refer to the application note, SRAM System Design Guidelines for more information on best-practices recommendations. Cypress Semiconductor Corporation Document Number: 001-00208 Rev. *D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 8, 2010 [+] Feedback CY7C1324H Logic Block Diagram A0,A1,A ADDRESS REGISTER A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BWB DQB,DQPB WRITE REGISTER BWA DQA,DQPA WRITE REGISTER DQB,DQPB WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQA,DQPA WRITE DRIVER DQs DQPA DQPB BWE GW CE1 CE2 CE3 ENABLE REGISTER INPUT REGISTERS OE ZZ SLEEP CONTROL Document Number: 001-00208 Rev. *D Page 2 of 19 [+] Feedback CY7C1324H Contents 2-Mbit (128 K x 18) Flow-Through Sync SRAM .............. 1 Features ............................................................................. 1 Functional Description ..................................................... 1 Selection Guide ................................................................ 1 Logic Block Diagram ........................................................ 2 Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences .............................................................. 6 Sleep Mode ........................................................................ 7 Interleaved Burst Address Table (MODE = Floating or VDD) ............................................... 7 Linear Burst Address Table (MODE = GND) .................. 7 ZZ Mode Electrical Characteristics ................................. 7 Truth Table ........................................................................ 7 Truth Table for Read/Write .............................................. 8 Document Number: 001-00208 Rev. *D Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 Electrical Characteristics ................................................. 9 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 Switching Characteristics .............................................. 11 Timing Diagrams ............................................................ 12 Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 16 Package Diagram ............................................................ 16 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC Solutions ......................................................... 19 Page 3 of 19 [+] Feedback CY7C1324H Pin Configurations A A 35 36 37 38 39 40 41 42 45 46 47 48 49 50 A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A NC/4M 44 34 A 43 81 82 83 84 BWE OE ADSC ADSP ADV 85 86 GW 89 87 CLK 91 88 VDD VSS 93 90 BWA CE3 94 92 NC BWB 95 CE2 NC 96 98 97 A CE1 99 A 31 VSS VDDQ NC NC NC 33 VSS DQB DQB VDDQ VSS DQB DQB DQPB NC CY7C1324H A BYTE B DQB DQB VSS VDDQ DQB DQB NC VDD NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 VDDQ VSS NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A NC NC NC 100 Figure 1. 100-Pin TQFP Pinout[2] A NC NC VDDQ VSS NC DQPB DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ BYTE A DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Note 2. Refer to the application note, AN4025 for more information on SRAM address and I/O pin order. Document Number: 001-00208 Rev. *D Page 4 of 19 [+] Feedback CY7C1324H Pin Definitions Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the 128 K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA,BWB InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a Byte Write. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. OE InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical Asynchronous "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs DQPA, DQPB I/OSynchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tristate condition. VDD Power Supply Power supply inputs to the core of the device. VSS Ground Ground for the device. Document Number: 001-00208 Rev. *D Page 5 of 19 [+] Feedback CY7C1324H Pin Definitions Name (continued) I/O Description VDDQ I/O power supply Power supply for the I/O circuitry. MODE Input-static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. NC No Connects. Not internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133 MHz device). The CY7C1324H supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:B]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a Write) on the next clock rise, the appropriate data is latched and written into the device. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are tristated during a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:B]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] is written into the specified address location. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are tristated when a Write is detected, even a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1324H provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to an interleaved burst sequence. Document Number: 001-00208 Rev. *D Page 6 of 19 [+] Feedback CY7C1324H Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Address Table (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD- 0.2 V 40 mA tZZS Device operation to ZZ ZZ > VDD - 0.2 V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V tZZI ZZ Active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled 2tCYC ns 2tCYC 0 ns ns Truth Table Cycle Description[3, 4, 5, 6] Address Used Deselected cycle, power-down None H Deselected cycle, power-down None L Deselected cycle, power-down None L Deselected cycle, power-down None L Deselected cycle, power-down None X None X External L Sleep mode, power-down Read cycle, begin burst CE1 CE2 CE3 ZZ ADSP ADSC ADV X L X L X X X L-H Tristate L X L L X X X X L-H Tristate X H L L X X X X L-H Tristate L X L H L X X X L-H Tristate X X L H L X X X L-H Tristate X X H X X X X X X Tristate H L L L X X X L L-H Q X WE OE CLK DQ Read cycle, begin burst External L H L L L X X X H L-H Tristate Write cycle, begin burst External L H L L H L X L X L-H D Read cycle, begin burst External L H L L H L X H L L-H Q Read cycle, begin burst External L H L L H L X H H L-H Tristate Read cycle, continue burst Next X X X L H H L H L L-H Q Read cycle, continue burst Next X X X L H H L H H L-H Tristate Read cycle, continue burst Next H X X L X H L H L L-H Q Read cycle, continue burst Next H X X L X H L H H L-H Tristate Write cycle, continue burst Next X X X L H H L L X L-H D Document Number: 001-00208 Rev. *D Page 7 of 19 [+] Feedback CY7C1324H Truth Table Cycle Description[3, 4, 5, 6] Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WE OE CLK DQ Write cycle, continue burst Next H X X L X H L L X L-H D Read cycle, suspend burst Current X X X L H H H H L L-H Q Read cycle, suspend burst Current X X X L H H H H H L-H Tristate Read cycle, suspend burst Current H X X L X H H H L L-H Q Read cycle, suspend burst Current H X X L X H H H H L-H Tristate Write cycle, suspend burst Current X X X L H H H L X L-H D Write cycle, suspend burst Current H X X L X H H L X L-H D Truth Table for Read/Write Function[3, 4] GW BWE BWB BWA Read H H X X Read H L H H Write byte (A, DQPA) H L H L Write byte (B, DQPB) H L L H Write all bytes H L L L Write all bytes L X X X Notes 3. X = "Do not care." H = Logic HIGH, L =Logic LOW. 4. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA, BWB), BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-00208 Rev. *D Page 8 of 19 [+] Feedback CY7C1324H Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Storage temperature ................................ -65 C to +150 C Latch-up Current.................................................... > 200 mA Ambient temperature with power applied . -55 C to +125 C Operating Range Supply voltage on VDD relative to GND ........-0.5 V to +4.6 V Range Ambient Temperature DC voltage applied to outputs in tristate-0.5 V to VDDQ + 0.5 V Commercial 0 C to +70 C DC input voltage .................................. -0.5 V to VDD + 0.5 V Industrial Supply voltage on VDDQ relative to GND....... -0.5 V to +VDD -40 C to +85 C VDD VDDQ 3.3 V -5%/+10% 2.5 V -5% to VDD Current into outputs (LOW) ......................................... 20 mA Electrical Characteristics Over the operating range [7, 8] Parameter Description VDD Power supply voltage VDDQ I/O supply voltage VOH VOL VIH VIL IX Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[7] Input leakage current except ZZ and MODE Input current of MODE Test Conditions Min Max Unit 3.135 3.6 V For 3.3 V I/O 3.135 VDD V For 2.5 V I/O 2.375 2.625 V For 3.3 V I/O, IOH = -4.0 mA 2.4 For 2.5 V I/O, IOH = -1.0 mA 2.0 For 3.3 V I/O, IOL = 8.0 mA 0.4 For 2.5 V I/O, IOL = 1.0 mA 0.4 V For 3.3 V I/O 2.0 VDD + 0.3 V For 2.5 V I/O 1.7 VDD + 0.3 V For 3.3 V I/O -0.3 0.8 For 2.5 V I/O -0.3 0.7 GND VI VDDQ 5 5 Input = VSS -30 Input = VDD Input current of ZZ V Input = VSS V A A 5 A 30 A -5 Input = VDD V A IOZ Output leakage current GND VI VDDQ, output disabled 5 A IDD VDD operating supply current VDD = Max, IOUT = 0 mA, f = fMAX= 1/tCYC 7.5 ns cycle, 133 MHz 225 mA ISB1 Automatic CE power-down current--TTL inputs Maximum VDD, 7.5 ns cycle, 133 MHz device deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching 90 mA ISB2 Automatic CE power-down Current--CMOS inputs Maximum VDD, 7.5 ns cycle, 133 MHz device deselected, VIN VDD - 0.3 V or VIN 0.3 V, f = 0, inputs static 40 mA -5 Notes 7. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2 V (Pulse width less than tCYC/2). 8. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 001-00208 Rev. *D Page 9 of 19 [+] Feedback CY7C1324H Electrical Characteristics Over the operating range (continued)[7, 8] Max Unit ISB3 Parameter Automatic CE power-down current--CMOS inputs Description Maximum VDD, device deselected, VIN VDDQ - 0.3 V or VIN 0.3 V, f = fMAX, inputs switching Test Conditions 7.5 ns cycle, 133 MHz Min 75 mA ISB4 Automatic CE power-down current--TTL inputs Maximum VDD, 7.5 ns cycle, 133 MHz device deselected, VIN VDD - 0.3 V or VIN 0.3 V, f = 0, inputs static 45 mA Capacitance Parameter[9] Description CIN Input capacitance CCLK Clock input capacitance CI/O I/O capacitance Test Conditions 100 TQFP Max Unit 5 pF TA = 25 C, f = 1 MHz, VDD = 3.3 V VDDQ = 2.5 V 5 pF 5 pF 100 TQFP Package Unit 30.32 C/W 6.85 C/W Thermal Resistance Parameter[9] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Figure 2. AC Test Loads and Waveforms 3.3-V I/O Test Load R = 317 3.3 V OUTPUT ALL INPUT PULSES VDD OUTPUT RL = 50 Z0 = 50 10% GND 5 pF VL = 1.5 V (a) INCLUDING JIG AND SCOPE 2.5-V I/O Test Load R = 351 (b) (c) 10% (a) 90% 10% 90% GND 5 pF VT = 1.25 V ALL INPUT PULSES VDDQ OUTPUT RL = 50 Z0 = 50 1 ns 1 ns R = 1667 2.5 V OUTPUT 90% 10% 90% R =1538 INCLUDING JIG AND SCOPE (b) 1 ns 1 ns (c) Note 9. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-00208 Rev. *D Page 10 of 19 [+] Feedback CY7C1324H Switching Characteristics Over the operating range[10, 11] Parameter tPOWER Description VDD(typical) to the first access[12] -133 Min Max 1 Units ms Clock tCYC Clock cycle time 7.5 ns tCH Clock HIGH 2.5 ns tCL Clock LOW 2.5 ns Output Times tCDV Data output valid after CLK Rise tDOH Data output hold after CLK Rise tCLZ Clock to low Z[13, 14, 15] 6.5 ns 2.0 ns 0 ns tCHZ Clock to high Z[13, 14, 15] 3.5 ns tOEV OE LOW to output valid 3.5 ns tOELZ OE LOW to output low Z[13, 14, 15] tOEHZ OE HIGH to output high Z[13, 14, 15] 3.5 ns 0 ns Setup Times tAS Address setup before CLK rise 1.5 ns tADS ADSP, ADSC setup before CLK rise 1.5 ns tADVS ADV setup before CLK rise 1.5 ns tWES GW, BWE, BW[A:B] setup before CLK Rise 1.5 ns tDS Data input setup before CLK rise 1.5 ns tCES Chip enable setup 1.5 ns tAH Address hold after CLK rise 0.5 ns tADH ADSP, ADSC hold after CLK rise 0.5 ns tWEH GW, BWE, BW[A:B] hold after CLK rise 0.5 ns tADVH ADV hold after CLK rise 0.5 ns tDH Data input hold after CLK rise 0.5 ns tCEH Chip enable hold after CLK rise 0.5 ns Hold Times Notes 10. Timing reference level is 1.5 V when VDDQ = 3.3 V and 1.25 V when VDDQ = 2.5 V 11. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied higher than VDD(minimum) initially before a read or write operation can be initiated. 13. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 14. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 15. This parameter is sampled and not 100% tested. Document Number: 001-00208 Rev. *D Page 11 of 19 [+] Feedback CY7C1324H Timing Diagrams Figure 3. Read Cycle Timing[16] tCYC CLK t tADS CH t CL tADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 t WES t WEH GW, BWE,BW [A:B] tCES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OELZ tCDV t CHZ tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Single READ BURST READ DON'T CARE Burst wraps around to its initial state UNDEFINED Note 16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-00208 Rev. *D Page 12 of 19 [+] Feedback CY7C1324H Timing Diagrams (continued) Figure 4. Write Cycle Timing[16, 17] t CYC CLK t tADS t CH CL tADH ADSP tADS ADSC extends burst. tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst. tWES tWEH BWE, BW[A:B] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst. OE t Data in (D) High-Z t OEHZ t DS DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON'T CARE Extended BURST WRITE UNDEFINED Note 17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW Document Number: 001-00208 Rev. *D Page 13 of 19 [+] Feedback CY7C1324H Timing Diagrams (continued) Figure 5. Read/Write Timing[16, 18, 19] tCYC CLK t CH tADS tADH tAS tAH t CL ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) t t WES WEH BWE, BW[A:B] tCES tCEH CE ADV OE tDS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH tOELZ D(A3) tCDV Q(A2) Back-to-Back READs Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON'T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 18. The data bus (Q) remains in high Z following a write cycle unless an ADSP, ADSC, or ADV cycle is performed. 19. GW is HIGH. Document Number: 001-00208 Rev. *D Page 14 of 19 [+] Feedback CY7C1324H Timing Diagrams (continued) Figure 6. ZZ Mode Timing[20, 21] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I t RZZI DDZZ ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON'T CARE Notes 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in High Z when exiting ZZ sleep mode. Document Number: 001-00208 Rev. *D Page 15 of 19 [+] Feedback CY7C1324H Ordering Information Table 1 lists the CY7C1324H key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Key Features and Ordering Information Speed (MHz) 133 Package Diagram Ordering Code Package Type CY7C1324H-133AXC 51-85050 100-pin TQFP (14 x 20 x 1.4 mm) Pb-free Operating Range Commercial Ordering Code Definitions CY 7 C 13XX H XXX A(X,C) Package Type: A = TQFP, X = Pb-free Temperature Grade: C = Commercial Maximum operating frequency 90 nm 2-Mbit (128 K x 18) Flow-Through Sync SRAM Technology: CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Package Diagram 51-85050 *C Document Number: 001-00208 Rev. *D Page 16 of 19 [+] Feedback CY7C1324H Acronyms Table 2. Acronyms Used in this Document Acronym Description I/O input/output JEDEC joint electron device engineering council TQFP thin quad flat pack Document Conventions Units of Measure Table 3. Units of Measure Symbol Unit of Measure C degree Celsius MHz megahertz A micro amperes mA milliamperes mm millimeters ns nano seconds ohms % percent pF pico Farad V volts W watts Document Number: 001-00208 Rev. *D Page 17 of 19 [+] Feedback CY7C1324H Document History Page Document Title: CY7C1324H 2-Mbit (128 K x 18) Flow-Through Sync SRAM Document Number: 001-00208 Revision ECN Orig. of Change Submission Date Description of Change ** 347377 PCI See ECN New datasheet *A 428408 NXR See ECN Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed 100 MHz Speed-bin Changed Three-State to tristate. Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table. Modified test condition from VIH < VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the Ordering Information Table. Replaced Package Diagram of 51-85050 from *A to *B *B 459347 NXR See ECN Included 2.5 V I/O option Updated the Ordering Information table. *C 2897120 NJY 03/22/10 Removed inactive parts from Ordering Information table; Updated package diagram. *D 3025128 RAJA/NJY 09/08/10 Template update. Added ordering code definitions, acronyms, units of measure, reference documents, and table of contents. Document Number: 001-00208 Rev. *D Page 18 of 19 [+] Feedback CY7C1324H Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive PSoC Solutions cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-00208 Rev. *D (R) Revised October 8, 2010 Page 19 of 19 (R) PSoC DesignerTM is a trademark and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback