CY7C1324H
2-Mbit (128 K × 18) Flow-Through
Sync SRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-00208 Rev. *D Revised October 8, 2010
2-Mbit (128 K × 18) flow-through Sync SRAM
Features
■128 K × 18 common I/O
■3.3 V core power supply
■3.3- / 2.5-V I/O supply
■Fast clock-to-output times
❐6.5 ns (133 MHz version)
■Provide high-performance 2-1-1-1 access rate
■User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■Separate processor and controller address strobes
■Synchronous self-timed write
■Asynchronous output enable
■Offered in JEDEC-standard Pb-free 100-pin thin quad flat
pack (TQFP) package
■“ZZ” sleep mode option
Functional Description
The CY7C1324H[1] is a 128 K × 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin. The
CY7C1324H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are acti ve. Subs equent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1324H operates from a +3.3 V core power supply
while all outputs may operate with either a +3.3 V or +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz Unit
Maximum access time 6.5 ns
Maximum operating current 225 mA
Maximum standby current 40 mA
Note
1. Refer to the applicatio n note, SRAM System Design Guidelines for more inf ormation on best-practices recommendations.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 2 of 19
ADDRESS
REGISTER
ADV
CLK BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE1
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE2
CE3
GW
BWE
A0,A1,A
BWB
BWA
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQP
A
DQP
B
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
SLEEP
CONTROL
ZZ
Logic Block Diagram
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 3 of 19
Contents
2-Mbit (128 K × 18) Flow-Through Sync SRAM ..............1
Features .............................................................................1
Functional Description ................... ... ............................ ...1
Selection Guide ................................................................1
Logic Block Diagram .............. .. ............................ ... ... ......2
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ................... ... ............................ ... ...6
Single Read Accesses ...... .............................. ............6
Single Write Accesses Initiated by ADSP ...................6
Single Write Accesses Initiated by ADSC ...................6
Burst Sequences ..............................................................6
Sleep Mode ........................................................................7
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................ ...7
Linear Burst Address Table (MODE = GND) ............ ... ...7
ZZ Mode Electrical Characteristics .................................7
Truth Table ........................................................................7
Truth Table for Read/Write ..............................................8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
Electrical Characteristics .................................... ... ... .......9
Capacitance ....................................................................10
Thermal Resistance ........................................................10
Switching Characteristics ..............................................11
Timing Diagrams ............................................................12
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagram ............................................................16
Acronyms ........................................................................17
Document Conventions ............. .. ............................. .. ...17
Units of Measure ..................... ... ............................ ...17
Document History Page ..................... ............................18
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products .................................................................... 19
PSoC Solutions ..................... ....................................19
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 4 of 19
Pin Configurations
Figure 1. 100-Pin TQFP Pinout[2]
Note
2. Refer to the application note, AN4025 for more information on SRAM address and I/O pin order.
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/9M
A
A
A
A
A
NC/4M
A
NC
VDDQ
VSS
NC
DQPB
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSP
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE A
AADV
ADSC
ZZ
MODE
NC/18M
NC
BYTE B CY7C1324H
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 5 of 19
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous Address Inputs used to select one of the 128 K address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW , and CE1, CE2, and CE3 are sampled active.
A[1:0] feed the 2-bit counter.
BWA,BWBInput-
Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.
GW Input-
Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
BWE Input-
Synchronous Byte Write Enable Input, active LOW . Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a Byte Write.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW , during a burst operation.
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled
only when a new external address is loaded.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the ri sing edge of CLK. Used in conjuncti on
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external
address is loaded.
OE Input-
Asynchronous Output Enable, as ynchronous input, active LOW. Controls the directio n of the I/O pins.
When LOW , the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and
act as input data pins. OE is masked during the first clock of a Read cycle when emerging from
a deselected state.
ADV Input-
Synchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP Input-
Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH
ADSC Input-
Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized.
ZZ Input-
Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
DQPA, DQPBI/O-
Synchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed in a tristate condition.
VDD Power
Supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 6 of 19
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
The CY7C1324H supports secondary cache in systems utilizing
either a linear or interleave d burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LO W (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the me mory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW , BWE,
and BW[A:B]) are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a Write) on the next clock rise,
the appropriate data is latched and written into the device. Byte
Writes are allowed. During Byte Writes, BWA controls DQA and
BWB controls DQB. All I/Os are tristated during a Byte Write.
Since this is a common I/O device, the asynchronous OE input
signal must be deasserted and the I/Os must be tristated prior to
the presentation of data to DQs. As a safety precaution, the data
lines are tristated once a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:B])
indicate a write access. ADSC is ignored if ADSP is active LOW .
The addresses presented are loa ded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ[A:D] is written into the
specified address location. Byte Writes are allowed. During Byte
Writes, BWA controls DQA and BWB controls DQB. All I/Os are
tristated when a Write is detected, even a Byte Write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tristated once a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1324H provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can
follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects
a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to
default to an interleaved burst sequence.
VDDQ I/O power
supply Power supply for the I/O circuitry.
MODE Input-static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operatio n. Mode Pin has an internal pull-up.
NC No Connects. Not internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M,
576M, and 1G are address expansion pins and are not internally conne cted to the die.
Pin Definitions (continued)
Name I/O Description
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 7 of 19
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guara nteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V 40 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2 V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC ns
tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Truth Table
Cycle Desc ription[3, 4, 5, 6] Address
Used CE1CE2CE3ZZ ADSP ADSC ADV WE OE CLK DQ
Deselected cycle, power-down None H X X L X L X X X L-H Tristate
Deselected cycle, power-down None L L X L L X X X X L-H Tristate
Deselected cycle, power-down None L X H L L X X X X L-H Tristate
Deselected cycle, power-down None L L X L H L X X X L-H Tristate
Deselected cycle, power-down None X X X L H L X X X L-H Tristate
Sleep mode, power-down None X X X H X X X X X X Tristate
Read cycle, begin burst External L H L L L X X X L L-H Q
Read cycle, begin burst External L H L L L X X X H L-H Tristate
Write cycle, begin burst External L H L L H L X L X L-H D
Read cycle, begin burst External L H L L H L X H L L-H Q
Read cycle, begin burst External L H L L H L X H H L-H Tristate
Read cycle, continue burst Next X X X L H H L H L L-H Q
Read cycle, continue burst Next X X X L H H L H H L-H Tristate
Read cycle, continue burst Next H X X L X H L H L L-H Q
Read cycle, continue burst Next H X X L X H L H H L-H Tristate
Write cycle, continue burst Next X X X L H H L L X L-H D
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 8 of 19
Write cycle, continue burst Next H X X L X H L L X L-H D
Read cycle, suspend burst Current X X X L H H H H L L-H Q
Read cycle, suspend burst Current X X X L H H H H H L-H Tristate
Read cycle, suspend burst Current H X X L X H H H L L-H Q
Read cycle, suspend burst Current H X X L X H H H H L-H Tristate
Write cycle, suspend burst Current X X X L H H H L X L-H D
Write cycle, suspend burst Current H X X L X H H L X L-H D
Truth Table for Read/Write
Function[3, 4] GW BWE BWBBWA
Read H H X X
Read H L H H
Write byte (A, DQPA)HLHL
Write byte (B, DQPB)HLLH
Write all bytes H L L L
Write all bytes L X X X
Truth Table
Cycle Desc ription[3, 4, 5, 6] Address
Used CE1CE2CE3ZZ ADSP ADSC ADV WE OE CLK DQ
Notes
3. X = “Do not care.” H = Logic HIGH, L =Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals (BW A, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA,
BWB), BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on su bsequent
clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate.
OE is a don't care for the remaind er of the write cycle.
6. OE is asynchronous and is not sampled wit h the clock rise. It is masked in ternally during write cycles. During a read cycle all data b it s are trist ate when O E is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 9 of 19
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User gui d el i ne s are not tested.
Storage temperature ................................–65 C to +150 C
Ambient temperature with power applie d . –55 C to +125 C
Supply voltage on VDD relative to GND........–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC voltage applied to outputs in tristate–0.5 V to VDDQ + 0.5 V
DC input voltage..................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW ) ..................... .. ..................20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient
Temperature VDD VDDQ
Commercial 0 °C to +70 °C 3.3 V
–5%/+10% 2.5 V –5%
to VDD
Industrial –40 °C to +85 °C
Electrical Characteristics
Over the operating range [7, 8]
Parameter Description Test Conditions Min Max Unit
VDD Power supply voltage 3.135 3.6 V
VDDQ I/O supply voltage For 3.3 V I/O 3.135 VDD V
For 2.5 V I/O 2.375 2.625 V
VOH Output HIGH voltage For 3.3 V I/O, IOH = –4.0 mA 2.4 V
For 2.5 V I/O, IOH = –1.0 mA 2.0
VOL Output LOW voltage For 3.3 V I/O, IOL = 8.0 mA 0.4 V
For 2.5 V I/O, IOL = 1.0 mA 0.4
VIH Input HIGH voltage For 3.3 V I/O 2.0 VDD + 0.3 V V
For 2.5 V I/O 1.7 VDD + 0.3 V
VIL Input LOW voltage[7] For 3.3 V I/O –0.3 0.8 V
For 2.5 V I/O –0. 3 0.7
IXInput leakage current
except ZZ and MODE GND VI VDDQ 55µA
Input current of MODE Input = VSS –30 µA
Input = VDD 5µA
Input current of ZZ Input = VSS –5 µA
Input = VDD 30 µA
IOZ Output leakage current GND VI VDDQ, output disabled –5 5 µA
IDD VDD operating supply
current VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC 7.5 ns cycle, 133 MHz 225 mA
ISB1 Automatic CE
power-down
current—TTL in p uts
Maximum VDD,
device deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
7.5 ns cycle, 133 MHz 90 mA
ISB2 Automatic CE
power-down
Current—CMOS inputs
Maximum VDD,
device deselected,
VIN VDD – 0.3 V or VIN 0.3 V ,
f = 0, inputs static
7.5 ns cycle, 133 MHz 40 mA
Notes
7. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 10 of 19
ISB3 Automatic CE
power-down
current—CMOS inputs
Maximum VDD,
device deselected,
VIN VDDQ – 0.3 V or
VIN 0.3 V,
f = fMAX, inputs switching
7.5 ns cycle, 133 MHz 75 mA
ISB4 Automatic CE
power-down
current—TTL in p uts
Maximum VDD,
device deselected,
VIN VDD – 0.3 V or VIN 0.3 V ,
f = 0, inputs static
7.5 ns cycle, 133 MHz 45 mA
Electrical Characteristics
Over the operating range (contin ued)[7, 8]
Parameter Description Test Conditions Min Max Unit
Capacitance
Parameter[9] Description Test Conditions 100 TQFP
Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VDD = 3.3 V
VDDQ = 2.5 V
5pF
CCLK Clock input capacitance 5 pF
CI/O I/O capacitance 5pF
Thermal Resist ance
Parameter[9] Description Test Conditions 100 TQFP
Package Unit
JA Thermal resistance
(junction to ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
30.32 C/W
JC Thermal resistance
(junction to case) 6.85 C/W
Figure 2. AC Test Loads and Waveforms
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
V
L
= 1.5 V
3.3 V ALL INPUT PULSES
VDD
GND
90%
10% 90%
10%
1 ns 1 ns
(c)
3.3-V I/O Test Load
OUTPUT
R = 1667
R =1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
1 ns 1 ns
(c)
2.5-V I/O Test Load
Note
9. Tested initially and after any design or process change that may affect these parameters.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 11 of 19
Switching Characteristics
Over the operating range[10, 1 1]
Parameter Description –133 Units
Min Max
tPOWER VDD(typical) to the first access[12] 1ms
Clock
tCYC Clock cycle time 7.5 ns
tCH Clock HIGH 2.5 ns
tCL Clock LOW 2.5 ns
Output Times
tCDV Data output valid after CLK Rise 6.5 ns
tDOH Data output hold after CLK Rise 2.0 ns
tCLZ Clock to low Z[13, 14, 15] 0ns
tCHZ Clock to high Z[13, 14, 15] 3.5 ns
tOEV OE LOW to output valid 3.5 ns
tOELZ OE LOW to output low Z[13, 14, 15] 0ns
tOEHZ OE HIGH to output high Z[13, 14, 15] 3.5 ns
Setup Times
tAS Address setup be fo re CLK rise 1.5 ns
tADS ADSP, ADSC setup before CLK rise 1.5 ns
tADVS ADV setup before CLK rise 1.5 ns
tWES GW, BWE, BW[A:B] setup before CLK Rise 1.5 ns
tDS Data input setup before CLK rise 1.5 ns
tCES Chip enable setup 1.5 ns
Hold Times
tAH Address hold after CLK rise 0.5 ns
tADH ADSP, ADSC hold after CLK rise 0.5 ns
tWEH GW, BWE, BW[A:B] hold after CLK rise 0.5 ns
tADVH ADV hold after CLK rise 0.5 ns
tDH Data input hold after CLK rise 0.5 ns
tCEH Chip enable hold after CLK rise 0.5 ns
Notes
10.Timing reference level is 1.5 V when VDDQ = 3.3 V and 1.25 V when VDDQ = 2.5 V
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied higher than VDD(minimum) initially before a read or write
operation can be initiated.
13.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. T ransition is measured ± 200 mV from steady-state voltage.
14.At any voltage and temperature , tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contenti on between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve high Z prior to low Z under the same system conditions.
15.This parameter is sampled and not 100% tested.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 12 of 19
Timing Diagrams
Figure 3. Read Cycle Timing[16]
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
Data Out (Q) High-Z
tCLZ tDOH
tCDV
tOEHZ
tCDV
Single READ BURST
READ
tOEV tOELZ tCHZ
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2) Q(A2 + 1) Q(A2 + 2)
Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2)Q(A2 + 3)
A2
ADV suspends burst.
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
GW, BWE,BW
[A:B]
CE
ADV
OE
Note
16.On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 13 of 19
Figure 4. Write Cycle Timing [16, 17]
Timing Diagrams (continued)
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
High-Z
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1)
D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
A2 A3
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
tOEHZ
tADVH
tADVS
tWEH
tWES
tDH
tDS
tWEH
tWES
Byte write signals are ignored for first cycle when
ADSP initiates burst.
ADSC extends burst.
ADV suspends burst.
DON’T CARE UNDEFINED
ADSP
ADSC
BWE,
BW[A:B]
GW
CE
ADV
OE
Data in (D)
Data Out (Q)
Note
17.Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 14 of 19
Figure 5. Read/Write Timing[1 6, 18, 19]
Timing Diagrams (continued)
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3 A4
BURST READBack-to-Back READs
High-Z
Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)
tWEH
tWES
tOEHZ
tDH
tDS
tCDV
tOELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW[A:B]
CE
ADV
OE
Data In (D)
Data Out (Q)
Notes
18.The data bus (Q) remains in high Z following a write cycle unless an ADSP, ADSC, or ADV cycle is performed.
19.GW is HIGH.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 15 of 19
Figure 6. ZZ Mode Timing[20, 21]
Timing Diagrams (continued)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
20.Device must be deselected when entering ZZ mode. Se e Cycle De scriptions table for all possible signal conditions to deselect the device.
21.DQs are in High Z when exiting ZZ sleep mode.
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 16 of 19
Ordering Information
Table 1 lists the CY7C1324H key package features and ordering codes. The table contains only the parts that are currently available.
If you do not see what yo u are looki ng for, contact your local sales representative. For more information, visit the Cypress website at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Ordering Code Definitions
Package Diagram
Table 1. Key Features and Ordering Information
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
133 CY7C1324H-133AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
CY
Marketing Code: 7 = SRAM
7C13XX
Technology: CMOS
Company ID: CY = Cypress
H
2-Mbit (128 K × 18) Flow-Throu gh
Sync SRAM
90 nm
Maximum operating frequency
A(X,C) Package Type:
A = TQFP, X = Pb-free
Tem perature Grad e: C = C om mercial
XXX
51-85050 *C
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 17 of 19
Acronyms
Document Conventions
Units of Measure
Table 2. Acronyms Used in this Document
Acronym Description
I/O input/output
JEDEC joint electron device engineering council
TQFP thin quad flat pack
Table 3. Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA micro amperes
mA milliamperes
mm millimeters
ns nano seconds
ohms
% percent
pF pico Farad
Vvolts
Wwatts
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CY7C1324H
Document Number: 001-00208 Rev. *D Page 18 of 19
Document History Page
Document Title: CY7C1324H 2-Mbit (128 K × 18) Flow-Through Sync SRAM
Document Number: 001-00208
Revision ECN Orig. of
Change Submission
Date Description of Chang e
** 347377 PCI See ECN New datasheet
*A 428408 NXR See ECN Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100 MHz Speed-bin
Changed Three-State to tristate.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from VIH < VDD to VIH VDD
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 fro m *A to *B
*B 459347 NXR See ECN Included 2.5 V I/O option
Updated the Ordering Information table.
*C 2897120 NJY 03/22/10 Removed inactive parts from Ordering Information table; Updated package
diagram.
*D 3025128 RAJA/NJY 09/08/10 Te mp late update.
Added ordering code definitions, acronyms, units of measure, reference
documents, and table of contents.
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Document Number: 001-00208 Rev. *D Revised October 8, 2010 Page 19 of 19
PSoC Designer™ is a trademark and PSoC® and Cap Se nse® are registered trademarks of Cypress Semiconductor Corporation.
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation.
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1324H
© Cypress Semicondu ctor Corpor ation, 2005-2010. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss pro duc ts are n ot war ran ted no r int end ed to be us ed for
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to an express written agreement wit h Cypr ess. Fu rth er mor e, Cypre ss does not author iz e it s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protec tion (Unit ed States and fore ign),
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a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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