Synchronous Equipment Timing Source
for SONET or SDH Network Elements
ACS8510 SETS
Description Features
Block Diagram
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
ADVANCED COMMUNCIATIONS FINAL
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Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia specifi-
cations
Accepts 14 individual input reference clocks
Generates 11 output clocks
Supports Free-Run, Locked and Holdover
modes of operation
Robust input clock source quality monitoring on
all inputs
Automatic hit-less source switchover on loss
of input
Phase build-out for output clock phase conti-
nuity during input switchover and mode transi-
tions
Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EEPROM
Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
Support for Master/Slave device configuration
alignment and hot/standby redundancy
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 v operation. 5 v I/O compatible
Operating temperature (ambient) -40°C to
+85°C
Available in 100 pin LQFP package
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
DPLL/Freq. Synthesis
T
OUT0
selector
T
OUT4
selector
Chip Clock
Generator
Divider
PFD
D PLL/Fr eq. Synthesis
Divider
Monitors
Digital
Loop
Filter APLL
Frequency
Dividers
Microprocessor
Port
14 Input
Reference
Source
including:
AMI 64/8 kHz
2 kHz
8 kHz
N x 8 kHz
1.544 M Hz
2.048 M Hz
6.48 M Hz
19.44 MH z
25.92 MH z
38.88 MH z
51.84 MH z
77.76 MH z
155.52 MHz
DTO
Digital
Loop
Filter
PFD
11 Ou tput Po rts
including:
1.544/2.048 MHz
3.088/4.096 MHz
6.176/8.182 MHz
12.352/16.384 MHz
6.48 MH z
19.44 MH z
25.92 MH z
38.88 MH z
51.84 MH z
77.76 MH z
155.52 MH z
311.04 MHz
AMI 64/8 kH z
2 kHz MFrSync
8 kHz FrSync
Input
Ports
6xT
IN1
4xT
IN2
4xT
IN3
Output
Ports
2xT
OUT4
7xT
OUT0
MFrSync
FrSync
TCXO (*OC XO)
CLK
IEEE
1149.1
JTAG
TCK
TDI
TMS
TRST
TDO
Priorit y
Table
Register
Set
Priorit y
Table
Register
Set
DTO
MFrSync
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Table of Contents
Pin diagram................................................................................................................................................3
Pin descriptions.........................................................................................................................................4
Functional description...............................................................................................................................7
Electrical specification............................................................................................................................45
Microprocessor interface timing characteristics.......................................................................................56
Package information................................................................................................................................65
Application information............................................................................................................................67
Revision History.......................................................................................................................................68
Order information....................................................................................................................................69
Local oscillator clock..........................................................................................................................................................8
Input Interfaces..................................................................................................................................................................8
Over voltage protection.......................................................................................................................................................8
Input reference clock ports................................................................................................................................................9
Input wander and jitter tolerance...................................................................................................................................11
Output clock ports...........................................................................................................................................................13
Output wander and jitter..................................................................................................................................................14
Phase variation.................................................................................................................................................................16
Phase build-out.................................................................................................................................................................17
Microprocessor interface................................................................................................................................................17
Interrupt enable and clear...............................................................................................................................................19
Register map description.................................................................................................................................................21
Register map description.................................................................................................................................................25
Selection of input reference clock source.....................................................................................................................33
Clock quality monitoring..................................................................................................................................................34
Activity monitoring...........................................................................................................................................................35
Modes of operation..........................................................................................................................................................38
Protection facility.............................................................................................................................................................39
JTAG..............................................................................................................................................................................42
Power on reset - PORB.....................................................................................................................................................42
Absolute maximum range...............................................................................................................................................45
Operating conditions.......................................................................................................................................................45
TTL DC characterisitics...................................................................................................................................................45
PECL DC characteristics..................................................................................................................................................47
LVDS DC characteristics..................................................................................................................................................48
AMI DC characteristics....................................................................................................................................................49
Jitter characteristics........................................................................................................................................................52
JTAG timing........................................................................................................................................................................55
Motorola mode..................................................................................................................................................................56
Intel mode................................................................................................................................................................58
Multiplexed mode.............................................................................................................................................................60
Serial mode.......................................................................................................................................................................62
EEPROM mode.................................................................................................................................................................64
Simplified application schematic...................................................................................................................................67
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Figure 1: Top view of 100 pin LQFP package.
NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float.
100 SONSDHB
99 MSTSLVB
98IC
97IC
96IC
95 TO9
94 TO5
93 TO4
92 DGND
91 VDD
90 TO3
89 TO2
88 TO1
87 DGND
86 VDD
85 VDD
84 DGND
83 AD0
82 AD1
81 AD2
80 AD3
79 AD4
78 AD5
77 AD6
76 AD7
75 RDY
74 PORB
73 ALE
72 RDB
71 WRB
70 CSB
69 A0
68 A1
67 A2
66 A3
65 A4
64 A5
63 A6
62 DGND
61 VDD
60 UPSEL0
59 UPSEL1
58 UPSEL2
57 I14
56 I13
55 I12
54 I11
53 I10
52 I9
51 I8
ACS8510
SDH/SONET SETS
Rev 2.x
1
1 AGND
2 TRST
3IC
4NC
5 AGND
6 VA1+
7 TMS
8 INTREQ
9 TCK
10 REFCLK
11 DGND
12 VD+
13 VD+
14 DGND
15 DGND
16 VD+
17 NC
18 SRCSW
19 VA2+
20 AGND
21 TDO
22 IC
23 TDI
24 I1
25 I2
26 VAMI+
27 TO8NEG
28 TO8POS
29 GND_AMI
30 FrSync
31 MFrSync
32 GND_DIFF
33 VDD_DIFF
34 TO6POS
35 TO6NEG
36 TO7POS
37 TO7NEG
38 GND_DIFF
39 VDD_DIFF
40 I5POS
41 I5NEG
42 I6POS
43 I6NEG
44 VDD5
45 SYNC2K
46 I3
47 I4
48 I7
49 DGND
50 VDD
Pin Diagram
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com4
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
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Pin Descriptions
Power
No connections
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com5
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Others
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com6
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com7
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Functional description
The ACS8510 is a highly integrated, single-chip
solution for the SETS function in a SONET/SDH
Network Element, for the generation of SEC
and frame synchronisation pulses. In Free-Run
mode, the ACS8510 generates a stable, low-
noise clock signal from an internal oscillator.
In Locked mode, the ACS8510 selects the most
appropriate input reference source and
generates a stable, low-noise clock signal locked
to the selected reference. In Holdover mode,
the ACS8510 generates a stable, low-noise
clock signal from the internal oscillator,
adjusted to match the last-known-good
frequency of the last-selected reference source.
In all modes, the frequency accuracy, jitter and
drift performance of the clock meet the
requirements of ITU G.812, G.813, G.823, GR
1244-CORE.
The ACS8510 supports all three types of
reference clock source: recovered line clock
(TIN1), PDH network synchronisation timing (TIN2)
and node synchronisation (TIN3). The ACS8510
generates independent TOUT0 and T
OUT4 clocks,
an 8 kHz Frame Synchronisation clock and a 2
kHz Multi-Frame Synchronisation clock.
The ACS8510 has a high tolerance to input
jitter and wander. The output jitter and wander
are low, where the wander transfer is
programmable (0.1 Hz up to 20 Hz cut-off
points).
The ACS8510 supports protection. Two
ACS8510 devices can be configured to provide
protection against a single ACS8510 failure.
The protection maintains alignment of the two
ACS8510 devices (Master and Slave) and
ensures that both ACS8510 devices maintain
the same priority table, choose the same
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com8
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
reference input and generate the TOUT0 clock,
the 8 kHz Frame Synchronisation clock and
the 2 kHz Multi-Frame Synchronisation clock
with the same phase. The ACS8510 includes a
microprocessor port, providing access to the
configuration and status registers for device
setup and monitoring.
Local Oscillator Clock
The Master system clock on the ACS8510
should be provided by an external clock oscillator
of frequency 12.80 MHz. The clock specification
is important for meeting the ITU/ETSI and
Telcordia performance requirements in Holdover
mode. ITU and ETSI specifications permit a
combined drift characteristic, at constant
temperature, of all non-temperature-related
parameters, of up to 10 ppb per day. The same
specifications allow a drift of 1 ppm over a
temperature range of 0 to 70 Celsius. Telcordia
specifications are somewhat tighter, requiring
a non-temperature-related drift of less than 40
ppb per day and a drift of 280 ppb over the
temperature range 0 to 50 Celsius.
ITU and ETSI specification
Tolerance: +/- 4.6 ppm over 20 year life time.
Drift*: +/- 0.05 ppm/15 seconds @ constant temp.
+/- 0.01 ppm/day @ constant temp.
+/- 1 ppm over temp. range 0-70 Celsius
*Frequency drift over supply voltage range of 2.7 V to 3.3 V.
Telcordia GR-1244 CORE specification
Tolerance: +/- 4.6 ppm over 20 year life time.
Drift*: +/- 0.05 ppm/15 seconds @ constant temp.
+/- 0.04 ppm/day @ constant temp.
+/- 0.28 ppm over temp. range 0-50 Celsius
*Frequency drift over supply voltage range of 2.7 V to 3.3 V.
Please contact Semtech for information on
crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less
important than the stability since any frequency
offset can be compensated by adjustment of
register values in the IC. This allows for
calibration and compensation of any crystal
frequency variation away from its nominal value.
+/- 50 ppm adjustment would be sufficient to
cope with most crystals, in fact the range is an
order of magnitude larger due to the use of
two 8 bit register locations. The setting of the
conf_nominal_frequency register allows for this
adjustment. An increase in the register value
increases the output frequencies by 0.02 ppm
for each LSB step. The default value (in decimal)
is 39321. The minimum being 0 and the
maximum 65535, gives a +500 ppm to -700
ppm adjustment range of the output
frequencies.
For example, if the crystal was oscillating at
12.8 MHz + 5 ppm, then the calibration value
in the register to give a -5 ppm adjustment in
output frequencies to compensate for the
crystal inaccuracy, would be : 39321 - (5 /
0.02) = 39071 (decimal).
Input Interfaces
The ACS8510 supports up to fourteen input
reference clock sources from input types TIN1,
TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and
AMI buffer I/O technologies. These interface
technologies support 3.3 V and 5 V operation.
Over-Voltage Protection
The ACS8510 may require Over-Voltage
Protection on input reference clock ports
according to the ITU Recommendation K.41.
Semtech recommends the use of their
protection devices for this purpose (see
separate Semtech data book).
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com9
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Input Reference Clock Ports
Table 1 gives details of the input reference
ports, showing the input technologies and the
range of frequencies supported on each port;
the default spot frequencies and default
priorities assigned to each port on power-up or
by reset are also shown. Note that SDH and
SONET networks use different default
frequencies; the network type is pin-selectable
(using the SONSDHB pin). Specific frequencies
and priorities are set by configuration.
Although each input port is shown as belonging
to one of the types, TIN1, TIN2 or TIN3, they are
fully interchangeable as long as the selected
speed is within the maximum operating speed
of the input port technology.
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
100). Specific frequencies and priorities are set
by configuration.
TTL ports (compatible also with CMOS signals)
support clock speeds up to 100 MHz, with the
highest spot frequency being 77.76 MHz. The
actual spot frequencies supported are; 8 kHz
(and N x 8 kHz), 1.544 MHz/2.048 MHz, 6.48
MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz. The frequency
selection is programmed via the
cnfg_ref_source_frequency register. The
internal DPLL will normally lock to the selected
input at the frequency of the input, eg. 19.44
MHz will lock the DPLL phase comparisons at
19.44 MHz. It is, however, possible to utilise
an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase
comparisons in the DPLL. This pre-divider can
be used in one of 2 ways:
(i) any of the supported spot frequencies can be divided
to 8 kHz by setting the "lock8K" bit (bit 6) in the
appropriate cnfg_ref_source_frequency register
location
(ii) any multiple of 8 kHz between 1544 kHz to 100
MHz can be supported by using the "DivN" feature (bit
7 of the cnfg_ref_source_frequency register). Any
reference input can be set to use DivN independently
of the frequencies and configurations of the other
inputs.
Any reference input with the "DivN" bit set in
the cnfg_ref_source_frequency register will
employ the internal pre-divider prior to the DPLL
locking. The cnfg_freq_divn register contains
the divider ratio N where the reference input
will get divided by (N+1) where 0<N<214-1. The
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
input frequency. When using the "DivN" feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the lock8k bit high (bit
6 in cnfg_ref_source_ frequency register). Any
input set to DivN must have the frequency
monitors disabled (If the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the "DivN" feature, only one N can be
programmed, hence all inputs using the "DivN"
feature must require the same division to get
to 8 kHz.
PECL and LVDS ports support the spot clock
frequencies listed above plus 155.52 MHz and
311.04 MHz. The choice of PECL or LVDS
compatibility is programmed via the
cnfg_differential_inputs register. Unused PECL/
LVDS differential inputs should be fixed with
one input high (VDD) and the other input low
(GND), or set in LVDS mode and left floating, in
which case one input is internally pulled high
and the other low.
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Table 1: Input Reference Source Selection and Priority Table
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51
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Notes for Table 1.
Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot
frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz, 1.544 MHz/2.048 MHz, 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. There are different output clock frequencies available
for SONET and SDH applications. SONSDHB controls the default frequency output. F1/F2 means that the output
frequency is F1 when the SONSDHB pin is High and F2 when SONSDHB pin is Low.
Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz.
Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or
PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin.
An AMI port supports a composite clock,
consisting of a 64 kHz AMI clock with 8 kHz
boundaries marked by deliberate violations of
the AMI coding rules, as specified in ITU
recommendation G.703. Departures from the
nominal pattern are detected within the
ACS8510, and may cause reference-switching
if too frequent. See Figure 9 for more details.
Input Wander and Jitter Tolerance
The ACS8510 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI T1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. Pull-
in, hold-in and pull-out ranges are specified for
each input port in Table 2. Minimum jitter
tolerance masks are specified in Figures 1 and
2, and Tables 3 and 4, respectively. The
ACS8510 will tolerate wander and jitter
components greater than those shown in Figure
1 and Figure 2, up to a limit determined by a
combination of the apparent long-term
frequency offset caused by wander and the
eye-closure caused by jitter (the input source
will be rejected if the offset pushes the
frequency outside the hold-in range for long
enough to be detected, whilst the signal will
also be rejected if the eye closes sufficiently to
affect the signal purity). The 8klocking mode
should be engaged for high jitter tolerance
according to these masks. All reference clock
DivN examples
To lock to 2.000 MHz.
(1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the
frequency to E1/T1. (XX = leaky bucket ID for this input).
(2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (T1).
(3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(4) the DivN register is set to F9 Hex (249 decimal).
To lock to 10.000 MHz.
(1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the
frequency to 6.48 MHz. (XX = leaky bucket ID for this input).
(2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(3) the DivN register is set to 4E1 Hex (1249 decimal).
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
ports are monitored for quality, including
frequency offset and general activity. Single
short-term interruptions in selected reference
clocks may not cause rearrangements, whilst
longer interruptions, or multiple, short-term
interruptions, will cause rearrangements, as will
frequency offsets which are sufficiently large
or sufficiently long to cause loss-of-lock in the
phase-locked loop. The failed reference source
will be removed from the priority table and
declared as unserviceable, until its perceived
quality has been restored to an acceptable
level.
The registers reg sts_curr_inc_offset (address
0C, 0D, 07) report the frequency of the DPLL
with respect to the external TCXO frequency.
This is a 19 bit signed number with one LSB
representing 0.0003 ppm (range of +/- 80
ppm). Reading this regularly can show how the
currently locked source is varying in value e.g.
due to wander on its input.
The ACS8510 performs automatic frequency
monitoring with an acceptable input frequency
offset range of +/- 16.6 ppm. The ACS8510
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the frequency monitors should be
disabled so the input reference source is not
automatically rejected as out of frequency
range.
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Table 2: Input Reference Source Jitter Tolerance.
Notes for Table 2.
Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the
external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.
Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal
frequency of 12.8 MHz.
Note 3. The power up default PDLL range is as stated in note 2, but the range is also programmable from 0 to 80 ppm
in 0.08 ppm steps.
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ADVANCED COMMUNCIATIONS FINAL
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Table 3: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.783 compliant sources
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Output Clock Ports
The device supports a set of main output clocks,
TOUT0 and TOUT4, and a pair of secondary output
clocks, 'Frame-Sync' and 'Multi-Frame-Sync'. The
two main output clocks, TOUT0 and TOUT4, are
independent of each other and are individually-
selectable. The two secondary output clocks,
'Frame-Sync' and 'Multi-Frame-Sync', are derived
from TOUT0. The frequencies of the output clocks
are selectable from a range of pre-defined spot
frequencies and a variety of output technologies
are supported, as defined in Table 5.
Performance-wise, the output ports are
specified in Figures 3, 4 and 5, in terms of
jitter, MTIE (and TDEV) and Phase Error,
respectively.
Low-speed Output Clock (TOUT4)
The TOUT4 clock is supplied on two output ports,
TO8 and TO9. The former port will provide an AMI
signal carrying a composite clock of 64 kHz
and 8 kHz, according to ITU Recommendation
G.703. The latter port will provide a TTL/CMOS
signal at either 1.544 MHz or 2.048 MHz,
depending on the setting of the SONSDHB pin.
High-speed Output Clock (Part of TOUT0)
The TOUT0 port has multiple outputs. Outputs TO1
and TO2 are TTL/CMOS output with a choice of
11 different frequencies up to 51.84 MHz.
Outputs TO3 to TO5 are all TTL/CMOS outputs
with fixed frequencies of 19.44 MHz, 38.88
MHz and 77.76 MHz, respectively. Output TO6
is differential and can support clocks up to
155.52 MHz. Output TO7 is also differential
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com14
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
and can support clocks up to 155.52 MHz.
Each output is individually configured to operate
at the frequencies shown in Table 5
(configuration must be consistent between
ACS8510 devices for protection-switching to be
effective - output clocks will be phase-aligned
between devices). Using the
cnfg_differential_outputs register, outputs TO6
and TO7 can be made to be LVDS or PECL
compatible.
Frame Sync and Multi-Frame Sync Clocks (Part of
TOUT0)
Frame Sync (8 kHz) and Multi-Frame Sync (2
kHz) clocks will be provided on outputs TO10
(FrSync) and TO11 (MFrSync). The FrSync and
MFrSync clocks have a 50:50 mark space ratio.
These will be driven from the TOUT0 clock. They
will be synchronised with their counterparts in
a second ACS8510 device (if used), using the
technique described later.
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
The magnitude of wander and jitter on the
selected input reference clock (in Locked mode);
The internal wander and jitter transfer
characteristic (in Locked mode);
The jitter on the local oscillator clock;
The wander on the local oscillator clock (in
Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources
Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com15
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Holdover mode).
Wander and jitter are treated in different ways
to reflect their differing impacts on network
design. Jitter is always strongly attenuated,
whilst wander attenuation can be varied to suit
the application and operating state. Wander and
jitter attenuation is performed using a digital
phase locked loop (DPLL) with a programmable
bandwidth. This gives a transfer characteristic
of a low pass filter, with a programmable pole.
It is sometimes necessary to change the filter
dynamics to suit particular circumstances - one
example being when locking to a new source,
the filter can be opened up to reduce locking
time and can then be gradually tightened again
to remove wander. Since wander represents a
relatively long-term deviation from the nominal
operating frequency, it affects the rate of supply
of data to the network element. Strong wander
attenuation limits the rate of consumption of
data to within a smaller range, so a larger buffer
Note for Table 5.
Frequencies supported: There are different output clock frequencies available for SONET and SDH applications. SONSDHB
controls the default frequency output. F1/F2 means that the output frequency is F1 when the SONSDHB pin is High and F2
when SONSDHB pin is Low.
Table 5: Output Reference Source Selection Table
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com16
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Figure 3: Wander and Jitter Transfer Characteristsics
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store is required to prevent data loss. But, since
any buffer store potentially increases latency,
wander may often only need to be removed at
specific points within a network where buffer
stores are acceptable, such as at digital cross
connects. Otherwise, wander is sometimes not
required to be attenuated and can be passed
through transparently. The ACS8510 has
programmable wander transfer characteristics
in a range from 0.1 Hz to 20 Hz. The wander
and jitter transfer characteristic is shown in
Figure 3.
Wander on the local oscillator clock will not
have significant effect on the output clock whilst
in Locked mode, so long as the DPLL bandwidth
is set high enough so that the DPLL can
compensate quickly enough for any frequency
changes in the crystal. In Free-Running or
Holdover mode wander on the crystal is more
significant. Variation in crystal temperature or
supply voltage both cause drifts in operating
frequency, as does ageing. These effects must
be limited by careful selection of a suitable
component for the local oscillator, as specified
in the section Local Oscillator Clock.
Phase Variation
There will be a phase shift across the ACS8510
between the selected input reference source
and the output clock. This phase shift may vary
over time but will be constrained to lie within
specified limits. The phase shift is characterised
using two parameters, MTIE (Maximum Time
Interval Error), and TDEV (Time Deviation), which,
although being specified in all relevent
specifications, differ in acceptable limits in each
one. Typical measurements for the ACS8510
are shown in Figures 4 and 5, for Locked mode
operation. Figure 6 shows a typical
measurement of Phase Error accumulation in
Holdover mode operation.
The required performance for phase variation
during Holdover is specified in several ways
depending upon the particular circumstances
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
pertaining:
1. ETSI 300 462-5, Section 9.1, requires that the short-
term phase error during switchover (i.e., Locked to Holdover
to Locked) be limited to an accumulation rate no greater
than 0.05 ppm during a 15 second interval.
2. ETSI 300 462-5, Section 9.2, requires that the long-
term phase error in the Holdover mode should not exceed
{(a1+a2)S+0.5bS2+c}, where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10-4 ns/s2 (allowance for ageing)
c = 120 ns (allowance for entry into Holdover mode).
3. ANSI Tin1.101-1994, Section 8.2.2, requires that the
phase variation be limited so that no more than 255 slips
(of 125 µs each) occur during the first day of Holdover.
This requires a frequency accuracy better than:
((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm.
Temperature variation is not restricted, except to within
the normal bounds of 0 to 50 Celsius.
4. Telcordia GR.1244.CORE, Section 5.2. Table 4. shows
that an initial frequency offset of 50 ppb is permitted on
entering Holdover, whilst a drift over temperature of 280
ppb is allowed; an allowance of 40 ppb is permitted for all
other effects.
5. ITU G.822, Section 2.6, requires that the slip rate during
category(b) operation (interpreted as being applicable to
Holdover mode operation) be limited to less than 30 slips
(of 125 µs each) per hour
((((60 x 60)/30)+125µs)/(60x60)) = 1.042 ppm.
Phase Build Out
Phase Transient Response and Holdover
Phase Build Out (PBO) is the function to minimise
phase transients on the output SEC clock during
input reference switching. If the currently
selected input reference clock source is lost
(due to a short interruption, out of frequency
detection, or complete loss of reference), the
second, next highest priority reference source
will be selected. During this transition, the
Lost_Phase mode is entered.
The typical phase disturbance on clock
reference source switching will be less than 12
ns on the ACS8510. For clock reference
switching caused by the main input failing or
being disconnected, then the phase disturbance
on the output will still be less than the 120 ns
allowed for in the G.813 spec. The actual value
is dependant on the frequency being locked to.
The PBO requirement, as specified in Telcordia
GR1244-CORE, Section 5.7, is that a phase
transient of greater than 3.5 µs occuring in
less than 0.1 seconds should be absorbed. This
will be implemented on a future version.
ITU-T G.813 states that the max allowable short
term phase transient response, resulting from
a switch from one clock source to another,
with Holdover mode entered in between, should
be a maximum of 1 µs over a 15 second
interval. The maximum phase transient or jump
should be less than 120 ns at a rate of change
of less than 7.5 ppm and the Holdover
performance should be better than 0.05 ppm.
On the ACS8510, PBO can be enabled, disabled
or frozen using the µP interface. By default, it
is enabled. When PBO is enabled, it can also
be frozen, which will disable the PBO operation
on the next input reference switch, but will
remain with the current offset. If PBO is disabled
while the device is in the Locked mode, there
will be a phase jump on the output SEC clocks
as the DPLL locks back to 0 degree phase
error.
Micro-Processor Interface
The ACS8510 incorporates a microprocessor
interface, which can be configured for the
following modes via the bus interface mode
control pins UPSEL(2:0) as defined in Table 6.
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Figure 4: Maximum Time Interval Error of TOUT0 output port
Figure 5: Time Deviation of TOUT0 output port
Figure 6: Phase error accumulation of TOUT0 output port in hold-over mode
10
1
0.1
0.01
Time
(ns)
0.01 0.1 110 100 1000 10000
Ob s e r vatio n in te r va l (s )
G .813 optio n 1 con stant temperature wander lim it
TD EV m easurem e nt on 155 M H z output, 19.44 MH z i/p (8kHz locking),
Vectron 6 664 xtal
100
10
1
0.1
0.01
0.01 0.1 110 100 1000 10000
O b s e rv a tio n in te rv a l ( s)
Time
(ns)
G .8 13 o ption 1, constant te m pe rature wander limit
M T IE measurement on 155 M H z output, 19.44 M H z i/p (8 kHz locking),
V ectron 6664 xtal
10000000
1000000
100000
10000
1000
100 1000 10000 100000
Observation interval (s)
Phase Error (ns)
Pe rm itted P hase Error Lim it
Typical m easurem ent, 25°C constant tem perature
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Motorola Mode
Parallel data + address: this mode is suitable
for use with Motorola's 68x0 type bus.
Intel Mode
Parallel data + address: this mode is suitable
for use with Intel's 80x86 type bus.
Multiplexed Mode
Data/address: this mode is suitable for use
with microprocessors which share bus signals
between address and data (e.g., Intel's 80x86
family).
Serial Mode
This mode is suitable for use with
microprocessor which use a serial interface.
EPROM Mode
This mode is suitable for use with an EPROM,
in which configuration data is stored (one-way
communication - status information will not be
accessible). A state machine internal to the
ACS8510 device will perform numerous EPROM
read operations to pull the data out of the
EPROM.
Register Set
All registers are 8-bits wide, organised with the
most-significant bit positioned in the left-most
bit, with bit-significance decreasing towards the
right most bit. Some registers carry several
individual data fields of various sizes, from
single-bit values (e.g. flags) upwards. Several
data fields are spread across multiple registers;
their organisation is shown in the register map,
Table 7.
Configuration Registers
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pin-
settable. All configuration registers can be read
out over the microprocessor port.
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writeable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the Chip_ID and Chip_revision
registers. Configuration registers may be written
to or read from at any time (the complete 8-bit
register must be written, even if only one bit is
being modified). All status registers may be read
at any time and, in some status registers (such
as the sts_interrupts register), any individual
data field may be cleared by writing a "1" into
each bit of the field (writing a "0" value into a
bit will not affect the value of the bit). A
description of each register follows.
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ
(active High).
Bits in the interrupt status register are set (high)
UPSEL(2:0) Mode Description
111 (7) OFF Interface disabled
110 (6) OFF Interface disabled
101 (5) SERIAL Serial uP bus interface
100 (4) MOTOROLA Motorola interface
011 (3) INTEL Intel compatible bus interface
010 (2) MULTIPLEXED Multiplexed bus interface
001 (1) EPROM EPROM read mode
000 (0) OFF Interface disabled
Table 6: Microprocessor Interface Mode Selection
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com20
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
by the following conditions;
(i) any reference source becoming valid or going invalid
(ii) a change in the operating state (eg. locked, holdover
etc.)
(iii) brief loss of the currently selected reference source
(iv) AMI input error
All interrupt sources are maskable via the mask
register, each one being enabled by writing a
'1' to the appropriate bit.
Any unmasked bit set in the interrupt status
register will cause the interrupt request pin to
be asserted (high).
All interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register.
When all pending unmasked interrupts are
cleared the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependant
on the leaky bucket configuration of the activity
monitors. The very fastest leaky bucket setting
will still take up to 128 ms to trigger the
interrupt. The interrupt caused by the brief
loss of the currently selected reference source
is provided to facilitate very fast source failure
detection if desired. It is triggered after missing
just a couple of cycles of the reference source.
Some applications require the facility to switch
downstream devices based on the status of
the reference sources. In order to provide extra
flexibility, it is possible to flag the "main
reference failed" interrupt (addr 06, bit 6) on
the pin TDO. This is simply a copy of the status
bit in the interrupt register and is independent
of the mask register settings. The bit is reset
by writing to the interrupt status register in the
normal way. This feature can be enabled and
disabled by writing to bit 6 of register 48Hex.
This section left blank
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com21
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPtiBataD
)bsm(7 654321 )bsl(0
00di_pihc
)ylnodaer( )0:7(rebmuntrapeciveD
10 )8:51(rebmuntrapeciveD
20noisiver_pihc
)ylnodaer( )0:7(rebmunnoisiverpihC
301lortnoc_gfnc
)etirw/daer( '0'otteS golanA
cnysvid '0'otteS'0'otteS'0'otteS'0'otteS
402lortnoc_gfnc
)etirw/daer( timilgalfssolesahP'0'otteS'1'otteS'0'otteS
50stpurretni_sts
)etirw/daer(
dilav>8_I<
egnahc
dilav>7_I<
egnahc
dilav>6_I<
egnahc
dilav>5_I<
egnahc
dilav>4_I<
egnahc
dilav>3_I<
egnahc
dilav>2_I<
egnahc
dilav>1_I<
egnahc
60gnitarepO
edom
.ferniaM
deliaf
dilav>41_I<
egnahc
dilav>31_I<
egnahc
dilav>21_I<
egnahc
dilav>11_I<
egnahc
dilav>01_I<
egnahc
dilav>9_I<
egnahc
80stupni_4T_sts
)etirw/daer( deliaffer4T 2imA
noitaloiV
2imA
.S.O.L
1imA
noitaloiV
1imA
.S.O.L
90edom_gnitarepo_sts
)ylnodaer( )0:2(edomgnitarepO
A0elbat_ytiroirp_sts
)ylnodaer(
ecruosdilavytiroirptsehgiH ecruosecnereferdetcelesyltnerruC
B0 3
dr
ecruosdilavytiroirptsehgih2
dn
ecruosdilavytiroirptsehgih
C0tesffo_cni_rruc_sts
)ylnodaer(
)0:7(tesffotnemercnitnerruC
D0 )8:51(tesffotnemercnitnerruC
70 )61:81(tesffotnemercnitnerruC
E0dilav_secruos_sts
)ylnodaer(
>8_I<>7_I<>6_I<>5_I<>4_I<>3_I<>2_I<>1_I<
F0 >41_I<>31_I<>21_I<>11_I<>01_I<>9_I<
Register map
Shaded areas in the map are dont care and writing either 0 or 1 will not affect any function of
the device.
Bits labelled Set to 0 or Set to 1 must be set as stated during initialisation of the device,
either following power up, or after a power on reset (POR). Failure to correctly set these bits may
result in the device operating in an unexpected way.
Some registers do not appear in this list. These are either not used, or have test functionality. Do
not write to any undefined registers as this may cause the device to operate in a test mode. If an
undefined register has been inadvertently addressed, the device should be reset to ensure the
undefined registers are at default values.
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com22
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPtiBataD
)bsm(7 654321 )bsl(0
01secruos_ecnerefer_sts
)etirw/daer( >2_I<sutats>1_I<sutats
11 >4_I<sutats>3_I<sutats
21 >6_I<sutats>5_I<sutats
31 >8_I<sutats>7_I<sutats
41 >01_I<sutats>9_I<sutats
51 >21_I<sutats>11_I<sutats
61 >41_I<sutats>31_I<sutats
81ytiroirp_noitceles_fer_gfnc
)etirw/daer( >2_I<ytiroirp_demmargorp >1_I<ytiroirp_demmargorp
91 >4_I<ytiroirp_demmargorp >3_I<ytiroirp_demmargorp
A1 >6_I<ytiroirp_demmargorp >5_I<ytiroirp_demmargorp
B1 >8_I<ytiroirp_demmargorp >7_I<ytiroirp_demmargorp
C1 >01_I<ytiroirp_demmargorp >9_I<ytiroirp_demmargorp
D1 >21_I<ytiroirp_demmargorp >11_I<ytiroirp_demmargorp
E1 >41_I<ytiroirp_demmargorp >31_I<ytiroirp_demmargorp
02ycneuqerf_ecruos_fer_gfnc
)etirw/daer( nvidk8kcol)0:1(>1_I<di_tekcub)0:3(>1_I<ycneuqerf_ecruos_ecnerefer
12 nvidk8kcol)0:1(>2_I<di_tekcub)0:3(>2_I<ycneuqerf_ecruos_ecnerefer
22 nvidk8kcol)0:1(>3_I<di_tekcub)0:3(>3_I<ycneuqerf_ecruos_ecnerefer
32 nvidk8kcol)0:1(>4_I<di_tekcub)0:3(>4_I<ycneuqerf_ecruos_ecnerefer
42 nvidk8kcol)0:1(>5_I<di_tekcub)0:3(>5_I<ycneuqerf_ecruos_ecnerefer
52 nvidk8kcol)0:1(>6_I<di_tekcub)0:3(>6_I<ycneuqerf_ecruos_ecnerefer
62 nvidk8kcol)0:1(>7_I<di_tekcub)0:3(>7_I<ycneuqerf_ecruos_ecnerefer
72 nvidk8kcol)0:1(>8_I<di_tekcub)0:3(>8_I<ycneuqerf_ecruos_ecnerefer
82 nvidk8kcol)0:1(>9_I<di_tekcub)0:3(>9_I<ycneuqerf_ecruos_ecnerefer
92 nvidk8kcol)0:1(>01_I<di_tekcub)0:3(>01_I<ycneuqerf_ecruos_ecnerefer
A2 nvidk8kcol)0:1(>11_I<di_tekcub)0:3(>11_I<ycneuqerf_ecruos_ecnerefer
B2 nvidk8kcol)0:1(>21_I<di_tekcub)0:3(>21_I<ycneuqerf_ecruos_ecnerefer
C2 nvidk8kcol)0:1(>31_I<di_tekcub)0:3(>31_I<ycneuqerf_ecruos_ecnerefer
D2 nvidk8kcol)0:1(>41_I<di_tekcub)0:3(>41_I<ycneuqerf_ecruos_ecnerefer
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com23
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPtiBataD
)bsm(7654321)bsl(0
03_secruos_etomer_sts_gfnc
dilav
)etirw/daer(
>1:8<slennahc,sutatsetomeR
13 >9:41<slennahc,sutatsetomeR
23edom_gnitarepo_gfnc
)etirw/daer( edomgnitarepodecroF
33noitceles_fer_gfnc
)etirw/daer( ecruos_ecnerefer_tceles_ecrof
43edom_gfnc
)etirw/daer( otuA
lanretxe
elbaneK2
esahP
mrala
tuoemit
elbane
egdekcolC
revodloH
tesffO
elbane
K2lanretxE
elbanecnyS
/TENOS
HDS
P/I
/retsaM
evalS
noisreveR
edom
534T_gfnc
)etirw/daer( hcleuqS tceleS
1T/0T
noitcelesecruostupni1TecroF
)01_Iot5_Istupnirofdilavylno(
63stupni_laitnereffid_gfnc
)etirw/daer(
>6_I<
LCEP
>5_I<
LCEP
73snip_lesPu_gfnc
)ylnodaer( epytrossecorp-orciM
83elbane_tuptuo_0T_gfnc
)etirw/daer( zHM40.113
60Tno
TENOS=1
HDS=0
2giDrof
TENOS=1
HDS=0
1giDrof
10T20T 30T
zHM44.91
40T
zHM88.83
50T
zHM67.77
93seicneuqerf_tuptuo_0T_gfnc
)etirw/daer( 2latigiD1latigiD20T10T
A3stuptuo_laitnereffid_gfnc
)etirw/daer(
ycneuqerF70T
noitceles
ycneuqerF60T
noitceles
SDVL70T
elbane
LCEP70T
elbane
SDVL60T
elbane
LCEP60T
elbane
B3htdiwdnab_gfnc
)etirw/daer(
w/botuA
hctiws
kcol/qcA
htdiwdnabnoitisiuqcA'0'otteShtdiwdnabdekcol/lamroN
C3ycneuqerf_lanimon_gfnc
)etirw/daer( )0:7(ycneuqerflanimoN
D3 )8:51(ycneuqerflanimoN
E3tesffo_revodloh_gfnc
)etirw/daer( )0:7(tesfforevodloH
F3 )8:51(tesfforevodloH
04otuA
revodloH
gnigarevA
)61:81(tesfforevodloH
14timil_qerf_gfnc
)etirw/daer( )0:7(timiltesffoycneuqerFLLPD
24 tesffoycneuqerFLLPD
)8:9(timil
34ksam_tpurretni_gfnc
)etirw/daer(
dilav>8_I<
egnahc
dilav>7_I<
egnahc
dilav>6_I<
egnahc
dilav>5_I<
egnahc
dilav>4_I<
egnahc
dilav>3_I<
egnahc
dilav>2_I<
egnahc
dilav>1_I<
egnahc
44gnitarepO
edom
.ferniaM
deliaf
dilav>41_I<
egnahc
dilav>31_I<
egnahc
dilav>21_I<
egnahc
dilav>11_I<
egnahc
dilav>01_I<
egnahc
dilav>9_I<
egnahc
54 fer4T 2imA
noitaloiV
2imA
S.O.L
1imA
noitaloiV
1imA
S.O.L
64nvid_qerf_gfnc
)etirw/daer( )0:7(oitarn-yb-tupni-ediviD
74 )8:31(oitarn-yb-tupni-ediviD
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com24
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPtiBataD
)bsm(7654321)bsl(0
84srotinom_gfnc
)etirw/daer( tsolfergalF
ODTno
tsaf-artlU
gnihctiws
lanretxE
ecruos
hctiws
elbane
esahpezeerF
tuodliub
esahP
tuodliub
elbane
srotinomycneuqerF
)0:1(noitarugifnoc
050dlohserht_reppu_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesmralaytivitcA:0noitarugifnoC
150dlohserht_rewol_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesermralaytivitcA:0noitarugifnoC
250ezis_tekcub_gfnc
)etirw/daer( )0:7(ezistekcubmralaytivitcA:0noitarugifnoC
350etar_yaced_gfnc
)etirw/daer( )0:1(etar_yaced:0gfC
451dlohserht_reppu_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesmralaytivitcA:1noitarugifnoC
551dlohserht_rewol_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesermralaytivitcA:1noitarugifnoC
651ezis_tekcub_gfnc
)etirw/daer( )0:7(ezistekcubmralaytivitcA:1noitarugifnoC
751etar_yaced_gfnc
)etirw/daer( )0:1(etar_yaced:1gfC
852dlohserht_reppu_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesmralaytivitcA:2noitarugifnoC
952dlohserht_rewol_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesermralaytivitcA:2noitarugifnoC
A52ezis_tekcub_gfnc
)etirw/daer( )0:7(ezistekcubmralaytivitcA:2noitarugifnoC
B52etar_yaced_gfnc
)etirw/daer( )0:1(etar_yaced:2gfC
C53dlohserht_reppu_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesmralaytivitcA:3noitarugifnoC
D53dlohserht_rewol_vitca_gfnc
)etirw/daer( )0:7(dlohserhttesermralaytivitcA:3noitarugifnoC
E53ezis_tekcub_gfnc
)etirw/daer( )0:7(ezistekcubmralaytivitcA:3noitarugifnoC
F53etar_yaced_gfnc
)etirw/daer( )0:1(etar_yaced:3gfC
F7lesPu_gfnc
)etirw/daer( epytrossecorp-orciM
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com25
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Register map description
.rddA
)xeH(
emaNretemaraPnoitpircseDtluafeD
)nib(eulaV
00 di_pihc .DIecivedehtsniatnocretsigerylno-daersihT
)xeh(E3:etybtnacifingis-tsaeL00sserddA
)xeh(12:etybtnacifingis-tsoM10sserddA
)ced(0158=)xeh(E312
01111100
10 10000100
20 noisiver_pihc rebmunnoisiverpihcehtsniatnocretsigerylnodaersihT 10000000
30
1lortnoc_gfnc tfelronoitasilaitinignirud'0'tatesrehtieebdluohsdnaslortnoctsetera5&)0:3(stiB
.degnahcnu
ehtnisredividehtotnoitcesLLPAtuptuoehtnisredividehtsesinorhcnys,hgihtesnehw,4tiB
tnemngilaesahpehtevahotyrassecensisihT.ngilasesahpriehttahthcusnoitcesLLPD
yB.)zHM67.77otzHM84.6(setardevired3COtaskcolctuptuodnastupniehtneewteb
sihtgnitteS.ffodenrutnehtsidnapurewopretfasdnoces2rofsrucconoitasinorhcnys,tluafed
fotuognittegsredividehtdiovaotyrassecenebyamhcihw,nonoitasinorhcnysspeekhgihtib
.edomnureerfotniecrofasahcusruccoycneuqerfnisegnahckciuqnehwcnys
000000XX
40
2lortnoc_gfnc .degnahcnutfelronoitasilaitinignirud'010'tatesebdluohsdnaslortnoctsetera)0:2(stiB
otsdnopserrochcihw)001(4ottestluafedyB.timilgalfssolesahpehtenifed)3:5(stiB
timilgalfehT.timilesahprewolgnidnopserrocasteseulavrewolA.°041yletamixorppa
esahpa,rettijtupnifotluserasatsolesahpsetacidniLLPDehthcihwtaeulavehtsenimreted
tupniehtnopmujycneuqerfaro,pmuj
010001XX
stpurretni_sts ecnereferfossolrofeno,dilav_secruos_stsfotibhcaeroftibenosniatnocretsigertib61sihT
.hgihevitcaerastibllA.edomgnitarepoehtrofrehtonadna,otdekcolsawecivedeht
tnevelerehtfoetatsehtni"egnahc"anotesera)41tib(tibdeliaf_fer_niamehttpecxestibllA
MSFehtfI.tpurretninareggirtlliwtidilavniseogro,dilavsemocebecruosafi.e.i,tibsutats
.detarenegeblliwtpurretniehtllataetatssegnahc
ecnereferehtnoytivitcanigalfotdesusiretsigersutatstpurretniehtfo)deliaf_fer_niam(41tiB
fo6tibfI.troppusnacsrotinomytivitcaehtnahtylkciuqeromhcumotdekcolsiecivedehttaht
otnonevirdsitibsihtfoetatsehtneht,tessi)ODTnossolfergalf(retsigersrotinom_gfnceht
.ecivedehtfonipODTeht
deraelcebyamtibhcaE.retsigerksam_tpurretni_gfncehtnistibehtybelbaksamerastibllA
ebnacstibforebmunynA.tpurretniehtgnittesersuht,tibtahtot'1'agnitirwybyllaudividni
.tceffeonevahlliws'0'gnitirW.noitarepoetirwelgnisahtiwderaelc
50 )0:7(etybtnacifingis-tsaeL 00000000
60 )8:51(etybtnacifingis-tsoM 00000000
80
stupni_4T_sts smralaehT.ecnerefer4TUOTehtdnastupniIMAehtfosgalfsutatsehtsdlohretsigersihT
ot'1'agnitirwybyllaudividnideraelcebyamtibhcaE.teserlitnuetatsriehtdlohlliwtesecno
etarenegoslanacstibesehT.tceffeonevahlliws'0'gnitirW.tpurretniehtgnittesersuht,tibtaht
.stpurretni
tnetnoCtiB
raelc1imA='0';langisfossoL1imA='1':0
raelc1imA='0';detcetednoitaloiV1imA='1':1
raelc2imA='0';langisfossoL2imA='1':2
raelc2imA='0';detcetednoitaloiV2imA='1':3
Tdilavon-deliafecnerefer4T='1':4
1NI
kcoltonnacLLPD4T,)>5_I<:>01_I<(tupni
;ecruosot
Tdilav-doogecnerefer4T='0'
1NI
elbaliavatupni
)x:eulav(desunu)7:5(
00001XXX
90
edom_gnitarepo_sts 7erugiF.enihcametatsniamehtfoetatsgnitarepotnerrucehtsdlohretsigerylno-daersihT
.setatslaudividniehthtiwhctamelbairav'etatsgnitarepo'ehtfoseulavehtwohwohs
tnetnoCtiB
)0:2(etatsgnitarepO0:2
etatS)0:2(stiB
nureerf100
revodloh010
dekcol001
dekcol-erp011
2dekcol-erp101
tsolesahp111
desunu)7:3(
100XXXXX
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com26
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPnoitpircseDtluafeD
)nib(eulaV
elbat_ytiroirp_sts .sesserddaowtgnikat,retsigerylno-daertib-61asisihT
ecruosecnerefertupniehtforebmunlennahcehtsisiht:ecruosecnereferdetceles-yltnerruC
.noitcnufGTESehtotdetcennocyltnerrucsihcihw
sihcihwecruosecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirp-tsehgiH
ecnereferdetceles-yltnerrucehtsaemasehtebtonyamti;ytiroirptsehgihehtsahdnadilav
.)ytiroirpdemmargorpnisegnahcroyrotsiheruliafoteud(ecruos
ecruosecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgih-dnoceS
.ecruosdilavytiroirp-tsehgihehtotytiroirptsehgih-txenehtsahdnadilavsihcihw
ecruosecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgih-drihT
.ecruosdilavytiroirp-tsehgih-dnocesehtotytiroirptsehgih-txenehtsahdnadilavsihcihw
ehtfostnetnocehtotesnopsernienihcametatsehtybdetadpuerasretsigeresehttahtetoN
lennahc;slennahclaudividnifosutatsgniognoehtdnaretsigerytiroirp_noitceles_fer_gfnc
rofelbaliavasilennahcontahtsetacidni,sretsigeresehtfoynanigniraeppa,'0000'rebmun
.ytiroirptaht
tnetnoCtiB
A0 ecruosdilavytiroirp-tsehgiH)4:7(
ecruosecnereferdetcelesyltnerruC)0:3( 00000000
B0 3)4:7(
dr
ecruosdilavytiroirp-tsehgih-
2)0:3(
dn
ecruosdilavytiroirp-tsehgih- 00000000
tesffo_cni_rruc_sts tnerrucehtfostib91ehtgnitneserpereulavregetni-dengisasniatnocretsigerylno-daersihT
lacirotsihapudliubotyllacidoirepdaerebyamretsigerehT.LLPlatigidehtfotesffotnemercni
lanretxenafiyrassecenebylnodluowsiht(sdoireprevodlohgnirudesuretalrofesabatad
sinoitceskcolCrotallicsOlacoLnidebircsedairetircytilibatsehtteemtondidhcihwrotallicso
.teserretfayletaidemmi00000000daerlliwretsigerehT.)desu
C0 eulavtesffofoetybtnacifingistsaeL 00000000
D0 eulavtesffofoetybtnacifingistxeN 00000000
70 desunu)4:7(stiB
eulavtesffofostibtnacifingistsom3)0:2(stiB 000XXXXX
E0 dilav_secruos_sts sihT.setybsecruos_ecnerefer_sutatsehtllamorf3tibfoseipocsniatnocretsigertib41sihT
.sdaer2tsujnisecruosllafoytidilavehttegotresuehtswolla
.airetirclladessapsahecruosatonrorehtehwsetacidniylnoretsigersihT
00000000
F0 000000XX
secruos_ecnerefer_sts ehT.secruosecnerefertupni41ehtfohcaefosutatsehtsdlohhcihwretsigeretyb-7asisihT
sutatsdiaoT.hgihevitcasitibhcaE.dleiftib-4aninwohssiecruosecnereferhcaefosutats
sisutatsehT.retsigerdilav_secruos_stsehtnidedivorpsi3tibsutatshcaefoypoca,gnikcehc
)yllaudividnideraelcebyamtibhcaE(:swollofsadetroper
mralakcolesahp=0tibsutatS
mralaytivitcaon=1tibsutatS
mraladnab-fo-tuo=2tibsutatS
))0:2(stibfonoitanibmocsi3tib()smralaon(dilavecruoS=3tibsutatS
.pamretsigerehtnidnawolebnwohssiretsigerehtfonoitasinagroehT
tnetnoCtiB
01 >1-I<ecruosecnerefertupnifosutatS)0:3(
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11 >3_I<ecruosecnerefertupnifosutatS)0:3(
>4_I<ecruosecnerefertupnifosutatS)4:7( 01100110
21 >5_I<ecruosecnerefertupnifosutatS)0:3(
>6_I<ecruosecnerefertupnifosutatS)4:7( 01100110
31 >7_I<ecruosecnerefertupnifosutatS)0:3(
>8_I<ecruosecnerefertupnifosutatS)4:7( 00100010
41 >9_I<ecruosecnerefertupnifosutatS)0:3(
>01_I<ecruosecnerefertupnifosutatS)4:7( 00100010
51 >11_I<ecruosecnerefertupnifosutatS)0:3(
>21_I<ecruosecnerefertupnifosutatS)4:7( 00100010
61 >31_I<ecruosecnerefertupnifosutatS)0:3(
>41_I<ecruosecnerefertupnifosutatS)4:7( 00100010
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com27
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPnoitpircseDtluafeD
)nib(eulaV
ytiroirp_noitceles_fer_gfnc seulavytiroirpehT.secruosecnerefertupni41ehtfohcaefoytiroirpehtsdlohhcihwretsigeretyb-7asisihT
)ced(51ot1seulavehtylnO.seitiroirprehgihgnikatsrebmundeulav-rewolhtiw,rehtohcaeotevitalerllaera
,rebmuneuqinuanevigebdluohsecruosecnereferhcaE.ecruosecnereferehtselbasid0-dilavera
.sisabtuotsrifnitsrifanodengissaeblliwrebmunytiroirpemasehtnevigsecruosowtrevewoh
eht,erofereht-ylfehtnoseitiroirpehtredro-erotyrassecensitiesacni'1'eulavehtevreserotelbisnessitI
noitcetorpehtrofdesuyllacitamotuasi1eulaveht,ecivedevalsani(desuebyllamrondluow51ot2egnar
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.pamretsigerehtnidnawolebnwohssiretsigerehtfonoitasinagroehT
,woldeitsiBVLSTSMfI.hgihdeitrodetcennocnutfelsinipBVLSTSMnehwdilavsinevigeulavtluafedehT*
.)xeh(CDsieulavtluafedeht
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81 )0:3(
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91 )0:3(
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>8_I<ecruosecnerefertupnifoytiroirpdemmargorP 00011001
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>21_I<ecruosecnerefertupnifoytiroirpdemmargorP *10001011
E1 )0:3(
)4:7(
>31_I<ecruosecnerefertupnifoytiroirpdemmargorP
>41_I<ecruosecnerefertupnifoytiroirpdemmargorP 01111111
ycneuqerf_ecruos_fer_gfnc ,secruosecnerefertupni41ehtfohcaefoseicneuqerfehtotsyekehtsdlohhcihwretsigeretyb-41asisihT
.wolebdetsilsa
:yekgniwollofehthtiwecnadroccaniecruosecnereferehtfoycneuqerfehtenifedetybhcaefo)0:3(stiB
0000
1000
0100
1100
0010
1010
0110
1110
0001
1001
0101
zHk8
)2tib,43retsigeRybdenifedsA()HDS(zHk8402/)TENOS(zHk4451
zHM84.6
zHM44.91
zHM29.52
zHM88.83
zHM48.15
zHM67.77
zHM25.551
zHk2
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05sretsigernidenifedsa,desuera)3-0(sgnittestekcubykaelhcihwenifedrehtegotetybhcaefo)4:5(stiB
.)xeh(F5ot)xeh(
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00
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11
.LLPDehtotniyltceriddefsiycneuqerftupniehT
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.ecnarelotrettijtnellecxesevig
.esutonod-noitarugifnocdetroppusnU
eulavsihtybtupniehtedividotnvid_qerf_gfncretsigerniderotstneiciffeocnoisividehtsesU
nwoddedividehT.delbasidebtsumsrotinomycneuqerfehT.LLPDehtotgniogotroirp
ycneuqerftopstseraenehtottesebdluohs)0:3(ycneuqerfehT.zHk8lauqedluohsycneuqerf
neewtebseicneuqerftupnirofskrowerutaefNviDehT.ycneuqerftupnilautcaehtwolebtsuj
.zHM001dnazHM445.1
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.)xeh(30sieulavtluafedeht
02 ylnozHk8rof00000000tadexif->1_I<ecruosecnereferfoycneuqerF 00000000
12 ylnozHk8rof00000000tadexif->2_I<ecruosecnereferfoycneuqerF 00000000
22 >3_I<ecruosecnereferfoycneuqerF 00000000
32 >4_I<ecruosecnereferfoycneuqerF 00000000
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com28
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPnoitpircseDtluafeD
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42 >5_I<ecruosecnereferfoycneuqerF 11000000
52 >6_I<ecruosecnereferfoycneuqerF 11000000
62 >7_I<ecruosecnereferfoycneuqerF 11000000
72 >8_I<ecruosecnereferfoycneuqerF 11000000
82 >9_I<ecruosecnereferfoycneuqerF 11000000
92 >01_I<ecruosecnereferfoycneuqerF 11000000
A2 >11_I<ecruosecnereferfoycneuqerF *01000000
B2 >21_I<ecruosecnereferfoycneuqerF 10000000
C2 >31_I<ecruosecnereferfoycneuqerF 10000000
D2 >41_I<ecruosecnereferfoycneuqerF 10000000
_secruos_etomer_sts_gfnc
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asitI.ecivedrehtonaotdeilppussecruosecnereferehtfosutatsehtsdlohretsigertib-41sihT
noitcetorpehtfotrapsiretsigerehT.retsigerdilav_secruos_stss'ecivedrehtoehtfoypoc
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03 ecruosecnerefeRtiB
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23
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.yllacitamotuaetarepootenihcametatslortnocehtswolla)xeh(0eulaV
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rehtoondedivorP.'1'ytiroirpottupnidetcelesehtsesiaryliraropmetretsigersihtotgnitirW
eblliwecruossiht,nosiedomevitreverdna,'1'ytiroirphtiwdemmargorpydaerlasitupni
.srotinomytivitcadnaycneuqerfehtybdetadilavneebsahtifi,detceles
.FXsitluafedehT*.secruosecnerefertupnillaelbasidlliw)xeh(FXro)xeh(0XgnitirW
noitamrofnItiB
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43
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1tiB
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fosnoisicedevitcaehtekamdnaedomretsamehttpodalliwecivedehT:edoMretsaM1=
,nipehtybdenimretedsieulavtluafedstitub,elbaetirwsitibsihT.cte,tcelesotecruoshcihw
.BVLSTSM
00010011
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com29
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
)xeH(
emaNretemaraPnoitpircseDtluafeD
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43
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.BHDSNOS,nipehtybdenimretedsieulavtluafed
eulavehtneviglennahctupniynafoycneuqerftupniehtstcepxeecivedehT:edoMTENOS1=
stitub,elbaetirwsitibsihT.zHk4451ebotretsigerycneuqerf_ecruos_fer_gfncehtni'1000'
.BHDSNOS,nipehtybdenimretedsieulavtluafed
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detareneg-yllanretnistifoesahpehtngilalliwecivedehT:elbanEcnySzHk2lanretxE1=
langisehtfotahthtiw)zHk2(langiscnySemarF-itluMdna)zHk8(langiscnySemarF
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53
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com30
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
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emaNretemaraPnoitpircseDtluafeD
)nib(eulaV
73
snip_lesPu_gfnc ehtrofyekehtsdlohtI.)xeh(73sserddataecapstib-8eritneehtseipuccoretsigertib-3sihT
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daerebllitsnactubderongierasnipehtpu-rewopretfA.teserropu-rewopnodetpodadna
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)delbasidecafretni(FFO000
MORPE100
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83
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)zHM44.91(delbane30TtroptuptuO='1'2
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delbane20TtroptuptuO='1'3
delbasid20TtroptuptuO='0'
seicneuqerf_tuptuo_0T_gfncretsigerees-
delbane10TtroptuptuO='1'4
delbasid10TtroptuptuO='0'
seicneuqerf_tuptuo_0T_gfncretsigerees-
1giDrofdetcelesedomtenoS='1'5
1giDrofdetcelesedomHDS='0'
seicneuqerf_tuptuo_0T_gfncretsigerees-
2giDrofdetcelesedomtenoS='1'6
2giDrofdetcelesedomHDS='0'
seicneuqerf_tuptuo_0T_gfncretsigerees-
zHM40.113ottesycneuqerftuptuo60T='1'7
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com31
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
.rddA
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emaNretemaraPnoitpircseDtluafeD
)nib(eulaV
A3
stuptuo_laitnereffid_gfnc laitnereffidehtrofepytygolonhcet-tropehtdnasnoitcelesycneuqerfehtsdlohretsigersihT
.wolebdeliatedsa,70Tdna60T,stuptuo
dleifnoitarugifnoCtiBdleifnoitarugifnoCtiB
70T)2:3(60T)0:1(
delbasidtroP00delbasidtroP00
*elbitapmoc-LCEP10elbitapmoc-LCEP10
elbitapmoc-SDVL01*elbitapmoc-SDVL01
desunu11desunu11
70T)6:7(60T)4:5(
zHM25.55100*zHM88.8300
zHM48.1510zHM44.9110
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01100011
B3
htdiwdnab_gfnc nehW.LLPlatigidehtfonoitarepoehtlortnocotdesunoitamrofnisniatnocretsigersihT
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,launamottesnehW.kcolninehwgnitteshtdiwdnabdekcol/lamronehtdna,kcolfotuonehw
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htdiwdnabnoitisiuqcA)4:6(htdiwdnabpooL)0:2(tiB
zH1.0000zH1.0000
zH3.0100zH3.0100
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noitarepolaunaM='0'
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101X1110
ycneuqerf_lanimon_gfnc .ycneuqerflanimonderisedehtgnitneserperregetnidengisnutib61asdlohretsigersihT
tsniagaetasnepmocotycneuqerftuptuolanimonehtetarbilacyllanoitpootelbaliavasisihT
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Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com32
ACS8510 SETS
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Selection of Input Reference Clock
Source
Under normal operation, the input reference
sources are selected automatically by an order
of priority. But, for special circumstances, such
as chip or board testing, the selection may be
forced by configuration.
Automatic operation selects a reference source
based on its pre-defined priority and its current
availability. A table is maintained which lists all
reference sources in the order of priority. This
is initially downloaded into the ACS8510 via
the micro-processor interface by the Network
Manager, and is subsequently modified by the
results of the ongoing quality monitoring. In this
way, when all the defined sources are active
and valid, the source with the highest
programmed priority is selected but, if this
source fails, the next-highest source is selected,
and so on.
Restoration of repaired reference sources is
handled carefully to avoid inadvertent
disturbance of the output clock. The ACS8510
has two modes of operation; Revertive and
Non-Revertive. In Revertive mode, if a re-
validated (or newly validated) source has a
higher priority than the reference source which
is currently selected, a switch over will take
place. Many applications prefer to minimise the
clock switching events and choose Non-
Revertive mode. In Non-Revertive mode , when
a re-validated (or newly validated) source has a
higher priority then the selected source will be
maintained. The re-validation of the reference
source will be flagged in the sts_sources_valid
register and, if not masked, will generate an
interrupt. Selection of the re-validated source
can only take place under software control -
the software should briefly enable Revertive
mode to affect a switch-over to the higher
priority source. If the selected source fails under
these conditions the device will still not select
the higher priority source until instructed to do
so by the software, by briefly setting the
Revertive mode bit. When there is a reference
available with higher priority than the selected
reference, there will be NO change of reference
source as long as the Non-Revertive mode
remains on. This is the case even of there are
lower priority references available or the
currently selected reference fails. When the
ONLY valid reference sources that are available
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
have a lower priority than the selected
reference, a failure of the selected reference
will always trigger a switch-over regardless of
whether Revertive or Non-revertive mode has
been chosen.
Also, in a Master/Slave redundancy-protection
scheme, the Slave device(s) must follow the
Master device. The alignment of the Master
and Slave devices is part of the protection
mechanism. The availability of each source is
determined by a combination of local and
remote monitoring of each source. Each input
reference source supplied to each ACS8510
device is monitored locally and the results are
made available to other devices.
Forced Control Selection
A configuration register, 'cnfg_ref_selection',
controls both the choice of automatic or forced
selection and the selection itself (when forced
selection is required). The forced selection of
an input reference source occurs when the
'cnfg_ref_selection' variable contains a non-zero
value, the value then representing the input
port required to be selected. This is not the
normal mode of operation, and the
'cnfg_ref_selection' variable is defaulted to the
all-zero value on reset, thereby adopting the
automatic selection of the reference source.
Automatic Control Selection
When an automatic selection is required, the
'cnfg_ref_selection' register must be set to all-
zero. The configuration registers,
'cnfg_ref_selection_priority', held in the µP port
block, consists of seven, 8 bit registers
organised as one 4 bit register per input
reference port. Each register holds a 4-bit value
which represents the desired priority of that
particular port. Unused ports should be given
the value, '0000' or '1111', in the relevant
register to indicate they are not to be included
in the priority table. On power-up, or following a
reset, the whole of the configuration file will be
defaulted to the values defined by Table 1. The
selection priority values are all relative to each
other, with lower-valued numbers taking higher
priorities. Each reference source should be given
a unique number, the valid values are 1 to 15
(dec). A value of 0 disables the reference
source. However if two or more inputs are given
the same priority number those inputs will be
selected on a first in, first out basis. If the first
of two same priority number sources goes
invalid the second will be switched in. If the
first then becomes valid again, it becomes the
second source on the first in, first out basis,
and there will not be a switch. If a third source
with the same priority number as the other two
becomes valid, it joins the priority list on the
same first in, first out basis. There is no implied
priority based on the channel numbers.
The input port <I_11> is for the connection of
the synchronous clock of the TOUT0 output of
the Master device (or the active-Slave device),
to be used to align the TOUT0 output with the
Master (or active-Slave) device if this device is
acting in a subordinate-Slave or subordinate-
Master role.
Clock Quality Monitoring
Clock quality is monitored and used to modify
the priority tables of the local and remote
ACS8510 devices. The following parameters are
monitored:
- Activity (toggling)
- Frequency (This monitoring is only performed when there
is no irregular operation of the clock or loss of clock
condition)
In addition, input ports <I_1> and <I_2> carry
AMI-encoded composite clocks which are
monitored by the AMI-decoder blocks. Loss of
signal is declared by the decoders when either
the signal amplitude falls below 0.3 v or there
is no activity for 1 ms.
Any reference source which suffers a loss-of-
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
signal, loss-of-activity, loss-of-regularity or clock-
out-of-band condition will be declared as
unavailable.
Clock quality monitoring is a continuous process
which is used to identify clock problems. There
is a difference in dynamics between the
selected clock and the other reference clocks.
Anomalies occurring on non-selected reference
sources affect only that source's suitability for
selection, whereas anomalies occurring on the
selected clock could have a detrimental impact
on the accuracy of the output clock.
Anomalies, whether affecting signal-purity or
signal frequency, could induce jitter or frequency
offsets in the output clock, leading to
anomalous behaviour. Anomalies on the
selected clock, therefore, have to be detected
as they occur and the phase locked loop must
be temporarily isolated until the clock is once
again pure. The clock monitoring process cannot
be used for this because the high degree of
accuracy required dictates that the process be
slow. To achieve the immediacy required by the
phase locked loop requires an alternative
mechanism. The phase locked loop itself
contains appropriate circuitry, based around the
phase detector, and isolates itself from the
selected reference source as soon as a signal
impurity is detected. It can likewise respond to
frequency offsets outside the permitted range
since these result in saturation of the phase
detector. When the phase locked loop is isolated
from the reference source, it is essentially
operating in a Hold-Over state; this is preferable
to feeding the loop with a standby source, either
temporarily or permanently, since excessive
phase excursions on the output clock are
avoided.
Anomalies detected by the phase detector are
integrated in a leaky bucket accumulator.
Occasional anomalies do not cause the
accumulator to cross the alarm-setting
threshold, so the selected reference source is
retained. Persistent anomalies cause the alarm-
setting threshold to be crossed and result in
the selected reference source being rejected.
Activity Monitoring
The ACS8510 has a combined inactivity and
irregularity monitor. The ACS8510 uses a "leaky
bucket" accumulator, which is a digital circuit
which mimics the operation of an analog
integrator, in which input pulses increase the
Figure 7: Inactivity and irregularity monitoring
reference
leaky bucket
source
response
alarm
bucket_size
upper_threshold
lower_threshold
(all programmable)programmable fall slopes
inactivities/irregularities
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output amplitude but die away over time. Such
integrators are used when alarms have to be
triggered either by fairly regular defect events,
which occur sufficiently close together, or by
defect events which occur in bursts. Events
which are sufficiently spread out should not
trigger the alarm. By adjusting the alarm-setting
threshold, the point at which the alarm is
triggered can be controlled. The point at which
the alarm is cleared depends upon the decay
rate and the alarm-clearing threshold. On the
alarm-setting side, if several events occur close
together, each event adds to the amplitude
and the alarm will be triggered quickly; if events
occur a little more spread out, but still
sufficiently close together to overcome the
decay, the alarm will be triggered eventually. If
events occur at a rate which is not sufficient to
overcome the decay, the alarm will not be
triggered. On the alarm-clearing side, if no defect
events occur for a sufficient time, the amplitude
will decay gradually and the alarm will be cleared
when the amplitude falls below the alarm-
clearing threshold. The ability to decay the
amplitude over time allows the importance of
defect events to be reduced as time passes
by. This means that, in the case of isolated
events, the alarm will not be set, whereas, once
the alarm becomes set, it will be held on until
normal operation has persisted for a suitable
time (but if the operation is still erratic, the
alarm will remain set). See Figure 7.
The "leaky bucket" accumulators are
programmable for size, alarm set & reset
thresholds and decay rate. Each source is
monitored over a 128 ms period. If, within a
128 ms period, an irregularity occurs that is
not deemed to be due to allowable jitter/wander,
then the accumulator is incremented. The
accumulator will continue to increment up to
the point that it reaches the programmed
bucket size. The "fill rate" of the leaky bucket
is, therefore, 8 units/second. The "leak rate"
of the leaky bucket is programmable to be in
multiples of the fill rate (x1, x0.5, x0.25 and
x0.125) to give a programmable leak rate from
The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky
bucket empty) will be:
(cnfg_activ_upper_threshold N)
8
where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then
this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is
0.75 s.
The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated
as:
2 x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N))
8
where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown
in the following:
2 x (8-4) = 1.0 s
8
secs
secs
(cnfg_decay_rate N)
Leaky bucket timing
1
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ACS8510 SETS
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8 units/sec down to 1 unit/sec. A conflict
between trying to leak at the same time as a
fill is avoided by preventing a leak when a
fill event occurs.
Disqualification of a non-selected reference
source is based on inactivity, or on an out of
band result from the frequency monitors. The
currently selected reference source can be
disqualified for phase, frequency, inactivity or if
the source is outside the DPLL lock range. If
the currently selected reference source is
disqualified, the next highest priority, active
reference source is selected.
Ultra Fast Switching
A reference source is normally disqualified after
the leaky bucket monitor thresholds have been
crossed. An option for a faster disqualification
has been implemented, whereby if register 48H,
bit 5 (Ultra Fast Switching), is set then a loss of
activity of just a few reference clock cycles will
set the no activity alarm and cause a
reference switch. This can be chosen to cause
an interrupt to occur instead of or as well as
causing the reference switch.
The sts_interrupts register 05 Hex Bit 15
(main_ref_failed) of the interrupt status register
is used to flag inactivity on the reference that
the device is locked to much faster than the
activity monitors can support. If bit 6 of the
cnfg_monitors register (flag ref loss on TDO) is
set, then the state of this bit is driven onto the
TDO pin of the device.
The flagging of the loss of the main reference
failure on TDO is simply allowing the status of
the sts_interrupt bit 15 to be reflected in the
state of the TDO output pin. The pin will,
therefore remain High until the interrupt is
cleared. This functionality is not enabled by
default so the usual JTAG functions can be
used. When JTAG is normally used straight out
of power-up, then this feature will have no
bearing on the functionality. The TDO flagging
feature will need to be disabled if JTAG is not
enabled on power-up and the feature has since
been enabled.
When the TDO output from the ACS8510 is
connected to the TDI pin of the next device in
the JTAG scan chain, the implementation should
be such that a logic change caused by the
action of the interrupt on the TDI input should
not effect the operation when JTAG is not
active.
External Protection Switching
Fast external switching between inputs <I_3>
and <I_4> can also be triggered directly from a
dedicated pin (SRCSW). This mode can be
activated either by holding this pin high during
reset, or by writing to bit 4 of register address
48Hex. Once external protection switching is
enabled, then the value of this pin directly
selects either <I_3> (SRCSW high) or <I_4>
(SRCSW low). If this mode is activated at reset
by pulling the SRCSW pin high, then it configures
the default frequency tolerance of <I_3> and
<I_4> to +/- 80 ppm (register address 41Hex
and 42Hex). Any of these registers can be
subsequently set by external software if
required.
When external protection switching is enabled,
the device will operate as a simple switch. All
clock monitoring is disabled and the DPLL will
simply be forced to try to lock on to the
indicated reference source.
Frequency Monitoring
The ACS8510 performs frequency monitoring
to identify reference sources which have drifted
outside the acceptable frequency range of +/-
16.6 ppm (measured with respect to the output
clock). The sts_reference sources out-of-band
alarm for a particular reference source is raised
when the reference source is outside the
acceptable frequency range. The ACS8510
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the activity monitors should be
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
disabled so the input reference source is not
automatically rejected as out of frequency
range.
Modes of Operation
The ACS8510 has three primary modes of
operation (Free-Run, Locked and Holdover)
supported by three secondary, temporary
modes (Pre-Locked, Lost_Phase and Pre-
Locked2). These are shown in the State
Transition Diagram, Figure 8.
The ACS8510 can operate in Forced or
Automatic control. On reset, the ACS8510
reverts to Automatic Control, where transitions
between states are controlled completely
automatically. Forced Control can be invoked
by configuration, allowing transitions to be
performed under external control. This is not
the normal mode of operation, but is provided
for special occasions such as testing, or where
a high degree of hands-on control is required.
Free-Run mode
The Free-Run mode is typically used following a
power-on-reset or a device reset before
network synchronisation has been achieved. In
the Free-Run mode, the timing and
synchronisation signals generated from the
ACS8510 are based on the Master clock
frequency provided from the external oscillator
and are not synchronised to an input reference
source. The frequency of the output clock is a
fixed multiple of the frequency of the external
oscillator, and the accuracy of the output clock
is equal to the accuracy of the Master clock.
The transition from Free-Run to Pre-locked(1)
occurs when the ACS8510 selects a reference
source.
Pre-Locked(1) mode
The ACS8510 will enter the Locked state in a
maximum of 100 seconds, as defined by GR-
1244-CORE specification, if the selected
reference source is of good quality. If the
device cannot achieve lock within 100 seconds,
it reverts to Free-Run mode and another
reference source is selected.
Locked mode
The Locked mode is used when an input
reference source has been selected and the
PLL has had time to lock. When the Locked
mode is achieved, the output signal is in phase
and locked to the selected input reference
source. The selected input reference source is
determined by the priority table. When the
ACS8510 is in Locked mode, the output
frequency and phase follows that of the
selected input reference source. Variations of
the external crystal frequency have a minimal
effect on the output frequency. Only the
minimum to maximum frequency range is
affected. Note that the term, 'in phase', is not
applied in the conventional sense when the
ACS8510 is used as a frequency translator (e.g.,
when the input frequency is 2.048 MHz and
the output frequency is 19.44 MHz) as the input
and output cycles will be constantly moving past
each other; however, this variation will itself be
cyclical over time unless the input and output
are not locked.
Lost_Phase mode
Lost_Phase mode is used whenever the
selected reference source suffers most kinds
of anomalous behaviour. Clock generation is
performed in the same way as in the Holdover
mode. If the leaky bucket accumulator
calculates that the anomaly is serious, the
device rejects the reference source and one of
the following transitions takes place:
Go to Pre-Locked(2);
- If a known-good standby source is available.
Go to Hold-Over;
- If no standby sources are available.
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Holdover mode
The Holdover mode is used when the ACS8510
was in Locked mode for long enough to acquire
stable frequency data, but the final selected
reference source has become unavailable and
a replacement has not yet been qualified for
selection.
In Holdover mode, the ACS8510 provides the
timing and synchronisation signals to maintain
the Network Element (NE), but they are not
phase locked to any input reference source.
The timing is based on a stored value of the
frequency ratio obtained during the last Locked
mode period.
The Holdover performance is mainly limited by
what is happening to the TCXO. The ACS8510
has 3 ways of determining Holdover, either;
1. By external frequency setting (cnfg_holdover_offset
register)
2. By an internal frequency measuring and averaging
system which averages the last 20 minutes
3. By just using the last frequency (as reported by the
sts_curr_inc_offset register). This value can be read out
of the device and used to build up a longer term average
using an external averaging circuit. This value can then to
readback into the device and used as the Holdover offset
(via cnfg_holdover_offset register).
By default it uses the internal averager. This
means that if the TCXO frequency is varying
due to temperature fluctuations in the room,
then the instantaneous value can be different
from the average value, and then it may be
possible to exceed the 0.05 ppm limit
(depending on how extreme the temperature
flucuations are). It is advantageous to shield
the TCXO to slow down frequency changes due
to drift and external temperature fluctuations.
The frequency accuracy of Holdover mode has
to meet the ITU-T, ETSI and Telcordia
performance requirements. The performance
of the external oscillator clock is critical in this
mode, although only the frequency stability is
important - the stability of the output clock in
Hold-Over is directly related to the stability of
the external oscillator.
Pre-Locked(2) mode
This state is very similar to the Pre-Locked(1)
state. It is entered from the Holdover state
when a reference source has been selected
and applied to the phase locked loop. It is also
entered if the device is operating in revertive
mode and a higher-priority reference source is
restored.
Upon applying a reference source to the phase
locked loop, the ACS8510 will enter the Locked
state in a maximum of 100 seconds, as defined
by GR-1244-CORE specification, if the selected
reference source is of good quality.
If the device cannot achieve lock within 100
seconds, it reverts to Holdover mode and
another reference source is selected.
Protection Facility
The ACS8510 supports redundancy protection.
The primary functions of this include:
- Alignment of the priority tables of both Master
and Slave ACS8510 devices so as to align the
selection of reference sources of both Master
and Slave ACS8510 devices.
- Alignment of the phases of the 8 kHz and 2
kHz clocks in both Master and Slave ACS8510
devices to within one cycle of the 77.76 MHz
internal clock.
When two ACS8510 devices are to be used in
a redundancy-protection scheme within an NE,
one will be designated as the Master and the
other as the Slave. It is expected that an NE
will use the TOUT0 output for its internal
operations because the TOUT4 output is intended
to feed an SSU/BITS system. An SSU/BITS will
not be bothered by phase differences between
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com40
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
signals arriving from different sources because
it typically incorporates line build-out functions
to absorb phase differences on reference
inputs. This means that the phasing of the
composite clocks between two ACS8510
devices do not have to be mutually-aligned. The
same is not true, however, of the TOUT0 output
signals (T01 - T
07, Frame clock and Multi-Frame
clock). It is usually important to align the phases
of all equivalent TOUT0 signals generated by
different sources so that switch-over from one
device to another does not affect the internal
operations of the NE. Both ACS8510 devices
will produce the same signals, which will be
routed around the NE to the various consumers
(clock sinks). With the possible exception of a
through-timing mode, the signals from the
Master device will be used by all consumers,
unless the Master device fails, when each
consumer will switch over to the signals
generated by the Slave device.
Switchover to a new TOUT0 clock should be as
hitless as possible. This requires the signals of
both ACS8510 devices to be phase aligned at
each consumer. Phase alignment requires
frequency alignment. To ensure that both
devices can generate output clocks locked to
the same source, both devices are supplied
with the same reference sources on the same
input ports and will have identical priority tables.
Failures of selected reference sources will result
in both ACS8510 devices making the same
updates to their priority tables as availability
information will be updated in both devices.
Although, in principle, the priority tables will be
the same if the same reference sources are
used on the same input port on each device, in
practice, this is only true if the reference
sources actually arrive at each device - failures
of a source seen only by one device and not by
the other, such as could be caused, for example,
by a backplane connector failure, would result
in the priority tables becoming misaligned. It is
thus necessary to force the priority tables to
be aligned under normal operating conditions
so that the devices can make the same
decisions - this can be achieved by loading the
availability seen by one device (via the
sts_reference_sources register) into the
cnfg_sts_remote_sources_valid register of the
other device. Another factor which could affect
hit-less switching is the frequency of the local
oscillator clock used by each ACS8510 device:
these clocks are not mutually aligned and,
whilst this has no impact on the frequency of
the output clocks during locked mode, it could
cause the output frequencies to diverge during
Holdover mode if no action were taken to avoid
it. In order to maintain alignment of the output
frequencies of each ACS8510 device even
during Holdover, the Master device's 6.48 MHz
output is fed into the Slave device on its <I_11>
pin, whilst the Multi-Frame Sync (2 kHz) output
is fed to the Sync2k input of the Slave. In this
way, the Slave locks to the master's output
and remains locked whilst the Master moves
between operating states. Only when the
Master fails does the Slave use its own
reference inputs - should the Master have been
in the Holdover state, the Slave device will see
the same lack of reference sources and also
enter the Holdover state. This scheme also
provides a convenient way to phase-align all
TOUT0 output clocks in Master and Slave devices,
and also to detect the failure of the Master
device.
If a Master device fails, the Slave has to take
over responsibility for the generation of the
output clocks, including the 8 kHz and 2 kHz
Frame and Multi-Frame clocks. The Slave device
is also given responsibility for building the priority
table and performing the reference switching
operations. The Slave device, therefore, adopts
a more active role when the Master has failed.
The cnfg_mode register 34 (Hex) Bit 1 contains
the "Master/Slave" control bit to determine the
designation of the device.
To restore redundancy protection, the Master
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
has to be repaired and replaced. When this
occurs, the new Master cannot immediately
adopt its normal role because it must not cause
phase hits on the output clocks. It has,
therefore, to adopt a subordinate role to the
active Slave device, at least until such time as
it has acquired alignment to the 8 kHz and 2
kHz frame and Multi-Frame clocks and the
priority table of the Slave device; then, when a
switch-back (restoration) is ordered, the Master
can take over responsibility. These activities, in
Master or Slave operation, are detailed in Table
8.
Alignment of priority tables in Master and Slave
ACS8510
Correct protection will only be achieved by
connecting individual reference sources to the
same input ports on each device and priority
tables in each device must be aligned to each
other.
The Master device must take account of the
availability of each reference source seen by
another device and a Slave device must adopt
the same order of priority as the Master device
(except that the slave's highest-priority input is
<I_11>). Both devices monitor the reference
sources and decide the availability of each
source; if the failure of a reference source is
seen by both devices, they will both update
their priority tables - however, if the reference
source failure is only seen by one device and
not by both, the priority tables could get out of
step: this could be catastrophic if it resulted in
two devices choosing different reference
sources since any slight differences in frequency
variation over time (e.g. wander) would mis-align
the phase of the 8 kHz Frame and 2 kHz Multi-
Frame clocks produced by the individual
devices, resulting in phase hits on switch-over.
It is therefore important that the same priority
table be built by each device, using the
reference source availability seen by each
device.
The monitoring of the reference sources
performed by a Master ACS8510 results in a
list of available sources being placed in a
sts_valid_sources register. This information is
used within the device as one of the masks
used to build the device's priority table. The
information is passed to the Slave device and
used to configure the
cnfg_sts_remote_sources_valid register so that
it can use it as a mask in building its own priority
tables. The information is passed between
devices using the microprocessor port.
Alignment of the selection of reference sources
for TOUT4 generation in the Master and Slave
ACS8510
As stated previously, there is no need to align
the phases of the TOUT4 outputs in Master and
Slave devices. There is a need, however, to
ensure that all devices select the same
reference source. But, since there is no
Holdover mode required for the generation of
the TOUT4 clock, and every reference source is
continuously monitored within each device, it is
permissible to rely on external intelligence to
command a switch-over to an alternative source
should the selected one fail. The time delay
involved in detecting the failure, indicating it to
the outside and selecting a new source, will
result only in the SSU/BITS entering its Hold-
Over mode for a short time.
Alignment of the phases of the 8kHz and 2kHz
clocks in both Master and Slave ACS8510
In addition to aligning the edges of the TOUT0
outputs of Master and Slave devices, it is
necessary to align the edges of the Frame and
Multi-Frame clocks. If this is not performed,
frame alignment may be lost in distant
equipment on switch-over to an alternative
device, resulting in anomalous network
operation of a very serious nature.
In accordance with the alignment mechanism
used with the main TOUT0 clock (described in the
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
opening paragraphs of this section), whereby
the 6.48 MHz output of the Master device is
supplied to the Slave device, the alignment of
both the 8 kHz and 2 kHz clocks is
accomplished (they are already synchronous to
the TOUT0 clocks) by feeding the 2 kHz clock of
the Master device into the Slave device. The
Multi-Frame Sync clock output of the Slave
device is also fed to the Sync2K input of the
Master device. Alignment of the Multi-Frame
Sync input occurs only when cnfg_mode
register, bit 3, address 34Hex External 2 kHz
Sync Enable is set to 1.
JTAG
The JTAG connections on the ACS8510 allow a
full boundary scan to be made. The JTAG
implementation is fully compliant to IEEE
1149.1, with the following minor exceptions,
and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
from the core, and so do not support EXTEST. However
this does not affect board testing.
2. In common with some other manufacturers, pin TRST
is internally pulled low to disable JTAG by default. The
standard is to pull high. The polarity of TRST is as the
standard: TRST high to enable JTAG boundary scan mode,
TRST low for normal operation.
3. The device does not support the optional tri-state
capability (HIGHZ). This will be supported on the next
revision of the device.
The JTAG timing diagram is shown on page 53.
PORB
The Power On Reset (PORB) pin resets the
device if forced Low for a power-on-reset to be
initiated. The reset is asynchronous, the
minimum Low pulse width is 5 ns. Reset is
needed to initialize all of the register values to
their defaults. Asserting Reset (POR) is required
at power on, and may be re-asserted at any
time to restore defaults. This is implemented
most simplistically by an external capacitor to
GND along with the internal pull-up resistor.
The ACS8510 is held in a reset state for 250
ms after the PORB pin has been pulled High. In
normal operation PORB should be held High.
Notes to Table 8
Note 1: Both ACS8510 must build a common priority table so that the Slave ACS8510 can select the same input reference
source as the Master ACS8510 if the Master fails (when the Master is OK, the Slave locks to the Master's output).
Note 2: Slave ACS8510 uses common priority table, built before Master ACS8510 failed - priority table can be modified as
status of the input reference sources changes
Note 3: Slave ACS8510 outputs must remain in phase with those of Master ACS8510
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
otsecruos_feR
0158SCAretsaM
otsecruos_feR
0158SCAevalS
0158SCAretsaM
sutats
0158SCAevalS
sutats 0158SCAretsaM 0158SCAevalS
tuptuo stnemmoC
doogllAdoogllAdooGdooG)x_fer(dekcoLretsamotdekcoL1etoN
deliafemoSdeliafsrehtoemoSdooGdooG)y_fer(dekcoLretsamotdekcoL1etoN
dooGdooGdooGdeliaF)x_fer(dekcoLdaeD
dooGdooGdeliaFdooGdaeD)x_fer(dekcoL2etoN
dooGdooGdeliaFdeliaFdaeDdaeD
deliaFdeliaFdeliaFdooGrevodloHretsamotdekcoL3etoN
deliaFdeliaFdooGdeliaFrevodloHdaeD
deliaFdeliaFdeliaFdooGdaeDrevodloH4etoN
deliaFdeliaFdeliaFdeliaFdaeDdaeD
Table 8: Master-Slave ACS8510 Relationship
MASTER
MSTSLVB
I_1
I_2
I_3
I_11
I_14
SYNC2K
.
.
.
T
V
01
02
03
04
011
07
DD
T
T
T
T
TrMF Sync
.
.
.
T
I_11
SYNC2K
I_14
.
.
.
MF
T011 ync
Sr
.
.
.
07
MSTSLVB
I_3
I_2
I_1
TCXO
04
T
03
T
02
T
SLAVE
T01
TCXO
SEC1
SEC2
SEC3
SEC13
SEC14
SEC1
SEC2
SEC3
GND
6.48 M H z
6.48 MHz
SYNC2K_EN=1
34Bit3
.
.
..
.
.
.
.
..
.
.
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Figure 8: Automatic Mode Control State Diagram.
pre-locked
wait for up to 100s
(state 110)
locked
keep ref
(state 100)
holdover
select ref
(state 010)
(2) all refs evaluated
&
at least one ref valid
(5) se lecte d ref
phase locked
(3) no valid standby ref
&
(ma i n ref in v alid
or out of lock >100s)
(14) all refs evaluated
&
at least one ref valid
pre-locked2
wait for up to 100s
(state 101)
(10) selected source phase
locked
(6) no valid standby ref
&
ma in re f inv a l id
free-run
select ref
(state 001)
(1)Reset
Reference sources are flagged as ’vali d’ when
active, ’in-band’ and have no phase alarm set.
All sources are c ontinuously checked for
activity and frequency.
Only the main so urce is checked for phase.
A phase lock alarm is only raised on a
reference when that reference ha s lo st pha se
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
A source is considered to have phase locked
when it has been co ntinuou sly in phase lock
for be tween 1 and 2 s econds
Lost phase
wait for up to 100s
(state 111)
(7) phase lost
on main ref
(8) phase
regaine d within
100s
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(9) valid standby ref
&
[ main re f invalid or
(higher- priority ref v alid
& in re v erti v e mode) ]
(15) valid standby ref
&
[ main re f in v alid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
(4) valid standby ref
&
[ main re f invalid or
(higher- priority ref v alid
& in revertive mode) or
out of lock >100s]
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ADVANCED COMMUNCIATIONS FINAL
Electrical Specification
Important Note: The "Absolute Maximum Ratings" are stress ratings only, and functional operation
of the device at conditions other than those indicated in the "Operating Conditions" sections of
this specification are not implied. Exposure to the absolute maximum ratings for an extended
period may reduce the reliability or useful lifetime of the product.
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
PRETEMARA SLOBMY MNIMXAUSTIN
ppuSegatloVyl
V
DD
V,
D
V,+
A
,+1V
A
+2 V
DD
5.0-6.3V
egatloVtupnI
)snipylppus-non( niV- 5.5V
egatloVtuptuO
)snipylppus-non( tuoV- 5.5V
erutarepmeTgnitarepOtneibmA
egnaR T
A
04-58°C
erutarepmeTegarotST
rots
05-051°C
DC CHARACTERISTICS: TTL Input pad.
RETEMARAP LOBMYS NIM PYT XAM STINU
V
ni
hgiHV
hi
0.2--V
V
ni
woLV
li
-- 8.0V
tnerructupnII
ni
--01Aµ
Across operating conditions, unless otherwise stated
PRETEMARA SLOBMY NIM PYT XAM STINU
)egatlovcd(ylppuSrewoP
VDD+2AV,+1AV,+DV,,+IMAV,
FFID_DDV
DDV0.33.36.3V
)egatlovcd(ylppuSrewoP
5DDV 5DDV0.30.5/3.35.5V
egnaRerutarepmettneibmAT
A
04--58°C
tnerrucylppuS
)tuptuozHM91eno-lacipyT(
DDI-011002Am
noitapissidrewoplatoTP
TOT
-063027Wm
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
DC CHARACTERISTICS: TTL Input pad with internal pull-up.
DC CHARACTERISTICS: TTL Input pad with internal pull-down.
DC CHARACTERISTICS: TTL Output pad.
RETEMARAP LOBMYS NIM PYT XAM STINU
V
ni
hgiHV
hi
0.2--V
V
ni
woLV
li
-- 8.0V
rotsiserpu-lluPUP03-08Wk
tnerructupnII
ni
-- 021Aµ
RETEMARAP LOBMYS NIM PYT XAM STINU
V
ni
hgiHV
hi
0.2--V
V
ni
woLV
li
-- 8.0V
rotsisernwodu-lluPDP03-08Wk
tnerructupnII
ni
-- 021Aµ
RETEMARAP LOBMYS NIM PYT XAM STINU
woLtuoV
Am4=loI loV0- 4.0V
hgiHtuoV
Am4=hoI hoV4.2- V
tnerrucevirDDI--4Am
Across operating conditions, unless otherwise stated
Across operating conditions, unless otherwise stated
Across operating conditions, unless otherwise stated
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com47
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
DC CHARACTERISTICS: PECL Input/Output pad.
Notes:
Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs
tied to VDD and GND respectively.
Note 1. Assuming a differential input voltage of at least 100 mV.
Note 2. Unused differential input terminated to VDD-1.4v.
Note 3. With 50W load on each pin to VDD-2v. i.e. 82W to GND and 130W to VDD.
RETEMARAP LOBMYS NIM PYT XAM STINU
egatlovwoLtupnILCEP
stupnilaitnereffiD)1etoN(
V
LCEPLI
-DDV5.2- 5.0-DDVV
egatlovhgiHtupnILCEP
stupnilaitnereffiD)1etoN(
V
LCEPHI
-DDV4.2- 4.0-DDVV
egatlovlaitnereffiDtupnIV
LCEPDI
1.0-4.1V
egatlovwoLtupnILCEP
tupnidedneelgniS)2etoN(
V
S_LCEPLI
-DDV4.2- 5.1-DDVV
egatlovhgiHtupnILCEP
tupnidedneelgniS)2etoN(
V
S_LCEPHI
1-DDV3.- 5.0-DDVV
tnerruchgiHtupnI
egatlovlaitnereffidtupnI
V
DI
v4.1=
I
LCEPHI
01--01+Aµ
tnerrucwoLtupnI
egatlovlaitnereffidtupnI
V
DI
v4.1=
I
LCEPLI
01--01+Aµ
egatlovwoLtuptuOLCEP
)3etoN(
V
LCEPLO
-DDV01.2- 26.1-DDVV
egatlovhgiHtuptuOLCEP
)3etoN(
V
LCEPHO
52.1-DDV-88.0-DDVV
egatlovlaitnereffiDtuptuOLCEP
)1etoN(
V
LCEPDO
085-009Vm
Across operating conditions, unless otherwise stated
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com48
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
130R
I6POS
I6NEG
I5NEG
I5POS T06POS
T06NEG
T07POS
T07NEG
ZO=50Ω
ZO=50Ω
ZO=50Ω
ZO=50Ω
ZO=50Ω
ZO=50Ω
82R
DD
V
82R
130R
ZO=50Ω
ZO=50Ω130R
82R
82R
130R
DD
V
DD
82R
130R
V
82R
130R
130R
82R
82R
130R
DD
V
GND
GND GND
GND
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
51.84, 77.76 or
155.52 MHz
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
19.44, 38.88, 155.52,
311.04 MHz & DIG1
19.44, 51.84, 77.76,
155.52 MHz
Recommended line termination for PECL Input/Output ports for VDD = 3.3V
DC CHARACTERISTICS: LVDS Input/Output pad.
RETEMARAP LOBMYS NIM PYT XAM STINU
LSDVegnaregatlovtupnI
Vm001=egatlovtupnilaitnereffiD
V
SDVLRV
0- 04.2V
dlohserhttupnilaitnereffiDSDVLV
HTID
001--001+mV
egatlovlaitnereffiDtupnISDVLV
SDVLDI
1.0-4.1V
ecnatsisernoitanimrettupnISDVL
ehtssorcayllanretxedecalpebtsuM
.0158SCAfosniptupni-/+SDVL
%5htiwW001ebdluohsrotsiseR
ecnarelot
R
MRET
59001501W
egatlovhgihtuptuOSDVL
)1etoN(
V
SDVLHO
-- 585.1V
egatlovwoltuptuOSDVL
)1etoN(
V
SDVLLO
588.0--V
egatlovtuptuolaitnereffiDSDVL
)1etoN(
V
SDVLDO
052-054Vm
LSDVfoedutingamniegrahC
rofegatlovtuptuolaitnereffid
setatsyratnemilpmoc
)1etoN(
V
SDVLSOD
-- 52Vm
LSDVegatlovtesffotuptuo
C°52=erutarepmeT
)1etoN(
V
SDVLSO
521.1-572.1V
Note 1. With 100W load between the differential outputs.
Across operating conditions, unless otherwise stated
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com49
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
I6POS
I6NEG
I5NEG
I5POS T06POS
T06NEG
T07POS
T07NEG
ZO=50Ω
ZO=50Ω
ZO=50Ω
ZO=50Ω
ZO=50Ω
ZO=50Ω
100R
ZO=50Ω
ZO=50Ω
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
51.84, 77.76 or
155.52 MHz
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
19.44, 38.88, 155.52,
311.04 MHz & DIG1
19.44, 51.84, 77.76,
155.52 MHz
100R
100R
100R
Recommended line termination for LVDS Input/Output ports
The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative
pulses with a peak to peak voltage of 2.0 +/- 0.2V.
The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64kbit/s centralized
clock interface, from ITU G.703.
RETEMARAPGNIMIT
epahsesluP esirhtiw,ralugnatceryllanimoN
sµ1<semitllafdna
ecnedepmidaoltsetlanimoNsmhO011
)eslup("kram"afoegatlovkaePV1.0-/+0.1
"ecaps"afoeulavkaePV1.0-/+0.0
htdiwesluplanimoNsµ8.7
The electrical characteristics of 64kbits/s interface are as follows;
Nominal bit rate: 64kbit/s. The tolerance is determined by the network clock stability.
There should be a symmetrical pair carrying the composite timing signal (64kHz and 8kHz). The
use of transformers is recommended.
Over-voltage protection requirement; refer to Recommendation K.41.
Code conversion rules;
The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals
convey the 64kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the
8kHz octet phase information by introducing violations in the code rule. The structure of the
signals and voltage levels are shown in Figure 9 and Figure 10.
Across operating conditions, unless otherwise stated
DC CHARACTERISTICS: AMI Input/Output pad.
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ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Figure 9: Signal structure of 64 kHz/8 kHz central clock interface after suitable input/output transformer (also
see Figure 6/G.703).
15.6us
7.8us
2Vp-p 1V
+1.0V
IH
-1.0V
IL
0V
IM
1V
15.6us
7.8us
2Vp-p 1V
+1.0V
IH
-1.0V
IL
0V
IM
1V
Figure 10: AMI input and output signal levels.
15.6us
7.8us
2Vp-p 1V
+1.0V
IH
-1.0V
IL
0V
IM
1V
15.6us
7.8us
2Vp-p 1V
+1.0V
IH
-1.0V
IL
0V
IM
1V
C1
C1
C2
TO8POS
TO8NEG
I_1
I_2
15.6us
7.8us
+VDD
0V
15.6us
7.8us
+VDD
0V
Signal structure of 64 kHz/
8 kHz central clock interface
after suitable transformer.
15.6us
7.8us
0V
+VDD
15.6us
7.8us
0V
+VDD
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com51
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Recommended line termination for AMI Input/Output ports
The AMI inputs <I_1> and <I_2> should be connected to the external AMI clock source by 470 nF coupling
capacitor C1.
The AMI differential output O8POS/O8NEG should be coupled to a line transformer with a turns ration of 3:1.
Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential
divider Rload must be used to achieve the required 1 V pp voltage level for the positive and negative pulses.
NOTE: For 1:1 turn ratio, a 3:1 potential
divider Rload is required to give AMI
output with 1 V pp for positive and
negative pulses.
C1
C1
C2 C3
R
TO8POS
TO8NEG
<I_1>
<I_2>
AMI input
GND
AM I output signal
to external devices
Turns
ratio
1:1
signal
AMI input
signal
load
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com52
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8MHz
TCXO on ICT Flexacom + 10MHz reference from Wavetek 905.
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
1noitpozHM25.551rof318GzHM3.1otzH005IU
pp
5.0=)2etoN(850.0
1noitpozHM25.551rof318GzHM3.1otzHk56IU
pp
1.0= )3etoN(840.0
)2etoN(840.0
2noitpozHM25.551rof318GzHM3.1otzHk21IU
pp
1.0=
)4etoN(350.0
)5etoN(350.0
)6etoN(850.0
)7etoN(350.0
)2etoN(350.0
)3etoN(850.0
)8etoN(750.0
)9etoN(550.0
)01etoN(750.0
)11etoN(750.0
)21etoN(750.0
)31etoN(350.0
zHM840.2rof218G&318G
1noitpo zHk001otzH02IU
pp
50.0=)41etoN(640.0
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
zHM445.1rof218GzHk04otzH01IU
pp
50.0=)41etoN(630.0
lacirtcelezHM25.551rof218GzHM3.1otzH005IU
pp
5.0=)51etoN(850.0
lacirtcelezHM840.2rof218GzHM3.1otzHk56 IU
pp
=
570.0 )51etoN(840.0
Across operating conditions, unless otherwise stated
DC CHARACTERISTICS: Output Jitter Generation
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com53
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
zHM840.2rof3-264-003-STE
CES zHk001otzH02IU
pp
5.0=)41etoN(640.0
zHM840.2rof3-264-003-STE
CES
)zHk001otzH94cepsretliF(
zHk001otzH02IU
pp
2.0=)41etoN(640.0
zHM840.2rof3-264-003-STE
USS zHk001otzH02IU
pp
50.0=)41etoN(640.0
zHM25.551rof3-264-003-STEzHM3.1otzH005IU
pp
5.0=)51etoN(850.0
zHM25.551rof3-264-003-STEzHM3.1otzHk56IU
pp
1.0=)51etoN(840.0
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
48.15,f/itenEROC-352-RG
zHM zHk004otzH001IU
pp
5.1=)51etoN(220.0
48.15,f/itenEROC-352-RG
zHM
)zHk004otzHk02cepsretliF(
zHk004otzHk81IU
pp
51.0=)51etoN(910.0
25.551,f/itenEROC-352-RG
zHM zHM3.1otzH005IU
pp
5.1=)51etoN(850.0
25.551,f/itenEROC-352-RG
zHM zHM3.1otzHk56IU
pp
51.0=)51etoN(840.0
,f/itceleIItacEROC-352-RG
zHM25.551 zHk004otzHk21
IU
pp
1.0=)51etoN(750.0
IU
smr
10.0=)51etoN(600.0
,f/itceleIItacEROC-352-RG
zHM48.15 zHM3.1otzHk21
IU
pp
1.0=)51etoN(710.0
IU
smr
10.0=)51etoN(300.0
445.1,f/i1SDEROC-352-RG
zHM zHk04otzH01
IU
pp
1.0=)41etoN(630.0
IU
smr
10.0=)41etoN(5500.0
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com54
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
zHM445.1rof11426T&TA
)zHk8otzH01cepsretliF( zHk04otzH01IU
smr
20.0=)41etoN(5500.0
zHM445.1rof11426T&TAzHk04otzH01 IU
smr
=
520.0 )41etoN(5500.0
zHM445.1rof11426T&TAzHk04otzH01 IU
smr
=
520.0 )41etoN(5500.0
zHM445.1rof11426T&TAdnabdaorBIU
smr
50.0=)41etoN(5500.0
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
zHM840.2rof247-GzHk001otCDIU
pp
52.0=)41etoN(740.0
zHM840.2rof247-G
)zHk001otzHk81cepsretliF( zHk001otzH02IU
pp
50.0=)41etoN(640.0
zHM840.2rof247-GzHk001otzH02IU
pp
50.0=)41etoN(640.0
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
rof428G&994000-TWN-RT
zHM445.1 zHk04otzH01IU
pp
0.5=)41etoN(630.0
rof428G&994000-TWN-RT
zHM445.1
)zHk04otzHk8cepsretliF(
zHk04otzH01IU
pp
1.0=)41etoN(630.0
noitinifedtseTdesuretliFcepsIU 0158SCAnotnemerusaemIU
2veR
zHM445.1rofEROC-4421-RGzH01>IU
pp
50.0=)41etoN(630.0
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com55
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Notes for the output jitter generation tables
Note 1. Filter used is that defined by test definition unless otherwise stated
Note 2. 5 Hz bandwidth, 19.44 MHz direct lock
Note 3. 5 Hz bandwidth, 8 kHz lock
Note 4. 20 Hz bandwidth, 19.44 MHz direct lock
Note 5. 20 Hz bandwidth, 8 kHz lock
Note 6. 10 Hz bandwidth, 19.44 MHz direct lock
Note 7. 10 Hz bandwidth, 8 kHz lock
Note 8. 2.5 Hz bandwidth, 19.44 MHz direct lock
Note 9. 2.5 Hz bandwidth, 8 kHz lock
Note 10. 1.2 Hz bandwidth, 19.44 MHz direct lock
Note 11. 1.2 Hz bandwidth, 8 kHz lock
Note 12. 0.6 Hz bandwidth, 19.44 MHz direct lock
Note 13. 0.6 Hz bandwidth, 8 kHz lock
Note 14. 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input
Note 15. 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input
JTAG Timing
tSUR tHT
tDOD
tCYC
TCK
TMS
TDO
TDI
RETEMARAP LOBMYS NIM PYT XAM STINU
emitelcyCt
CYC
05--sn
egdegnisirKCTotIDT/SMT
emit t
RUS
3- -sn
dlohIDT/SMTotgnisirKCT
emit t
TH
32--sn
dilavODTotgnillafKCTt
DOD
--5sn
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com56
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
MOTOROLA Mode
In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0
type bus. The following figures show the timing diagrams of write and read accesses for this
mode.
address
data
Z
Z Z
Z
XX
X X
td1
td2 tpw2 th3 td4
td3
tsu1 th1
tsu2 th2
tpw1
CSB
WRB
A
AD
RDY
(DTACK)
Read access timing in MOTOROLA Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns.
Microprocessor interface timing
lobmyS retemaraP NIM PYT XAM
t
1us
BSCotdilavAputeS
egdegnillaf
0sn- -
t
2us
BSCotdilavBRWputeS
egdegnillaf
sn0--
t
1d
BSCyaleD
egdegnillaf
dilavDAot--sn771
t
2d
BSCyaleD
egdegnillaf
KCATDot
egdegnisir
-- sn31
t
3d
BSCyaleD
egdegnisir
Z-hgihDAot--sn0
t
4d
BSCyaleD
egdegnisir
Z-hgihYDRot--sn7
t
1wp
emitwolBSC sn584
)1(
--
t
2wp
emithgihKCATD sn013- sn274
t
1h
BSCretfadilavAdloH
egdegnisir
sn3--
t
2h
BSCretfahgihBRWdloH
egdegnisir
sn0--
t
3h
KCATDretfawolBSCdloH
egdegnillaf
sn0--
t
p
BSC(sesseccaevitucesnocneewtebemiT
egdegnisir
BSCot
egdegnillaf
)sn023--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com57
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Write access timing in MOTOROLA Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns.
address
data
Z
X X
Z
XX
X X
tsu3
td2 tpw2 th3 td4
th4
tsu1 th1
tsu2 th2
tpw1
CSB
WRB
A
AD
RDY
(DTACK)
lobmyS retemaraP NIM PYT XAM
t
1us
BSCotdilavAputeS
egdegnillaf
0sn- -
t
2us
BSCotdilavBRWputeS
egdegnillaf
sn0--
t
3us
BSCerofebdilavDAputeS
egdegnisir
sn3--
t
2d
BSCyaleD
egdegnillaf
KCATDot
egdegnisir
-- sn31
t
4d
BSCyaleD
egdegnisir
Z-hgihYDRot--sn7
t
1wp
emitwolBSC sn584
)1(
--
t
2wp
emithgihKCATD sn013- sn274
t
1h
BSCretfadilavAdloH
egdegnisir
sn3--
t
2h
BSCretfawolBRWdloH
egdegnisir
sn0--
t
3h
KCATDretfawolBSCdloH
egdegnillaf
sn0--
t
4h
BSCretfadilavDAdloH
egdegnisir
sn4
t
p
BSC(sesseccaevitucesnocneewtebemiT
egdegnisir
BSCot
egdegnillaf
)sn023--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com58
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
INTEL Mode
In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following
figures show the timing diagrams of write and read accesses for this mode.
Read access timing in INTEL Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
address
data
Z
Z Z
Z
td1
td2 tpw2 th3
td3
td4
tsu1 th1
tsu2 th2
tpw1
CSB
WRB
A
AD
RDY
RDB
td5
lobmyS retemaraP NIM PYT XAM
t
1us
BSCotdilavAputeS
egdegnillaf
0sn- -
t
2us
BSCputeS
egdegnillaf
BDRot
egdegnillaf
sn0--
t
1d
BDRyaleD
egdegnillaf
dilavDAot--sn771
t
2d
BSCyaleD
egdegnillaf
evitcaYDRot--sn31
t
3d
BDRyaleD
egdegnisir
YDRot
egdegnillaf
-- sn41
t
4d
BDRyaleD
egdegnisir
Z-hgihDAot--sn01
t
5d
BSCyaleD
egdegnisir
Z-hgihYDRot sn9
t
1wp
emitwolBDR sn684
)1(
--
t
2wp
emitwolYDR sn013- sn274
t
1h
BDRretfadilavAdloH
egdegnisir
sn0--
t
2h
BDRretfawolBSCdloH
egdegnisir
sn0--
t
3h
YDRretfawolBDRdloH
egdegnisir
sn0--
t
p
BDR(sesseccaevitucesnocneewtebemiT
egdegnisir
BDRot
egdegnillaf
ro,
BDR
egdegnisir
BRWot
egdegnillaf
)sn023--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com59
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Write access timing in INTEL Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
Note 2: Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge.
address
data
Z Z
td2 tpw2 th3
td3
th4
tsu1 th1
tsu2 th2
tpw1
CSB
WRB
A
AD
RDY
RDB
td5
su3
t
lobmyS retemaraP NIM PYT XAM
t
1us
BSCotdilavAputeS
egdegnillaf
0sn- -
t
2us
BSCputeS
egdegnillaf
BRWot
egdegnillaf
sn0--
t
3us
BRWotdilavDAputeS
egdegnisir
sn3--
t
2d
BSCyaleD
egdegnillaf
evitcaYDRot--sn31
t
3d
BRWyaleD
egdegnillaf
YDRot
egdegnillaf
-- sn41
t
5d
BSCyaleD
egdegnisir
Z-hgihYDRot sn9
t
1wp
emitwolBRW sn684
)1(
--
t
2wp
emitwolYDR sn013- sn274
t
1h
BRWretfadilavAdloH
egdegnisir
sn071
)2(
--
t
2h
BRWretfawolBSCdloH
egdegnisir
sn0--
t
3h
YDRretfawolBRWdloH
egdegnisir
sn0--
t
4h
BRWretfadilavDAdloH
egdegnisir
sn4
t
p
BRW(sesseccaevitucesnocneewtebemiT
egdegnisir
BRWot
egdegnillaf
ro,
BRW
egdegnisir
BDRot
egdegnillaf
)sn023--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com60
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
MULTIPLEXED Mode
In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/
data bus. The following figures show the timing diagrams of write and read accesses for this mode.
Read access timing in MULTIPLEXED Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
address data
Z Z
td1
td2 tpw2 th3
td3
td4
th1
th2
tpw1
CSB
WRB
AD
RDY
RDB
td5
ALE
pw3
t
su1
t
X X
tp1
su2
t
lobmyS retemaraP NIM PYT XAM
t
1us
ELAotdilavsserddaDAputeS
egdegnillaf
sn2--
t
2us
BSCputeS
egdegnillaf
BDRot
egdegnillaf
sn0--
t
1d
BDRyaleD
egdegnillaf
dilavatadDAot--sn771
t
2d
BSCyaleD
egdegnillaf
evitcaYDRot--sn31
t
3d
BDRyaleD
egdegnillaf
YDRot
egdegnillaf
-- sn51
t
4d
BDRyaleD
egdegnisir
Z-hgihatadDAot--sn9
t
5d
BSCyaleD
egdegnisir
Z-hgihYDRot--sn01
t
1wp
emitwolBDR sn784
)1(
--
t
2wp
emitwolYDR sn013- sn274
t
3wp
emithgihELA sn2
t
1h
ELAretfadilavsserddaDAdloH
egdegnillaf
sn3--
t
2h
BDRretfawolBSCdloH
egdegnisir
sn0--
t
3h
YDRretfawolBDRdloH
egdegnisir
sn0--
t
1p
ELAneewtebemiT
egdegnillaf
BDRdna
egdegnillaf
sn0--
t
2p
BDR(sesseccaevitucesnocneewtebemiT
egdegnisir
ELAot
egdegnisir
)sn023--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com61
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Write access timing in MULTIPLEXED Mode.
Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.
address data
Z Z
tsu3
td2 tpw2 th3
td3
th4
th1
th2
tpw1
CSB
WRB
AD
RDY
RDB
td5
ALE
pw3
t
su1
t
X X
tp1
su2
t
lobmyS retemaraP NIM PYT XAM
t
1us
ELAotdilavsserddaDAputeS
egdegnillaf
sn2--
t
2us
BSCputeS
egdegnillaf
BRWot
egdegnillaf
sn0--
t
3us
BRWotdilavatadDAputeS
egdegnisir
sn3--
t
2d
BSCyaleD
egdegnillaf
evitcaYDRot--sn31
t
3d
BRWyaleD
egdegnillaf
YDRot
egdegnillaf
-- sn51
t
5d
BSCyaleD
egdegnisir
Z-hgihYDRot sn9
t
1wp
emitwolBRW sn784
)1(
--
t
2wp
emitwolYDR sn013- sn274
t
3wp
emithgihELA sn2--
t
1h
ELAretfadilavsserddaDAdloH
egdegnillaf
sn3--
t
2h
BRWretfawolBSCdloH
egdegnisir
sn0--
t
3h
YDRretfawolBRWdloH
egdegnisir
sn0--
t
4h
BRWretfadilavdlohatadDA
egdegnisir
sn4
t
1p
ELAneewtebemiT
egdegnillaf
BRWdna
egdegnillaf
sn0--
t
2p
BRW(sesseccaevitucesnocneewtebemiT
egdegnisir
ELAot
egdegnisir
)sn023--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com62
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
tsu1 th1
tsu2 th2
tpw2
CSB
ALE=SCLK
AD(0)=SDO
A(0)=SDI R/W
_A0 A1 A2 A3 A4 A5 A6
pw1
t
d1
t
D0 D5D3D2 D4 D7D6
td2
D1
h2
AD(0)=SDO D0 D1 D2 D3 D4 D5 D6
R/W
ALE=SCLK
A(0)=SDI
CSB
A3A1A0
_A2 A5A4 A6
t
d1
t
D7
td2
SERIAL Mode
In SERIAL mode, the device is configured to interface with a serial microprocessor bus. The following figures
show the timing diagrams of write and read accesses for this mode.
During read access the output data SDO (AD(0)) is clocked out on the rising edge of SCLK (ALE) when the active
edge selection control bit CLKE (A(1)) is 0 and on the falling edge when CLKE = 1.
Address, read/write control bit and write data are always clocked into the interface on the rising edge of SCLK.
Both input data SDI and clock SCLK are oversampled, filtered and synchronized to the 6MHz internal clock.
The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1).
Read access timing in SERIAL Mode.
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com63
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Read access timing in SERIAL Mode.
Write access timing in SERIAL Mode.
lobmyS retemaraP NIM PYT XAM
t
1us
KLCSotdilavIDSputeS
egdegnisir
0sn- -
t
2us
BSCputeS
egdegnillaf
KLCSot
egdegnisir
sn061--
t
1d
KLCSyaleD
egdegnisir
KLCS(
egdegnillaf
dilavODSot)1=EKLCrof--sn71
t
2d
BSCyaleD
egdegnisir
Z-hgihODSot--sn01
t
1wp
emitwolKLCS sn081--
t
2wp
emithgihKLCS sn081--
t
1h
KLCSretfadilavIDSdloH
egdegnisir
sn071--
t
2h
KLCSretfawolBSCdloH
egdegnisir
0=EKLCrof,
KLCSretfawolBSCdloH
egdegnillaf
1=EKLCrof, sn5--
t
p
BSC(sesseccaevitucesnocneewtebemiT
egdegnisir
BSCot
egdegnillaf
)sn061--
tsu1 th1
tsu2 th2
tpw2
CSB
ALE=SCLK
D(0)=SDO
A(0)=SDI R/W
_A0 A1 A2 A3 A4 A5 A6
pw1
t
D0 D5D3D2 D4 D7D6D1
lobmyS retemaraP NIM PYT XAM
t
1us
KLCSotdilavIDSputeS
egdegnisir
0sn- -
t
2us
BSCputeS
egdegnillaf
KLCSot
egdegnisir
sn061--
t
1wp
emitwolKLCS sn081--
t
2wp
emithgihKLCS sn081--
t
1h
KLCSretfadilavIDSdloH
egdegnisir
sn071--
t
2h
KLCSretfawolBSCdloH
egdegnisir
sn5--
t
p
BSC(sesseccaevitucesnocneewtebemiT
egdegnisir
BSCot
egdegnillaf
)sn061--
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com64
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
EPROM Mode
In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD
AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state
machine in the up interface sequences the accesses.
Further details can be found in the AMD AM27C64 data sheet.
Read access timing in EPROM Mode.
address
data
Z Z
tacc
CSB (=OEB)
A
AD
lobmyS retemaraP NIM PYT XAM
t
cca
BSCyaleD
egdegnillaf
dilavDAotegnahcAro--sn029
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com65
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Package information
E
D
AA2
A1 b
e
b1
b
cc1
L
L1
AN4
AN3
AN2
S
AN1 R2
Section A-A
Section B-B
AA
Seating plane
1
2
3
4
5
6
D1
E1
1
1
2
3
7
7
7
78
Notes
1
2
3
4
5
6
7
8
R1
B
B
The top package body may be smaller than the bottom packa ge body by as much as 0.15 mm.
To be determined at seating plane.
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
Details of pin 1 identifier are optional but will be locat ed within the zone indicated.
Exact shape of corners can vary.
A1 is defined as the distance from the seating plane to the lo west point of the pac kage body.
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
Shows plating.
123
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com66
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Thermal conditions
The device is rated for full temperature range when this package is used with a 4 layer or more
PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum
operating temperature must be reduced when the device is used with a PCB with less than these
requirements.
PFQL001
egakcaP
snoisnemiD
mmni
E/D1E/1DA1A2Ae 1NA2NA3NA4NA1R2RL1LSb1bc1c
niM04.150.053.1°11°11°0°080.080.054.002.071.071.090.090.0
moN00.6100.4105.101.004.105.0°21°21- °5.3-- 06.0 00.1
)fer( -22.002.0--
xaM06.151.054.1°31°31-°7- 02.057.0-72.032.002.061.0
Notes
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com67
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Figure 11: A simplified Application Schematic.
A simplified Application Schematic for the ACS8510 is illustrated in Figure 11.
100nF
C11
C14
100nF
C20
100nF C15 100nF
C10
100nF
10R
R7
10R
R1
C8
1nF
100nF
C13
C12
100nF
C21
440pF
C16
470nF 470nF
C17
C3
100nF
C2
100uF 10uF_TANT
C5 C6
100nF C7
100nF
C4
10uF_TANT
100nF
C1
100nF
C9
C22
2nF
O4
O2
O9
O3
O5
O1
ZD1 ZD1
VIN
3
GND
1
VOUT
2
EZ1086
IC2
output 1
vdd
2
gnd1
3optn 4
gnd2 5
X1
_txco 12.8MHz
I7 I9 I11 I13
I3
GND(GR)
1BSMODE
2IREF1
3NC
4GND(A1)
5VA1+
6TMS
7Int
8TCK
9REFCLK
10 GND(D1)
11 VD+(D1)
12 VD+(D3)
13 GND(D3)
14 GND(D2)
15 VD+(D2)
16 NC
17 SrcSwit
18 VA2+
19 GND(A2)
20 TDO
21 IREF2
22 TDI
23 I1
24 I2
25
VDD(AMI)
26 O8NEG
27 O8POS
28 GND(AMI)
29 O10
30 O11
31 VSS_DIFFa
32 VDD_DIFFa
33 O6POS
34 O6NEG
35 O7POS
36 O7NEG
37 VSS_DIFFb
38 VDD_DIFFb
39 I5POS
40 I5NEG
41 I6POS
42 I6NEG
43 VDD5
44 SYNC2K
45 I3
46 I4
47 I7
48 VSSe
49 VDDe
50
I8 51
I9 52
I10 53
I11 54
I12 55
I13 56
I14 57
UPSEL(2) 58
UPSEL(1) 59
UPSEL(0) 60
VDDd 61
VSSd 62
A(6) 63
A(5) 64
A(4) 65
A(3) 66
A(2) 67
A(1) 68
A(0) 69
CSB 70
WRB 71
RDB 72
ALE 73
PORB 74
RDY 75
AD(7)
76 AD(6)
77 AD(5)
78 AD(4)
79 AD(3)
80 AD(2)
81 AD(1)
82 AD(0)
83 VSSc
84 VDDc
85 VDDb
86 VSSb
87 O1
88 O2
89 O3
90 VDDa
91 VSSa
92 O4
93 O5
94 O9
95 TSCAN
96 TEST1
97 TEST2
98 MSTSLVB
99 SDHB
100
ACS8510
IC1
SYNC2K I4 I8 I10 I12I6NI6PI5NI5PO7N
O6N O7P
I1 I2 O6P
5
6
8
7
I14
O11O10
O8
P1
term_connect
A0
10
A1
9
A2
8
A3
7
A4
6
A5
5
A6
4
A7
3
A8
25
A9
24
A10
21
A11
23
A12
2
Q0
11
Q1
12
Q2
13
Q3
15
Q4
16
Q5
17
Q6
18
Q7
19
VCC
28
GND
14
OE_B 22
CE_B 20
P_B 27
Am27c64IC3
L6
L5
L4
L3
L2
L1
AGND
AGND
AGND
VDD3
DGND3
VDD
DGND
DGND2DGND
VDD2VDD
VDDA
DGND
DGND
VDD
DGND
VDD5v VDD
DGND
VDD3
DGND2
VDD2
VDDA
DGND
VDD
VDD
DGND
DGND
VDD
DGND2DGND DGND
VDD5v
DGND
DGND3
A[0:7]
AD[0:7]
ALE
SrcSwit WRB
CSB
RDY RDB
Int
Optional Processor
interface
(+)
5v
0v
(+)(+)
Typical power
supply
Optional boot
EPROM
Optional
Processor
interface type
selection
Application information
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com68
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Revision History
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1stnetnocfoelbaT2 yrotsiHnoisiveRfonoisulcnI
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60
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70
stluafedLCEP/SDVLrofdetcerroc
4retsigeR
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5retsigeR
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6retsigeR
noitpircsed 82dettamrof-erretsigerdilav_secruos_etomer_sts_gfnc
7retsigeR
noitpircsed 82detcerrocrorreretsigeredom_gnitarepo_gfnc
8retsigeR
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xobgnimit 63noitauqegnittestluafednidetcerrocnoissimO
01edomrevodloH93detcerrocrorregnillepS
11yrotsiHnoisiveR86deddanoitceS
Changes from revision 2.06 to 2.07. January 2001.
Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com69
ACS8510 SETS
ADVANCED COMMUNCIATIONS FINAL
Ordering information
ISO9001
CERTIFIED
REBMUNTRAP NOITPIRCSED
0158SCA PFQLnip001,noitasinorhcnySHDS/TENOS
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-Mail: AdvCom@semtech.com
Internet: http://www.semtech.com
USA: 652 Mitchell Road, Newbury Park, CA 91320-2289
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.
Tel: +886 2 2748 3380, Fax: +886 2 2748 3390
EUROPE: Delta House, Chilworth Science Park, Southampton, Hants, SO16 7NS, UK
Tel: +44 23 80 769008, Fax: +44 23 80 768612
Disclaimers
Life support - This product is not designed or intended for use in life suport equipment, devices or
systems, or other critical applications. This product is not authorized or warranted by Semtech
Corporation for such use.
Right to change - Semtech Corporation reserves the right to make changes, without notice, to this
product. Customers are advised to obtain the latest version of the relevant information before
placing orders.