Features Fast Read Access Time - 120 ns Automatic Page Write Operation Internal Address and Data Latches for 128-Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 128-Byte Page Write Operation Low Power Dissipation 80 mA Active Current 300 LA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 10 or 10 Cycles Data Retention: 10 Years Single 5V + 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Description The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers (continued) Pin Configurations 44LCC Pin Name Function Top View AO - A16 Addresses AIS NC NC VCC NC AIS = a16 NC NC WE NC CE Chip Enable OE Output Enable WE Write Enable VO0 - 07 Data Inputs/Outputs NC No Connect 17:19 21 23 25 27 20 18 20 22 24 26 28 WOO VO2 NC Os VO6 Ao UO1 VSS 1/03 YOS VO7 CERDIP, FLATPACK ; ran Top View op View P ; 32 LCC 4) 34 | 27 | 26 2 Top View : 3 Ae | a7 | A14; WE | A13 3 12 AI8VEC. NC 5 2 28 | 24 | 25 5 Ath NC WE A5 | A12; VCC] Ag | AB 8 7 6 29 | 22 | 23 ? AB | Aa [A185 | OF | AIT ; 9 i 8&8 , 30; 20 | 21 Al | a2 A16| CE | A10 [10] 14] 16 19 vOo' AO | GND| VO4 1/07 | 12 13 15/17 | 18 VO1 | /O2 VYO3| VOS | 1/06 AT28C010 Mil 1 Megabit (128K x 8) Paged CMOS E?PROM Military 0353C 2-243Almet Description (Continued) access times to 120 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 300 pA. The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writ- ing of up to 128-bytes simultaneously. During a write cy- cle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other opera- tions. Following the initiation of a write cycle, the device will automatically write the latched data using an internal Block Diagram control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmels 28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inad- vertent writes. The device also includes an extra 128- bytes of E2PROM for device identification or tracking. Voc - DATA INPUTS/OUTPUTS GND > YOO - VO7 AAAS GAS OE "| of ceanpwe | 7 DATA LATCH WE ->| "Logic INPUT/OUTPUT cE --> BUFFERS ADD css _*| DECODER > Y-GATING R iq INPUTS * *| CELL MATRIX X DECODER iy IDENTIFICATION Absolute Maximum Ratings* Temperature Under Bias................. -5C to +125C Storage Temperature... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ow. -0.6V to +6.25V All Output Voltages with Respect to Ground ............. -0.6V ta Voc + 0.6V Voltage on OE and AQ with Respect to Ground 0.0... -0.6V to +13.5V AT28C010 Mil 2-244 NOTICE: Stresses beyond those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.mes =A | OSC) 1) Mil Device Operation READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cy- cle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of twc, a read operation will effectively be a poll- ing operation. PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 ad- ditional bytes. Each successive byte must be written within 150 us (taLc) of the previous byte. If the tatc limit is ex- ceeded the AT28C010 will cease accepting data and com- mence the internal programming operation. All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The AO to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on 1/07. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in /O6 toggling be- tween one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. AIMEL DATA PROTECTION: If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C010 in the follow- ing ways: (a) Vcc sense - if Vcc is below 3.8V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write:_(c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typi- cal) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after twc the entire AT28C010 will be pro- tected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C010. This is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable com- mand sequence is issued. Power transitions do not dis- able SDP and SDP will protect the AT28C010 during power-up and power-down conditions. All command se- quences must conform to the page write timing specifica- tions. The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of twc, read operations will effectively be polling operations. (continued) 2-245Device Operation (Continued) DEVICE IDENTIFICATION: An extra 128-bytes of E2PROM memory are available to the user for device identification. By raising A9 to 12V + 0.5V and using ad- AIMEL dress locations 1FF80H to 1FFFFH the bytes may be writ- ten to or read from in the same manner as the regular memory array. DC and AC Operating Range OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Soft- ware Chip Erase application note for details. AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25 Sooreture (Case) Mill -55C - 125C -55C - 125C -55C - 125C -55C - 125C Vcc Power Supply 5V+ 10% 5V+10% 5V + 10% 5V + 10% Operating Modes Mode cE OE WE vo Read Vit Vit Vin Dout Write (2) Vit VIH Vit Din Standby/Write Inhibit Vin x x High Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable x ViIH Xx High Z Notes: 1. X can be Vit or Vin. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol Parameter Condition Min Max Units lu Input Load Current Vin = OV to Voc + 1V 10 nA ILo Output Leakage Current Vio = OV to Vcc 10 HA Isat Voc Standby Current CMOS CE = Vcc- 0.3V to Vcc + 1V 300 LA Isp2 Vec Standby Current TTL CE =2.0V to Veo + 1V 3 mA loc Voc Active Current f = 5 MHz; louT = 0 mA 80 mA VIL Input Low Voltage 0.8 vO Vik Input High Voltage 2.0 Vv VoL Output Low Voltage lo. = 2.1 mA 45 Vv VoHi Output High Voltage loo = -400 pA 2.4 Vv VoH2 Output High Voltage CMOS oH = -100 A; Voc = 4.5V 4.2 Vv 2-246 AT28C010 Milees $= | 28C010 Nil AC Read Characteristics AT28C010-12 | AT28C010-15 | AT28C010-20 | AT28C010-25 Symbol Parameter Min Max Min Max Min Max Min Max Units tacc Address to Output Delay 120 150 200 250 ns tce M") CE to Output Delay 120 150 200 250 ns toe OE to Output Delay 0 50 0 55 0 55 0 55 ns tor 4) | CE or OF to Output o 50/0 55] 0 55 | o 55 | avs Float Qutput Hold from OE, toH CE or Address, 0 0 0 0 ns whichever occurred first AC Read Waveforms "* * *) ADDRESS x{ ADDRESS VALID CE oe tOE a E OE tOF tOH -> tacc --- OUTPUT HIGH Z OUTPUT VALID Notes: 1. CE may be delayed up to tacc - tce after the address 3. tor is specified from OE or CE whichever occurs first transition without impact on tacc. 2. OE may be delayed up to tce - tog after the falling edge of CE without impact on tce or by tacc - toe after an address change without impact on tacc . {CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Output Test Load Measurement Level 5.0V 3.0V AG AC 1.8K DRIVING MEASUREMENT our LEVELS LEVEL 0.0V ta, tp<5ns 1.3K L 00 eF Pin Capacitance (f = 1 MHz, T = 25C) Typ Max Units Conditions CIN 4 10 pF Vin = OV Cout 8 12 pF Vout = 0V Note: 1. This parameter is characterized and is not 100% tested. 2-247 AIMELAIMEL AC Write Characteristics Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 _ns tAH Address Hold Time 50 ns tcs Chip Select Set-up Time 0 ns tcH Chip Select Hold Time 0 ns twp Write Pulse Width (WE or CE) 100 ns tos Data Set-up Time 50 ns tou, toEH Data, OE Hold Time 0 ns AC Write Waveforms WE Controlled OE rs i tOES oe ce ADDRESS SK we ~ DATA IN CE Controlled IN DATA 2-248 AT28C010 Milees =A 1 O8C() 10 Mil Page Mode Characteristics Symboi Parameter Min Max Units twc Write Cycle Time _ 10 ms tas Address Set-up Time 0 ns taH Address Hold Time 50 ns tos Data Set-up Time 50 ns tbH Data Hold Time 0 ns twp Write Pulse Width 100 ns tBLc Byte Load Cycle Time 150 us tWPH Write Pulse Width High 50 ns Page Mode Write Waveforms ") ne ven me f form ef tWPH tBLC p tT Rr Rr Ry y - i-tDS yy ya DATA XVALID DATA x x BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 126 BYTE 127 LtWC Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE). 2, OE must be high only when WE and CE are both low. foe Chip Erase Waveforms VIH ~~ s VIL re VH poo OE a : VIH its VIH . WE iN v VIL Vw tWe ts = 5yusec (min.) tw = tH = 10 msec (min.) Vu = 12,0V + 0.5V AIMEL 228AImEt Software Data ' Protection Enable Algorithm LOAD DATA AA TO AODRESS 5555 LOAD DATA 55 To ADDRESS 2AAA LOAD DATA AG ADDRESS 5555 WRITES ENABLED ) LOAD DATA Xx TO ANY ADDRESS ) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Notes: 1. Data Format: 1/07 - I/O0 (Hex); Address Format: A14 - AQ (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period aven if no other data is loaded. 4. 1 to 128-bytes of data are loaded. Software Data ' Protection Disable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 ADDAESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT state ) LOAD DATA XX ANY ADDREss ) LOAD LAST BYTE TO LAST ADDRESS Software Protected Program Cycle Waveform ":* ) ea we ey fe a or SA NIN INS NDOT OOO tWPH tBLC we PRO ART na _ ve af AO - A6 BYTE ADDRESS Xe x ao of f A7- A116 = YX PAGE ADDRESS a tDH 7 fo DATA mA Ks S XK 7 BYTE 0 BYTE 126 BYTE 127 re wo Notes: 1. AQ - A14 must conform to the addressing sequence for the first 3-bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). AT28C010 Mil 2-250 3. OE must be high only when WE and CE are both low.ees =f | OSC () 1 () [Vil Data Polling Characteristics Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns {OEH OE Hold Time 10 ns toe OE to Output Delay 2) ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms WE {~ 7 ce | LN LN LON SN an SNS NSN SN {DH IP 4 OE HeHz {wR vo? Nee LN AON SftoN AO - A16 An An An An >< An) Toggle Bit Characteristics Symbol Parameter Min Typ Max Units tOH Data Hold Time 10 ns tOEH OE Hold Time 10 ns toE OE to Output Delay @) ns toEHP OE High Pulse 150 ns twa Write Recovery Time 0 ns Notes: 1, These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. : (1, 2, 3) Toggle Bit Waveforms WE CE \ / \ Sf NS oN \ . fey tOEH OF obs SS ON [Ne _ ae (DH 10E s\ GHZ pS Net (2) VO6 > Ae {WR Notes: 1. Toggling either OE or CE or both OE and CE will 3. Any address location may be used but the address operate toggle bit. should not vary. 2. Beginning and ending state of I/O6 will vary. AIMEL 2-251 |eAIMEL Ordering Information tacc lec (mA) : . (ns) Active | Standby Ordering Code Package Operation Range 120 80 0.3 AT28C010(E)-12DM/883 32D6 Military/883C AT28C010(E)-12EM/883 32L Class B, Fully Compliant AT28C010-12FM/883 32F (-55C to 125C) AT28C010(E)-12LM/883 44L AT28C010(E)-12UM/883 30U 150 80 0.3 AT28C010(E)-15DM/883 32D6 Military/883C AT28C010(E)-15EM/883 32L Class B, Fully Compliant AT28C010-15FM/883 32F (-55C to 125C) AT28C010(E)-15LM/883 44L AT28C010(E)-15UM/883 30U 200 80 0.3 AT28C010(E)-20DM/883 32D6 Military/883C AT28C010(E)-20EM/883 32L Class B, Fully Compliant AT28C010-20FM/883 32F (-55C to 125C) AT28C010(E)-20LM/883 44L AT28C010(E)-20UM/883 30U 250 80 0.3 AT28C010(E)-25DM/883 32D6 Military/883C AT28C010(E)-25EM/883 32L Class B, Fully Compliant AT28C010-25FM/883 32F (-55C to 125C) AT28C010(E)-25LM/883 44L AT28C010(E)-25UM/883 30U 120 80 0.3 5962-38267 07 MXX 32D6 Military/883C 5962-38267 07 MZX 32F Class B, Fully Compliant 5962-38267 07 MYX 44L (-55C to 125C) 5962-38267 07 MTX 30U 150 80 0.3 5962-38267 05 MXX 32D6 Military/883C 5962-38267 05 MUX 32L Class B, Fully Compliant 5962-38267 05 MZX 32F (-55C to 125C) 5962-38267 05 MYX 44L 962-38267 05 MTX 30U 200 80 0.3 5962-38267 03 MXX 32D6 Military/883C 5962-38267 03 MUX 32L Class B, Fully Compiiant 5962-38267 03 MZX 32F (-55C to 125C) 962-38267 03 MYX 44. 5962-38267 03 MTX 30U 250 80 0.3 5962-38267 01 MXX 32D6 Military/883C 5962-38267 01 MUX 32L Class B, Fully Compliant 5962-38267 01 MZX 32F (-55C to 125C) 5962-38267 01 MYX 44. 5962-38267 01 MTX 30U 80 0.3 AT28C010-W DIE Note: 1. See Valid Part Number table on next page. 2-252 AT28CO10 Mil mmsmes 8A 1 OSC) 1 () Vi! Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C010 12 DM/883, EM/883, FM/883, LM/883, UM/883 AT28CO10E 12 DM/883, EM/883, LM/883, UM/883 AT28C010 15 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 15 DM/883, EM/883, LM/883, UM/883 AT28C010 20 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 20 DM/883, EM/883, LM/883, UM/883 AT28C010 25 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 25 DM/883, EM/883, LM/883, UM/883 Package Type 32D6 32 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (CERDIP) 32F 32 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 30U 30 Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles ANMEL 2-253