IS61LV12824 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES * High-speed access time: 8, 9, 10, 12 ns * CMOS low power operation -- 720 mW (typical) operating @ 9 ns -- 36 mW (typical) standby @ 9 ns * TTL compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three state outputs * Available in 119-pin 14x22mm PBGA DESCRIPTION The ICSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ICSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE1, CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV12824 is packaged in the JEDEC standard 119-pin 14*22mm PBGA. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 24 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O23 CE2 CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR021-0B 1 IS61LV12824 PIN CONFIGURATION 119-pin 14x22mm PBGA 2 PIN DESCRIPTIONS A0-A16 Address Inputs 1 2 3 4 5 6 7 A NC A11 A14 A15 A16 A4 NC CE1, CE2 Chip Enable Input LOW B NC A12 A13 CE1 A5 A3 NC CE2 Chip Enable Input HIGH C I/O16 NC CE2 NC CE2 NC I/O0 OE Output Enable Input D I/O17 VCCQ GND GND GND VCCQ I/O1 WE Write Enable Input E I/O18 GND VCC GND VCC GND I/O2 NC No Connection F I/O19 VCCQ GND GND GND VCCQ I/O3 Vcc Power G I/O20 GND VCC GND VCC GND I/O4 VCCQ I/O Power H I/O21 VCCQ GND GND GND VCCQ I/O5 GND Ground J VCCQ GND VCC GND VCC GND VCCQ K I/O22 VCCQ GND GND GND VCCQ I/O6 L I/O23 GND VCC GND VCC GND I/O7 M I/O12 VCCQ GND GND GND VCCQ I/O8 N I/O13 GND VCC GND VCC GND I/O9 P I/O14 VCCQ GND GND GND VCCQ I/O10 R I/O15 NC NC NC NC NC I/O11 T NC A10 A8 WE A0 A1 NC U NC A9 A7 OE A6 A2 NC I/O0-I/O23 Data Inputs/Outputs Integrated Circuit Solution Inc. SR021-0B IS61LV12824 TRUTH TABLE Mode Not Selected Output Disabled Read Write WE CE1 CE2 CE2 OE I/O0-I/O23 Vcc Current X H X H H L L H L L L L L L X H H H H H H X L L L L L L X H X L H X H High-Z High-Z High-Z DOUT High-Z DIN HIHG-Z ISB1, ISB2 ICC 1 2 1CC ICC 3 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current Value -0.5 to 5.0 -0.5 to Vcc + 0.5 -65 to + 150 -10 to + 85 -45 to + 90 2.0 20 4 Unit V V C C C W mA 5 6 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC (8, 9, 10 ns) 3.3V + 10%, - 5% 3.3V + 10%, - 5% 8 VCC (12 ns) 3.3V 10% 3.3V 10% 9 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA 2.4 -- V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA -- 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V -0.3 0.8 V Voltage(1) VIL Input LOW ILI Input Leakage GND VIN VCC -1 1 A ILO Output Leakage GND VOUT VCC, Outputs Disabled -1 1 A 10 11 12 Note: 1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width 2.0 ns). VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width 2.0 ns). Integrated Circuit Solution Inc. SR021-0B 3 IS61LV12824 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions ICC Vcc Dynamic Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX ISB1 ISB2 -8 ns -9 ns -10 ns -12 ns Min. Max. Min. Max. Min. Max. Min. Max. Unit Com. Ind. -- -- 210 -- -- -- 200 220 -- -- 180 210 -- -- 190 190 mA TTL Standby Current (TTL Inputs) VCC = Max., Com. VIN = VIH or VIL, f = 0 Ind. CE1, CE2, VIH, CE2 VIL -- -- 70 70 -- -- 60 70 -- -- 50 55 -- -- 50 55 mA CMOS Standby Current (CMOS Inputs) VCC = Max., Com. CE1, CE2 VCC - 0.2V, Ind. CE2 0.2V, VIN VCC - 0.2V, or VIN 0.2V, f = 0 -- -- 10 -- -- -- 10 20 -- -- 10 20 -- -- 10 20 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 2 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 ZO = 50 3.3V OUTPUT 50 1.5V Figure 1 4 OUTPUT 353 5 pF Including jig and scope Figure 2 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -8 Min. Max. -9 Min. Max. -10 Min. Max. -12 Min. Max. tRC Read Cycle Time 9 -- 10 -- 12 -- 15 -- ns tAA Address Access Time -- 9 -- 10 -- 12 -- 15 ns tOHA Output Hold Time 3 -- 3 -- 3 -- 3 -- ns tACE tACE2 CE1, CE2 Access Time CE2 Access Time -- 8 -- 9 -- 10 -- 12 ns OE Access Time -- 4 -- 4 -- 4 -- 4 ns OE to High-Z Output 0 5 0 5 0 6 0 7 ns tLZOE(2) OE to Low-Z Output 0 -- 0 -- 0 -- 0 -- ns tHZCE(2) CE1, CE2 to High-Z Output tHZCE2(2) CE2 to High-Z Output 0 5 0 5 0 6 0 7 ns tLZCE(2) CE, CE2 to Low-Z Output tLZCE2(2) CE2 to Low-Z Output 3 -- 3 -- 3 -- 3 -- ns tDOE tHZOE (2) 1 Unit 2 3 4 5 Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. 6 7 8 9 10 11 12 Integrated Circuit Solution Inc. SR021-0B 5 IS61LV12824 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE1, CE2 CE2 t ACE1 t ACE2 t LZCE1 t LZCE2 DOUT HIGH-Z t HZCE1 t HZCE2 DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH. 3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition. 6 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Min. Max. Symbol Parameter -9 Min. Max. -10 Min. Max. -12 Min. Max. 1 Unit tWC Write Cycle Time 8 -- 9 -- 10 -- 12 -- ns tSCE tSCE2 CE1, CE2 to Write End CE2 to Write End 7 7 -- -- 8 8 -- -- 8 8 -- -- 9 9 -- -- ns tAW Address Setup Time to Write End 7 -- 8 -- 8 -- 9 -- ns tHA Address Hold from Write End 0 -- 0 -- 0 -- 0 -- ns tSA Address Setup Time 0 -- 0 -- 0 -- 0 -- ns tPWE1 WE Pulse Width (OE = HIGH) 6 -- 8 -- 8 -- 9 -- ns tPWE2 WE Pulse Width (OE = LOW) 6 -- 9 -- 9 -- 10 -- ns tSD Data Setup to Write End 4.5 -- 5 -- 5 -- 5 -- ns tHD Data Hold from Write End 0 -- 0 -- 0 -- 0 -- ns tHZWE(2) WE LOW to High-Z Output -- 3.5 -- 3.5 -- 3.5 -- 3.5 ns tLZWE(2) WE HIGH to Low-Z Output 3 -- 3 -- 3 -- 3 -- ns 2 3 4 5 Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 7 WRITE CYCLE NO. 1 (WE Controlled) 8 t WC VALID ADDRESS ADDRESS t SCE1 t SCE2 t SA 9 t HA CE1, CE2 10 CE2 t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED DIN Integrated Circuit Solution Inc. 11 t LZWE HIGH-Z t SD SR021-0B 6 12 t HD DATAIN VALID 7 IS61LV12824 WRITE CYCLE NO. 2(1) (CE Controlled: OE = HIGH or LOW: CE1, CE2 or CE2 Terminates Write) t WC ADDRESS VALID ADDRESS t HA OE CE1, CE2 LOW HIGH CE2 t AW t PWE1 WE t HZWE t SA DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 2(1) (WE Controlled: OE = LOW, CE1, CE2 = LOW; CE2 = HIGH: WE TEMINATES WRITE) t WC ADDRESS VALID ADDRESS OE LOW CE1, CE2 LOW t HA HIGH CE2 t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Note: 1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 8 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 1 ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. Package 8 IS61LV12824-8B 14*22mm PBGA 9 IS61LV12824-9B 14*22mm PBGA 10 IS61LV12824-10B 14*22mm PBGA 12 IS61LV12824-12B 14*22mm PBGA 2 3 4 5 6 7 8 9 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. SR021-0B 9 10 11 12 IS61LV12824 10 Integrated Circuit Solution Inc. SR021-0B