3236 Scott Boulevard Santa Clara, California 95054 Phone: (408) 986-5060 Fax: (408) 986-5095
CHP1206-QM
Features
❏InGaP HBT Technology
❏4mm Square, 50 Ohm Power Module
❏Single Positive Supply
❏35% Linear Power Added Efficiency
❏+28.5 dBm Output Power (CDMA)
❏+28.0 dBm Output Power (CDMA2K 1X)
❏27 dB Gain at Operating Output Power
❏On-Board Power Down Mode
Applications
❏Korea PCS Handsets
❏CDMA Handsets
❏CDMA2K 1X Handsets
Description
The CHP1206-QM is a 50 ohm matched, single sup-
ply, linear power amplifier module intended for use in Korean
handsets. The highly integrated amplifier meets the require-
ments of Korea PCS CDMA systems.It is a member of
Celeritek’s new QuadAmps™family of 3V power amplifier
modules that are packaged in a low-cost, space efficient, 4mm
square, matched module that provides excellent electrical sta-
bility and low thermal resistance. The module operates from a
fixed positive voltage and requires no external matching
which significantly reduces space, cost and enhances ease of
use. A current adjustment pin (Vcntrl) is provided to improve
efficiency for the low RF power range of operation.
The 4x4 mm package is self contained, incorporating
50 ohm input and output matching networks optimized for
output power, linearity and efficiency.
Celeritek’s InGaP HBT technology offers a thermally
robust and reliable PAM (power amplifier module) solution.
1.75 to 1.78 GHz
28.5 dBm, Korea PCS
InGaP HBT Amplifier Module
Advanced Product Information
May 2002 (1 of 4)
Functional Block Diagram
Application Information
The CHP1206-QM is a two-stage amplifier that requires a
single regulated positive supply along with the unregulated bat-
tery voltage for proper operation. Vref is a regulated 3.0 refer-
ence voltage for the bias control circuitry. It can also be used as
a power down mode select. Vcc is an unregulated supply volt-
age directly from the battery. Vcc should be applied prior to
Vref and before RF input power. Vmode is a control voltage
selection between high and low gain mode. The CHP1206-QM
can be operated over a range of supply voltages and bias points
by adjustment of Vref. It is important that the maximum power
dissipation of the package be observed at all times and that the
maximum voltage across the device is not exceeded.
Circuit Design Considerations
Biasing The positive Vcc supply voltages are applied to pins
1 and 10. Most bypass decoupling is provided on-board. Vref
is applied to pin 5.
The recommended DC bypass capacitance is shown in the
schematic diagram on Page 3.
Inadequate bypass capacitance and inductance around the
DC supply lines can compromise the adjacent channel power
ratio (ACPR), reduce power gain and/or create oscillations.
– Continued on Page 2 –
Absolute Maximum Ratings
Parameter Rating Parameter Rating Parameter Rating
Collector Voltage (+Vcc) +6.0 V* Reference Voltage (Vref) +3.1 V Operating Temperature -30°C to +95°C
Collector Current (Icc) 1.2 A Power Dissipation 4 W Storage Temperature -55°C to +135°C
RF Input Power (High Mode) 7 dBm Vcntrl +3.1 V Soldering Temperature 260°C for 5 Sec.
RF Input Power (Low Mode) 13 dBm
Recommended Operating Conditions
Parameter Typ Units Parameter Typ Units
Collector Voltage (+Vcc) 3.2 to 4.2 Volts Operating Temperature (PC Board) -20 to +70 °C
Reference Voltage (Vref) +3.0 (±0.1V) Volts Control Voltage (Vcntrl) High 2.5-3.0 V
(Fixed and regulated) Low 0-0.5 V
* RF Off.
Vcc11
RF IN 2
GND 3
10 Vcc2
8 RF OUT
6 GND
Ground connection: pins 3,
6, 7, 9 and on backside
Vcntrl 4
Vref 5
9 GND
7 GND
BIAS