1White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
WEDPF2M64-XBX3
2Mx64 3.3V Simultaneous Operation Multi-Chip Package *Preliminary
FEATURES
nAccess Times of 70, 100, 120, 150ns
nPackaging
119 ball stacked TSOP BGA
n1,000,000 Erase/Program Cycles
nSector Architecture
252 32K word sectors and 32 4K word
sectors
Any combination of sectors can be concur-
rently erased. Also supports full chip erase
nOrganized as 2Mx64
nCommercial, Industrial and Military Temperature
Ranges
n3.3 Volt for Read and Write Operations
nSimultaneous Read/Write Operation
Data can be continuously read from one bank
while executing erase/program functions in
other banks
nEmbedded Erase and Program Algorithms
nErase Suspend/Resume
Supports reading data from or programing
data to a sector not being erased
nData Polling and Toggle Bits
Provides a software method of detecting the
status of program or erase cycles
nUnlock Bypass Program command
Reduces overall programming time when
issuing multiple program command se-
quences
nReady/Busy output (RY/BY)
Hardware method for detecting program or
erase cycle completion
nHardware reset pin (RESET)
Hardware method of resetting the internal
state machine to the read mode
nWP/ACC input pin
Write protect (WP) function allows protection
of two outermost boot sectors, regardless of
sector protect status
Acceleration (ACC) function accelerates
program timing
nSector Protection
Hardware method of locking a sector, either
in-system or using programming equipment,
to prevent any program or erase operation
within that sector
Temporary Sector Unprotect allows changing
data in protected sectors in-system
Note:For programming information refer to Flash Programming
WEDPF2M64-XXX3 Application Note.
Sept. 2001 Rev. 3
* Preliminary datasheet. This datasheet describes a product that is not fully
qualified or characterized and is subject to change without notice.
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPF2M64-XBX3
123456789101112131415
H
G
F
E
D
C
B
A
A
2
A
1
DQ
57
DQ
48
DQ
35
DQ
34
DQ
40
DQ
32
DQ
19
DQ
18
DQ
24
CS
4
CS
2
A
A
5
A
4
A
3
DQ
50
DQ
56
DQ
43
DQ
42
DQ
41
DQ
33
DQ
27
DQ
26
DQ
17
CS
3
CS
1
OE
A
18
A
17
A
7
A
6
DQ
49
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
25
DQ
16
DQ0DQ
8
DQ
1
A21/NC
RESET WE
1
RY/BY
WP/AC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
A
19
A
20
A
8
A
9
DQ
61
V
SS
V
SS
V
SS
V
SS
V
SS
DQ
47
DQ
12
DQ
5
DQ
13
DQ
4
A
11
A
10
A
13
WE
4
DQ
53
V
SS
V
SS
V
SS
V
SS
V
SS
DQ
39
DQ
21
DQ
30
DQ
14
DQ
6
A
12
A
15
WE
2
DQ
51
DQ
52
DQ
62
DQ
63
DQ
44
DQ
37
DQ
38
DQ
20
DQ
29
DQ
23
DQ
15
DQ
7
A
14
WE
3
DQ
58
DQ
59
DQ
60
DQ
54
DQ
55
DQ
36
DQ
45
DQ
46
DQ
28
DQ
22
DQ
31
A
16
NC
wedpf2m64-xbx3pc.eps
FIG 1: PIN CONFIGURATION FOR WEDPF2M64-XBX3
PIN DESCRIPTION
I/O0-63 Data Inputs/Outputs
A0-20 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
RESET Reset/Powerdown
VCC Power Supply
VSS Ground
BLOCK DIAGRAM
TOP VIEW
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WEDPF2M64-XBX3
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Parameter Unit
Operating Temperature -55 to +125 °C
Supply Voltage Range (VCC) -0.5 to +4.0 V
Signal Voltage Range -0.5 to Vcc +0.5 V
Storage Temperature Range -65 to +150 °C
Endurance (write/erase cycles) 1,000,000 min. cycles
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage VCC 3.0 3.6 V
Input High Voltage VIH 0.7 x Vcc VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp. (Mil.) TA-55 +125 °C
Operating Temp. (Ind.) TA-40 +85 °C
CAPACITANCE
(TA = +25°C)
Parameter Symbol Conditions Min Typ Max Unit
Input Leakage Current I LI VCC = 3.6, VIN = GND or VCC 10 µA
Output Leakage Current ILOx32 VCC = 3.6, VIN = GND or VCC 10 µA
VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz 65 mA
VCC Active Current for Program or Erase (2) ICC2 CS = VIL, OE = VIH 120 mA
VCC Standby Current ICC3 VCC = 3.6, CS = VIH, f = 5MHz 20 mA
VCC Reset Current (2) ICC4 RESET = VSS ± 0.3V 1 20 mA
Automatic Sleep Mode (2,4) ICC5 VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 1 20 mA
VCC Active Read-While-Program ICC6
Current (1,2) CE = VIL, OE = VIH Word 85 180 mA
VCC Active Program-While-Erase ICC7
Current (1,2) CE = VIL, OE = VIH Word 85 180 mA
VCC Active Program-While-Erase-Suspended ICC8
Current (2,5) CE = VIL, OE = VIH 70 140 mA
ACC Accelerated Program Current IACC ACC Pin 20 40
CE = VIL, OE = VIH VCC Pin 60 120 mA
Output Low Voltage VOLIOL = 5.8 mA, VCC = 3.0 0.45 V
Output High Voltage VOH1 IOH = -2.0 mA, VCC = 3.0 0.85 X VCC V
Low VCC Lock-Out Voltage (4) VLKO 2.3 2.5 V
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 3.3V, VSS = 0V, TA = -55°C to +125°C)
NOTES:
1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency
component typically is less than 8 mA/MHz, with OE at VIH.
2.ICC active while Embedded Algorithm (program or erase) is in progress.
3.DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
4.Guaranteed by design, but not tested.
DATA RETENTION
Parameter Test Conditions Min Unit
Minimum Pattern Data 150°C 10 Years
Retention Time 125°C 20 Years
Parameter
Symbol
Conditions Max Unit
WE1-4 capacitance CWE
V
IN
= 0 V, f = 1.0 MHz
8pF
CS1-4 capacitance CCS
V
IN
= 0 V, f = 1.0 MHz
10 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
12 pF
Address input capacitance CAD
V
IN
= 0 V, f = 1.0 MHz
25 pF
RESET capacitance CRS
V
IN
= 0 V, f = 1.0 MHz
20 pF
RY/BY capacitance CRB
V
IN
= 0 V, f = 1.0 MHz
20 pF
WP/AC capacitance C WA
V
IN
= 0 V, f = 1.0 MHz
30 pF
This parameter is guaranteed by design but not tested.
4
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WEDPF2M64-XBX3
Parameter Symbol -70 -100 -120 -150 Unit
Min Max Min Max Min Max Min Max
Write Cycle Time t AVAV tWC 70 100 120 150 ns
Write Enable Setup Time tWLEL tWS 0 0 0 0 ns
Chip Select Pulse Width tELEH tCP 35 45 50 50 ns
Address Setup Time t AVEL tAS 0 0 0 0 ns
Data Setup Time tDVEH tDS 45 45 50 50 ns
Data Hold Time tEHDX tDH 0 0 0 0 ns
Address Hold Time tELAX tAH 45 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 30 30 30 30 ns
Duration of Byte Programming Operation (1) t WHWH1 300 300 300 300 µs
Sector Erase Time tWHWH2 15 15 15 15 sec
Read Recovery Time (2) tGHEL 0 0 0 0 µs
Chip Programming Time 50 50 50 50 sec
1. Typical value for tWHWH1 is 9µs.
2. Guaranteed by design, but not tested.
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 3.3V, VSS = 0V, TA = -55°C to +125°C)
FIG 2: AC TEST CIRCUIT AC TEST CONDITIONS
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive
load circuit.
ATE tester includes jig capacitance.
Parameter Typ Unit
Input Pulse Levels
VIL = 0, VIH = 2.5
V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
5White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPF2M64-XBX3
Parameter Symbol -70 -100 -120 -150 Unit
Min Max Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 70 10 0 120 150 n s
Chip Select Setup Time tELWL tCS 0 0 0 0 n s
Write Enable Pulse Width tWLWH tWP 35 50 50 65 ns
Address Setup Time tAVWL tAS 0 0 0 0 n s
Data Setup Time tDVWH tDS 4 5 5 0 5 0 6 5 n s
Data Hold Time tWHDX tDH 0 0 0 0 n s
Address Hold Time tWLAX tAH 45 50 50 65 n s
Write Enable Pulse Width High tWHWL tWPH 30 3 0 30 3 5 n s
Duration of Byte Programming Operation (1) tWHWH1 300 30 0 300 300 µ s
Sector Erase tWHWH2 15 15 15 15 se c
Read Recovery Time before Write (3) tGH
W
L 0 000 µs
VCC Setup Time tVCS 50 50 50 50 µs
Chip Programming Time 50 50 50 50 sec
Output Enable Setup Time tOES 0 0 0 0 n s
Output Enable Hold Time (2) tOEH 10 1 0 1 0 1 0 n s
Address Setup Time to OE low during toggle bit polling tASO 15 1 5 1 5 1 5 n s
Address Hold Time From CS or OE high 0
during toggle tAHT 0 0 0 n s
Output Enable High during toggle bit polling tOEPH 20 20 20 20 ns
Latency Between Read and Write Operations tsr/W 0 0 0 0 n s
Write Recovery Time from RY/BY tRB 0 0 0 0 n s
Program/Erase Valis to RY/BY tBUSY 90 90 90 9 0 n s
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 3.3V, TA = -55°C to +125°C)
1.Typical value for tWHWH1 is 9µs.
2.For Toggle and Data Polling.
3.Guaranteed by design, but not tested.
AC CHARACTERISTICS READ-ONLY OPERATIONS
(VCC = 3.3V, TA = -55°C to +125°C)
1. Guaranteed by design, not tested.
Parameter Symbol -70 -100 -120 -150 Unit
Min Max Min Max Min Max Min Max
Read Cycle Time t AVAV tRC 70 100 120 150 ns
Address Access Time tAVQV tACC 70 100 120 150 n s
Chip Select Access Time tELQV tCE 70 100 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 40 50 5 5 n s
Chip Select High to Output High Z (1) tEHQZ tDF 3 0 3 0 3 0 4 0 n s
Output Enable High to Output High Z (1) tGHQZ tDF 30 30 30 40 n s
Output Hold from Addresses, CS or OE Change, tAXQX tOH 0 0 0 ns
Whichever is first
Read tOEH 0 0 0 0
Output Enable Hold Time (1) Toggle and
Data Polling 10 1 0 10 1 0
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPF2M64-XBX3
FIG 3: AC WAVEFORMS FOR READ OPERATIONS
Addresses
CS
OE
WE
Outputs High Z
Addresses Stable
t
OE
t
RC
Output Valid
t
CE
t
ACC
t
OH
High Z
t
DF
RESET
RY/BY OV
fig3/waveforms.eps
7White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPF2M64-XBX3
AC CHARACTERISTICS HARDWARE RESET (RESET)
Parameter Symbol -100 -120 -150 Unit
Min Max Min Max Min Max
RESET Pin Low (During Embedded Algorithms)
to Read Mode (See Note) tready 20 20 20 µs
RESET Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note) tready 500 500 500 ns
RESET Pulse Width t RP 500 500 500 ns
RESET High Time Before Read (See Note) tRH 50 50 50 ns
RESET Low to Standby Mode tRPD 20 20 20 µs
RY/BY Recovery Time t RB 000ns
Note: Not 100% tested.
RY/BY
CS, OE
RESET
tRP
tReady
tRH
tReady
tRB
tRP
RY/BY
CS, OE
RESET
newresetchart.eps
FIG 4: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS
FIG 5: RESET TIMINGS DURING EMBEDDED ALGORITHMS
8
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WEDPF2M64-XBX3
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
FIG 6: WRITE/ERASE/PROGRAM
OPERATION, WE CONTROLLED
RY/BY
tRB
t
BUSY
Addresses
CS
OE
WE
Data
AAAH PA PA
t
WC
t
CS
PD
D
7
D
OUT
t
AH
t
WPH
t
DH
t
DS
Data Polling
t
AS
t
RC
t
WP
A0H
t
OE
t
DF
t
OH
t
GHWL
t
WHWH1
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WEDPF2M64-XBX3
FIG 8: CHIP/SECTOR ERASE OPERATION TIMINGS
NOTES:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status").
FIG 7: ACCELERATED PROGRAM TIMING DIAGRAM
VHH
tVHH tVHH
VIL or VIH
WP/ACC VIL or VIH
wedpf2m64fig18.eps
t
H
Addresses
SA
2AAh
VA VA
t
WC
CS#
OE#
WE#
Data
t
AS
555h for chip erase
t
AH
t
CH
t
WPH
t
WP
t
CS
55h 30h
In
Progress Complete
t
VCS
RY/BY#
Vcc
t
DH
t
DS
10 for chip erase
t
BUSY
t
RB
WEDPF2M64FIG8.EPS
10
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WEDPF2M64-XBX3
FIG 9: BACK TO BACK READ/WRITE CYCLE TIMINGS
tAH
Addresses Valid PA Valid RA Valid PA Valid PA
Valid In Valid Out Valid In Valid In
tWC tRC tWC tWC
CE
OE
WE
Data
tACC
tCE
tCPH
tCP
tWP tOEH tGHWL
tWPH
tDS tDH tOH
tDF
tOE
WE Controlled Write Cycle Read Cycle CE Controlled Write Cycle
tSW/W
wedpf2m64fig20.eps
NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
FIG. 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
Addresses
VA VA VA
t
RC
CS
Complement Complement
True
DQ0-DQ6
t
ACC
t
CE
t
CH
t
OE
OE
WE
t
OEH
t
DF
t
OH
Valid Data High Z
Status Data Status Data
True Valid Data High Z
RY/BY
t
BUSY
wedpf2m64fig10.eps
CS
CS
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WEDPF2M64-XBX3
Enter
Embedded
Erasing
WE
Erasing
Suspend Enter Erase
Suspend Program Erase
Resume
DQ6
Erase Erase Suspend
Read Erase
Suspend
Program
Erase
Suspend
Read
Erase Erase
Complete
wedpf2m64fig12.eps
FIG 11: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after comand sequence, last status read cycle, and array data read cycle.
FIG 12: DQ2 VS. DQ6
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE or CS.
VA
t
AS
t
AHT
t
AHT
t
ASO
t
CEPH
t
ASO
t
OEPH
t
DH
Valid Data Valid Status Valid Status Valid Status Valid
Data
t
OE
(First Read) (Second Read) (Stops Toggling)
RY/BY
DQ6/DQ2
OE
CS
Addresses
WE
wedpf2m64fig11.eps
12
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WEDPF2M64-XBX3
FIG 13: ALTERNATE CS CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS
NOTES:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
Addresses
555 for Program
2AA for Erase
PA
t
WC
WE
OE
CS
Data
t
AS
t
AH
tC
PH
tWS
In
Progress Complete
RESET
t
DH
t
DS
PD for Program
30 for Sector Erase
10 for Chip Erase
WEDPF2M64FIG13.EPS
PA for Program
SA for Sector Erase
555 for Chip Erase Data
Polling
t
WH
t
GHEL
tWHWH1 OR 2
tBUSY
tHR
A0 for Program
55 for Erase
RB/RY
13 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPF2M64-XBX3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H
G
F
E
D
C
B
A
1.27/2
8.89 (0.35)
typ
24.00 (0.944) MAX
17.78 (0.700) typ
14.00
(0.551)
MAX
7.56 (0.298)
MAX
0.76 (0.030)
typ
119 x 0.76
1.27/2
WED P F 2M64 B - XXX X B 3
ORDERING INFORMATION
PROGRAMMING VOLTAGE
3 = 3.3V
DEVICE GRADE:
M = Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE TYPE:
B = 119 Stacked TSOP BGA
ACCESS TIME (ns)
IMPROVEMENT MARK
B = Boot Block (Bottom Sector)
ORGANIZATION, 2M x 64
User configurable as 4M x 32, 8M x 16 or 16M x 8
Flash
Plastic
WHITE ELECTRONIC DESIGNS CORP.
PACKAGE: 119 STACKED TSOP BGA
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
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