FN8212 Rev 2.00 Page 1 of 12
July 18, 2006
FN8212
Rev 2.00
July 18, 2006
X95820
Dual Digital Controlled Potentiometers (XDCP™) Low Noise/Low Power/I2C
Bus/256 Taps
DATASHEET
The X95820 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Two potentiometers in one package
• 256 resistor taps-0.4% resolution
•I
2C serial interface
- Three address pins, up to eight devices/bus
• Wiper resistance: 70 typical @ 3.3V
• Non-volatile storage of wiper position
• Standby current < 5µA max
• Power supply: 2.7V to 5.5V
•50k, 10k total resistance
• High reliability
- Endurance: 150,000 data changes per bit per register
- Register data retention: 50 years @ T 75°C
• 14 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
Pinouts
X95820
(14 LD TSSOP)
TOP VIEW
Ordering Information
PART NUMBER
PART
MARKING
RESISTANCE
OPTION PACKAGE
X95820WV14I-2.7* X95820WV G 10k14 Ld TSSOP
X95820WV14IZ-2.7*
(Note)
X95820WV Z G 10k14 Ld TSSOP
(Pb-free)
X95820UV14I-2.7* X95820UV G 50k14 Ld TSSOP
X95820UV14IZ-2.7*
(Note)
X95820UV Z G 50k14 Ld TSSOP
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
A2
1
2
3
4
5
6
7SDA
SCL 8
9
10
14
13
12
11
WP
RW0
RL0
RH0
A1
VCC
RW1
RL1
RH1
A0
GND
X95820
FN8212 Rev 2.00 Page 2 of 12
July 18, 2006
Block Diagram
RH1
WR1 RW1
RL1
RH0
WR0 RW0
RL0
POWER-UP,
INTERFACE,
CONTROL AND
STATUS LOGIC
NON-VOLATILE
REGISTERS
I2C
INTERFACE
SDA
SCL
A2
A1
A0
WP GND
VCC
PiN Descriptions
PIN SYMBOL DESCRIPTION
1V
CC Power supply pin
2WP
Hardware write protection pin. Active low. Prevents any “Write” operation of the I2C interface.
3 RH0 “High” terminal of DCP0
4 RL0 “Low” terminal of DCP0
5 RW0 “Wiper” terminal of DCP0
6 A2 Device address for the I2C interface
7SCLI
2C interface clock
8 SDA Serial data I/O for the I2C interface
9 GND Ground
10 RW1 “Wiper” terminal of DCP1
11 RL1 “Low” terminal of DCP1
12 RH1 “High” terminal of DCP1
13 A0 Device address for the I2C interface
14 A1 Device address for the I2C interface
X95820
FN8212 Rev 2.00 Page 3 of 12
July 18, 2006
Absolute Maximum Ratings Recommended Operating Conditions
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Voltage at Any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at Any DCP Pin with Respect to GND . . . . . . -0.3V to VCC
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Analog Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 1) MAX UNIT
RTOTAL RH to RL Resistance W, U versions respectively 10, 50 k
RH to RL Resistance Tolerance -20 +20 %
RWWiper Resistance VCC = 3.3V @ 25°C
Wiper current = VCC/RTOTAL
70 200
CH/CL/CWPotentiometer Capacitance (Note 15) 10/10/25 pF
ILkgDCP Leakage on DCP Pins (Note 15) Voltage at pin from GND to VCC 0.1 1 µA
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1)
INL (Note 6) Integral Non-linearity -1 1 LSB
(Note 2)
DNL (Note 5) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB
(Note 2)
ZSerror
(Note 3)
Zero-scale Error U option 0 1 7 LSB
(Note 2)
W option 0 0.5 2
FSerror
(Note 4)
Full-scale Error U option -7 -1 0 LSB
(Note 2)
W option -2 -1 0
VMATCH
(Note 7)
DCP to DCP Matching Any two DCPs at same tap position, same
voltage at all RH terminals, and same
voltage at all RL terminals
-2 2 LSB
(Note 2)
TCV (Note 8) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not
connected. i = 0 or 1)
RINL
(Note 12)
Integral Non-linearity DCP register set between 20 hex and
FF hex. Monotonic over all tap positions
-1 1 MI
(Note 9)
RDNL
(Note 11)
Differential Non-linearity -0.5 0.5 MI
(Note 9)
Roffset
(Note 10)
Offset DCP Register set to 00 hex, U option 0 1 7 MI
(Note 9)
DCP Register set to 00 hex, W option 0 0.5 2 MI
(Note 9)
RMATCH
(Note 13)
DCP to DCP Matching Any two DCPs at the same tap position with
the same terminal voltages.
-2 2 MI
(Note 9)
TCR
(Note 14)
Resistance Temperature Coefficient DCP register set between 20 hex and FF
hex
±45 ppm/°C
X95820
FN8212 Rev 2.00 Page 4 of 12
July 18, 2006
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 1) MAX UNITS
ICC1 VCC Supply Current
(Volatile write/read)
fSCL = 400kHz;SDA = Open; (for I2C,
Active, Read and Volatile Write States only)
1mA
ICC2 VCC Supply Current
(nonvolatile write)
fSCL = 400kHz; SDA = Open; (for I2C,
Active, Nonvolatile Write State only)
3mA
ISB VCC Current (standby) VCC = +5.5V, I2C Interface in Standby State 5 µA
VCC = +3.6V, I2C Interface in Standby State 2 µA
ILkgDig Leakage Current, at Pins A0,
A1, A2, SDA, SCL, and WP
Pins
Voltage at pin from GND to VCC -10 10 µA
tDCP
(Note 15)
DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to
wiper change
1µs
Vpor Power-on Recall Voltage Minimum VCC at which memory recall occurs 1.8 2.6 V
VccRamp VCC Ramp Rate 0.2 V/ms
tD (Note 15) Power-up Delay VCC above Vpor, to DCP Initial Value Register recall
completed, and I2C Interface in standby state
3ms
EEPROM SPECS
EEPROM Endurance 150,000 Cycles
EEPROM Retention Temperature 75°C 50 Years
SERIAL INTERFACE SPECS
VIL WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
-0.3 0.3*Vcc V
VIH WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
0.7*Vcc Vcc+0.3 V
Hysterisis
(Note 15)
SDA and SCL input buffer
hysterisis
0.05*
Vcc
V
VOL
(Note 15)
SDA Output Buffer LOW
Voltage, Sinking 4mA
00.4V
Cpin
(Note 15)
WP
, A2, A1, A0, SDA, and
SCL Pin Capacitance
10 pF
fSCL SCL Frequency 400 kHz
tIN
(Note 15)
Pulse Width Suppression
Time at SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50 ns
tAA
(Note 15)
SCL Falling Edge to SDA
Output Data Valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window.
900 ns
tBUF
(Note 15)
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VCC during a STOP condition,
to SDA crossing 70% of VCC during the following
START condition.
1300 ns
tLOW Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
tHIGH Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
tSU:STA START Condition Setup
Time
SCL rising edge to SDA falling edge. Both crossing
70% of VCC.
600 ns
tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC.
600 ns
X95820
FN8212 Rev 2.00 Page 5 of 12
July 18, 2006
SDA vs. SCL Timing
WP, A0, A1, and A2 Pin Timing
tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100 ns
tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA
entering the 30% to 70% of VCC window.
0ns
tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA
rising edge crossing 30% of VCC.
600 ns
tHD:STO STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600 ns
tDH (Note 15) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window.
0ns
tR (Note 15) SDA and SCL Rise Time From 30% to 70% of VCC 20 +
0.1 * Cb
250 ns
tF (Note 15) SDA and SCL Fall Time From 70% to 30% of VCC 20 +
0.1 * Cb
250 ns
Cb (Note 15) Capacitive Loading of SDA
or SCL
Total on-chip and off-chip 10 400 pF
Rpu (Note 15) SDA and SCL Bus Pull-up
resIstor Off-chip
Maximum is determined by tR and tF
.
For Cb = 400pF, max is about 2~2.5k.
For Cb = 40pF, max is about 15~20k
1k
tWP
(Notes 15, 16)
Non-volatile Write Cycle
Time
12 20 ms
tSU:WPA A2, A1, A0, and WP Setup
Time
Before START condition 600 ns
tHD:WPA A2, A1, A0, and WP Hold
Time
After STOP condition 600 ns
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 1) MAX UNITS
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tFtLOW
tBUF
tAA
tR
tHD:WPA
SCL
SDA IN
WP, A0, A1, or A2
tSU:WPA
Clk 1
START STOP
X95820
FN8212 Rev 2.00 Page 6 of 12
July 18, 2006
NOTES:
1. Typical values are for TA = 25°C and 3.3V supply voltage.
2. LSB: [V(RW)255 - V(RW)0] / 255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0 / LSB.
4. FS error = [V(RW)255 - VCC] / LSB.
5. DNL = [V(RW)i - V(RW)i-1] / LSB-1, for i = 1 to 255. i is the DCP register setting.
6. INL = [V(RW)i – (i • LSB – V(RW)0)]/LSB for i = 1 to 255.
7. VMATCH = [V(RWx)i - V(RWy)i] / LSB, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.
8.
for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
9. MI = |R255 - R0| / 255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
10. Roffset = R0 / MI, when measuring between RW and RL.
Roffset = R255 / MI, when measuring between RW and RH.
11. RDNL = (Ri - Ri-1) / MI, for i = 32 to 255.
12. RINL = [Ri - (MI • i) - R0] / MI, for i = 32 to 255.
13. RMATCH = (Ri,x - Ri,y) / MI, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.
14.
for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
15. This parameter is not 100% tested.
16. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
TCV
Max V RW
i
Min V RW
i
–
Max V RW
i
Min V RW
i
+2
----------------------------------------------------------------------------------------------106
125°C
-----------------
=
TCR
Max RiMin Ri–
Max RiMin Ri+2
----------------------------------------------------------------106
125°C
-----------------
=
Typical Performance Curves
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC/RTOTAL ] FOR 50k (U)
FIGURE 2. STANDBY ICC vs VCC
0
20
40
60
80
100
120
140
160
0 50 100 150 200 250
TAP POSITION (DECIMAL)
WIPER RESISTANCE ()
VCC = 5.5, T = 25°C
VCC = 5.5, T = -40°C
VCC = 2.7, T = 25°C
VCC = 5.5, T = 85°C
VCC = 2.7, T = 85°C
VCC = 2.7, T = -40°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.7 3.2 3.7 4.2 4.7 5.2
VCC (V)
STANDBY ICC (µA)
-40°C
85°C
25°C
X95820
FN8212 Rev 2.00 Page 7 of 12
July 18, 2006
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 5. ZSerror vs TEMPERATURE FIGURE 6. FSerror vs TEMPERATURE
FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR
50k (U)
FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR
50k (U)
Typical Performance Curves (Continued)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 50 100 150 200 250
TAP POSITION (DECIMAL)
DNL (LSB)
VCC = 5.5, T = 25°C
VCC = 2.7, T = 25°C
VCC = 5.5, T = -40°C VCC = 2.7, T = -40°C
VCC = 2.7, T = 85°C VCC = 5.5, T = 85°C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 50 100 150 200 250
TAP POSITION (DECIMAL)
INL (LSB)
VCC = 2.7, T = 85°C
VCC = 5.5, T = -40°C
VCC = 2.7, T = -40°C
VCC = 5.5, T = 85°C
VCC = 5.5, T = 25°C
VCC = 2.7, T = 25°C
0.15
0.2
0.25
0.3
0.35
0.4
-40-200 20406080
TEMPERATURE (°C)
ZSerror (LSB)
5.5V
2.7V
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
-40 -20 020 40 60 80
TEMPERATURE (°C)
FSerror (LSB)
VCC = 5.5V
VCC = 2.7V
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
32 82 132 182 232
TAP POSITION (DECIMAL)
DNL (LSB)
VCC = 2.7, T = -40°C
VCC = 5.5, T = -40°C
VCC = 5.5, T = 85°C
VCC = 2.7, T = 25°C
VCC = 5.5, T = 25°C
VCC = 2.7, T = 85°C
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
32 82 132 182 232
TAP POSITION (DECIMAL)
INL (LSB)
VCC = 2.7, T = -40°C
VCC = 5.5, T = 25°C
VCC = 5.5, T = 85°C
VCC = 5.5, T = -40°C
VCC = 2.7, T = 25°C
VCC = 2.7, T = 85°C
X95820
FN8212 Rev 2.00 Page 8 of 12
July 18, 2006
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 11. TC FOR Rheostat MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0) FIGURE 14. LARGE SIGNAL SETTLING TIME
Typical Performance Curves (Continued)
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
-40-200 20406080
TEMPERATURE (°C)
END TO END RTOTAL CHANGE (%)
5.5V
2.7V
-20
-10
0
10
20
32 82 132 182 232
TAP POSITION (DECIMAL)
TC (ppm/°C)
-25
-15
-5
5
15
25
35
32 57 82 107 132 157 182 207 232
TAP POSITION (DECIMAL)
TC (ppm/°C)
Tap Position = Mid Point
RTOTAL = 9.4K
OUTPUT
INPUT
Wiper Movement Mid Point
From 80h to 7fh
Signal at Wiper (Wiper Unloaded)
SCL
Signal at Wiper
(Wiper Unloaded Movement
From to 00h)
X95820
FN8212 Rev 2.00 Page 9 of 12
July 18, 2006
Principles of Operation
The X95820 in as integrated circuit incorporating two DCPs
with their associated registers, non-volatile memory, and a I2C
serial interface providing direct communication between a host
and the potentiometers and memory.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position of
the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (00h) to all ones
(255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the X95820 is being powered up, all two WRs are reset
to 80h (128 decimal), which locates RW roughly at the center
between RL and RH. Soon after the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the X95820 reads the value stored on two different
non-volatile Initial Value Registers (IVRs) and loads them into
their corresponding WRs.
The WRs and IVRs can be read or written directly using the
I2C serial interface as described in the following sections.
Memory Description
The X95820 contains eight non-volatile bytes. they are
accessed by I2C interface operations with Address Bytes 0
through 7 decimal. The first two non-volatile bytes at
addresses 0 and 1 contain the initial value loaded at power-up
into the volatile Wiper Registers (WRs) of DCP0 and DCP1
respectively. Bytes at addresses 2, 3, 4, 5, and 6 are available
to the user as general purpose registers. The byte at address 7
is reserved; the user should not write to it, and its value should
be ignored if read.
The volatile WR, and the non-volatile Initial Value Register
(IVR) of a DCP are accessed with the same Address Byte.
A volatile byte at address 8 decimal, controls what byte is read
or written when accessing DCP registers: the WR, the IVR, or
both.
When the byte at address 8 is all zeroes, which is the default at
power up:
• A read operation to addresses 0 or 1 outputs the value of the
non-volatile IVRs.
• A write operation to addresses 0 or 1 writes the same value
to the WR and IVR of the corresponding DCP.
When the byte at address 8 is 80h (128 decimal):
• A read operation to addresses 0 or 1 outputs the value of the
volatile WR.
• A write operation to addresses 0 or 1only writes to the
corresponding volatile WR.
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
00h and 80h are the only values that should be written to
address 8. All other values are reserved and must not be
written to address 8.
To access the general purpose bytes at addresses 2, 3, 4, 5, or
6, the value at address 8 must be all zeros.
The X95820 is pre-programmed with 80h in the two IVRs.
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The X95820 supports a bidirectional I2C bus oriented protocol.
The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the X95820 operates as a slave device
in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (See Figure 15). On
power up of the X95820 the SDA pin is in the input mode.
TABLE 1. MEMORY MAP
ADDRESS NON-VOLATILE VOLATILE
8 - Access Control
7Reserved
6
5
4
3
2
General Purpose Not Available
1
0
IVR1
IVR0
WR1
WR0
X95820
FN8212 Rev 2.00 Page 10 of 12
July 18, 2006
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The X95820 continuously monitors the SDA and SCL
lines for the START condition and does not respond to any
command until this condition is met (See Figure 15). A START
condition is ignored during the power up sequence and during
internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL
is HIGH (See Figure 15). A STOP condition at the end of a
read operation, or at the end of a write operation to volatile
bytes only places the device in its standby mode. A STOP
condition during a write operation to a non-volatile byte,
initiates an internal non-volatile write cycle. The device enters
its standby state when the internal non-volatile write cycle is
completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits of
data (See Figure 16).
The X95820 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
X95820 also responds with an ACK after receiving a Data Byte
of a write operation. The master must respond with an ACK
after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as the four MSBs, and
the following three bits matching the logic values present at
pins A2, A1, and A0. The LSB in the Read/Write bit. Its value is
“1” for a Read operation, and “0” for a Write operation (See
Table 2).
TABLE 2. IDENTIFICATION BYTE FORMAT
1 0 1 0 A2 A1 A0 R/W
(MSB) (LSB)
Logic values at pins A2, A1, and A0 respectively
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
X95820
FN8212 Rev 2.00 Page 11 of 12
July 18, 2006
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte, and
a STOP condition. After each of the three bytes, the X95820
responds with an ACK. At this time, if the Data Byte is to be
written only to volatile registers, then the device enters its
standby state. If the Data Byte is to be written also to non-
volatile memory, the X95820 begins its internal write cycle to
non-volatile memory. During the internal non-volatile write
cycle, the device ignores transitions at the SDA and SCL pins,
and the SDA output is at a high impedance state. When the
internal non-volatile write cycle is completed, the X95820
enters its standby state (See Figure 17).
The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See “Memory Description” on page 9.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile and
non-volatile registers. During a Write sequence, the Data Byte
is loaded into an internal shift register as it is received. If the
Address Byte is 0, 1, or 8 decimal, the Data Byte is transferred
to the appropriate Wiper Register (WR) or to the Access
Control Register, at the falling edge of the SCL pulse that loads
the last bit (LSB) of the Data Byte. If the Address Byte is
between 0 and 6 (inclusive), and the Access Control Register
is all zeros (default), then the STOP condition initiates the
internal write cycle to non-volatile memory.
Read Operation
A Read operation consists of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the X95820 responds with an ACK. Then the X95820 transmits
Data Bytes as long as the master responds with an ACK during
the SCL cycle following the eight bit of each byte. The master
terminates the read operation (issuing a STOP condition)
following the last bit of the last Data Byte (See Figure 18).
The Data Bytes are from the memory location indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 01Fh (8 decimal) the
pointer “rolls over” to 00h, and the device continues to output
data for each ACK received.
The byte at address 00001000 bin (8 decimal) determines if
the Data Bytes being read are from volatile or non-volatile
memory. See “Memory Description” on page 9.
Signals
from the
Master
Signals from the
Slave
Signal at SDA
S
t
a
r
t
Identification
Byte
with
R/W=0 Address
Byte
A
C
K
A
C
K
10
100
S
t
o
p
A
C
K
11
100
Identification
Byte
with
R/W=1
A
C
K
S
t
a
r
t
Last Read Data
Byte
First Read Data
Byte
A
C
K
FIGURE 18. READ SEQUENCE
FN8212 Rev 2.00 Page 12 of 12
July 18, 2006
X95820
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
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All trademarks and registered trademarks are the property of their respective owners.
Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
0o8o0o8o-
Rev. 2 4/06