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FEATURES
SN54LVTH16373. . . WD PACKAGE
SN74LVTH16373. . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
DESCRIPTION/ORDERING INFORMATION
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
•Members of the Texas Instruments Widebus™Family
•State-of-the-Art Advanced BiCMOSTechnology (ABT) Design for 3.3-V Operationand Low Static-Power Dissipation•Support Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V V
CC
)•Support Unregulated Battery Operation Downto 2.7 V•Typical V
OLP
(Output Ground Bounce) <0.8 Vat V
CC
= 3.3 V, T
A
= 25 °C•I
off
and Power-Up 3-State Support HotInsertion
•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Distributed V
CC
and GND Pins MinimizeHigh-Speed Switching Noise•Flow-Through Architecture Optimizes PCBLayout
•Latch-Up Performance Exceeds 500 mA PerJESD 17•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)
The 'LVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for low-voltage(3.3-V) V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment. Thesedevices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, andworking registers.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
FBGA – GRD SN74LVTH16373GRDR
Reel of 1000 LL373FBGA – ZRD (Pb-free) SN74LVTH16373ZRDR
Tube of 25 SN74LVTH16373DL
SN74LVTH16373DLG4SSOP – DL LVTH16373–40 °C to 85 °C Reel of 1000 SN74LVTH16373DLR
SN74LVTH16373DLRG4TSSOP – DGG Reel of 2000 SN74LVTH16373DGGR LVTH16373VFBGA – GQL SN74LVTH16373GQLR
Reel of 1000 LL373VFBGA – ZQL (Pb-free) SN74LVTH16373ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1992–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters areInstruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, productionnecessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
K
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
ORDERING INFORMATION (continued)
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SNJ54LVTH16373WD–55 °C to 125 °C CFP – WD SNJ54LVTH16373WD5962-9681001QXA
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, theQ outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at theD inputs.
A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high orlow logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive thebus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lineswithout interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered whilethe outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldownresistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitrydisables the outputs, preventing damaging current backflow through the devices when they are powered down.The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,which prevents driver conflict.
TERMINAL ASSIGNMENTS
(1)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
A1 OE NC NC NC NC 1CLK
B1Q2 1Q1 GND GND 1D1 1D2
C1Q4 1Q3 V
CC
V
CC
1D3 1D4
D1Q6 1Q5 GND GND 1D5 1D6
E1Q8 1Q7 1D7 1D8
F2Q1 2Q2 2D2 2D1
G2Q3 2Q4 GND GND 2D4 2D3
H2Q5 2Q6 V
CC
V
CC
2D6 2D5
J2Q7 2Q8 GND GND 2D8 2D7
K2 OE NC NC NC NC 2CLK
(1) NC – No internal connection
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GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1 2Q1
To Seven Other Channels
1
48
47
24
25
36 C1
1D 132
C1
1D
Pin numbers shown are for the DGG, DL, and WD packages.
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
1 2 3 4 5 6
A1Q1 NC 1 OE 1LE NC 1D1
B1Q3 1Q2 NC NC 1D2 1D3
C1Q5 1Q4 V
CC
V
CC
1D4 1D5
D1Q7 1Q6 GND GND 1D6 1D7
E2Q1 1Q8 GND GND 1D8 2D1
F2Q3 2Q2 GND GND 2D2 2D3
G2Q5 2Q4 V
CC
V
CC
2D4 2D5
H2Q7 2Q6 NC NC 2D6 2D7
J2Q8 NC 2 OE 2LE NC 2D8
(1) NC – No internal connection
FUNCTION TABLE(8-BIT SECTION)
INPUTS
OUTPUT
QOE CLK D
L H H HL H L LL L X Q
0
H X X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 VV
I
Input voltage range
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high state
(2)
–0.5 V
CC
+ 0.5 VSN54LVTH16373 96I
O
Current into any output in the low state mASN74LVTH16373 128SN54LVTH16373 48I
O
Current into any output in the high state
(3)
mASN74LVTH16373 64I
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mADGG package 70DL package 63θ
JA
Package thermal impedance
(4)
°CGQL/ZQL package 42GRD/ZRD package 36T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) This current flows only when the output is in the high state and V
O
> V
CC
.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
SN54LVTH16373 SN74LVTH16373
UNITMIN MAX MIN MAX
V
CC
Supply voltage 2.7 3.6 2.7 3.6 VV
IH
High-level input voltage 2 2 VV
IL
Low-level input voltage 0.8 0.8 VV
I
Input voltage 5.5 5.5 VI
OH
High-level output current –24 –32 mAI
OL
Low-level output current 48 64 mA∆t/ ∆v Input transition rise or fall rate Outpts enabled 10 10 ns/V∆t/ ∆V
CC
Power-up ramp rate 200 200 µs/VT
A
Operating free-air temperature –55 125 –40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVTH16373 SN74LVTH16373PARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN TYP
(1)
MAX
V
IK
V
CC
= 2.7 V, I
I
= –18 mA –1.2 –1.2 VV
CC
= 2.7 V to 3.6 V, I
OH
= –100 µA V
CC
– 0.2 V
CC
– 0.2V
CC
= 2.7 V, I
OH
= –8 mA 2.4 2.4V
OH
VI
OH
= –24 mA 2V
CC
= 3 V
I
OH
= –32 mA 2I
OL
= 100 µA 0.2 0.2V
CC
= 2.7 V
I
OL
= 24 mA 0.5 0.5I
OL
= 16 mA 0.4 0.4V
OL
VI
OL
= 32 mA 0.5 0.5V
CC
= 3 V
I
OL
= 48 mA 0.55I
OL
= 64 mA 0.55V
CC
= 0 or 3.6 V, V
I
= 5.5 V 10 10Control
V
CC
= 3.6 V, V
I
= V
CC
or GND ±1±1inputsI
I
µAV
I
= V
CC
1 1Data
V
CC
= 3.6 Vinputs
V
I
= 0 –5 –5I
off
V
CC
= 0, V
I
or V
O
= 0 to 4.5 V ±100 µAV
I
= 0.8 V 75 75V
CC
= 3 VDataI
I(hold)
V
I
= 2 V –75 –75 µAinputs
V
CC
= 3.6 V,
(2)
V
I
= 0 to 3.6 V ±500I
OZH
V
CC
= 3.6 V, V
O
= 3 V 5 5 µAI
OZL
V
CC
= 3.6 V, V
O
= 0.5 V –5 –5 µAV
CC
= 0 to 1.5 V, V
O
= 0.5 V to 3 V,I
OZPU
±100
(3)
±100 µAOE = don't careV
CC
= 1.5 V to 0, V
O
= 0.5 V to 3 V,I
OZPD
±100
(3)
±100 µAOE = don't care
Outputs high 0.19 0.19V
CC
= 3.6 V,I
CC
I
O
= 0, Outputs low 5 5 mAV
I
= V
CC
or GND
Outputs disabled 0.19 0.19V
CC
= 3 V to 3.6 V, One input at V
CC
– 0.6 V,∆I
CC
(4)
0.2 0.2 mAOther inputs at V
CC
or GNDC
i
V
I
= 3 V or 0 3 3 pFC
o
V
O
= 3 V or 0 9 9 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state toanother.
(3) On products compliant to MIL-PRF-38535, this parameter is not production tested.(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
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Timing Requirements
Switching Characteristics
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
SN54LVTH16373 SN74LVTH16373
V
CC
= 3.3 V V
CC
= 3.3 VV
CC
= 2.7 V V
CC
= 2.7 V UNIT±0.3 V ±0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LE high 3 3 3 3 nst
su
Setup time, data before LE ↓2 2 1 0.6 nst
h
Hold time, data after LE ↓3 3.3 1 1.1 ns
over recommended operating free-air temperature range, C
L
= 50 pF (unless otherwise noted) (see Figure 1 )
SN54LVTH16373 SN74LVTH16373
FROM TO V
CC
= 3.3 V V
CC
= 3.3 VPARAMETER V
CC
= 2.7 V V
CC
= 2.7 V UNIT(INPUT) (OUTPUT) ±0.3 V ±0.3 V
MIN MAX MIN MAX MIN TYP
(1)
MAX MIN MAX
t
PLH
1.4 4.5 5.2 1.5 2.7 3.8 4.2D Q nst
PHL
1.4 4.4 4.8 1.5 2.5 3.6 4t
PLH
1.8 5.5 5.8 2.1 3 4.3 4.8LE Q nst
PHL
1.8 5.2 5.6 2.1 2.9 4 4t
PZH
1.4 5.7 6.7 1.5 2.8 4.3 5.1OE Q nst
PZL
1.4 5.5 6 1.5 2.8 4.3 4.7t
PHZ
2 6 6.2 2.4 3.5 5 5.4OE Q nst
PLZ
1.4 5.2 5.6 2 3.2 4.7 4.8t
sk(LH)
0.5
nst
sk(HL)
0.5
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.
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PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Data Input
Timing Input 2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE W AVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH − 0.3 V
≈0 V
2.7 V
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
6 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
th
tsu
1.5 V 1.5 V
1.5 V
1.5 V
SN54LVTH16373 , , SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
SCBS144P – MAY 1992 – REVISED NOVEMBER 2006
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9681001QXA ACTIVE CFP WD 48 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9681001QX
A
SNJ54LVTH16373
WD
74LVTH16373DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373
74LVTH16373DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373
SN74LVTH16373DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373
SN74LVTH16373DL ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373
SN74LVTH16373DLG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373
SN74LVTH16373DLR ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH16373
SN74LVTH16373GQLR OBSOLETE BGA
MICROSTAR
JUNIOR
GQL 56 TBD Call TI Call TI -40 to 85 LL373
SN74LVTH16373GRDR OBSOLETE BGA
MICROSTAR
JUNIOR
GRD 54 TBD Call TI Call TI -40 to 85 LL373
SN74LVTH16373ZQLR ACTIVE BGA
MICROSTAR
JUNIOR
ZQL 56 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 LL373
SN74LVTH16373ZRDR ACTIVE BGA
MICROSTAR
JUNIOR
ZRD 54 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 LL373
SNJ54LVTH16373WD ACTIVE CFP WD 48 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9681001QX
A
SNJ54LVTH16373
WD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVTH16373, SN74LVTH16373 :
•Catalog: SN74LVTH16373
•Enhanced Product: SN74LVTH16373-EP, SN74LVTH16373-EP
•Military: SN54LVTH16373
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVTH16373DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74LVTH16373DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
SN74LVTH16373ZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1
SN74LVTH16373ZRDR BGA MI
CROSTA
R JUNI
OR
ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVTH16373DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74LVTH16373DLR SSOP DL 48 1000 367.0 367.0 55.0
SN74LVTH16373ZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
SN74LVTH16373ZRDR BGA MICROSTAR
JUNIOR ZRD 54 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2012
Pack Materials-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WD (R-GDFP-F**) CERAMIC DUAL FLATPACK
4040176/D 10/97
48 LEADS SHOWN
48
48
25
56
0.610
(18,80)
0.710
(18,03)
0.7400.640
0.390 (9,91)
0.370 (9,40)
0.870 (22,10)
1.130 (28,70)
1
A
0.120 (3,05)
0.075 (1,91)
LEADS**
24
NO. OF
A MIN
A MAX (16,26)
(15,49)
0.025 (0,635)
0.009 (0,23)
0.004 (0,10)
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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