Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 3 1Publication Order Number:
MC74HC541A/D
MC74HC541A
Octal 3-State Noninverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pull–up
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS and TTL
•Operating Voltage Range: 2 to 6V
•Low Input Current: 1 A
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With the JEDEC Standard No. 7A Requirements
•Chip Complexity: 134 FETs or 33.5 Equivalent Gates
1920 18 17 16 15 14
21 34567
VCC 13
8
12
9
11
10
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
Figure 1. Pinout: 20–Lead Packages (Top View)
L
L
H
X
L
L
X
H
L
H
X
X
Inputs Output Y
OE1 OE2 A
L
H
Z
Z
X = Don’t Care
Z = High Impedance
FUNCTION TABLE
1440/BoxMC74HC541AN PDIP–20
MC74HC541ADWR2 SOIC–WIDE 1000/Reel
ORDERING INFORMATION
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MARKING
DIAGRAMS
Device Package Shipping
MC74HC541ADW SOIC–WIDE 38/Rail
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
TSSOP–20
DT SUFFIX
CASE 948E
HC541A
ALYW
20
1
SO–20
DW SUFFIX
CASE 751D
1
20
HC541A
AWLYYWW
PDIP–20
N SUFFIX
CASE 783
1
20 MC74HC541AN
AWLYYWW
TSSOP–20 75/Rail
TSSOP–20 2500/Reel
MC74HC541ADT
MC74HC541ADTR2
MC74HC541A
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2
18 Y1
2
A1
17 Y2
3
A2
16 Y3
4
A3
15 Y4
5
A4
14 Y5
6
A5
13 Y6
7
A6
12 Y7
8
A7
11 Y8
9
A8
OE1
OE2 1
19
Output
Enables
Data
Inputs Noninverting
Outputs
PIN 20 = VCC
PIN 10 = GND
Figure 2. Logic Diagram
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3
MAXIMUM RATINGS (Note 1)
Symbol Parameter Value Unit
VCC DC Supply Voltage 0.5 to 7.0 V
VIDC Input Voltage 0.5 VI 0.5 V
VODC Output Voltage (Note 2) 0.5 VO 0.5 V
IIK DC Input Diode Current 20 mA
IOK DC Output Diode Current 35 mA
IODC Output Sink Current 35 mA
ICC DC Supply Current per Supply Pin 75 mA
IGND DC Ground Current per Ground Pin 75 mA
TSTG Storage Temperature Range 65 to 150 C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 C
TJJunction Temperature under Bias 150 C
JA Thermal Resistance PDIP
SOIC
TSSOP
67
96
128
C/W
PDPower Dissipation in Still Air at 85C PDIP
SOIC
TSSOP
750
500
450
mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% – 35% UL–94–VO (0.125 in)
VESD ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 4000
> 300
> 1000
V
ILatch–Up Latch–Up Performance Above VCC and Below GND at 85C (Note 6) 300 mA
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. IO absolute maximum rating must be observed.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
7. For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
2.0
ÎÎÎÎ
ÎÎÎÎ
6.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VIN, VOUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
ÎÎÎÎÎ
ÎÎÎÎÎ
55
ÎÎÎÎ
ÎÎÎÎ
125
ÎÎÎ
ÎÎÎ
C
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall Time VCC = 2.0 V
(Figure 3) VCC = 4.5 V
VCC = 6.0 V
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
0
0
0
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
1000
500
400
ÎÎÎ
Î
Î
Î
ÎÎÎ
ns
8. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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4
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Condition V55C to 25C85C125C Unit
VIH Minimum High–Level Input
Voltage VOUT = 0.1 V
|IOUT| ≤ 20 A2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low–Level Input
Voltage VOUT = VCC – 0.1 V
|IOUT| ≤ 20 A2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH Minimum High–Level Output
Voltage VIN = VIL
|IOUT| ≤ 20 A2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN = VIL |IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low–Level Output
Voltage VIN = VIH
|IOUT| ≤ 20 A2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH |IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IIN Maximum Input Leakage Current VIN = VCC or GND 6.0 0.1 1.0 1.0 A
IOZ Maximum Three–State Leakage
Current Output in High Impedance State
VIN = VIL or VIH
VOUT = VCC or GND
6.0 0.5 5.0 10.0 A
ICC Maximum Quiescent Supply
Current (per Package) VIN = VCC or GND
IOUT = 0 A6.0 4 40 160 A
9. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
VCC Guaranteed Limit
Symbol Parameter V 55C to 25C85C125C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5) 2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6) 2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6) 2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition T ime, Any Output
(Figures 3 and 5) 2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
CIN Maximum Input Capacitance 10 10 10 pF
COUT Maximum Three–State Output Capacitance (High Impedance State Output) 15 15 15 pF
10.For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer) (Note 11) 35 pF
11. Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
MC74HC541A
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5
Figure 3. Switching Waveform
VCC
GND
INPUT A
OUTPUT Y
tPLH
OE1 or OE2 50%
VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
tPHL
90%
50%
10%
tr
tTLH
tf
tTHL
Figure 4. Switching Waveform
90%
50%
10%
50%
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5. Test Circuit Figure 6. Test Circuit
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT 1 kCONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in non–inverted
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
Output enables (active–low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
device functions as an non–inverting buffer. When a high
voltage i s applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either non–inverting outputs
or high–impedance outputs.
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6
VCC
To 7 Other Buffers
Figure 7. Logic Detail
One of Eight
Buffers
INPUT A
OE1
OE2
OUTPUT Y
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7
PACKAGE DIMENSIONS
PDIP
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A25.66 27.171.010 1.070
B6.10 6.600.240 0.260
C3.81 4.570.150 0.180
D0.39 0.550.015 0.022
G2.54 BSC0.100 BSC
J0.21 0.380.008 0.015
K2.80 3.550.110 0.140
L7.62 BSC0.300 BSC
M0 15 0 15
N0.51 1.010.020 0.040
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
hX 45
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
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8
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
–T–
0.100 (0.004)
C
DGH
SECTION N–N
K
K1
JJ1
N
N
M
F
–W–
SEATING
PLANE
–V–
–U–
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
--- ---
S
U0.15 (0.006) T
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MC74HC541A/D
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