ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 1 -
GENERAL DESCRIPTION
The AK4382A offers the perfect mix for cost and performance based audio systems. Using AKM's multi
bit architecture for its modulator the AK4382A delivers a wide dynamic range while preserving linearity
for improved THD+N performance. The AK4382A has full differential SCF outputs, removing the need
for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit
word length and 216kHz sampling rate make this part ideal for a wide range of applications including
DVD-Audio. The AK4382A is offered in a space saving 16pin TSSOP package.
FEATURES
o Sampling Rate Ranging from 8kHz to 216kHz
o 128 times Oversampling (Normal Speed Mode)
o 64 times Oversampling (Double Speed Mode)
o 32 times Oversampling (Quad Speed Mode)
o 24-Bit 8 times FIR Digital Filter
o On chip SCF
o Digital de-emphasis for 32k, 44.1k and 48kHz sampling
o Soft mute
o Digital Attenuator (256 steps)
o I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
o Master clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
o THD+N: -94dB
o Dynamic Range: 112dB
o High Tolerance to Clock Jitter
o Power supply: 4.75 to 5.25V
o Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
PDN
∆Σ
Modulator
AOUTL+
8X
Interpolator
SCF
AOUTR+
SCF
VDD
VSS
De-emphasis
Control
µP
Interface
Clock
Divider
CSN
CDTI
DZFR
∆Σ
Modulator
8X
Interpolator
AOUTL-
AOUTR-
DZFL
112dB 192kHz 24-Bit 2ch ∆Σ
DAC
AK4382A
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 2 -
n Ordering Guide
AK4382AVT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4382 Evaluation Board for AK4382A
n Pin Layout
1
MCLK
LRCK
BICK
CSN
CCLK
CDTI
Top
View
2
3
4
5
6
7
8
DZFL
DZFR
VSS
VDD
AOUTL+
AOUTL-
AOUTR+
AOUTR-
16
15
14
13
12
11
10
9
PDN
SDTI
PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power-Down Mode Pin
When at “L”, the AK4382A is in the power-down mode and is held in reset.
The AK4382A should always be reset upon power-up.
6 CSN I Chip Select Pin
7 CCLK I Control Data Input Pin
8 CDTI I Control Data Input Pin in serial mode
9 AOUTR- O Rch Negative Analog Output Pin
10 AOUTR+ O Rch Positive Analog Output Pin
11 AOUTL- O Lch Negative Analog Output Pin
12 AOUTL+ O Lch Positive Analog Output Pin
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 DZFR O Rch Data Zero Input Detect Pin
16 DZFL O Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD -0.3 6.0 V
Input Current (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 VDD+0.3 V
Ambient Operating Temperature Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply VDD 4.75 5.0 5.25 V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 4 -
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥2kΩ; unless otherwise specified)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 3)
fs=44.1kHz
BW=20kHz 0dBFS
-60dBFS -94
-48 -86
- dB
dB
fs=96kHz
BW=40kHz 0dBFS
-60dBFS -92
-45 -84
- dB
dB
THD+N
fs=192kHz
BW=40kHz 0dBFS
-60dBFS -92
-45 -
- dB
dB
Dynamic Range (-60dBFS with A-weighted) (Note 4) 102 112 dB
S/N (A-weighted) (Note 5) 102 112 dB
Interchannel Isolation (1kHz) 90 110 dB
Interchannel Gain Mismatch 0.2 0.5 dB
DC Accuracy
Gain Drift 100 - ppm/°C
Output Voltage (Note 6) ±2.55 ±2.75 ±2.95 Vpp
Load Resistance (Note 7) 2 kΩ
Power Supplies
Power Supply Current (VDD)
Normal Operation (PDN = “H”, fs≤96kHz)
Normal Operation (PDN = “H”, fs=192kHz)
Power-Down Mode (PDN = “L”) (Note 8)
20
25
10
34
42
100
mA
mA
µA
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5.
7. For AC-load. 4kΩ for DC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 5 -
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 9)
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 9) SB 24.1 kHz
Passband Ripple PR ± 0.02 dB
Stopband Attenuation SA 54 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
Digital Filter + SCF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.2
± 0.3
+0/-0.6
-
-
-
dB
dB
dB
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.04dB (Note 11)
-3.0dB PB
0
-
18.2 8.1
- kHz
kHz
Stopband (Note 11) SB 39.2 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 72 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
Digital Filter + SCF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
+0/-5
+0/-4
+0/-5
-
-
-
dB
dB
dB
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
DC CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage (Iout=80µA) VOH
VOL VDD-0.4
- - -
0.4 V
V
Input Leakage Current Iin - - ± 10 µA
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 6 -
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle
fCLK
dCLK 2.048
40 11.2896
41.472
60 MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
60
120
45
54
108
216
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK Period
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK Edge (Note 12)
LRCK Edge to BICK rising (Note 12)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 13)
tPD
150
ns
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.
13. The AK4382A can be reset by bringing PDN= “L”.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 7 -
n Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x
fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Serial Interface Timing
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Command Input Timing
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tPD
VIL
PDN
Power-down Timing
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4382A, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter
and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”:
Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4382A is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the
appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4382A is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4382A may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4382A should be reset by PDN= “L” after threse clocks are provided. If the
external clocks are not present, the AK4382A should be in the power-down mode (PDN= “L”). After exiting reset at
power-up etc., the AK4382A is in the power-down mode until MCLK and LRCK are input.
DFS1 DFS0 Sampling Rate (fs)
0 0 Normal Speed Mode 8kHz~54kHz Default
0 1 Double Speed Mode 60kHz~108z
1 0 Quad Speed Mode 120kHz~216kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK MCLK BICK
fs 128fs 192fs 256fs 384fs 64fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK MCLK BICK
fs 128fs 192fs 64fs
176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
- 10 -
MCLK Sampling Speed
512fs 768fs Normal
256fs 384fs Double
128fs 192fs Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs Sampling Speed
32.0kHz - - - - 16.3840 24.5760
44.1kHz - - - - 22.5792 33.8688
48.0kHz - - - - 24.5760 36.8640 Normal
88.2kHz - - 22.5792 33.8688 - -
96.0kHz - - 24.5760 36.8640 - - Double
176.4kHz 22.5792 33.8688 - - - -
192.0kHz 24.5760 36.8640 - - - - Quad
Table 6. System Clock Example (Auto Setting Mode)
n Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial data
modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can
be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format BICK Figure
0 0 0 0 16bit LSB Justified ≥32fs Figure 1
1 0 0 1 20bit LSB Justified ≥40fs Figure 2
2 0 1 0 24bit MSB Justified ≥48fs Figure 3 Default
3 0 1 1 24bit I2S Compatible ≥48fs Figure 4
4 1 0 0 24bit LSB Justified ≥48fs Figure 2
Table 7. Audio Data Formats
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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SDTI
BICK
LRCK
SDTI
15
14
6
5
4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3
2
1
0
15
14
(32fs)
(64fs)
0 141 15 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0
15
14
0
Mode 0
Don’t care Don’t care
15:MSB, 0:LSB
Mode 0
15
14
6
5
4
3
2
1
0
Lch Data Rch Data
Figure 1. Mode 0 Timing
SDTI
LRCK
BICK
(64fs)
0 91 10 11 12 31 0 1 9 10 11 12 31 0 1
19
0
19
0
Mode 1
Don’t care
Don’t care
19:MSB, 0:LSB
SDTI
Mode 4
23:MSB, 0:LSB
20
19
0
20
19
0
Don’t care
Don’t care
22
21
22
21
Lch Data Rch Data
8
23
23
8
Figure 2. Mode 1,4 Timing
LRCK
BICK
(64fs)
SDTI
0 221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23 30 222 2423 30
22 1
0
Don’t care
23
22
23
Figure 3. Mode 2 Timing
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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LRCK
0 31 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data Rch Data
23 25 32 2423 25
22
1
0
Don’t care
23
23
Figure 4. Mode 3 Timing
n De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with
DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1 DEM0 Mode
0 0 44.1kHz
0 1 OFF Default
1 0 48kHz
1 1 32kHz
Table 8. De-emphasis Filter Control (Normal Speed Mode)
n
Output Volume
The AK4382A includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing levels,
transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time of 1
level and all 256 levels is shown in Table 9.
Transition Time Sampling Speed
1 Level 255 to 0
Normal Speed Mode 4LRCK 1020LRCK
Double Speed Mode 8LRCK 2040LRCK
Quad Speed Mode 16LRCK 4080LRCK
Table 9. ATT Transition Time
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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n Zero Detection
The AK4382A has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data
of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin of both
channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H”
only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be
disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.
n Soft Mute Operation
Soft mute operation is performed at digital domain. When th e SMUTE bit goes to “1”, the output signal is attenuated by -∞
during ATT_DATA×ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to “0”, the
mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time.
If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the
signal transmission.
SMUTE bit
Attenuation
DZF pin
ATT Level
-∞
AOUT
8192/fs
GD GD
(1)
(2)
(3)
(4)
(1)
Notes:
(1) ATT_DATA ×ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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n System Reset
The AK4382A should be reset once by bringing PDN= ”L” upon power-up. The AK4382A is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4382A is in the power-down
mode until MCLK and LRCK are input.
n Power-down
The AK4382A is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PDN
Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1) (3)
(6)
DZFL/DZFR
External
MUTE
(5)
(3)
(1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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n
Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM
voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit.
Internal
State
RSTN bit
Digital Block Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZF
(3)
(1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is out put even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal
RSTN “1”.
Figure 7. Reset Sequence Example
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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n
Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of
Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and
Control Data (MSB first, 8bits). AK4382A latches the data on the rising edge of CCLK, so data should clocked in on the
falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max). The CSN must be fixed
to “H” when the register does not be accessed.
PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are
not initialized.
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*The AK4382A does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4382A is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
is inhibited.
n Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
02H Control 3 0 0 0 0 0 DZFB 0 0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.
All data can be written to the register even if PW or RSTN bit is “0”.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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n
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
default 1 0 0 0 1 0 1 1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the AK4382A should be reset by PDN pin or RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected a utomatically at ACKS bit “1”. In this case, the setting of DFS1-0 are
ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
default 0 0 0 0 0 0 1 0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 8)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 0 0 0 0 0 DZFB 0 0
default 0 0 0 0 0 0 0 0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
default 1 1 1 1 1 1 1 1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4382) is available in order to allow an easy study
on the layout of a surrounding circuit.
1
2
SDTI3
4
5
6
CCLK
7
8
16
DZFR 15
VDD 14
13
12
AOUTL- 11
AOUTR+ 10
9
Master Clock
Micro-
controller
AK4382A
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u
+
Lch
LPF
Rch
LPF
Rch Out
Lch Out
Analog Ground
Digital Ground
Lch
MUTE
Rch
MUTE
Analog
Supply 5V
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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1. Grounding and Power Supply Decoupling
VDD and VSS are supp lied from analog supply and should be separated from system digital supply. Decoupling capacitor,
especially 0.1 µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The differential Voltage
between VDD and VSS pins set the analog output range.
3. Analog Outputs
The analog outputs are full-differential outputs and 0.55 x VDD Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-.
If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is
supplied externally. The input data format is 2 ’s complement. The output voltage (VAOUT) is a positive full scale for 7FFFFF
(@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator
beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog outputs are
differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.
4.7k 4.7k
R1
4.7k R1
4.7k 470p
Vop
470p
Vop
1k
1k
47u
0.1u
BIAS
AOUT-
AOUT+
3300p
When R1=200Ω
When R1=180Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Analog
Out
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k 4.7k
R1
4.7k R1
4.7k
470p
+Vop
470p
-Vop
AOUT-
AOUT+
3300p
When R1=200Ω
When R1=180Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Analog
Out
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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PACKAGE
0-10°
Detail A
Seating Plane
0.10
0.17±0.05
0.22±0.1
0.65
*5.0±0.1
1.05±0.05
A
1
8
9
16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13
M
n
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder(Pb free) plate
ASAHI KASEI [AK4382A]
MS0071-E-02 2002/12
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MARKING
AKM
4382AT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4382AT
4) Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for
and hold AKM harmless from any and all claims arising from the use of said product in the absence
of such notification.