HT9200A/HT9200B
DTMF Generators
Selection Table
Function
Part No.
Operating
Voltage
OSC
Frequency Interface Package
HT9200A 2.5V~5.5V 3.58MHz Serial 8 DIP/SOP
HT9200B 2.5V~5.5V 3.58MHz Serial/Parallel 14 SOP
Block Diagram
Pin Assignment
Rev. 1.40 1 August 30, 2004
Features
·Operating voltage: 2.5V~5.5V
·Serial mode for the HT9200A
·Serial/parallel mode for the HT9200B
·Low standby current
·Low total harmonic distortion
·3.58MHz crystal or ceramic resonator
·HT9200A: 8-pin DIP/SOP package
HT9200B: 14-pin SOP package
General Description
The HT9200A/B tone generators are designed for MCU
interfaces. They can be instructed by a MCU to gener-
ate 16 dual tones and 8 single tones from the DTMF pin.
The HT9200A provides a serial mode whereas the
HT9200B contains a selectable serial/parallel mode in-
terface for various applications such as security sys-
tems, home automation, remote control through
telephone lines, communication systems, etc.
S / P
C o n t r o l
C i r c u i t
3 . 5 8 M H z
C r y s t a l / R e s o n a t o r
O s c i l l a t o r
S e r i a l D a t a
I n p u t C i r c u i t
D T M F
G e n e r a t o r
P a r a l l e l D a t a
I n p u t C i r c u i t
X 1
X 2
D A T A
C L K
C E D 0D 3
D T M F
D 2 D 1
C E
C E
1
2
3
4
8
7
6
5
X 2
X 1
V S S
V D D
D T M F
D A T A
C L K
H T 9 2 0 0 A
8 D I P - A / S O P - A
S / P
1 4
1 3
1 2
1 1
1 0
9
8
1
2
3
4
5
6
7
H T 9 2 0 0 B
1 4 S O P - A
X 2
X 1
V S S
N C
D 0
D 1
V D D
D T M F
D A T A
C L K
D 3
D 2
Pad Assignment Pad Coordinates Unit: mm
Pad
No. XY
Pad
No. XY
1-553.30 430.40 8 553.30 -523.50
2-553.30 -133.50 9 553.30 -190.30
3-553.30 -328.50 10 553.30 4.70
4-553.30 -523.50 11 553.30 340.30
5-220.10 -523.50 12 374.90 523.50
6-25.10 -523.50 13 -279.30 523.50
7 308.10 -523.50
Chip size: 1460 ´1470 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin Name I/O Internal
Connection Description
CE I CMOS IN Chip enable, active low.
No internal pull-high resistor.
X2 O
Oscillator
The system oscillator consists of an inverter, a bias resistor, and the required load
capacitor on chip.
The oscillator function can be implemented by Connect a standard 3.579545MHz
crystal to the X1 and X2 terminals.
X1 I
VSS ¾¾
Negative power suppl, ground
NC ¾¾
No connection
D0~D3 I
CMOS IN
Pull-high
or Floating
Data inputs for the parallel mode
When the IC is operating in the serial mode, the data input terminals (D0~D3) are
included with a pull-high resistor. When the IC is operating in the parallel mode,
these pins become floating.
S/P I CMOS IN
Operation mode selection input
S/P=²H²: Parallel mode
S/P=²L²: Serial mode
CLK I
CMOS IN
Pull-high
or Floating
Data synchronous clock input for the serial mode
When the IC is operating in the parallel mode, the input terminal (CLK) is included
with a pull-high resistor. When the IC is operating in the serial mode, this pin be-
comes floating.
DATA I
CMOS IN
Pull-high
or Floating
Data input terminal for the serial mode
When the IC is operating in the parallel mode, the input terminal (DATA) is included
with a pull-high resistor. When the IC is operating in the serial mode, this pin be-
comes floating.
DTMF O CMOS OUT Output terminal of the DTMF signal
VDD ¾¾
Positive power supply, 2.5V~5.5V for normal operation
HT9200A/HT9200B
Rev. 1.40 2 August 30, 2004
C E
S / P
1
8
29
3
1 0
4
1 1
5
1 2
6
1 3
7
( 0 , 0 )
X 2
X 1
V S S
D 1 D 2
D 0
D 3
C L K
D A T A
D T M F
V D D
Approximate Internal Connection Circuits
Absolute Maximum Ratings
Supply Voltage ..............................VSS-0.3V to VSS+6V Storage Temperature ............................-50°Cto125°C
Input Voltage ................................VSS-0.3 to VDD+0.3V Operating Temperature...........................-20°Cto75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Electrical Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾¾2.5 ¾5.5 V
IDD Operating Current
2.5V S/P=VDD,D0~D3=VSS,
CE=VSS, No load
¾240 2500
mA
5.0V ¾950 3000
VIL ²Low²Input Voltage ¾¾
VSS ¾0.2VDD V
VIH ²High²Input Voltage ¾¾
0.8VDD ¾VDD V
ISTB Standby Current
2.5V S/P=VDD,CE=VDD, no load ¾¾ 1
mA
5.0V ¾¾ 2
RPPull-high Resistance
2.5V VOL=0V 120 180 270
kW
5.0V 45 68 100
tDE DTMF Output Delay Time
(Parallel Mode) 5V ¾¾
tUP+6 tUP+8 ms
VTDC DTMF Output DC Level 2.5V~
5.5V DTMF Output 0.45VDD ¾0.75VDD V
ITOL DTMF Sink Current 2.5V VDTMF=0.5V -0.1 ¾¾
mA
VTAC DTMF Output AC Level 2.5V Row group, RL=5kW0.12 0.15 0.18 Vrms
ACR Column Pre-emphasis 2.5V Row group=0dB 1 2 3 dB
RLDTMF Output Load 2.5V tHD £-23dB 5¾¾kW
HT9200A/HT9200B
Rev. 1.40 3 August 30, 2004
C M O S O U T
C M O S I N
P u l l - h i g h
C M O S I N
O S C I L L A T O R
X 1 X 2
E N
10M
2 0 p F 1 0 p F
VD D
VD D VD D
C M O S I N ( F o r D 0 ~ D 3 ,
C L K , D A T A )
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
tHD Tone Signal Distortion 2.5V RL=5kW¾-30 -23 dB
fCLK Clock Input Rate (Serial
Mode) ¾¾ ¾
100 500 kHz
tUP Oscillator Starting Time
(When CE is low) 5.0V
The time from CE falling
edge to normal oscillator
operation
¾¾10 ms
fOSC System Frequency ¾Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz
HT9200A/HT9200B
Rev. 1.40 4 August 30, 2004
Table 1: Digits vs. Input Data vs. Tone Output Frequency (Serial Mode)
Digit D4 D3 D2 D1 D0 Tone Output
Frequency (Hz)
100001
697+1209
200010
697+1336
300011
697+1477
400100
770+1209
500101
770+1336
600110
770+1477
700111
852+1209
801000
852+1336
901001
852+1477
001010
941+1336
*01011
941+1209
#01100
941+1477
A01101
697+1633
B01110
770+1633
C01111
852+1633
D00000
941+1633
¾10000 697
¾10001 770
¾10010 852
¾10011 941
¾1 0 1 0 0 1209
¾1 0 1 0 1 1336
¾1 0 1 1 0 1477
¾1 0 1 1 1 1633
DTMF OFF 1 1 1 1 1 ¾
Note: The codes not listed in Table 1 are not used D4 is MSB
HT9200A/HT9200B
Rev. 1.40 5 August 30, 2004
Functional Description
The HT9200A/B are DTMF generators for MCU inter-
faces. They are controlled by a MCU in the serial mode
or the parallel mode (for the HT9200B only).
Serial Mode (HT9200A/B)
The HT9200A/B employ a data input, a 5-bit code, and a
synchronous clock to transmit a DTMF signal. Every
digit of a phone number to be transmitted is selected by
a series of inputs which consist of 5-bit data. Of the 5
bits, the D0(LSB) is the first received bit. The
HT9200A/B will latch data on the falling edge of the
clock (CLK pin). The relationship between the digital
codes and the tone output frequency is shown in Table
1. As for the control timing diagram, refer to Figure 1.
When the system is operating in the serial mode a
pull-high resistor is attached to D0~D3 (for parallel
mode) on the input terminal.
Table 2: Digits vs. Input Data vs. Tone Output Frequency (Parallel Mode)
Digit D3 D2 D1 D0 Tone Output
Frequency (Hz)
10001
697+1209
20010
697+1336
30011
697+1477
40100
770+1209
50101
770+1336
60110
770+1477
70111
852+1209
81000
852+1336
91001
852+1477
01010
941+1336
*1011
941+1209
#1100
941+1477
A1101
697+1633
B1110
770+1633
C1111
852+1633
D0000
941+1633
HT9200A/HT9200B
Rev. 1.40 6 August 30, 2004
For the HT9200B, the S/P pin has to be connected low for
serial mode operation.
Parallel Mode (HT9200B)
The HT9200B provides four data inputs D0~D3 to gener-
ate their corresponding DTMF signals. The S/P has to be
connected high to select the parallel operation mode.
Then the input data codes should be determined. Finally,
the CE is connected low to transmit the DTMF signal from
the DTMF pin.
The TDE time (about 6ms) will be delayed from the CE fall-
ing edge to the DTMF signal output.
The relationship between the digital codes and the tone
output frequency is illustrated in Table 2. As for the control
timing diagram, see Figure 2.
When the system is operating in the parallel mode,
D0~D3 are all in the floating state. Thus, these data in-
put pins should not float.
C E
S / P
X 2
D A T A
C L K
L S B M S B
D T M F
L S B M S B L S B M S B
11111
D i g i t 1 D i g i t 2
D i g i t 1
D T M F s i g n a l
D i g i t 2
D T M F s i g n a l
S t o p c o d e
( O s c i l l a t o r )
tU P
Figure 1
Tone Frequency
Output Frequency (Hz) %Error
Specified Actual
697 699 +0.29%
770 766 –0.52%
852 847 –0.59%
941 948 +0.74%
1209 1215 +0.50%
1336 1332 –0.30%
1477 1472 –0.34%
% Error does not contain the crystal frequency drift
HT9200A/HT9200B
Rev. 1.40 7 August 30, 2004
S / P
C E
tD E
D 0 ~ D 3
D T M F tD E
X 2
( O s c i l l a t o r )
N o t e : T h e d a t a ( D 0 ~ D 3 ) s h o u l d b e r e a d y b e f o r e t h e C E b e c o m e s l o w .
Figure 2
Application Circuits
Serial Mode
Serial/Parallel Mode
HT9200A/HT9200B
Rev. 1.40 8 August 30, 2004
H T 9 2 0 0 B
1 4
1 3
1 2
1 1
1 0
9
8
1
2
3
4
5
6
7
C E
X 2
X 1
V S S
N C
D 0
D 1
V D D
D T M F
D A T A
C L K
S / P
D 3
D 2
3.579545M H z
VD D
C E
D 0
D 1
D 2
D 3
S / P
C L K
D A T A
VD D
T o n e
O u t p u t
V D D
V S S
20pF
20pF
V S S
M C U
H T 9 2 0 0 A
V D D
D T M F
D A T A
C L K
1
2
3
4
8
7
6
5
C E
X 2
X 1
V S S
3.579545M H z
V
D D
T o n e
O u t p u t
V
D D
V D D
V S S
C E
C L K
D A T A
2 0 p F
2 0 p F
M C U
Package Information
8-pin DIP (300mil) Outline Dimensions
Symbol Dimensions in mil
Min. Nom. Max.
A 355 ¾375
B 240 ¾260
C 125 ¾135
D 125 ¾145
E16
¾20
F50
¾70
G¾100 ¾
H 295 ¾315
I 335 ¾375
a0°¾15°
HT9200A/HT9200B
Rev. 1.40 9 August 30, 2004
=
85
4
1
A
B
C
D
E
F
G
H
I
8-pin SOP (150mil) Outline Dimensions
Symbol Dimensions in mil
Min. Nom. Max.
A 228 ¾244
B 149 ¾157
C14
¾20
C¢189 ¾197
D53
¾69
E¾50 ¾
F4
¾10
G22¾28
H4
¾12
a0°¾10°
HT9200A/HT9200B
Rev. 1.40 10 August 30, 2004
D
F
C ' G
H
=
E
8
1
AB
C
4
5
14-pin SOP (150mil) Outline Dimensions
Symbol Dimensions in mil
Min. Nom. Max.
A 228 ¾244
B 149 ¾157
C14
¾20
C¢336 ¾344
D53
¾69
E¾50 ¾
F4
¾10
G22¾28
H4
¾12
a0°¾10°
HT9200A/HT9200B
Rev. 1.40 11 August 30, 2004
1 4
1
8
7
=
AB
C
D
EF
G
H
C '
Product Tape and Reel Specifications
Reel Dimensions
SOP 8N
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
C Spindle Hole Diameter 13.0+0.5
-0.2
D Key Slit Width 2.0±0.15
T1 Space Between Flange 12.8+0.3
-0.2
T2 Reel Thickness 18.2±0.2
SOP 14N
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
C Spindle Hole Diameter 13.0+0.5
-0.2
D Key Slit Width 2.0±0.5
T1 Space Between Flange 16.8+0.3
-0.2
T2 Reel Thickness 22.2±0.2
HT9200A/HT9200B
Rev. 1.40 12 August 30, 2004
AC
B
T 1
T 2 D
Carrier Tape Dimensions
SOP 8N
Symbol Description Dimensions in mm
W Carrier Tape Width 12.0+0.3
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 5.5±0.1
D Perforation Diameter 1.55±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.4±0.1
B0 Cavity Width 5.20±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 9.3
SOP 14N
Symbol Description Dimensions in mm
W Carrier Tape Width 16.0+0.3
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 7.5±0.1
D Perforation Diameter 1.5+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.5±0.1
B0 Cavity Width 9.5±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 13.3
HT9200A/HT9200B
Rev. 1.40 13 August 30, 2004
PD 1
W
P 1P 0
D
E
F
t
K 0
B 0
A 0
C
HT9200A/HT9200B
Rev. 1.40 14 August 30, 2004
Copyright Ó2004 by HOLTEK SEMICONDUCTOR INC.
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sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
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without further modification, nor recommends the use of its products for application that may present a risk to human life
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