5962-8512704XA - INTERSIL - Datasheet.Live

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

A

Add two packages, C-5 and C-4. Make changes to ta ble I, and throughout. For

case X, the dimensions have be en changed and figure 2 has be en repla ce d with

D-10 configura tion. Inactiva te devices 01XX and 02XX for new design. Use

M38510 device . Add a truth table.

90-01-24

M. A. Frye

B

Add device types 05, 06, 07, and 08. Add vendors CAGES 1ES66, OH9K9, a nd

33256. Editorial cha nges throughout.

93-03-15

M. A. Frye

C

Add class V de vice s. Add Z package. Editorial changes thro ughout.

97-04-15

R. Monnin

D

Changes in accordance with NOR 5962-R368-97. – drw

97-06-23

Raymond Mo nnin

E

Change descriptive designator for ca se outline Z from GDFP2-F28 to

CDFP3-F28. Editorial changes throughout. Redrawn. - drw

99-12-30

Raymond Mo nnin

F

Sheet 7, table I, VIL test, change max limit from –0.8 V to 0.8 V. - drw

00-03-01

Raymond Mo nnin

G

Add radiation feature s a nd post irradiation limits. - drw

01-05-16

Raymond Mo nnin

H

Add device type 01 to the post irra diation limits in table I. - drw

02-07-10

Raymond Mo nnin

J

Sheet 6, table I, Integral li nearity error test (ILE), post irradiation limi ts for

device types 01 and 02, subgr oup 1, change fr om -1. 0 LSB m in to

-1.5 LSB min and from 1. 0 LSB max to 1. 5 LSB max.

03-04-25

Raymond Mo nnin

THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED

REV

SHEET

REV H H H H H H

SHEET 15 16 17 18 19 20

REV STATUS REV J H H H H J H H H H H H H H

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A PREPARED BY

Sandra B. Rooney

DEF ENS E SUPP L Y CE NTE R CO L UMBUS

STANDA RD

MICROCIRCUIT

DRAWING

CHECKED BY

Charles E. Be sore

COLUMBUS, OHIO 43216

http://www.dscc.dla.mil

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

APPROVED BY

Michael A. Frye

MICROCIRCUIT , L INE A R, MICRO P RO CESSOR

COMPATIBLE, 12-BIT ANALOG-TO-DIGITAL

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

86-07-10

CONVE RTE RS , MO NOL ITHIC S IL ICO N

AMSC N/A

REVISION LEVEL

J SIZE

A CAGE CODE

67268

5962-85127

SHEET

1 OF

20

DSCC FORM 2233

APR 97 5962-E297-03

DISTRIBUTION STATEMENT A. Approve d for public relea se; distribution is unlimited.

STANDA RD

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DEFENSE SUPPLY CENTER COLUMBUS

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H SHEET 2

DSCC FORM 2234

APR 97

1. SCOPE

1.1 Scope. This dra w ing documents two product assurance class levels cons isting of high re li ability (device classes Q and M)

and space appli cation (device class V). A choice of case outlines and lead finishes are avail able and are reflected in the Part or

Identifying Number (PIN). When avai lable, a choice of Radiation Hardness Assurance (RHA) lev els are reflected in the PIN.

1.2 PIN. The PIN is as shown in the following examples.

For device classes M and Q:

5962 - 85127 01 X X

Federal

stock class

designator

RHA

designator

(see 1.2. 1)

Device

ty pe

(see 1.2. 2)

Case

outline

(see 1.2. 4)

Lead

fini s h

(see 1.2. 5)

\ /

\/

Drawing number

For devi ce class V:

5962 - 85127 01 V X X

Federal

stock class

designator

RHA

designator

(see 1.2. 1)

Device

ty pe

(see 1.2. 2)

Device

class

designator

Case

outline

(see 1.2. 4)

Lead

fini s h

(see 1.2. 5)

\ / (see 1.2.3)

\/

Drawing number

1.2.1 RHA de signator. Device clas ses Q and V RHA mar ked devices me et the MIL-PRF-38535 spe cified RHA levels a nd are

ma rke d with the appropriat e RHA des ignator. Device clas s M RHA marked devices me et the MIL-PRF-38535, appendix A

specified RHA lev e ls and are marked with the appropriate RHA desi gnator. A dash (-) indicates a non- RHA device.

1.2.2 De vice types. The devi ce types i dentify the circuit function as follows:

Device type Generic number Circuit function

01 574AU Monolithic, high per for m ance, 12-bit A/D conver ter with

microprocessor interface

02 574AT Monolithic, m edium per for m ance, 12-bit A/D conver ter with

microprocessor interface

03 574AU Mult i-chip, high pe rf ormance, 12-bit A/D conver te r with

microprocessor interface

04 574AT Mult i-chip, me dium performance, 12-bit A/D conver ter with

microprocessor interface

05 574ZA Monolithic, high per for m ance, low power , 12-bit A/ D converter

with microprocessor interface

06 574ZB Monolithic, m edium per for m ance, low power , 12- bit A/D convert er

with microprocessor interface

07 574AU Monolithic, high per for m ance, low power , 12- bit A/D convert er

with microprocessor interface

08 574AT Monolithic, m edium per for m ance, low power , 12-bit A/ D converter

with microprocessor interface

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DEFENSE SUPPLY CENTER COLUMBUS

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H SHEET 3

DSCC FORM 2234

APR 97

1.2.3 De vice class designator. The devi ce class designator is a singl e let ter identifying the product ass urance level as list ed

below. Since the device clas s designat or has been a dded af ter the or igi nal i ssua nce of this drawing, device class es M and Q

designators will not be included in the PIN and will not be marked on the device.

De vice class Device require m ents documentation

M Vendor se lf-certifica tion to the require m ent s for MIL-STD-883 com pli ant , non- JAN

clas s level B microcircuit s in accordance wit h M IL-PRF- 38535, a ppendix A

Q or V Cert ification and qua li fication to MIL-PRF-38535

1.2.4 Ca se out li nes. The case outlines are as des ignat ed in MI L-STD- 1835 and as follows:

Outline letter Descriptive designator Terminals Package style

X GDIP1-T28 or CDIP2-T28 28 dual-in-line

Y CQCC1- N 44 44 squa re leadles s chip carrier

Z CDFP3-F28 28 flat pack

3 CQCC1-N28 28 square leadless chip car rier

1.2.5 Le ad finish. The lea d finish is a s spe cified in MIL-PRF-38535 for devi ce class es Q and V or M IL-PRF- 38535,

appendix A for device class M .

1.3 Absolute m axi m um ratings. 1/

V

CC to digita l common.......................................................................................................... 0 to +16.5 V dc

V

EE to digita l common .......................................................................................................... 0 to - 16.5 V dc

V

LOG to digita l common ........................................................................................................ 0 to +7 V dc

Analog to digita l common:

Device types 01, 02, 03, 04.............................................................................................. +1 V dc

Device types 05, 06, 07, 08.............................................................................................. -0.5 V dc t o +1 V dc

Contr ol i nputs (CE, CS, AO, 12/8, R/C) to digita l common.................................................. -0.5 V dc to VLOG +0.5 V dc

Analog inputs (REF IN, BIP OFF, 10 VIN) to analog common............................................ VEE to VCC

20 VIN ana log input volt age t o analog common................................................................... +24 V dc

V

REF OUT................................................................................................................................. Indefinite s hort to common,

10 ms short to VCC

Power dis sipation at 75°C:

Device types 01, 02, 05, 06, 07, 08.................................................................................. 1,000 mW 2/

Device types 03, 04 .......................................................................................................... 2,080 m W 2/

Lead temperature (solder ing, 10 se conds).......................................................................... +300°C

Storage temperature............................................................................................................ -65°C to +150°C

Therma l res ist ance, junct ion-t o-ambient (θJA):

Cases X and 3 .................................................................................................................. 70°C/W

Case Y............................................................................................................................... 38°C/W

Case Z............................................................................................................................... 60°C/W

Thermal resistance, junction-to-case (θJC)........................................................................... See MI L-STD-1835

Junction temperature (TJ) .................................................................................................... +175°C

1/ Str esse s above t he absolut e maxim um rating may cause perm anent damage t o the de vice . Exte nded operat ion at the

maximum levels may degrade performance and affect reliability.

2/ For cas es X and 3, derate li nearly a bove TA = +75°C at 20.8 mW/°C.

For cases Y , derate linearly above TA = +75°C at 22.7 mW/°C.

For cases Z, derate li nearly above TA = +115°C at 17 mW/°C.

STANDA RD

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DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OH IO 43216-5000 REVISION LEVEL

H SHEET 4

DSCC FORM 2234

APR 97

1.4 Recomm ended operat ing condi tions.

Power supply

Operating voltage range:

Positive supply (VLOG).................................................................................................... +4.5 V dc to +5.5 V dc

Positive supply (VCC)..................................................................................................... +11.4 V dc to +16.5 V dc

Negative supply (VEE).................................................................................................... -11.4 V dc to -16.5 V dc

Ambient operating temperature range................................................................................. -55°C to +125°C

1.5 Radiation fe atures .

M aximum tota l dose available (dose r at e = 50 – 300 rad(Si)/s).......................................... ≤100 Krads (Si)

2. APPLICABLE DOCUMENTS

2.1 Government specif icat ion, s tandards, a nd handbooks. The f oll owing specifica tion, sta ndards , and ha ndbooks f orm a par t of

this drawing to the extent specifie d herein. Unle s s otherwise specified, the issues of these documents are those li ste d i n the issue

of the Depar tment of De fens e Index of Spe cifications and Standards ( DoDISS) and s upplement thereto, cited in the solicita tion.

SPECIFICATION

DEPARTMENT OF DEFENSE

MIL-PRF-38535 - Inte grat ed Circuits, Manufacturing, Gene ral Specifi cati on for .

STANDARDS

DEPARTMENT OF DEFENSE

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Inte rf ace Standard Electronic Component Case O utlines .

HANDBOOKS

DEPARTMENT OF DEFENSE

MIL-HDBK-103 - List of St andar d Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Unless other wise indicat ed, copie s of the specifica tion, sta ndards, a nd handbooks are a va il able f rom t he Standardization

Docume nt Or der Desk, 700 Robbins Avenue, Buil ding 4D, Philade lphi a, PA 19111-5094. )

2.2 Order of pr ecedence . In the event of a conflict between the text of this drawing and the references cite d herein, the tex t of

this dr awing ta kes precede nce. Nothing in this docume nt, however, super sedes applicable laws and re gulat ions unles s a specif ic

exem ption has been obt ained.

3. REQUIREMENTS

3.1 Ite m requirements. The indi vidual ite m require m ents for device clas ses Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or a s modified in t he device manuf acturer's Q uality Management (QM) plan. The

modifica tion in the QM plan s hall not a ff ect the form, f it, or f unction as descr ibed her ein. The indi vidual ite m require m ents for device

clas s M shall be in accordance with MIL-PRF-38535, a ppendix A for non-JAN class level B devices a nd as specified he rein.

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DEFENSE SUPPLY CENTER COLUMBUS

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H SHEET 5

DSCC FORM 2234

APR 97

3.2 Design, construction, and physical dim ensions. The des ign, construct ion, and physical dimensions s hall be as specifie d in

MIL-PRF-38535 and he rein for device class es Q and V or M IL-PRF- 38535, a ppendix A and her ein for device clas s M.

3.2.1 Ca se out li nes. The case outlines shall be in accor dance with 1.2.4 he rein.

3.2.2 Te rminal connections. The term inal connect ions sha ll be as specif ied on figure 1.

3.2.3 Truth t able. The trut h table sha ll be as specif ied on f igure 2.

3.2.4 Block or logic diagr ams. The block or logic diagra m s shall be as specifie d on figure 3.

3.2.5 Radiat ion exposur e circuit . The r adiat ion exposur e circuit shall be maintained by the m anufacturer under document

revi sion l evel control and sha ll be m ade available to the preparing and acquiring a ctiv ity upon request.

3.3 Elect rical perfor m ance characteris tics and posti rra diat ion para m eter limits . Unless otherwise specified herein, the electrical

perf ormance characteristics a nd postirradiation par ameter limits a re a s specified in t able I and s hall apply over t he f ull a m bient

operat ing te m perature range.

3.4 El ectrical t est re quirements. The elect rical t est require m ents shall be t he subgroups s pecified in table II A. The e lect rical te st s

for e ach subgroup ar e defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked

as liste d in MIL-HDBK-103. For packa ges where marking of the entire SMD PIN number is not f easibl e due to spa ce lim ita tions, the

ma nufacturer has the opt ion of not m arki ng the "5962-" on the de vice. For RHA pr oduct us ing this option, the RHA designat or

shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M

shall be in accor dance with MIL- PRF-38535, appendix A.

3.5.1 Ce rt ifica tion/compliance mark. The ce rt ification mark for device class es Q a nd V shall be a "QML " or "Q" as r equire d in

MIL-PRF-38535. The compliance mar k for device clas s M sha ll be a "C" as required in MIL- PRF-38535, appendix A.

3.6 Cer tifica te of com pli ance. For de vice class es Q a nd V, a ce rt ificate of com plia nce shall be required from a QML-38535 list ed

ma nufacturer in order to supply to t he re quirements of this drawing (s ee 6.6.1 herein). For device class M , a ce rt ificate of

compliance s hall be require d fr om a manufact urer in orde r t o be listed as an approved sour ce of supply in MIL- HDBK-103 ( see

6.6.2 he rein). The ce rt ificate of complia nce submitted t o DSCC-VA pr ior t o li st ing as an a pproved s ource of supply for this dr awing

shall af firm that the manufacturer's product m eets, for devi ce class es Q a nd V, t he re quire m ents of MIL-PRF-38535 and her ein or

for de vice class M , the require m ents of M IL-PRF- 38535, appe ndix A and he rein.

3.7 Cer tifica te of confor m ance. A cer tifica te of confor m ance as require d for devi ce class es Q a nd V in MIL- PRF-38535 or for

device class M in MIL- PRF-38535, appendix A shall be provided wit h each lot of microcir cuits de li vered to this drawing.

3.8 Notifica tion of change for devi ce clas s M. For devi ce class M, not ifica tion to DSCC-VA of change of product (s ee 6.2 her ein)

invol ving de vices acquired to t his dr awing is r equire d for any change as defined in MI L-PRF- 38535, a ppendix A.

3.9 Ver ification and re view f or device class M . For devi ce class M, DSCC, DSCC's agent, and the acquiri ng activ ity reta in the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available

onshore a t t he option of the reviewer.

3.10 Microcircuit group as signment for de vice class M. De vice class M devi ces cover ed by this drawing shall be in microcircuit

group number 81 (se e MIL-PRF- 38535, appe ndix A) .

STANDA RD

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DEFENSE SUPPLY CENTER COLUMBUS

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J SHEET 6

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristi cs.

Test

Symbol

Conditions

-55°C ≤ TA ≤ +125°C

VCC = +15 V, VLOG = +5 V,

VEE = -15 V 1/

Group A

subgroups

Device

ty pe

Limits Unit

unle ss ot herwise specif ied Min Ma x

Power supply curr ent ILOG 1, 2, 3 01, 02,

40 mA

From VLOG 03, 04

M, D, P, L, R 1 01, 02 40

1, 2, 3 05, 06,

07, 08 1

Power supply curr ent ICC 1, 2, 3 01, 02 5 mA

From VCC M, D, P, L, R 1 01, 02 5

1, 2, 3 03, 04 15

05, 06,

07, 08 9

Power supply curr ent IEE 1, 2, 3 01, 02,

-30 mA

03, 04

From VEE M, D, P, L, R 1 01, 02 -30

1, 2, 3 05, 06,

07, 08 0

Resolution 1, 2, 3 Al l 12 Bit s

Integral li nearity error ILE 1 All -0.5 0.5 LSB

2, 3 -1.0 1.0

M, D, P, L, R 1 01, 02 -1.5 1.5

Differential linearity error

(minimum resolution for DLE 1 All 12 Bits

which no miss ing codes

guaranteed) 2/ 2, 3 12

Unipolar offset voltage error VIO TA = +25°C 1 All -2.0 2.0 LSB

M, D, P, L, R 1 01, 02 -3.0 3.0

12 01 -1.0 1.0

Unipolar offset drift ∆VIO Using internal refe rence 1, 2, 3 3/ 01, 02 -1.0 1.0 LSB

2/ ∆T 2, 3 03, 04

05, 06

07, 08

Bipolar offset voltage error BZ TA = +25°C 1 All -4.0 4.0 LSB

M, D, P, L, R 1 01, 02 -5.0 5.0

12 01 -2.0 2.0

Bipola r z e ro offset drift ∆BZ Using inte rnal refe rence 1, 2, 3 3/ 01 -1.0 1.0 LSB

2/ T 2, 3 03,

05, 07

1, 2, 3 3/ 02 -2.0 2.0

2, 3 04,

06, 08

See footnot es at end of table.

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DEFENSE SUPPLY CENTER COLUMBUS

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H SHEET 7

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristi cs – continued.

Test

Symbol

Conditions

-55°C ≤ TA ≤ +125°C

VCC = +15 V, VLOG = +5 V,

VEE = -15 V 1/

Group A

subgroups

Device

ty pe

Limits Unit

unle ss ot herwise specif ied Min Ma x

Gain error ∆AE T

A = +25°C 1 01, 02 0.25 % of

M, D, P, L, R 1 01, 02 0.35 F.S.

With 50Ω resistor from 1 03, 04, 0.30

REF OUT to REF IN 05, 06,

07, 08

12 01 0.125

Gain error drift ∆AE Using i nternal re ference 1, 2, 3 3/ 01 -12.5 12.5

ppm/°C

2/ ∆T 2, 3 03,

05, 07

1, 2, 3 3/ 02 -25.0 25.0

2, 3 04,

06, 08

Power supply sens itivi ty +PSS1 +13.5 V < VCC < +16.5 V 1 All -1.0 1.0 LSB

(Max imum change in TA = +25°C

full scale calibration) +PSS2 +11.4 V < VCC < +12.6 V

2/ TA = +25°C

+PSS3 +4.5 V < VLOG < +5.5 V 1 All -0.5 0.5

TA = +25°C

-PSS1 -16.5 V < VEE < -13.5 V 1 Al l -1.0 1.0

TA = +25°C

-PSS2 -12.6 V < VEE < -11.4 V

TA = +25°C

Input Impedance ZIN 10 V span, TA = +25°C 4 All 3 7

kΩ

2/ 20 V span, TA = +25°C 4 01, 02, 6 14

03, 04

05, 06, 15 25

07, 08

Internal reference voltage VREF TA = +25°C 4/ 1 01, 02 9.98 10.02 V

M, D, P, L, R 1 01, 02 9.95 10. 05

1 03, 04 9.90 10.10

07, 08

05, 06 9.97 10.03

12 01 9.99 10.01

Output cur rent IO Available for e xter nal loads 1 01, 02,

1.5 mA

2/, 5/ TA = +25°C 03, 04

05, 06, 2.0

07, 08

See footnot es at end of table.

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DEFENSE SUPPLY CENTER COLUMBUS

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H SHEET 8

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristi cs – continued.

Test

Symbol

Conditions

-55°C ≤ TA ≤ +125°C

VCC = +15 V, VLOG = +5 V,

VEE = -15 V 1/

Group A

subgroups

Device

ty pe

Limits Unit

unle ss ot herwise specif ied Min Ma x

Input v olta ge ( CE, CS, 12/8, VIH Logi c “1” , TA = +25°C 1 01, 02, 2.0 5.5 V

R/C, AO) 05, 06,

2/, 6/ 07, 08

03, 04 2.4 5.5

VIL Logic “ 0”, TA = +25°C 1 All -0.5 0.8

Input curr ent IIN T

A = +25°C 1 01, 02, -20 +20 µA

2/ 03, 04,

07, 08

05,06 -1 1

Output voltage VOL Logic “ 0”, T A = +25°C, 1 All 0.4 V

(DB11-DB0, STS) 2/ I

SINK = +1. 6 m A

Output voltage VOH Logi c “1” , TA = +25°C, 1 All 2.4 V

(DB11-DB0) 2/ ISOURCE = +500 µA 1

High impedance st ate IZ High-Z state, TA = +25°C, 1 01, 02, -20 +20 µA

output current 2/ DB11 – DB0 only 03, 04,

07, 08

05, 06 -5 +5

Functional tests See 4.4.1b, TA = +25°C 7 All

See figure 4 9, 10, 11 01, 02 250 ns

Low R/C pulse width tHRL 03, 04 350

2/, 7/ 05, 06, 50

07, 08

See figure 4 9, 10, 11 01, 02, 600 ns

STS delay from R/ C tDS 03, 04

2/, 7/ 05, 06, 200

07, 08

See figure 4 9, 10, 11 01, 02, 25 ns

Data v a lid after R/C low tHDR 05, 06,

2/, 7/ 07, 08

03, 04 15

See figure 4 9, 10, 11 01, 02, 300 1000 ns

STS dela y after va lid data tHS 05, 06,

2/,7/ 07, 08

03, 04 300 1200

See figure 4 9, 10, 11 01, 02, 300 ns

High R/C pulse width tHRH 03, 04

2/, 8/ 05, 06, 150

07, 08

See footnot es at end of table.

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DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristi cs – continued.

Test

Symbol

Conditions

-55°C ≤ TA ≤ +125°C

VCC = +15 V, VLOG = +5 V,

VEE = -15 V 1/

Group A

subgroups

Device

ty pe

Limits Unit

unle ss ot herwise specif ied Min Max

Data access time tDDR See figure 4 9, 10, 11 01, 02, 250 ns

2/,8/ 03, 04

05, 06, 150

07, 08

STS delay from CE tDSC See figure 4 9, 10, 11 01, 02, 350 ns

2/, 8/ 03, 04

05, 06, 200

07, 08

CE puls e widt h tHEC See f igure 5 9, 10, 11 01, 02, 300 ns

2/, 8/ 03, 04

05, 06, 50

07, 08

Conversion time tC 8-bit cycle 9, 10, 11 01,02 5/ 10 24 µs

2/, 9/ See figure 5 03, 04, 10 17

05, 06,

07, 08

12-bit cycle 9, 10, 11 01,02 5/ 15 35

See figure 5 03, 04, 15 25

05, 06,

07, 08

Access time (from CE) tDD See figure 6 9, 10, 11 01, 02 200 ns

2/, 7/ 03, 04 250

05, 06, 150

07, 08

Data v a lid after CE low tHD See f igure 6 9, 10, 11 01, 02, 25 ns

2/, 7/ 05, 06,

07, 08

03, 04 15

Output f loat delay tHL See figure 6 9, 10, 11 01, 02 100 ns

2/, 7/ 03, 04, 150

05, 06,

07, 08

1/ Devi ces s uppli ed to this drawing have be en char act erize d thr ough all levels M, D, P, L, a nd R of irradiation. Howe ver, this device

is only tested at the “R” level. Pre and post irradiation v alues are identical unless otherwise specified in table I. When performing

post irradiation electrical measurements for any RHA lev el, TA = +25°C.

2/ This parameter is not tested post i rra di a tion.

3/ Guarante ed to the limits specif ied, if not tes ted for subgroup 1.

4/ The reference voltage external load current shall be a constant dc and shall not exceed 1.5 mA.

5/ Ref erence should be buffe red for oper at ion on +12 V supplies. External load s hould not change during conv er sion.

6/ For de vices 01 and 02, 12/8 is not TTL com patible and must be hard wire d to VLOG or digi tal ground.

7/ Subgroups 10 and 11, if not t ested, shall be guarant eed to the specifie d limits.

8/ Parameters tHRH, tDDR, tDSC, and t HEC, if not tested, shall be guaranteed to the specified limits .

9/ For de vices 03 and 04, time m easured from 50 per cent level of digital transit ions, tes te d with 50 pF and 3.0 kΩ load.

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Device types All 01, 02 01, 02, 05, 06, 07, 08 03, 04

Case out lines X Z 3 Y

Terminal number Terminal symbol Terminal symbol

1 VLOG V

LOG

2 12/8 12/8

3 CS CS

4 AO AO

5 R/C NC

6 CE NC

7 VCC NC

8 REF OUT NC

9 AGND R/C

10 REF IN CE

11 VEE V

CC

12 BIP OFF REF OUT

13 10 VIN AGND

14 20 VIN REF IN

15 DGND VEE

16 DB0 NC

17 DB1 BIP OFF

18 DB2 10 VIN

19 DB3 20 VIN

20 DB4 NC

21 DB5 NC

22 DB6 NC

23 DB7 NC

24 DB8 DGND

25 DB9 NC

26 DB10 NC

27 DB11 (MSB) DB0

28 STS DB1

29 DB2

30 NC

31 DB3

32 DB4

33 DB5

34 DB6

35 DB7

36 DB8

37 DB9

38 NC

39 NC

40 NC

41 NC

42 DB10

43 DB11 (MSB)

44

STS

FIGURE 1. Te rminal connections.

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CE

CS

R/C

12/8

AO Operation

0

X

None

X

1

X

None

1 0 0 X 0 Initiate 12-bit conversion

1 0 0 X 1 Initiate 8-bit conversion

1

0

1

X

Enable 12-bit pa rallel output

1 0 1 0 0 Enable 8 most significant bits

1

0

1

0

1

Enable 4 LSBs + 4 trailing zer os

FIGURE 2. Truth table.

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Device types 01, 02, 03, and 04

NOTE: For device types 03 and 04, the r esistor value is 9.95 kΩ.

FIGURE 3. Block diagram.

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Device types 05, 06, 07, and 08

FIGURE 3. Block diagram - cont inued.

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B

O

FIGURE 4. High/low pulse for R/C outputs.

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FIGURE 5. Conv e rt s ta rt dia gram.

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FIGURE 6. Read cycle timing.

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4. QUALI TY ASSURANCE PROVISIONS

4.1 Sampli ng and inspe ction. For device class es Q and V, sampling and inspection procedures shall be in accordance wit h M IL-

PRF-38535 or a s modified in the devi ce manuf act urer ' s Quality Manage m ent (Q M ) plan. The modification i n the QM plan s hall not

aff ect the f orm, fit, or f unction as descr ibed her ein. For device class M , sa m pli ng and inspection procedur es sha ll be in accordance

wit h MIL-PRF- 38535, appe ndix A.

4.2 Scre ening. For device clas ses Q and V, s cre ening shall be in accordance with MIL-PRF-38535, and s hall be conducted on

all de vices prior to qualification and te chnology conf ormance inspe ction. For devi ce class M , screening sha ll be in accorda n ce wi th

me thod 5004 of M IL-STD- 883, and s hall be conducted on all devices pr ior t o quality conform ance inspe ction.

4.2.1 Additiona l criteria for devi ce clas s M.

a. Bur n-in test , met hod 1015 of MIL-STD-883.

(1) Test condi tion A, B, C or D. The t est circuit shall be maintained by the m anuf acturer under document r evi sion level

control and shall be made a vaila ble to the prepar ing or acquiring a ctivity upon re quest. The tes t circuit shall spe cify

the inputs, out puts , bias es, and power dissipat ion, as applicable, in accor dance wit h the inte nt spe cified in test

me thod 1015.

(2) TA = +125°C, minimum.

b. I nterim and final e lectrical test parameters shall be as s pecified in table IIA herein.

c. Optional subgroup 12, f or device 01, is used f or gr ading the part se lection at 25°C.

4.2.2 Additiona l criteria for devi ce clas ses Q and V.

a. The bur n-in test durat ion, test condition and t est temperature, or approved alte rnatives shall be as s pecified in the devi ce

ma nufacturer's Q M plan in accordance wit h M IL-PRF- 38535. The burn-in test circuit shall be mainta ined under docum ent

revi sion level control of the device manuf acture r's Technology Revi ew Boar d (TRB) in accorda nce wit h

MIL-PRF- 38535 and shall be m ade available to the acquiring or preparing act ivity upon r equest. The te st circuit shall

specif y the inputs, out puts , bias es, and power dissipat ion, as applicable, in accor dance wit h the inte nt spe cified in test

me thod 1015 of M IL-STD-883.

b. I nterim and final e lectrical test parameters shall be as s pecified in table IIA herein.

c. Additional screening f or devi ce clas s V beyond the re quirement s of dev ice clas s Q shall be as s pecified in

MIL-PRF- 38535, appe ndix B.

4.3 Qualificat ion i nspection for device class es Q a nd V . Qualifica tion inspection for devi ce class es Q a nd V shall be in

accordance with MIL-PRF-38535. Inspe ctions t o be per for m ed sha ll be thos e specified in MIL-PRF-38535 and herein for groups

A, B, C, D, a nd E inspections ( see 4.4. 1 through 4.4. 4).

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TABLE IIA. Electri cal te s t re quirements.

Test require m ents

Subgroups

(in accorda nce with

MIL-STD-883,

me thod 5005, table I)

Subgroups

(in accorda nce with

MIL-PRF-38535, table III)

Device

class M Device

class Q Device

class V

Interim electrical

parameters (see 4.2) 1 1 1

Final el ectrical

parameters (see 4.2)

1/

1, 2, 3, 4, 12 1/

1, 2, 3, 4, 12 1/, 2/

1, 2, 3, 4, 12

Group A test

requirem ents (s ee 4.4)

1, 2, 3, 4, 7, 9,

10, 11, 12 1, 2, 3, 4, 7, 9,

10, 11, 12

Group C end-point electrical

parameters (see 4.4) 1, 4 1, 4 2/

1, 4

Group D end-point electrical

parameters (see 4.4) 1, 4 1, 4 1, 4

Group E end-point electrical

parameters (see 4.4) - - - - - - 1

1/ PDA appli es to subgroup 1.

2/ Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be computed

with reference to the prev ious interim electrical parameters.

TABLE IIB. 240 hour burn- in and gr oup C end-point e lect rical parameters.

Endpoint li m its

Test title Min Max

Delta limits Units

Uni Vio -1 2 +0.5 LSB

Bpze -5.5 4.5 +1 LSB

Ae -0.35 0.35 +.10 %FSR

4.4 Conform ance inspe ction. Technology conformance inspe ction for classe s Q and V shall be in accordance with

MIL-PRF-38535 including groups A, B, C, D, and E inspections and a s spe cified. Quality conformance inspection for device clas s

M s hall be in accordance with MIL- PRF-38535, appendix A and as specif ied herein. Inspections to be per for m ed f or device class M

shall be those s pecif ied in met hod 5005 of MIL-STD-883 and her ein for groups A, B, C, D, and E inspe ctions (se e 4.4.1 t hrough

4.4.4).

4.4.1 Gr oup A inspection.

a. Tests shall be as specified in table IIA herein.

b. For device class M , subgroups 7 te sts shall be suf ficient to ver ify the tr uth t able. For device class es Q and V, subgroups 7

shall i nclude verifying the funct ionali ty of the device.

c. Subgroups 5, 6, and 8 in ta ble I, me thod 5005 of M IL-STD- 883 shall be omitted.

d. Optional subgroup 12, f or device type 01, is used for gr ading the part se lection at 25°C.

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4.4.2 Gr oup C inspection. The group C inspection end-point e lect rical par ameters shall be as specifie d in ta ble II A herein.

4.4.2.1 Additional criteria for device class M . St eady-state life te st condi tions, m et hod 1005 of MIL-STD-883:

a. Test condition A, B, C or D. The test circuit sha ll be maint ained by the m anuf acturer under document r evi sion level control

and shall be made available to the preparing or acquir ing activi ty upon re quest. The tes t circuit shall specify the inputs ,

outputs , biases, and power dissipat ion, a s applicable, in accorda nce with the inte nt s pecified in test m ethod 1005 of MIL-

STD-883.

b. TA = +125°C, minimum.

c. Test duration: 1, 000 hours, except a s per m itted by m ethod 1005 of MIL-STD-883.

4.4.2. 2 Additional cr iter ia f or device class es Q a nd V . The s tea dy-st ate li fe test dura tion, test condition and test te m peratur e, or

approved alterna tiv es s hall be as specifie d in the device manufacturer's QM plan in accor dance with MIL- PRF-38535. The test

cir cuit s hall be maintained under docum ent revision level control by t he devi ce manufa ctur er's TRB in accordance with

MIL-PRF-38535 and s hall be made a vaila ble t o the a cquiring or preparing act ivity upon re quest. The test circuit shall specify the

input s, output s, bi ases, and power dissipation, a s applicable, in accorda nce with the int ent specified in t est method 1005 of MIL-

STD-883.

4.4.3 Gr oup D inspection. The group D inspe ction end-point e lect rical par amet ers shall be as specified in table IIA here in.

4.4.4 Gr oup E inspection. Gr oup E inspection i s require d only f or parts intende d to be mar ked as radiation har dness assured

(see 3.5 her ein).

a. End- point elect rical parameters shall be as specifi ed in ta ble II A herein.

b. For device class es Q a nd V, t he devi ces or tes t vehicle shall be subjecte d to r adiat ion hardne ss assured t ests as specifie d

in MIL-PRF-38535 for the RHA level being t ested. For device class M, t he devices s hall be subject ed to radiation

hardnes s ass ure d tes ts a s spe cified in MI L-PRF- 38535, a ppendix A for the RHA level being test ed. All device clas ses

mus t meet the pos tirradiation end-point e lect rical par ameter limits as de fined in t able I at

T

A = +25°C ±5°C, after exposur e, to t he subgr oups spe cified in t able IIA here in.

c. Whe n specifie d in the purchase order or cont ract, a copy of the RHA delta li m its shall be s uppli ed.

5. PACKAGING

5.1 Packaging require m ents. The requirements for packaging sha ll be in accorda nce with MIL-PRF-38535 for devi ce class es Q

and V or MIL-PRF-38535, appe ndix A f or device clas s M.

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6. NOTES

6.1 Inte nded use. Microcircuits conforming to this dra w ing are intende d for use f or Government m icrocircuit applications (or igina l

equipment) , des ign applications , and logistics pur poses.

6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-

prepared specification or drawing.

6.2 Configura tion control of SMD's. All propose d changes to exist ing SMD's will be coordinated with the users of record for the

individual documents. This coordination will be accomplished using DD Form 1692, Engi neering Change Proposal.

6.3 Recor d of us ers. Military and industr ial users s hould i nfor m Defense Supply Cent er Columbus when a syste m application

requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will

be used for coor dinat ion and dist ribution of changes to t he drawings. Users of drawings covering micr oelect ronic devices (F SC

5962) should contact DSCC-VA, t elephone (614) 692-0544.

6.4 Comm ents . Comment s on thi s drawing should be dir ected to DSCC-VA, Columbus, O hio 43216-5000, or t elephone (614)

692-0547.

6.5 Abbre viations, sym bols, and defini tions. The abbr evi ations , symbol s, and defini tions used herein are defined in

MIL-PRF-38535 and MIL-HDBK-1331.

V

LOG Logic supply

12/8 Data mode select input

CS Chip select input

A0 Byte address/short cycle input

R/C Read/convert input

CE Chip enable input

V

CC Pos itive power supply

REF OUT Reference output

AGND Analog ground

REF IN Reference input

V

EE Negative power s upply

BIP OFF Bipolar offset input

V

IN Span input

DGND Digital ground

D0-D11 Tree-state data outputs

STS Status output

NC No connection

6.6 Source s of supply.

6.6.1 Sources of supply for device class es Q and V. Sources of supply for devi ce class es Q a nd V are li sted in QML-38535.

The vendors listed in QM L-38535 have subm itt ed a certifica te of com pli ance ( see 3.6 herein) to DSCC-VA and ha ve agre ed t o this

drawing.

6.6.2 Approve d sour ces of supply for device class M . Appr oved sour ces of supply for class M are li st ed in MIL-HDBK- 103. The

vendors list ed in MIL-HDBK- 103 have agr eed to this dr awing and a ce rt ificate of com pli ance (see 3.6 her ein) has been submitt ed to

and accepted by DSCC-VA.

STANDARD MICROCIRCUIT DRAWING BULLETIN

DATE: 03-04-25

Approved sour ces of supply for SMD 5962-85127 ar e liste d below for immediate acquisit ion informat ion onl y and shall

be added to MIL-HDBK- 103 and QM L-38535 dur ing the next revision. MIL-HDBK-103 and QML-38535 will be revised

to incl ude the addition or de let ion of sources. The vendor s listed below have agreed to this drawing and a ce rt ificate of

compliance ha s been s ubmitt ed t o and acce pte d by DSCC-VA. This bullet in i s superseded by the next da ted r evi sion of

MIL-HDBK-103 and QML-38535.

Standard

microcir cuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-85127013A 24355 AD574AUE/883B

5962-8512701XA 24355 AD574AUD/883B

5962-8512701XC 1ES66 MX574AUD/883B

5962-8512701VXA 24355 AD574AUD/QMLV

5962-8512701VZA 24355 AD574AUF/QMLV

5962R8512701VXA 24355 AD574AUD/QMLR

5962R8512701VZA 24355 AD574AUF/QMLR

5962-85127023A 24355 AD574ATE/883B

5962-85127023C 1ES66 MX574ATE/883B

24355 AD574ATD/883B

5962-8512702XA 1ES66 MX574ATQ/883B

5962-8512702XC 1ES66 MX574ATD/883B

5962-8512702VXA 24355 AD574ATD/QMLV

5962-8512702VZA 24355 AD574ATF/QMLV

5962R8512702VXA 24355 AD574ATD/QMLR

5962R8512702VZA 24355 AD574ATF/QMLR

5962-8512703XA 34371 HI1-574AUD/883

5962-8512703YA 3/ HI4-574AUE/883

5962-8512704XA 34371 HI1-574ATD/883

5962-8512704YA 3/ HI4-574ATE/883

5962-85127053A 3/ HADC574ZAMC/883

5962-8512705XC 3/ HADC574ZAMJ/883

5962-85127063A 3/ HADC574ZBMC/883

5962-8512706XC 3/ HADC574ZBMJ/883

5962-85127073C 3/ HS574AU/B-LCC

5962-8512707XC 3/ HS574AU/B

5962-85127083C 3/ HS574AT/B-LCC

5962-8512708XC 3/ HS574AT/B

1/ The lea d finish shown for e ach PIN r epresenting

a hermetic package is the most readil y available

from the manufacturer l isted for that part. If the

desire d lead f ini sh is not li ste d contact the vendor

to determine its availability.

2/ Caution. Do not use this number for item

acquisition. Items a cquire d to t his number may not

satis fy the performance r equire m ent s of this drawing.

3/ Not avail able f rom an appr oved source .

Sheet 1 of 2

STANDARD MICROCIRCUIT DRAWING BULLETIN - continued

Vendor CAGE Vendor name

numbe r and address

24355 Analog Devices Incorporated

Route 1 Industrial Park

PO Box 9106

Norwood, MA 02062-9106

Point of contact:

1500 Space Park Driv e

PO Box 58020

Sant a Clara, CA 95050-8020

1ES66 Ma xim Integrated Products

120 San G abriel Dri ve

Sunnyvale, CA 94086-5126

34371 Intersil Corporation

2401 Palm Bay Bl vd

PO Box 883

Me lbourne, FL 32902-0883

The infor m ation contained herein is disseminated for conve nience only and the

Government assumes no liability whatsoever for any inaccuracies in the

inf ormat ion bul letin.