ISL54505 - Intersil Corporation

FN6552.1

ISL54504, ISL54505

+1.8V to +5.5V, 2.5

, Single SPST Analog

Switches

The Intersil ISL54504 and ISL5450 5 devices are low

ON-resistance, low voltage, bidirectional, single pole/single

throw (SPST) analog switches designed to opera te from a

single +1.8V to +5.5V supply. Targeted applications include

battery powered equipment that benefit from low rON

resistance (2.5Ω), excel l e nt rON flatness (0.6Ω), and fast

switching speeds (tON = 25ns, tOFF = 15ns). The digital logic

input is 1.8V CMOS compatible when using a single +3V

supply.

Cell phones, for example, often face ASIC functi onality

limitations. The number of analog input or GPIO pins may be

limited and digital geometries are not well suited to anal og

switch performance. This family of parts may be used to

switch in additional functionality while reducing ASIC design

risk. The ISL54054, ISL54055 are offered in a 6 Ld

1.2mmx1.0mmx0.4mm pitch µTDFN package, alleviating

board space limitations.

The ISL54504 has one norma lly open (NO) switch and

ISL54505 has one normally closed (NC) switch.

Features

• ON-resistance (rON)

-V

CC = +5.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5Ω

-V

CC = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0Ω

-V

CC = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0Ω

•r

ON flatness (+4.5V Supply). . . . . . . . . . . . . . . . . . . . . . 0.6Ω

• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V

• Fast switching action (+4.5V Supply)

-t

ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns

-t

OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns

• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV

• 1.8V CMOS logic compatible (+3V supply)

• Available in 6 Ld µTDFN Package

• Pb-free available (RoHS compliant)

Applications

• Battery powered, handheld, and portable equipment

- Cellular/mobile phones

- Pagers

- Laptops, notebooks, palmtops

• Portable Test and Measurement

• Medical Equipment

• Audio and video switching

Related Literature

• Techn ical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mo unt Devices

(SMDs)”

TABLE 1. FEATURES AT A GLANCE

ISL54504 ISL54505

Number of Switches 11

SW NO NC

1.8V rON 6Ω6Ω

1.8V tON/tOFF 65ns/40ns 65ns/40ns

3V rON 4Ω4Ω

3V tON/tOFF 30ns/20ns 30ns/20ns

5V rON 2.5Ω2.5Ω

5V tON/tOFF 25ns/15ns 25ns/15ns

Package 6 Ld µTDFN

Data Sheet August 29, 2007

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN6552.1

August 29, 2007

Ordering Information

PART NUMBER

(Note) PART

MARKING TEMP. RANGE

(°C) PACKAGE

(Pb-Free) PKG. DWG. #

ISL54504IRUZ-T* 4 -40 to +85 6 Ld μTDFN (Tape and Reel) L6.1.2x1.0A

ISL54505IRUZ-T* 5 -40 to +85 6 Ld μTDFN (Tape and Reel) L6.1.2x1.0A

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and

NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinouts (Note 1)

ISL54504

(6 LD μTDFN)

TOP VIEW

ISL54505

(6 LD μTDFN)

TOP VIEW

NOTE:

1. Switches Shown for Logic “0” Input.

V+

GND

N.C. COM 3

V+

GND

N.C.

COM

T ruth Table

LOGIC ISL54504 ISL54505

0OffOn

1OnOff

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

Pin Descriptions

NAME FUNCTION

V+ System Power Supply Input (+1.8V to +5.5V)

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

N.C. No Connect

ISL54504, ISL54505

3FN6552.1

August 29, 2007

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V

Input Voltages

NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Output Voltages

COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . ± 600mA

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . .>1400V

Thermal Resistance (Typical, Notes 3, 4) θJA (°C/W) θJC (°C/W)

6 Ld µTDFN Package . . . . . . . . . . . . . 239.2 111.6

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperatur e Range. . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

V+ (Positive DC Supply Voltage). . . . . . . . . . . . . . . . . 1.8V to 5.5V

Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+

VIN (Digital Logic Input Voltage (IN) . . . . . . . . . . . . . . . . . 0V to V+

Temperature Range

ISL54504IRUZ, ISL54505IRUZ . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and

result in failures not covered by warranty.

NOTES:

2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 5),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 6, 7) TYP MAX

(Notes 6, 7) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON-Resistance, rON V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,

(Note 9, See Figure 4) 25 - 2.2 2.5 Ω

Full - - 3 Ω

rON Flatness, rFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,

(Notes 8, 9) 25 - 0.6 0.65 Ω

Full - - 0.7 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V 25 -25 1.5 25 nA

Full -150 - 150 nA

COM ON Leakage Current,

ICOM(ON) V+ = 5.5V , VCOM = 0.3V , 5V, or VNO or VNC = 0.3V , 5V,

or Floating 25 -30 2.8 30 nA

Full -300 - 300 nA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF

(See Figure 1, Note 9) 25 - 25 - ns

Full - 25 - ns

Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF

(See Figure 1, Note 9) 25 - 15 - ns

Full - 16 - ns

Break-Before-Make Ti me Delay , tDV+ = 5.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF

(See Figure 3, Note 9) Full - 15 - ns

Charge Injection, Q VG = 0V, RG = 0Ω, CL = 1.0nF (See Figure 2) 25 - 24 - pC

OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VP-P

(See Figure 3) 25 - 70 - dB

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω25 - 0.15 - %

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω25 - 0.014 - %

-3dB Bandwidth Signal = 0dBm, RL = 50Ω25 - 250 - MHz

NO or NC OFF Capacitance,

COFF V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V

(See Figure 5) 25 - 7 - pF

COM ON Capacitance,

CCOM(ON) V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V

(See Figure 5) 25 - 18 - pF

ISL54504, ISL54505

4FN6552.1

August 29, 2007

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.8 - 5.5 V

Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ 25 - 0.028 0.1 μA

Full - 1.1 2.5 μA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full - - 0.8 V

Input Voltage High, VINH Full 2.4 - - V

Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full -0.1 0.053 0.1 μA

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 5),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 6, 7) TYP MAX

(Notes 6, 7) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,

(Note 9, See Figure 4) 25 - 3.3 3.5 Ω

Full - - 4.5 Ω

rON Flatness, rFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,

(Notes 7, 9) 25 - 1 1.1 Ω

Full - - 1.2 Ω

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF

(See Figure 1, Note 9) 25 - 30 - ns

Full - 30 - ns

Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF

(See Figure 1, Note 9) 25 - 20 - ns

Full - 20 - ns

Charge Injection, Q VG = 0V, RG = 0Ω,CL = 1.0nF (See Figure 2) 25 - 16 - pC

OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VP-P

(See Figure 3) 25 - -70 - dB

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω25 - 0.36 - %

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω25 - 0.03 - %

-3dB Bandwidth Signal = 0dBm, RL = 50Ω25 - 250 - MHz

NO or NC OFF Capacitance,

COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) 25 - 6 - pF

COM OFF Capacitance,

CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) 25 - 15 - pF

COM ON Capacitance,

CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5) 25 - 18 - pF

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ 25 - 0.013 - μA

Full - 0.7 - μA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full - - 0.5 V

Input Voltage High, VINH Full 1.4 - - V

Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full -0.1 0.058 0.1 μA

Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 5),

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 6, 7) TYP MAX

(Notes 6, 7) UNITS

ISL54504, ISL54505

5FN6552.1

August 29, 2007

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 5),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 6, 7) TYP MAX

(Notes 6, 7) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON-Resistance, rON V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+

(Note 9, See Figure 4) 25 - 6 6.5 Ω

Full - - 7 Ω

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF

(See Figure 1, Note 9) 25 - 65 - ns

Full - 95 - ns

Turn-OFF Time, tOFF V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF

(See Figure 1, Note 9) 25 - 40 - ns

Full - 65 - ns

Charge Injection, Q VG = V+/2, RG = 0Ω, CL = 1.0nF (See Figure 2) 25 - 8.2 - pC

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full - - 0.4 V

Input Voltage High, VINH Full 1 - - V

NOTES:

5. VIN = input voltage to perform proper function.

6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

9. Limits established by characterization and are not production tested.

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

50%

tr < 20ns

tf < 20ns

tOFF

90%

V+

VNO

tON

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

VOUT

VOUT V(NO or NC) RL

RLrON()

----------------------------

SWITCH

INPUT

LOGIC

INPUT

VOUT

RL CL

COM

NO OR NC

50Ω35pF

GND

V+ C

ISL54504, ISL54505

6FN6552.1

August 29, 2007

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3. OFF ISOLATION TEST CIRCUIT FIGURE 4. rON TEST CIRCUIT

FIGURE 5. CAPACITANCE TEST CIRCUIT

Test Circuits and Waveforms (Continued)

VOUT

ΔVOUT

ON OFF ON

Q = ΔVOUT x CL

SWITCH

OUTPUT

LOGIC

INPUT

VINH

VINL CL

VOUT

VGGND

COM

NO OR NC

V+ C

LOGIC

INPUT

ANALYZER

SIGNAL

GENERATOR

V+ C

0V OR V+

NO OR NC

COM

GND

V+

VINL OR VINH

NO OR NC

COM

GND

VNX

100mA

rON = V1/I1 *

* I1 = 10mA AT V+ = 1.8V

V+ C

GND

NO OR NC

COM

IMPEDANCE

ANALYZER

VINL OR VINH

ISL54504, ISL54505

7FN6552.1

August 29, 2007

Detailed Description

The ISL54504 and ISL54505 are bi directional, single

pole/single throw (SPST) analog switches. They offer

precise switching capability from a single 1.8V to 5.5V

supply with low ON-resistance (2.5Ω) and high speed

operation (tON = 25ns, tOFF = 15ns). The de vice s are

especially well suited for portable battery powered

equipment due to their low operating supply voltage (1.8V),

low power consumption (0.15µW), low lea kage current s

(300nA max) and tiny µTDFN package.

The ISL54504 is a single normally open (NO) SPST analog

switch. The ISL54505 is a single normally closed (NC) SPST

analog switch.

External V+ Series Resistor

For improved ESD and latch-up immunity, Intersil

recommends adding a 100Ω resistor in series with the V+

power supply pin of the ISL54050 IC (see Figure 6).

During an overvoltage transient event (such as occurs

during system level IEC 61000 ESD testing), substrate

currents can be generated in the IC that can trigger parasitic

SCR structures to turn ON, creating a low impedance path

from the V+ power supply to ground. This will result in a

significant amount of current flow in the IC, which can

potentially create a latch-up state or permanently damage

the IC. The external V+ resistor limits the current during this

over-stress situation and has been found to prevent latch-up

or destructive damage for many overvoltage transient

events.

Under normal operation the sub-microamp IDD current of the

IC produces an insignificant voltage drop across the 100Ω

series resistor resulting in no impact to switch operation or

performance.

Supply Sequencing And Over voltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents,

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 7). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

If these conditions cannot be guaranteed then pre ca utions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provide additional protection to limi t the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 7). The resistor

limits the input current below the threshold that produces

permanent damage and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

purpose of using a low rON switch. Connecting Schottky

diodes to the signal pins (as shown in Figure 7) will shunt the

fault current to the supply or to ground, thereby protecting

the switch. These Schottky diodes must be sized to handle

the expected fault current.

Power-Supply Considerations

The ISL54504/ISL54505 constructi on is typical of most

single supply CMOS analog switches in that they have two

supply pins: V+ and GND. V+ and GND drive the internal

CMOS switches and set their analog voltage limits. Unlike

switches with a 4V maximum supply voltage, the

ISL54504/ISL54505 5.5V maximum supply voltage provides

plenty of room for the 10% tolerance of 3.6V supplies, as

well as room for overshoot and noise spikes.

FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED ESD AND

LATCH-UP IMMUNITY

COM

100Ω

V+

GND

OPTIONAL

PROTECTION

RESISTOR

FIGURE 7. OVERVOLTAGE PROTECTION

GND

VCOM

VNX

V+

INX

OPTIONAL

PROTECTION

RESISTOR

OPTIONAL

SCHOTTKY

DIODE

OPTIONAL

SCHOTTKY

DIODE

ISL54504, ISL54505

8FN6552.1

August 29, 2007

The minimum recommende d supply voltage is 1.8V but the

part will operate with a supply below 1.8V. It is important to

note that the input signal range, switching times, and

ON-resistance degrade at lower supply voltages. Refer to

the “Electrical Specifications” tables starting on page 3 and

the “Typical Performance Curves” starting on page 8 for

details.

V+ and GND also power the internal logic and level shiftier.

The level shiftier converts the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies because the input switchin g point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)

over a supply range of 2V to 3.6V (see Figure 14). At 3.6V

the VIH level is abou t 0.95V. This is still below the 1.8V

CMOS guaranteed high output minimum level of 1.4V, but

noise margin is reduced.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes pow er di ssi pation.

High-Frequency Performance

In 50Ω systems, the ISL54504/ISL54505 has a -3dB

bandwidth of 250MHz (see Figure 15). The frequency

response is very consistent over a wide V+ range and for

varying analog signal levels.

An OFF switch behaves like a capacitor and passes higher

frequencies with less attenuatio n, resulting in signal

feedthrough from a switch’s input to output. Off isolation is

the resistance of this signal feedthrough. Figure 16 d etails

the high off isolation provided by the ISL54504/ISL54505. At

1MHz, off isolation is about 70dB in 50Ω systems,

decreasing approximately 20dB per decade as frequency

increases. Higher load impedances decrease off isolation

due to the voltage divider action of the switch OFF

impedance and the load imp edance.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND. One of

these diodes conducts if any analog signal exceeds V+ or

GND.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biase d by eith er

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes th e analog-

signal-path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and V+ or GND.

Typical Performance Curves TA = +25°C, Unless Otherwise Specified.

FIGURE 8. ON-RESISTANCE vs SUPPL Y VOL TAGE vs

SWITCH VOLTAGE FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE

rON (Ω)

VCOM (V)

012345

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

ICOM = 100mA

V+ = 2.7V

V+ = 3V

V+ = 4.5V

V+ = 5V

(Ω)

VCOM (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

V+ = 4.5V

ICOM = 100mA

+25°C

+85°C

-40°C

ISL54504, ISL54505

9FN6552.1

August 29, 2007

FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 11. O N-RESISTANCE vs SWITCH VOLTAGE

FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE

FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FIGURE 15. FREQUENCY RESPONSE

Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)

rON (Ω)

COM

(V)

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 0.5 1.0 1.5 2.0 2.5

V+ = 2.7V

COM

= 100mA

+25°C

+85°C

-40°C

rON (Ω)

VCOM (V)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

V+ = 1.8V

ICOM = 10mA

+25°C

+85°C

-40°C

tON (ns)

V+ (V)

100

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

+25°C

+85°C

-40°C

tOFF (ns)

V+ (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

+25°C

+85°C

-40°C

V+ (V)

VINH AND VINL (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VINH

VINL

FREQUENCY (Hz)

NOR M A L IZED GAIN (dB)

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

100k 1M 10M 100M 1G

COM

= 1V

P-P

V+ = 1.8V TO 5.5V

ISL54504, ISL54505

10 FN6552.1

August 29, 2007

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

PROCESS:

Submicron CMOS

FIGURE 16. OFF ISOLATION FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE

Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)

FREQUENCY (Hz)

(dB)

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

1k 10k 100k 1M 10M 100M 1G

V+ = 1.8V TO 5.5V

Q (pC)

VCOM (V)

-20

-15

-10

-5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

V+ = 5V

V+ = 3.3V

V+ = 1.8V

ISL54504, ISL54505

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6552.1

August 29, 2007

ISL54504, ISL54505

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

0.10 C

PIN 1

TOP VI EW

0.10 C

REFERENCE

DETAIL A

0.10 C

0.08 C

A3A1

SEATING

PLANE

BOTTOM VIEW

SIDE VIEW

0.10 CAB

0.05 C

b6X

NOTE 3

DETAIL A DETAIL B PIN 1 LEAD

0.1x45°

CHAMFER

DETAIL B

1.40

LAND PATTERN

1.00

0.30

0.35

0.20

0.45

0.40

0.20

L6.1.2x1.0A

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

0.45 0.50 0.55

- - 0.05

0.127 REF

0.15 0.20 0.25

0.95 1.00 1.05

1.15 1.20 1.25

0.40 BSC

0.30 0.35 0.40

0.40 0.45 0.50

0-12

Rev. 2 8/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Ne refers to the number of terminals on E side.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located wi thin the zone indicated. The pin #1 identif ier may be

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.