Exar Corporation 48720 Kato Road, Fremont CA, 94538 • ( 510) 668-7000 • FAX (510) 668-7017 • www.exar .co m
XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDW ARE DESCRIPTION
JANUARY 2007 REV. V1.2.0
GENERAL DESCRIPTION
The XRT86VL32 is a two-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless,
Reconfigurable, Redundancy). The physical
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86VL32
provides protection from power failures and hot
swapping.
The XRT86VL32 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/ E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDL C buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Lin k bits of the inboun d T1/E1/J1 frames .
The X RT86VL32 f ull y me ets all of the l ate st T 1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT& T TR 6 2411 (12-90) T R54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, J T G706 , I.431. Ex ten sive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
APPLICATIONS AND FEATU RES (NEXT PAGE)
FIGURE 1. XRT86VL32 2-CHANNEL DS1 (T1/E1/J1) FRAMER/L IU C OMBO
Performance
Monitor
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
LIU &
Loopback
Control
DMA
Interface
Signaling &
Alarms JTAG
WR
ALE_AS
RD
RDY_DTACK
μP
Select
A[13:0]D[7:0]
Microprocessor
Interface
4
3
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Local PCM
Highway
ST-BUS
2-Frame
Slip Buffer
Elastic Store
Tx Ser i a l
Data In Tx LIU
Interface
2-Frame
Slip Buffer
Elastic Store
Rx LIU
Interface
Rx Framer
Rx Serial
Data O u t
RTIP
RRING
TTIP
TRING
External Data
Link Controller
Tx Overhead In Rx Overhead Out
XRT86VL32
1 of 2-channels
Tx Frame r
LLB LB
System (Terminal) Side
Line Side
1:1 Turns Ratio
1:2 Turns Ratio
Memory I n te l/Mo to r o l a µ P
Configuration, Control &
Status Monitor
RxLOS
TxON
INT
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
APPLICATIONS
•High-Density T1/E1/J1 interfaces for Mu ltiplexers, Switches, LAN Routers and Digital Modems
•SON ET/SDH termina l or Add/Drop multiplexers (ADMs)
•T1/E1/J1 add/drop multiplexers (MUX)
•Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
•Digital Access Cross-conn ec t System (DACs)
•Digital Cross-co nnect Systems (DCS)
•Frame Relay Switches and Acce ss Devices (FRADS)
•ISDN Primary Rate Interfaces (PRA)
•PBXs and PCM chann el bank
•T3 channelized access concentrators and M13 MUX
•Wireless base station s
•ATM equip men t with integrated DS1 interfaces
•Multichannel DS1 Test Equipment
•T1/E1/J1 Perform ance Moni toring
•Voice over packet gateways
•Routers
FEATURES
•Two independent, full duplex DS1 Tx and Rx Framer/LIUs
•Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx prov ide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
•Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
•Programm able output clocks for Fractional T1/E1/J1
•Supp orts Channel Associated Signal ing (CAS)
•Supp orts Comm on Channel S igna lling (CCS )
•Supp orts ISDN Primary Rate Interface (ISDN PRI) signaling
•Extracts and inserts robbed bit signaling (RBS)
•3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte
buffers (buffer 0 / buff er 1)
•HDLC Controllers Support SS7
•Timeslot assignabl e HDLC
•V5.1 or V5.2 In te r face
•Autom atic Performance Report Ge neration (PM ON Status) ca n be inserted into the transm it LAP D interface
every 1 secon d or fo r a single transmission
•Alarm Indication Signal with Customer Installation signature (AIS-CI)
•Remote Alarm Indication with Customer Installation (RAI-CI)
•Gapped Clock interface m ode for Transmit and Receive.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
•Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
•Parallel search algorithm for fast fra me synchronizat ion
•W ide choice of T1 framing structures: SF/D4 , ESF, SLC®96, T1DM and N-Frame (non-signaling)
•Direct access to D and E channels for fast transm ission of data link information
•PRBS , QRSS , and Network Loop Code generation and det ection
•Program m able Interrupt output pin
•Supp orts programmed I/O and DMA modes of Read-Write access
•Each framer block encodes and decodes the T1/E1/J1 Frame serial data
•Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
•Detects OOF, LOF, LOS errors and COFA conditions
•Loopbacks: Local (LLB) and Line remote (LB)
•F ac ilitates Inv er s e Mult ip lex ing for AT M
•Performance monitor with one second polling
•Boun dary scan (IEEE 1149.1) JTAG test port
•Accepts external 8kHz Sync reference
•1.8V Inne r Core
•3.3V CMO S operation with 5V tolera nt inputs
•225-pin P BGA package with -40°C to +85°C operation
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT86VL32IB 22 5 Plast ic Ball Grid Array -40°C to +85°C
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
LIST OF PARAGRAPHS
1. 0 PIN LIST ......... ..... .............. .... ........ .... ..... ....... ..... .............. ..... .............. ..... .............. ..................................4
2. 0 PIN DESCRIP TIONS ......... .... ............... .... ............... .... ............... .... .............. ..... .............. .........................6
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
LIST OF TABLES
Tab l e 1 :: L is t by Pi n Num b e r .... ..... ... .... ..... ..... ... .... ..... ..... ... .... ..... ... ..... .... ..... ... ..... ..... .... ... ..... ............................................ 4
Tab l e 2 :: P in Typ e s ....... ..... ..... .. ..... ..... .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... ... ..... .... ... ................................................. 6
Tab l e 3 :: P in Des c ript io n Str u c tu re ....... ..... ..... ... .... ..... ... ..... .... ..... ... ..... .... ..... ... ..... ..... .... ... ..... ............................................ 6
Tab l e 4 :: XRT 8 6 V L 32 P ower Con s umpt io n . .. ... .... ..... ..... ... .... ..... ... ..... .... ..... ... ..... ..... .... ... ..... ..... .. ..... ..............................42
Tab l e 5 :: E 1 Rec e iv er El ec tr ic a l C ha r a ct er is tics .... ..... ... ..... .... ..... ... ..... .... ... ..... ..... ..... .. ..... ..... ..... .. ................................... 50
Table 6:: T1 Receiver Electrical Characteristics .............................................................................................................. 51
Tab l e 7 :: E 1 Tran s m it te r E le c tric al Cha ra c te ris tic s ........ ..... .... ... ..... ..... .... ... ..... ..... .. ..... ..... ..... .. ..... ................................... 52
Table 8:: E1 Transmi t Ret urn Loss Requirement .... .. .. ..... ....... ............... .. .................... .. .................... .. ........................... 52
Tab l e 9 :: T 1 Tran s m it te r E le c tric al Ch a racte ri st ic s ... ..... .. ..... ..... ..... .. ..... ..... .. ..... ..... ..... .. ..... ..... ..... .. ................................. 53
Tab l e 1 0: : T ra n sm it P u ls e M a s k Sp ec if ic a tio n ... .. ..... .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... ... .... ..... ..... ... .... .. ............................... 54
Table 11:: DSX1 Interface Isolated pulse mask and corner points ..................................................................................55
Tab l e 1 2: : A C Ele c tr ic a l Cha r ac t er isti cs ....... ..... .... ... ..... ..... .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... ..... .. ........................................ 56
Tab l e 1 3: : In te l Micr op r o ce s s or Int e rf ac e Ti mi n g Spe ci ficatio ns ...... ..... .. ..... ..... ..... ... .... ..... ... ..... .... ..... ... ......................... 57
Tab l e 1 4: : In te l Micr op r o ce s s or Int e rf ac e Ti mi n g Spe ci ficatio ns ...... ..... .. ..... ..... ..... ... .... ..... ... ..... .... ..... ... ......................... 58
Table 15:: Motorola Asychronous Mode Microprocessor Interface Timing Specifications .............................................. 59
Tab l e 1 6: : Po w er PC 4 03 M ic ro p ro c e ss o r In t er fa c e Timin g Sp ec if ica tio n s ....... ..... ..... .. ..... ..... ..... .. ..... ..... ... .... ................ 60
XRT86VL32
III
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
LIST OF FIGURES
Figure 1.: XRT86VL32 2-channel DS1 (T1/E1/J1) Framer/LIU Combo .............................................................................1
Fig u re 2. : F r a m e r Syste m T ra n smit T im in g D ia gr a m (B a se R at e /No n -M u x ) .. ... ..... ..... .. ..... ..... .. ..... ..... ..... .. ..... ..... .. .........43
Figure 3.: Framer System Receive Timing Diagram (RxSERCLK as an Output) ............................................................44
Figure 4.: Framer System Receive Timing Diagram (RxSERCLK as an Input) ...............................................................45
Fig u re 5. : F r a m e r Syste m T ra n smit T im in g D ia gr a m (H M V IP a n d H 1 00 M o d e) ...... ..... ... .... ..... ... ..... .... ..... ... ..... .... .........46
Figure 6.: Framer System Receive Timing Diagram (HMVIP/H100 Mode) .....................................................................47
Fig u re 7. : F r a m e r Syste m T ra n smit O v er h e ad Ti m in g Di a gr a m .... ... ..... ..... .... ... ..... ..... .. ..... ..... ..... .. ..... ..... ..... ..................48
Figure 8.: Framer System Receive Overhead Timing Diagr am (RxSERCLK as an Output) .... .. ............ ..... ............ ........49
Figure 9.: Framer System Receive Overhead Timing Diagr am (RxSERCLK as an Inp ut) ....... .......... .. .. ............... .. ........49
Figure 10.: IT U G.703 Pulse Template ......... ..... ............ ..... ............ ..... .................... .. ............... .. .....................................54
Figure 11.: DSX-1 Pulse Template (nor malized ampli tude) ....................... .. .. ............... .. ....... ..... ............ .........................55
Figure 12.: Intel µP Inter face Timing During Programmed I/O Read and Write Operations When ALE Is Not Tied ’H IGH’ 57
Figure 13.: Intel µP Inter face Timing During Programmed I/O Read and Write Operations When ALE Is Tied ’HI GH’ ..58
Figure 14.: Moto rol a Asychron ous M ode Interfa ce Signals Duri ng Programmed I/O Read and Write Operations .........59
Figure 15.: Power PC 403 Interface Signals Duri ng Programmed I/O Read and Write Operati ons ...... ................. ........60
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTIONREV. V1.2.0
4
1.0 PIN LIST
TABLE 1: LIST BY PIN
NUMBER
PIN PIN NAME
A1 GNDPLL
A2 AVDD18
A3 E1MCLKnOUT
A4 MCLKIN
A5 VSS
A6 TRST
A7 RXSERCLK0
A8 RXCHCLK0
A9 RXOHCLK0
A10 TXMSYNC0
A11 TXOHCLK0
A12 TXSERCLK0
A13 TXCHNCLK0
A14 TXCHN0_3
A15 NC
A16 NC
A17 NC
A18 NC
B1 VDDPLL18
B2 JTAG_Ring
B3 AGND
B4 T1MCLKnOUT
B5 aTEST
B6 TDI
B7 RXLOS0
B8 DVDD18
B9 RXCHN0_2
B10 RXCHN0_4
B11 TEST
B12 TXCHN0_0
B13 TXCHN0_2
B14 VSS
B15 NC
B16 NC
B17 NC
B18 NC
C1 GNDPLL
C2 VDDPLL18
C3 JTAG_Tip
C4 DVDD18
C5 DGND
C6 TMS
C7 TCLK
C8 RXCRCSYNC0
C9 RXCHN0_1
C10 RXCHN0_3
C11 RXOH0
C12 TXOH0
C13 NC
C14 TXCHN0_4
C15 NC
C16 VSS
C17 NC
C18 NC
D1 GNDPLL
D2 VDDPLL18
D3 VDDPLL18
D4 GNDPLL
D5 TDO
D6 RXSER0
D7 RXCHN0_0
D8 RXSYNC0
D9 TXSYNC0
PIN PIN NAME
D10 RXCASYNC0
D11 TXSER0
D12 TXCHN0_1
D13 NC
D14 NC
D15 RXSERCLK2
D16 VDD
D17 NC
D18 NC
E1 RTIP0
E2 RGND0
E3 RVDD0
E4 TTIP0
E5 ANALOG
E15 NC
E16 VSS
E17 NC
E18 NC
F1 RRING0
F2 TGND0
F3 TVDD0
F4 TRING0
F15 VSS
F16 NC
F17 NC
F18 RXSYNC2
G1 DGND
G2 RGND1
G3 RVDD1
G4 NC
G15 RXCHN2_1
G16 RXLOS2
G17 NC
PIN PIN NAME
G18 NC
H1 DGND
H2 TGND1
H3 TVDD1
H4 NC
H15 RXCASYNC2
H16 RXCHN2_0
H17 RXCHCLK2
H18 NC
J1 RTIP2
J2 RGND2
J3 RVDD2
J4 TTIP2
J15 TXSERCLK2
J16 DVDD18
J17 RXCRCSYNC2
J18 RXSER2
K1 RRING2
K2 TGND2
K3 TVDD2
K4 TRING2
K15 RXOH2
K16 RXCHN2_4
K17 RXOHCLK2
K18 RXCHN2_2
L1 DGND
L2 RGND3
L3 RVDD3
L4 NC
L15 TXSYNC2
L16 RXCHN2_3
L17 TXMSYNC2
L18 TXSER2
PIN PIN NAME
XRT86VL32
xr
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTIONREV. V1.2.0
5
M1 DGND
M2 TGND3
M3 TVDD3
M4 NC
M15 VSS
M16 VSS
M17 TXCHN2_1
M18 TXCHN2_0
N1 TxON
N2 LOP
N3 NC
N4 8KEXTOSC
N15 TXCHN2_4
N16 TXCHN2_3
N17 TXCHNCLK2
N18 TXOHCLK2
P1 RESET
P2 E1OSCCLK
P3 VDD
P4 T1OSCCLK
P15 TXOH2
P16 NC
P17 NC
P18 NC
R1 REQ0
R2 8KSYNC
R3 REQ1
R4 VSS
R5 ADDR2
R6 ADDR6
R7 ADDR10
R8 INT
R9 ADDR11
PIN PIN NAME
R10 ADDR12
R11 DATA7
R12 NC
R13 DVDD18
R14 VSS
R15 VDD
R16 NC
R17 NC
R18 NC
T1 fADDR
T2 ACK0
T3 RDY
T4 DATA0
T5 VSS
T6 ADDR3
T7 ADDR7
T8 PTYPE2
T9 VDD
T10 DATA4
T11 NC
T12 NC
T13 NC
T14 NC
T15 NC
T16 TXCHN2_2
T17 NC
T18 NC
U1 iADDR
U2 ACK1
U3 DATA1
U4 DBEN
U5 ADDR0
U6 ADDR4
PIN PIN NAME
U7 DVDD18
U8 ALE
U9 ADDR9
U10 BLAST
U11 DATA6
U12 NC
U13 NC
U14 NC
U15 NC
U16 VSS
U17 NC
U18 NC
V1 PCLK
V2 PTYPE0
V3 RD
V4 PTYPE1
V5 ADDR1
V6 ADDR5
V7 ADDR8
V8 DATA2
V9 DATA3
V10 DATA5
V11 ADDR13
V12 WR
V13 CS
V14 VSS
V15 NC
V16 NC
V17 NC
V18 NC
PIN PIN NAME
XRT86VL32
6
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
2.0 PIN DESCRIPTI ONS
There are six type s of pins defined throughout this pin description and the corresponding symbol is presented
in tabl e bel ow. The per-channel pin is i ndicated by the channel number or the letter ’ n’ whi ch is appended at the
end of the sign al name, for example, TxSERn, where "n" indicates chann els 0 and 2. All output pins are "tri-
stated" upon hardware RESET.
The structure of the p in description is divided into thirteen groups, as presented in the table below
TABLE 2: PIN TYPES
SYMBOL PIN TYPE
IInput
OOutput
I/O Bidirectional
GND Ground
PWR Power
NC No Connect
TABLE 3: PIN DESCRIPTION STRUCTURE
SECTION PAGE NUMBER
Trans mit System Side Interface page 7
Tr ansmit Overhead Interface page 15
Receive Overhead Interface page 17
Receive System Side Interface page 18
Receive Li ne Interface page 26
Transmit Line Interface page 28
Timi ng Int erface page 28
JTAG Interface page 30
Microprocessor Interface page 31
Power Pi ns (3. 3V) page 40
Power Pi ns (1. 8V) page 40
Ground Pins page 41
No Connect Pi ns page 41
XRT86VL32
7
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL# TYPE OUTPUT
DRIVE(MA) DESCRIPTION
TxSER0/
TxPOS0
TxSER2/
TxPOS2
D11
L18
I - T r ansmit Seri al Data Inp ut (TxSERn) /Transmit Posi tive Digit al
Input (TxPOSn):
The exact functi on of these pins depends on the mod e of opera-
tion selected, as described below.
DS1/E1 Mode - TxSERn
These pi ns funct ion as t he tr ansmi t seri al da ta i nput on the sys tem
side i nterface, which are latched on the rising edge of the TxSER-
CLKn pin. Any paylo ad dat a applied t o this pi n will be ins erted i nto
an outbound DS1/E1 frame and out put to the line. In DS1 mode,
the fr aming a li gnment bits, facility data link bits, CRC-6 bits, and
signaling information can al so be inserted from this i nput pin if
configured appropriately. In E1 mode, all data intended to be
tran sported vi a Ti me Slo ts 1 t hrough 15 an d T im e slot s 17 thr ough
31 m ust be a pplie d t o this i nput pin. Data intend ed for T im e Slot s 0
and 16 can also be applied to this input pin If configured accord-
ingly.
DS1 or E1 High-S peed Multiplex ed Mode* - TxSERn
In this mode, these pins are used as the high-speed multiplexed
data input pin on the system side. High-speed multiplexed data of
channels 0-3 mus t be appl ied to TxSER0 in a byte or bit -inter-
leaved way. The framer latches in the multiplexed data on
TxS ER0 using TxMSYNC/TxINCLK and demul tiplexes this data
int o 4 serial strea ms. The LIU bl ock wil l then output th e data t o the
line interface using TxSERCLKn.
DS1 or E1 Framer Bypass Mode - TxPOSn
In this mode, TxSERn is used for the positive digital input pin
(TxPOSn) to t he LIU.
NOTE:
1. *High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-multiplexed modes, and
(For T1 only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped into
an E1 frame by ignoring every fourth time slot (don’t
care).
3. These 8 pins are internally pulled “High” for each
channel.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxSERCLK0/
TxLINECLK0
TxSERCLK2/
TxLINECLK2
A12
J15
I/O 12 Transm it Serial Clock (Tx SERCLKn)/Tra nsm it L ine Clock
(TxSERCLKn):
The exact functi on of these pins depends on the mod e of opera-
tion selected, as described below.
In Base-Ra te Mode (1. 544MHz/2.048MHz) - TxSERCLKn:
This cl ock sign al i s used by the transmit seri al interf ace to latch
the contents on the TxSERn pins in to t he T1/E1 framer on the r is-
ing edge of Tx SERCLKn. These pins can be configured as input
or output as descri bed below.
When TxSERCLKn is configured as Input:
These pin s will be input s if the TxSERCLK is chosen as the ti ming
source for the t ransmit framer. Users must provide a 1.544MHz
clock rate to t his input pi n for T1 mode of operation, and
2.048MHz clock rat e in E1 mode.
When TxSERCLKn is configured as Output:
These pins will be outputs if either the recovered line clock or the
MCLK PLL is chosen as the timing source for the T1/E1 transmit
framer. The transmit fr am er will output a 1.544MHz clock rate in
T1 mode of operation, and a 2.048MHz clock rate in E1 mode.
DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as
INP UT O N LY
In this mode, TxSERCLK is an opti onal clock signal input whi ch is
used as the timing sour ce for the tr ansm it line int erface , and i s
only required if TxSERCLK is chosen as the timing source for t he
transmit f ramer. If TxSERCLK is chose n as th e timing source, sys -
tem equipment sho uld provide 1. 544M Hz (For T1 mode) or
2.048MHz (For E1 mode) to the TxSERCLKn pi ns on each chan-
nel. Tx SERCLK is not required if eit her the recovered clock o r
MCLK PLL is chosen as the timing source of th e device.
High s peed o r mult iplex ed dat a is l atched into t he device u sing t he
TxMSYNC/TxINCLK high-speed clock signal.
DS1 or E1 Framer Bypass Mode - TxLINECLKn
In this mode, TxSERCLKn is used as the transmit line clock (TxLI -
NECLK) to the LIU.
NOTE: *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP,
H.100, Bit-multiplexed modes, and (For T1 only)
12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into
an E1 frame by ignoring every fourth time slot (don’t
care).
NOTE: These 8 pins are internally pulled “High” for each channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TxSYNC0/
TxNEG0
TxSYNC2/
TxNEG2
D9
L15
I/O 12 Transm it Single Fra me Sync Pulse (TxSYNCn) / Transm it
Negative Digi tal Input (TxNEGn ):
The exact functi on of these pins depends on the mod e of opera-
tion selected, as described below.
DS1/E1 Base Rate Mode (1 .544MHz/2.048MHz) - TxSYNCn:
These TxSYNCn pins are used to i ndicate the si ngle frame
boundary withi n an outbound T1/E1 fr am e. In bo th DS1 or E1
mode, t he single frame boundary repeats every 125 microsec-
onds (8kHz).
In DS1/E1 base rate, TxSYNCn can be configured as either input
or output as descri bed below.
When TxSYNCn is configured as an Input:
Users m ust provide a signal which mu st pulse "High" for one
period of TxSERCLK during the first bit of an out bound DS1/E1
frame. It is imperat ive that th e TxSYNC input signal be synchro-
nized with the TxSERCLK input si gnal.
When TxSYNCn is confi gured as an Output:
The tra nsmi t T1/E1 fram er will out put a si gnal whic h pulses " High"
for one per iod of TxSERCLK during the first bit of an out bound
DS1/E1 fr ame.
DS1/E1 High-Speed Backplane Modes* - TxSYNCn as INPUT
ONLY:
In thi s mode, TxSYNCn must be an input regardl ess of the clock
source that is chosen to be the timing source for the transmit
framer. In 2.048MVIP/4.096/8.192MHz high-speed modes,
TxS YNCn pins must be pulsed ’High’ for one peri od of Tx SERCLK
during the first bit of the out bound T1/E1 frame. In HMVIP mode,
TxS YNC0 must be pulsed ’H igh’ for 4 clock cycles of the TxM-
SYNC/TxINCLK s ignal in the posit ion of the firs t two and the last
two bit s of a multiplexed frame. I n H.100 mode, TxSYNC0 must
be pulsed ’High’ for 2 clock cycles of the TxMSYNC/TxINCLK sig-
nal in the position of the first and the l ast bit of a multiplexed
frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this mode, TxSYNCn is used as the negative digital input pin
(TxNEG) t o the LI U.
NOTE: *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP,
H.100, Bit-multiplexed modes, and (For T1 only)
12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into
an E1 frame by ignoring every fourth time slot (don’t
care).
NOTE: These 8 pi ns are internally pulled “Low” for each channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
10
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxMSYNC0/
TxINCLK0
TxMSYNC2/
TxINCLK2
A10
L17
I/O 12 Multiframe Sync Pulse (TxMSYNCn) / Transmit Input Clock
(TxINCLKn)
The exact functi on of these pins depends on the mod e of opera-
tion selected, as described below.
DS1/E1 Base Rate Mode (1 .544MHz/2.048MHz) - TxMSYNCn
In this mode, these pins are used to indicate the multi-frame
boundary within an outbound DS1/E1 frame.
In DS1 ESF mode, TxMSYNCn repeats every 3ms.
In DS1 SF mode, TxMSYNCn repeats every 1.5ms.
In E1 mode, TxMSYNCn repeats every 2ms.
If TxMSYNCn is configured as an input , TxMSYNCn m ust pulse
"Hig h" f or one period of TxSERCL K duri ng the first bit of an out-
bound DS1/ E1 multi-frame. It is imperative that the TxMSYNC
input signal be synchronized with the TxSERCLK input signal.
If TxMSYNCn is configured as an output, the transm it secti on of
the T1/E1 framer will output and pulse TxMSYNC "High" for one
period of TxSERCLK during the first bit of an out bound DS1/E1
frame.
DS1/E1 Hig h-Speed Ba ckpl ane Modes* - ( TxINCLKn as INPUT
ONLY)
In this m ode, TxINCLK0 must be used as the high-s peed input
clock pin f or the back plane inter fac e to la tch in hig h-speed or mul-
tip lexed data on the TxSERn pin. The frequency of TxINCLK0 is
presented in the table below.
NOTES:
1. *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP,
H.100, Bit-multiplexed modes, and (For T1 only)
12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped into
an E1 frame by ignoring every fourth time slot (don’t
care).
3. These 8 pins are internally pulled “Low” for each
channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
OPERATION MODE FREQUENCY OF
TXINCLK0(MHZ)
2.048MVIP non-multiplexed 2.048
4.096MHz non-multiplexed 4.096
8.192MHz non-multiplexed 8.192
12.352MHz Bit -multiplexed
(DS1 ONLY) 12.352
16.384MHz Bit -multiplexed 16. 384
16.384 HMVIP Byt e-multiplexed 16.384
16.384 H.100 Byte-mul tiplexed 16.384
XRT86VL32
11
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TxCHCLK0
TxCHCLK2 A13
N17 O 8 Transmit Channel Clock Out put Si gnal (TxCHCLKn):
The exact functi on of this pin depen ds on wheth er or not the trans -
mit fr am er enables the transmit fractional/signaling interface to
input fractional data, as described below.
If transmit fractional/signaling interface is disabled:
This pi n indicates the boundary of each time sl ot of an outbound
DS1/E1 fr ame. In T1 mode, each of these out put pins is a 192k Hz
clock which pulses "High" during the L SB of eac h 24 time slots. In
E1 mode, each of these output pins is a 256kHz clock which
pulses "High" duri ng the LSB of each 32 time sl ots. The Terminal
Equipment can use thi s clock signal to sampl e the TxCHN0
through TxCHN4 time slot i dentifier pins to determ ine which time
slot is being processed.
If transm it fractional/signaling in terface is enabl ed:
TxCHCLKn is the fractional interface clock which either outputs a
cloc k signal f or the time slot that has been conf igur ed to input frac-
tional data, or outpu ts an enable signal for the fr actional time slo t
so that fractional data can be clocked into the device using the
TxSER CLK pin.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
12
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxCHN0_0/
TxSIG0
TxCHN2_0/
TxSIG2
B12
M18
I/O 8Transmit Time Slot Octet Identifier O utput 0 (TxCHNn_0) /
Transmit Serial Signaling Input (TxSIGn):
The exact functi on of these pins depends on whether or not the
transmit framer enables the transmit fractional /signaling interf ace,
as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_0:
These output pins ( TxCHNn_4 through TxCHNn_0) refle ct t he
fiv e-bit binary val ue of the curr ent time slo t being processe d by the
transmit serial interface. Terminal Equi pment can use the TxCH-
CLK to sample the five output pins of each channel in or der to
ident ify t he time slo t being pr ocessed. This pin i ndicat es the Least
Signi ficant Bi t (LSB) of the time slo t channel being processed.
If transm it fractional/signaling in terface is enabled - TxSIGn:
These pins can be used to input robbed- bit signal ing data to be
inserted within an outbound DS1 frame or to input Channel Asso-
ciat ed Signaling ( CAS) dat a within an out bound E1 frame, as
describ ed be low.
T1 Mode: Signaling data (A,B,C,D) of each channel must be pro-
vided on bit 4,5,6,7 of each time sl ot on the TxSIG pin if 16-code
signaling is used. If 4-code signaling is selected, signaling data
(A,B) of each channel must be provided on bit 4, 5 of each tim e
slot on the TxSIG pin. If 2-code si gnaling is selected, signaling
data (A) of each channel must be provided on bit 4 of each t ime
slot on the TxSIG pin.
E1 Mode: Signaling data in E1 mode can be provided on the
TxSIGn pins on a time-sl ot-basis as in T1 mode, or it can be pro-
vided on time slot 16 onl y via t he TxSIGn input pi ns. In the latter
case, signal ing data (A,B,C,D) of channel 1 and channel 17 m ust
be inserted on the TxSI Gn pin during tim e slot 16 of frame 1, sig-
nali ng data ( A,B,C,D) of channel 2 and channel 18 must be
inserted on the TxSI G n pin during time slot 16 of frame 2. .. etc.
The CAS m ult iframe Alignments bit s (00 00 bits) and the extra bits/
alarm bit (xyxx) must be inserted on the TxSIGn pin during ti m e
slot 16 of frame 0.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
NOTE: These 8 pi ns are internally pulled “Low” for each channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
13
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TxCHN0_1/
TxFrTD0
TxCHN2_1/
TxFrTD2
D12
M17
I/O 8Transmit Time Slot Octet Identifier O utput 1 (TxCHNn_1) /
Transmit Serial Fractional Inp ut (TxFrTDn):
The exact functi on of these pins depends on whether or not the
transmit framer enables the transmit fractional /signaling interf ace,
as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_1
These output signals (TxCHNn_4 through TxCHNn_0) reflect the
fiv e-bit binary val ue of the curr ent time slo t being processe d by the
transmit serial interface. Terminal Equi pment can use the TxCH-
CLK to sample the five output pins of each channel in or der to
identify the time slot bei ng processed. This pin ind icates Bit 1 of
the time sl ot channel being processed.
If transm it fractional/signaling in terface is enabled - TxFrTDn
These pins are used as the f ractional data input pins to input frac-
tio nal DS1/E1 payload data which will be inse rted within an out-
bound DS1/E1 frame. In this mode, terminal equip me nt can use
eit her TxCHCLK or TxSERCLK to clock in fractio nal DS1/E1 pay-
load data depending on the fra me r configuration.
NOTES:
1. Transmit fractional/Signaling interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
2. These 8 pins are internally pulled “Low” for each
channel.
TxCHN0_2/
Tx32MHz0
TxCHN2_2/
Tx32MHz2
B13
T16
O 8 Transmit Time Slot Octet Identifier Output 2 (TxCHNn_2) /
Transmit 32.678MHz Clock Output (Tx32MHZ):
The exact functi on of these pins depends on whether or not the
transmit framer enables the transmit fractional /signaling interf ace,
as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_2
These output signals (TxCHNn_4 through TxCHNn_0) reflect the
fiv e-bit binary val ue of the curr ent time slo t being processe d by the
transmit serial interface. Terminal Equi pment can use the TxCH-
CLK to sample the five output pins of each channel in or der to
identify the time slot bei ng processed. This pin ind icates Bit 2 of
the time sl ot channel being processed.
If transm it fractional/ signaling i nterface is enabled - Tx32MHz
These p ins are u sed to out put a 3 2.6 78MHz c lock r efere nce which
is der ived from the MCLK IN in put pin.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
14
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxCHN0_3/
TxOHSYNC0
TxCHN2_3/
TxOHSYNC2
A14
N16
O
O
8Transmit Time Slot Octet Identifier Output 3 (TxCHNn_3) /
Transmit Overhead Synchro nization Puls e (TxOHSYNCn):
The exact functi on of these pins depends on whether or not the
transmit framer enables the transmit fractional /signaling interf ace,
as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_3
These output signals (TxCHNn_4 through TxCHNn_0) reflect the
fiv e-bit binary val ue of the curr ent time slo t being processe d by the
transmit serial interface. Terminal Equi pment can use the TxCH-
CLK to sample the five output pins of each channel in or der to
identify the time slot bei ng processed. This pin ind icates Bit 3 of
the time sl ot channel being processed.
If transm it fractional/signaling in terface is enabl ed -
TxOHSYNCn
These pins are used to out put an Overhea d Synchronization
Pulse whi ch indicates the first bit of each multi-fram e.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TxCHN0_4
TxCHN2_4 C14
N15 O 8 Transmit Time Slot Octet Ident if ier Output-Bit 4 (Tx CHNn_4):
These output signals (TxCHNn_4 through TxCHNn_0) reflect the
fiv e-bit binary val ue of the curr ent time slo t being processe d by the
transmit serial interface. Terminal Equi pment can use the TxCH-
CLK to sample the five output pins of each channel in or der to
identify t he ti m e slot being pr ocessed. This pin indi cates the M ost
Signi fi cant Bit (MSB) of the time slot channel being pro cessed.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME BALL#TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
15
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TRANSMIT OVERHEAD INTERFACE
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
TxOH0
TxOH2 C12
P15 I - Tran smit Overhead Input (TxOHn):
The exact function of these pins depends on the mode of oper-
ation selected , as described bel ow.
DS1 Mode
These pins oper ate as the source of Datal ink bit s which will be
inserted into the Dat alink bits within an outbound DS1 fr am e if
the framer is conf igured accordingly. Datalink Equipment can
provide data to this input pin using the TxOHCLKn clock at
either 2kHz or 4kHz depending on the transmit datalink ban d-
width selected.
NOTE: This input pin will be disabled if the framer is using the
Transmit HDLC Controller, or the TxSER input as the
source for the Data Link Bits.
E1 Mode
These pins operate as the s ource of Datal ink bits or Signaling
bits d epending on the fr am er configuration , as described
below.
Sourcing Datalink bits from TxOHn:
The E1 transmit framer will output a clock edge on TxOHCLKn
for each Sa bi t that has been configured to carr y datalink infor-
mation. Ter minal equipment can then use TxOHCLKn to pro-
vide datali nk bits on TxOH n to be in serted into t he Sa bits
within an outbound E1 f rame.
Sourcing Si gnaling bits from TxOHn:
Users must provide signaling data on TxOHn pins on tim e slot
16 only. Signaling dat a (A,B,C ,D) of channel 1 and channel 17
must be i ns erted o n the Tx OHn pi n d uring time sl ot 16 of frame
1, signaling data (A,B,C ,D) of channel 2 and channel 18 must
be inserted on the TxOHn pin during time slot 16 of frame
2... etc. The CAS multifr am e Alignm ents bit s (0000 bits) and
the extra bits/alarm bit (xyxx) must be inser ted on the TxOHn
pin duri ng ti m e slot 16 of frame 0.
NOTE: These 8 pins are internally pulled “Low” for each
channel.
XRT86VL32
16
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxOHCLK0
TxOHCLK2 A11
N18 O 8 Transmit OH Serial Clock Output Signa l( TxO HCLKn)
This pin functions as an overhea d output clock signal for the
transmit overhead inter face, and it s function is explained
below.
DS1 Mode
If the TxOH pi ns have been conf igured to be the source for
Datal ink bi ts, the DS1 tr ansmit f ramer wi ll provi de a cloc k edge
for each Data Link Bit. In DS1 ESF mode, t he TxO HCLK can
either be a 2kHz or 4kHz output signal depending on the
select ion of Data Li nk Bandwid th ( Re gister 0xn10A).
Data Li nk Equi pment can pro vide data to th e TxOHn p in on t he
rising edge of TxOHCLK. The framer latches the data on the
fall ing edge of thi s clock signal.
E1 Mode
If the TxOH pi ns have been conf igured to be the source for
Data Link bits, the E1 transmit framer wil l provide a clock edge
for ea ch Na tional Bit ( Sa bi ts ) that h as been conf igured to ca rry
data link information. (Register 0xn10A)
TRANSMIT OVERHEAD INTERFACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL32
17
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RECEIVE OVERHEAD INTERFACE
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
RxOH0
RxOH2 C11
K15 O 8 Receive Overhead Output (RxOHn):
These pins function as the Recei ve Overhead output, or
Receive Signal ing Output depending on the rec eive framer
configuration, as described below.
DS1 Mode
If t he RxO H pins hav e been configured as the destinat ion for
the Data Link bi ts within an inbound DS1 frame, dat alink bi ts
wil l be out put to the RxOHn pins at eit her 2kHz or 4kHz
depending on the Receive datalink bandwidth s elected.
(Register 0xn10C).
If configured appropriately, signaling information in the
receive signaling array registers (Registers 0xn500-0xn51F)
can also be output to the RxOHn output pins.
E1 Mode
These output pins will always output the contents of the
Nati onal Bits (Sa4 throug h Sa8) i f these Sa b it s have been
conf igured to carr y Dat a Li nk i nformat ion (Regi ster 0xn10 C).
The Receive Overhead O utput Inte rface will provide a clock
edge on RxO HCLKn for e ach Sa bit carrying Data Link i nfor-
mation.
If configured appropriately, signaling information in the
receive signaling array registers (Registers 0xn500-0xn51F)
can also be output to the RxOHn output pins.
RxOHCLK0
RxOHCLK2 A9
K17 O 8 Receive Over head Clock Output (RxOHCLKn):
This pin funct ions as an overhead output clock signal for the
receive over head interface, and its function is expl ained
below.
DS1 Mode
If t he RxO H pins have been con fi gured to be the destination
for Datalink bits, the DS1 trans mit framer will output a clock
edge for each Data Li nk Bit. In DS1 ESF mode, the RxO-
HCLK can either be a 2kHz or 4kHz output si gnal depending
on the selecti on of Data Link Bandwi dth (Register 0xn10C).
Data Link Equipment can clock out datalink bi ts on the
RxOHn pin using this clock signal.
E1 Mode
The E1 receive framer p rovides a cloc k edge for each
National Bi t (Sa bits) t hat is configured to carry data li nk infor-
mation.
Data Link Equipment can clock out datalink bi ts on the
RxOHn pin using this clock signal.
XRT86VL32
18
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
RxSYNC0/
RxNEG0
RxSYNC2/
RxNEG2
D8
F18
I/O 12 Receive Single Frame Sync Pul se (RxSYNCn):
The exact functi on of these pins depends on the mode of oper-
ation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - RxSYNCn:
These RxSYNCn pins are used to i ndicate the single frame
boundary within an inbound T1/E1 frame. In both DS1 or E1
mode, the single fram e boundary repeats every 125 microsec-
onds (8kHz).
In DS1/E1 base rate, RxSYNCn can be confi gured as either
input or output depending on the slip buffer configur ation as
described bel ow.
When RxSYNCn is configu red as an Input:
Users must provide a signal whic h mus t pul se "High" fo r one
perio d of RxSERCLK and repeats every 125μS. The receive
serial Interface will output the first bit of an inbou nd DS1/E1
frame during the provided RxSYNC pulse.
NOTE: It is imperative that the RxSYNC input signal be
synchronized with the RxSERCLK input si gnal.
When RxSYNCn is configu red as an Output:
The receive T1/E1 fr am er wi ll output a signal which p ulses
"High " f or one period of RxSERCLK during the first bit of an
inbound DS1/E1 f rame.
DS1/E1 High-Speed Backplane Modes* - RxSYNCn as
INPUT ONLY:
In this m ode, RxSYNCn must be an input regardless of the sli p
buf fer configuration. In 2 .048MVIP/4. 096/8.192MHz hi gh-speed
modes , RxSYNCn pi ns mu st be pul sed ’High’ for one period of
RxSERCLK during the first bit of the inbound T1/E1 frame. I n
HMVIP mode, RxSYNC0 must be pul sed ’High’ for 4 cl ock
cycles of the RxSERCLK signal in the positi on of t he fi rst two
and the las t two bits of a multi plexe d fra me . In H.100 m ode,
RxSYNC0 must be pulsed ’High’ for 2 clock cycles of the
RxSERCLK signal in the pos it ion of the first and the last bit of a
mu lt ip le x e d fra m e .
DS1 or E1 Framer Bypass Mode - RxNEGn
In this mode, RxSYNCn is used as the Receive negative di gital
output p in (RxNEG) from the LIU.
NOTE: *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP,
H.100, Bit-multiplexed modes, and (For T1 only)
12.352MHz Bit-multiplexed m ode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE: These 8 pins are internally pulled “Low” for each
channel.
XRT86VL32
19
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxCRCSYNC0
RxCRCSYNC2 C8
J17 O12 Receive Multiframe Sync Pulse (RxCRCSYNCn):
The RxCRCSYNCn pins are us ed to i ndicate the r eceive multi -
frame boundary. These pins pulse "High" for one period of
RxSERCLK when the first bit of an inbound DS1/E1 Multi-fr ame
is being output on the RxCRCSYNCn pin.
•In DS1 ESF mode, RxCRCSYNCn rep eats every 3m s
•In DS1 SF mode, RxCRCSYNCn rep eats every 1.5ms
•In E1 mode, RxCRCSYNCn re peats every 2ms.
RxCASYNC0
RxCASYNC2 D10
H15 O12 Receive CAS Mult if ram e Sync Pulse (RxCASYNCn):
- E1 Mode Only
The RxCASYNCn pins are us ed to i ndicate the E1 CAS Multif-
frame boundary. These pins pulse "High" for one period of
RxSERCLK when t he fir st bi t of an E 1 CAS Multi-f rame is being
output on the RxCASYNCn pin.
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
20
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxSERCLK0/
RxLINECLK0
RxSERCLK2/
RxLINECLK2
A7
D15
I/O 12 Receive Serial Clock Signal (RxSERCLKn) / Receive Line
Clock (RxLI NECLKn):
The exact functi on of these pins depends on the mode of oper-
ation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - RxSERCLKn:
These pins are used as the receive serial cl ock on the system
side i nterf ace whic h can be confi gured as ei ther input or output .
The receive seri al inter face outputs data on RxSERn on the ris-
ing edge of RxSERCLKn.
When RxSERCLKn is configu red as Input:
These pin s will b e inp ut s if the sl ip buf fe r on the Receive p at h is
enabled. System side equipment must provide a 1.544MHz
clock rate to this input pin for T1 mode of operation, and
2.048MHz clock rate in E1 mode.
When RxSERCLKn is configu red as Output:
These pi ns will be out puts if sl ip bu f fer i s byp ass ed. The rec eive
framer will output a 1.544MHz clock rate in T1 mode of opera-
tion, and a 2.048MHz cl ock rate in E1 mode.
DS1/E1 High-Speed Backplane Modes* - (RxSERCLK as
INPUT ONLY)
In this mode, this pin must be used as the high-speed input
clock for the back plane interface to output high-speed or multi -
plexed data on the RxSERn pin. The frequency of RxSERCLK
is pres ented in the t able below.
NOTES:
1. *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
2. For DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
OPERATION MODE FREQUENCY OF
RXSERCLK(MHZ)
2.048MVIP non-multi plexed 2.048
4.096MHz non-multiplexed 4.096
8.192MHz non-multiplexed 8.192
12.352MHz Bit-mul tiplex ed
(DS1 ONLY) 12.352
16.384MHz Bit-mul tiplex ed 16.384
16.384 HMVIP Byte-multiplexed 16.384
16.384 H.100 By te-multi plexed 16.384
XRT86VL32
21
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxSERCLK0/
RxLINECLK0
RxSERCLK2/
RxLINECLK2
A7
D15
I/O 12 (Continued)
DS1 or E1 Framer Bypass Mode - RxLINECLKn
In this mode, RxSERCLKn is used as the Receive Line Clock
output p in (RxLineCl k) from the LIU.
NOTE: These 8 pins are internally pulled “High” for each
channel.
RxSER0/
RxPOS0
RxSER2/
RxPOS2
D6
J18
O12 Receive Serial Dat a Output (RxSERn):
The exact functi on of these pins depends on the mode of oper-
ation selected, as described below.
DS1/E1 Mode - RxSERn
These pi ns function as the receive serial data output on the
system side inter face, which updates on the rising edge of the
RxSERCLKn pi n. All the framing alig nment bit s, f acilit y da ta l ink
bits, CRC bits, and signaling information will also be extracted
to thi s output pin.
DS1 or E1 High-S peed M ult ipl exed Mode* - RxSERn
In this mode, these pins are used as the high-speed multi-
plexed data output pin on the sy stem side. High- speed mult i-
plexed data of channels 0-3 will output on RxSER0 i n a byte or
bit- interl eaved way. The frame r outputs the mul ti plexe d data on
RxSER0 using t he high-speed input cloc k (RxSERCLKn).
DS1 or E1 Framer Bypass Mode
In this mo de, RxSERn is used as the positive digi tal output pin
(RxPOSn) fr om the LIU.
NOTE: *High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-mul tiplex ed mode s, and
(For T1 only) 12. 352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
22
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxCHN0_0/
RxSig0
RxCHN2_0/
RxSig2
D7
H16
O 8 Receive Time Slot Octet Identifier Output (RxCHNn_0) /
Receive Serial Signaling Output (RxSIG n):
The exact f uncti on of these pi ns depends on wheth er or not the
receive framer enables the receive frac tional/ signaling inter -
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_0:
These output pins (Rx CHNn_4 thr ough RxCHNn_0) refl ect the
five-bit binar y value of the current tim e slot being out put by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the fiv e output pins of each channel to identify
the ti me slot being output on these pins. RxCHNn_0 indicates
the Least Significant Bit (LSB) of the time slot channel being
output.
If receive fractional/signaling interface is enabled -
RxSIGn:
These pins can be used to output robbed- bit signal ing data
within an inbound DS1 frame or t o output Channel Ass ociated
Signal ing (CAS) d ata withi n an inbound E1 f rame, as desc ribed
below.
T1 Mode: Signaling data (A,B,C,D) of eac h channel will be out-
put on bit 4,5,6,7 of each time slot on the RxSIG pin if 16-code
signal ing is used. If 4-code signaling is sel e cted, signali ng data
(A,B) of each c hannel will be output on bit 4, 5 of each time slot
on the RxSI G pin. If 2-code si gnali ng is sel ected, signal ing dat a
(A) of eac h channel will be output on bit 4 of each ti me slot on
the RxSIG pin.
E1 Mode: Signal ing data in E1 mode wi ll be output on the
RxSIGn pi ns on a time-slot-basis as in T1 mode, or it can be
output on time slot 16 only via the RxSIGn output pins. In the
latter case, signaling data (A,B,C,D) of channel 1 and channel
17 will be out put on the RxSI Gn pin duri ng time sl ot 16 of frame
1, sig naling data (A,B,C,D) of channel 2 and channel 18 will be
output on the RxSIGn pin during time slot 16 of frame 2... etc.
The CAS m ultiframe Alignments bits (0000 bits) and the extra
bits/a larm bi t (xyxx) will be output on the RxSIGn pin during
time sl ot 16 of frame 0.
NOTE: Receive Fractional/signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 t o ‘1’.
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
23
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxCHN0_1/
RxFrTD0
RxCHN2_1/
RxFrTD2
C9
G15
O 8 Receive T ime Slot Octet I dentifie r Output Bi t 1 (RxCHNn_1 )
/ Receive Serial Fractional Output (RxFrTDn):
The exact f uncti on of these pi ns depends on wheth er or not the
receive framer enables the receive frac tional/ signaling inter -
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_1:
These output pins (Rx CHNn_4 thr ough RxCHNn_0) refl ect the
five-bit binar y value of the current tim e slot being out put by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the fiv e output pins of each channel to identify
the ti me slot being output on these pins. RxCHNn_1 indicates
Bit 1 of the ti m e slot channel being output.
If receive fractional/signaling interface is enabled -
RxFrTDn:
These pins are used as the fr action al data output pin s to out put
fractional DS1/ E1 payload data within an inbound DS1/E1
frame. In this mode, system equi pm ent can use either RxCH-
CLK or RxSERCLK to c lock out fracti onal DS1/E1 payloa d data
depending on the framer c onfiguration.
NOTE: Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 t o ‘1’.
RxCHN0_2/
RxCHN0
RxCHN2_2/
RxCHN2
B9
K18
O 8 Receive T ime S lot Octet Identi fier Output-B it 2 (RxCHNn_2)
/ Receive Time Slot Identifier Serial Output (RxCHNn):
The exact f uncti on of these pi ns depends on wheth er or not the
receive framer enables the receive frac tional/ signaling inter -
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_2:
These output pins (Rx CHNn_4 thr ough RxCHNn_0) refl ect the
five-bit binar y value of the current tim e slot being out put by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the fiv e output pins of each channel to identify
the ti me slot being output on these pins. RxCHNn_2 indicates
Bit 2 of the ti m e slot channel being output.
If receive fractional/signaling interface is enabled -
RxCHNn
These pi ns serially output the five-bit binary value of the time
slot being output by the receive serial interface.
NOTE: Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 t o ‘1’.
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
24
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxCHN0_3/
Rx8KHZ0
RxCHN2_3/
Rx8KHZ2
C10
L16
O 8 Receive T ime S lot Octet Identi fier Output-B it 3 (RxCHNn_3)
/ Receive 8KHz Clock Output (Rx8KHZn):
The exact f uncti on of these pi ns depends on wheth er or not the
receive framer enables the receive frac tional/ signaling inter -
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_3:
These output pins (Rx CHNn_4 thr ough RxCHNn_0) refl ect the
five-bit binar y value of the current tim e slot being out put by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the fiv e output pins of each channel to identify
the ti me slot being output on these pins. RxCHNn_3 indicates
Bit 3 of the ti m e slot channel being output.
If receive fractional/signaling interface is enabled -
Rx8KHZn:
These pins output a reference 8KHz clock signal derived from
the MCLKIN input.
NOTE: Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 t o ‘1’.
RxCHN0_4/
RxSCLK0
RxCHN2_4/
RxSCLK2
B10
K16
O 8 Receive T ime S lot Octet Identi fier Output-B it 4 (RxCHNn_4)
/ Receive Recovered Line Clock Output (RxSCLKn):
The exact f uncti on of these pi ns depends on wheth er or not the
receive framer enables the receive frac tional/ signaling inter -
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_4:
These output pins (Rx CHNn_4 thr ough RxCHNn_0) refl ect the
five-bit binar y value of the current tim e slot being out put by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the fiv e output pins of each channel to identify
the ti me slot being output on these pins. RxCHNn_4 indicates
the Most Si gnificant Bit (MSB) of the time sl ot channel being
output.
If rece ive fractional/ signalin g interf ace is enabled - Receive
Recovered Li ne Clock Output (RxSCLKn):
These pins outpu t the recov ered T1/E1 line cl ock (1.544MHz in
T1 mode and 2.048M Hz in E1 mode) for each channel.
NOTE: Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 t o ‘1’.
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
25
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxCHCLK0
RxCHCLK2 A8
H17 O 8 Receive Channel Clock Output (RxCHCLKn) :
The exact functi on of this pin depe nds on whether or not th e
recei ve framer enables the re ceive fractional/s ig naling interface
to output fractional data, as described below.
If receive fractional/signaling interface is disabled:
This pi n indicates the boundary of each time slot of an inbound
DS1/E1 frame. In T1 mode, each of these output pins is a
192kHz clock which pulses "Hig h" dur ing the LSB of each 24
time sl ots. In E1 mode, each of these out put pins is a 256kHz
clock which pulses "High" duri ng the LSB o f each 32 time slot s.
System Equipment can use this clock signal to sample the
RxCHN0 thr ough RxCHN4 time s lot ide nti fier pins t o determin e
which tim e slot is being output.
If receive fractional/signaling interface is enabled:
RxCHCLKn is t he fr action al inter face cl ock whi ch eith er outp uts
a clock signal for the time slot that has been configured to out-
put fractional data, or outputs an enable sig nal for the fractional
time sl ot so t hat fr actio nal dat a ca n be clock ed out of the device
using t he RxSERCLK pin.
NOTE: Receive fractional interface can be enabled by
programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 t o ‘1’.
RECEIVE SYSTEM SID E INTERF ACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
26
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE LINE I NTERFACE
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
RTIP0
RTIP2 E1
J1 I - Receive Positi ve Analog Input (RTIPn):
R TIP is the positive dif ferential input from the line int erface. Thi s
input pin, along with the RRING input pi n, fu nction s as the “Re ceive
DS1/E1 Line Signal” input for the XRT86VL32 device.
The user is e xpected to connect this si gnal and the RRING input
signal to a 1:1 transf ormer for proper operat ion. The center tap of
the receive transforme r should have a bypass capacitor of 0.1μF to
ground (Chip Side) to impr ove long haul application receive capa-
bilities.
RRING0
RRING2 F1
K1 I - Receive Negative Analog Input (RRINGn):
RRING is the negat ive differential input from the line interface. Thi s
input p in, along with the RTIP input pin, fun ctions as the “Re ceive
DS1/E1 Line Signal” input for the XRT86VL32 device.
The user is e xpected to connect this si gnal and the RTIP input si g-
nal to a 1:1 tra nsformer for proper operation . The center tap of the
receive transformer should have a bypass capacitor of 0.1μF to
ground (Chip Side) to impr ove long haul application receive capa-
bilities.
RxLOS_0
RxLOS_1 B7
G16 O 4 Receive Loss of Signal Output Indicator (RLOSn):
The XR T86VL32 device wil l assert th is output pi n (i .e. , toggle it
“high”) anytime (and for the duration that ) the Receive DS1/E1
Framer or LIU block decl ares the LOS defect condition.
Conversely, the XRT86VL32 device will tri-state thi s output pin any-
time (and for the duration that) the Receive DS1/E1 Framer or LIU
block is NOT de claring th e LOS defect condition.
NOTES:.
1. This output pin will toggle "high" (to denote that LOS is
being declared) whenever either the Receive DS1/E1
Framer or the Receive DS1/E1 LIU block (associated with
Channel N) declares the LOS defect condition. In other
words, the state of this output pin is a logic OR of the
Framer LOS and the LIU LOS condition.
2. Since the XRT86VL32 device tri-states this output pin
(anytime the channel is NOT declaring the LOS defect
condition). Therefore, the user MUST connect a "pull-
down" resistor (ranging from 1K to 10K) to each RxLOS
output pin, in order to pull this output pin to the logic
"LOW" condition, whenever the Channel is NOT declaring
the LOS defect condit ion.
XRT86VL32
27
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxTSEL N3 I - Receive Termination Control (RxTSEL):
Upon power up, the receivers are in "High" impedance. Switching
to internal termination can be selected through the microprocessor
interface by programming the appropriate channel register. How-
ever, to switch control to the hardware pin, RxTCNTL must be pro-
grammed to "1" in the appropriate global register (0x0FE2). Once
control has been granted to the hardware pin, it must be pulled
"High" to switch to internal termination.
NOTE: Inte rnal ly pulle d "Low" wit h a 50kΩ resistor.
RECEIVE LINE I NTERFACE
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
RxTSEL (pin) Rx Termination
External
Internal
0
1
Note: RxTCNTL (bit) must be set to "1"
XRT86VL32
28
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT LINE INTERF ACE
SIGNAL NAME BALL # TYPE DESCRIPTION
TTIP0
TTIP2 E4
J4 OTransmit Positive Analog Output (TTIPn):
TTIP is the positive differential output to the line interface. This output pin,
along wi th the corresponding TRING outpu t pi n, function as the Transmit DS1/
E1 output signal drivers for the XRT86VL32 device.
The user is expected to connect this signal and the corresponding TRING out-
put sig nal to a 1:2 step up transform er for proper ope ration.
This out put pin will be tr i-stat ed whenever the user sets the “TxON” input pin
or regi ster bit (0 xnF02, bit 3) to “0” .
NOTE: This pin should have a series line capacitor of 0.68
μ
F for DC blocking
purposes.
TRING0
TRING2 F4
K4 OTransmit Negative Analog Output (TRINGn):
TRING is the negative dif ferential out put to the line interface. Thi s output pin,
along wi th the c orresponding TTIP output pin, function as the T rans mit DS1/
E1 output signal drivers for the XRT86VL32 device.
The user is expected to connect this signal and the corresponding TRING out-
put sig nal to a 1:2 step up transform er for proper ope ration.
NOTE: This output pin will be tri-stated whenever the user sets the “TxON”
input pin or register bit (0xnF02, bit 3) to “0”.
TxON N1 ITransmit ter On
This i nput pin permits the user to eit her enable or disable the Transm it Ou tput
Drive r within the Transmit DS1/E1 LI U Block. If the TxON pin is pulled “Low”,
all 8 Channels are tr i-stated. When this p in is pulle d ‘High ’, tu rning on or of f t he
transmitters will be determined by the a ppropriate channe l re gisters (address
0x0Fn2, bit 3)
LOW = Disables the Transmit Output Driver within the Transmit DS1/E1 LIU
Block. In this set ting, t he TTIP and TRING output pins of all 8 channels will be
tri-stated.
HIGH = Enables the Transm it Output Driver within the Transm it DS1/E1 LI U
Block. In this sett ing, the cor responding TTIP and TRING output pi ns will be
enabled or disabl ed by programmi ng the appropri ate channe l re gister.
(address 0x0Fn2, bit 3)
NOTE: Whenever the transmitters are turned of f, the TTIP and TRING output
pins will be tri-stated.
TIMI N G I N TE R FAC E
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
MCLKIN A4 I - Ma ster Clock Input :
This pin is used to provide the timing reference for the internal
master clock of the device. The frequency of this clock is pro-
grammable from 8kHz to 16.384MHz in regis ter 0x0FE9.
E1MCLKnOUT A3 O12 LIU E1 Output Clock Refere nce
This output pin is defaulted to 2.048MHz, but can be programmed
to 4.096MHz, 8 .192MHz, or 16.384MHz in register 0x0FE4.
XRT86VL32
29
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
T1MCLKnOUT B4 O12 LIU T1 Output Clock Refer ence
This output pin is defaulted to 1.544 MHz , but can be programm ed
to output 3 .088MHz, 6. 176MHz, or 12. 352MHz i n regi ster 0x0 FE4.
E1OSCCLK P2 O 8 Framer E1 Output Clock Reference
This output pin is defaulted to 2.048 MHz , but can be programm ed
to 65.536MHz in register 0x011E.
T1OSCCLK P4 O 8 Framer T1 Output Clock Reference
This output pin is defaulted to 1.544 MHz , but can be programm ed
to output 49.408MHz in register 0x011E.
8KSYNC R2 O 8 8kHz Clock Output Reference
This pin is an out put r eference of 8kHz based on the MCLKIN
input. Therefore, the duty cycle of this output i s determ ined by the
time period of the input clock reference.
8KEXTOSC N4 I - External Oscillator Select
For normal o peration, this pin should not be used, or pul led “Low”.
This pin is inter nally pulled “Low” with a 50k Ω resistor.
ANALOG E5 OFactory Test Mode Pin
NOTE: For Internal Use Only
LOP N2 I - Loss of Power for E1 Only
This is a Loss of Power pin in the E1 applic ati on only. Upon
detecting LOP in E1 mode, the device will aut omatically transmit
the Sa5 and Sa6 bit to a di fferent pattern, so that the Receive ter-
minal can det ect a power failure in the netwo rk.
Please see registe r 0xn131 for the Transmit SA contr ol.
TIMI N G I N TE R FAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
30
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JTAG INTERFACE
The XRT86VL32 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry
specification for additional information on boundary scan operations.
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
TCK C7 I - Test clock: Boundar y Scan Test clock input:
The TCLK signal is t he clock for the TAP controller, and it
generat es the boundar y sc an data re gister clocki ng. The dat a
on TMS and TDI is loaded on the positive edge of TCK. Data
is obser ved at TDO on the falling edge of TCK.
TMS C6 I - Test Mode Sel ect: Bounda ry Scan Test Mode Select input.
The TMS signal control s the t ransiti ons of the TAP c ontroll er
in conjunction with the rising edge of the test clock ( TCK).
NOTE: For normal operation this pin MUST be pulled "High".
TDI B6 I - Test Data In: Boundary Scan Test dat a input
The TDI signal is the seri al test data input.
NOTE: This pin is internally pulled ’high’.
TDO D5 O 8 Test Data Out: Boundary Scan Test data output
The TDO signal is the serial test data output.
TRST A6 I - Test Reset Inp u t:
The TRST signal (Acti ve Low) async hronously reset s the T AP
controller to the Test-Logi c-Reset state.
NOTE: This pin is internally pulled ’high’
TESTMODE B11 I - Factory Test Mode Pin
NOTE: Thi s pin is internally pulled ’low’, and should be pulled
’low’ for normal operation.
aTESTMODE B5 I - Factory Test Mode Pin
NOTE: Thi s pin is internally pulled ’low’, and should be pulled
’low’ for normal operation.
ATP_Ring B2 I - ATP_Ring Test Pi n
This anal og tes t pi n is used for testing th e continuity between
the TTIP/TRING, RTIP/RRING of each channel and the on-
board tr ansforme r.
ATP_Tip C3 I - ATP_Tip Test Pin
This anal og tes t pi n is used for testing th e continuity between
the TTIP/TRING, RTIP/RRING of each channel and the on-
board tr ansforme r.
XRT86VL32
31
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
T4
U3
V8
V9
T10
V10
U11
R11
I/O 8Bidirectional Mic roprocesso r Data Bus
These pin s are used to driv e an d recei ve data ove r the bi-di rec-
tional dat a bus, whenever the Microprocesso r performs READ
or WRITE operations with the Microprocessor Interface of the
XRT86VL32 device.
When DMA interface is enabled, these 8-bit bid ir ectional data
bus is al so used by the T1/E1 Framer or the external DMA
Controller for st oring and retrieving information.
REQ0 R1 O 8 DMA Cycle Request Output—DMA Controller 0 (Write):
These output pins ar e used to indicate that DMA transfers
(W rite) are requested by the T1/E1 Framer.
On the transmit si de (i .e., To transm it data from exter nal DMA
contr oller to HDLC buffers withi n the XRT86VL32 ), DMA trans-
fers are only req uested when the tr ansm it buff er status bits
indicate that there is space fo r a complete mess age or cell.
The DMA Wri te cycle starts by T1/E1 Fram er asser ting the
DMA Reques t (REQ0) ‘low’, then the external DMA controller
should drive th e DMA Ackn owledge (ACK0) ‘low’ to indicate
that it is r eady to start the transfer. The external DM A controller
should place new data on the Microprocessor data bus each
time t he W ri te Signal i s Strobed low if the WR is configured as
a Wr it e Strobe. If WR is con fi gured as a direction si gnal, then
the external DMA control ler would pl ace new data on the
Microprocessor data bus each time the Read Signal (RD) is
Strobed low.
The Framer asserts this output pin (toggles it "Low") when at
least one of the T ransmi t HDLC buf fers are empty and can
receive one more HDLC message.
The Framer negat es this output pin (to ggles it “High” ) when the
HDLC buffer can no lon ger receive anot her HDLC message.
XRT86VL32
32
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REQ1 R3 O 8 DMA Cycle Request Output—DMA Controller 1 (Read):
These output pins ar e used to indicat e that DMA transfers
(Read) are requested by the T1/E1 Framer.
On the re cei v e si d e (i .e ., To tra n smit da ta fro m H D L C buffers
with in the XRT86VL32 to external DMA Contr oller), DMA t rans-
fers are only req uested when the receive buffer contains a
co mp let e m essage or cell.
The DMA Read cyc le st arts by T1/E1 Frame r assertin g the
DMA Reques t (REQ1) ‘low’, then the external DMA controller
should drive th e DMA Ackn owledge (ACK1) ‘low’ to indicate
that it is ready to r eceive the data. The T1/E1 Framer should
place new data on the Microprocessor data bus each time the
Read Signal is S trobed low if th e RD is configured as a Read
S t robe. I f RD is conf igured as a direct ion si gnal, then t he T1/ E1
Framer would place new dat a on the Microproces sor data bus
each time the Writ e Signal (WR) is Strobed low.
The Framer asser ts this output p in ( toggles it "Low") when one
of the Receive HDLC buf fer contains a complete HDLC mes-
sage that needs to be read by t he µC/µP.
The Framer negat es this output pin (to ggles it “High” ) when the
Receive HDLC buf fers are depl eted.
INT R8 O 8 Inte rrupt Request Output:
This act ive-low output signal will be asserted when t he
XRT86VL32 device is requesting interrupt ser vice from the
Microprocessor. This output pin should t ypically be connected
to the “ Interrupt Request” input of the Microproces sor.
The Framer will assert this active "Low" output (toggles it "Low"),
to the l ocal µP, anytim e it r equires interru pt service.
PCLK V1 I - Microprocessor Clock Input:
This cl ock inpu t si gnal is only used if the Mic roprocessor Inter-
face has been configured to operate in the Synchronous
Modes (e.g., Power PC 403 Mode). If the Microprocessor Inter-
face is config ured to operate in thi s m ode, then it will use this
clock signal to do the f ollowing.
1. To sample the CS*, WR*/R/W*, A[14:0], D[7:0], RD*/DS*
and DBEN input pins, and
2. To update the state of the D[7:0] and the RDY/DTACK
output signals.
NOTES:
1. The Microprocessor Interface can work with PCLK
freq uenci es ranging up to 33MHz .
2. This pin is inactive if the user has configured the
Microprocessor Interface to operate in either the In tel-
Asynchronous or the Motorola-Asynchronous Modes.
In this case, the user should tie this pin to GND .
When DMA interface is enabled, the PCLK input pi n is also
used by the T1/E1 Frame r t o latch in or latch ou t receive or out-
put data respectivel y.
iADDR U1 I - This Pin Must be Tied “Low” for Normal Operation.
This pi n is internall y pulled “Hi gh” with a 50k
Ω
res istor.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
33
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
fADDR T1 I - This Pin Must be Tied “High” for Normal Operation.
This pi n is internall y pulled “Low” with a 50k
Ω
re sisto r.
PTYPE0
PTYPE1
PTYPE2
V2
V4
T8
I - Microprocessor Type Inp ut:
These input pins p ermit the user to specify which t ype of Micro-
processor /Microcontroller to be inter faced to the XRT86VL32
device. The follow ing table presents the three different micro-
processor types that the XRT86VL32 supports.
NOTE: These pins are internally pulled “Low” with a 50k
Ω
resistor.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
0
1
1
°PType0
0
0
0
0
0
1
°PType1
°PType2
In tel Asynchronous
Motorola Asynchronous
IBM POWER PC 403
MICROPROCESSOR
TYPE
XRT86VL32
34
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RDY T3 O12 Ready/Data Transfer Acknowledge Output:
The exact behavior of this pin depends upon th e type of Micro-
proce ssor/Micr ocontroller the XRT86VL3 2 has been c onfigured
to operate in, as defi ned by the PTYPE[2:0] pins.
Intel Asynchronous Mode - RDY* - Ready Output
Ti s output pin will function as the “active-low” READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic low level, ONLY
when the Microprocessor Interface is ready t o complete or ter-
minate the curre nt READ or WRITE cycle. Once the Mi cropro-
cessor has determined that this input pin has toggled to the
logic “low” level, then it is now safe for it to move on and exe-
cute the next READ or WRITE cycl e.
If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is hol ding this out put pin at a logic “hi gh” level, then
the Micr oproces sor is expe cte d to extend this READ or WRITE
cycle, unti l i t detects this output pin being toggled to the logic
low level.
Motorola Asynchronous Mode - DTACK* - Dat a Transfer
Acknowledge Output
Ti s output pin will function as the “active-low” DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic low level, ONLY
when the Microprocessor Interface is ready t o complete or ter-
minate the curre nt READ or WRITE cycle. Once the Mi cropro-
cessor has determined that this input pin has toggled to the
logic “low” level, then it is now safe for it to move on and exe-
cute the next READ or WRITE cycl e.
If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is hol ding this out put pin at a logic “hi gh” level, then
the Micr oproces sor is expe cte d to extend this READ or WRITE
cycle, unti l i t detects this output pin being toggled to the logic
low level.
Power PC 403 Mode - RDY Ready Output:
This ou tput pi n will func tion as t he “active -high” READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic hi gh level, ONLY
when the Microprocessor Interface is ready t o complete or ter-
minate the curre nt READ or WRITE cycle. Once the Mi cropro-
cessor has sampled this signal being at the logic “high” level
upon the risi ng edge of PCLK, then it is now safe for i t to move
on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is hol ding this out put pin at a logic “l ow” level, then
the Micr oproces sor is expe cte d to extend this READ or WRITE
cycle, unti l i t samples this output pi n being at the logic low
level.
NOTE: The Microprocessor Interface will update the state of
thi s outp ut pin upon th e ri si ng edge of PCLK.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
35
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
U5
V5
R5
T6
U6
V6
R6
T7
V7
U9
R7
R9
R10
V11
I - Microproces sor In terface Address Bus I nput
These pins permit the Micropr ocessor to ident if y on-chip regis-
ters and Buffer/Memory locations within t he XRT86VL32
devi ce wheneve r it perf orms READ and WRITE operatio ns with
the XRT86VL32 dev ice.
NOTE: These pins are internally pulled “Low” with a 50k
Ω
resistor, except ADDR [8:13].
DBEN U4 I - Data Bus Enable Input pin.
This active- low input pi n permits the user to either enable or tri-
state the Bi- Directi onal Data Bus pins (D[7:0]), as des cri bed
below.
•Setting this input pin “low” enables the Bi-directional Data
bus.
•Setting this input pin “high” tri-states the Bi-directional Data
Bus.
ALE U8 I - Address Latch Enable Input Address Strobe
The exact behavior of this pin depends upon th e type of Micro-
proce ssor/Micr ocontroller the XRT86VL3 2 has been c onfigured
to operate in, as defi ned by the PTYPE[2:0] pins.
Intel-Asynchr onous Mode - ALE
This act ive-high input pi n is used to latc h the addr ess (present
at th e Micropr oces sor Int erfac e Address Bus pin s (A[14: 0]) int o
the XRT 86VL32 Micropro cess or Interf ace block and to indi cate
the start of a READ or WRITE cycle .
Pull ing this i nput pin “high” enables th e input bus driver s for th e
Address Bus input pins (A[14:0]). The contents of the Address
Bus wil l be la tched into th e XRT86VL32 Micr oproce ssor Inter-
face circui try, upon the falling edge of this inp ut si gnal.
Motorola-Asynchronous (68K) Mode - AS*
This act ive-low input pin is used to latch t he data residing on
the Address Bus, A[14:0] into the Microprocess or I nterface cir-
cuitry of the XRT86VL32 device.
Pull ing this in put pin “low” enables the input bus drivers f or the
Address Bus input pins. The contents of the Address Bus will
be latched int o the Microprocessor Interface circu itry, upon t he
ris ing edge of this signal.
Power PC 403 Mode - No Function -Ti e to GND:
This input pin has no role nor function and should be tied to
GND.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
36
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
CS V13 I - Microprocessor Interfac e—Chi p Select Input:
The use r mus t a ssert this acti ve low s ig nal i n order to sel ect t he
Microprocessor Inter face for READ and WRITE operat ions
between the Microprocessor and the XRT86VL32 on-chip reg-
isters and buffer/memory locations.
RD V3 I - Microproces sor In terface—Rea d Strobe Input:
The exact behavior of this pin depends upon th e type of Micro-
processor/Microcontroller the Framer has been configured to
operate in, as defined by the PT YPE[2:0] pi ns.
Inte l- Asynchronous Mode - RD* - READ Strobe Input:
This i nput pin will fun cti on as the RD* (Acti ve Low Read
Strobe) in put signal from the Microprocessor. Once this active-
low si gnal is assert ed, then the XRT86VL32 device will place
the contents of the addressed regis ter (or buf fer location) on
the
Microprocessor Interface Bi- directi onal data bus (D[7:0] ).
When t his signal is negated, then the Dat a Bus wil l be tri-
stated.
Motorol a-Asynchr onous (68K) Mode - DS* - Data Strobe:
This i nput pin will function as the DS* (Dat a Strobe) input sig-
nal.
Power PC 403 Mode - WE* - Writ e Enable Input:
This i nput pin will fun cti on as the WE* (Wr it e Enable) input pin.
Anytime the Mi croprocesso r Interface sampl e s this acti ve-lo w
input sign al (alon g with CS* and WR/R /W*) a lso bei ng assert ed
(at a l ogic low level) upon the rising edge of PCLK, then the
Microprocessor Interface wil l (upon the ver y sam e ri sing edge
of PCLK) latch the
contents on the Bi-Directional Data Bus (D[7:0]) into the “tar-
get” on-chip register or buffer location within the XRT86VL32
device.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
37
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
WR V12 I - Microprocessor Interface—Write Strobe Inpu t
The exact behavior of this pin depends upon th e type of Micro-
proce ssor/Micr ocontroller the XRT86VL3 2 has been c onfigured
to operate in, as defi ned by the PTYPE[2:0] pins.
Intel-Asynchr onous Mode - WR* - Write Strobe Input:
This input pi n funct ions a s the W R* (A cti ve Low WRI TE S t robe)
input signal from the Microprocessor. Once this acti ve-low sig-
nal is asserted, then the input buffers (associated with the Bi-
Directiona l Dat a Bus pin, D[7: 0]) wil l be enabled.
The Microprocessor Inter face will lat ch the contents on the Bi-
Directiona l Data Bus (into the “target” reg ister or addr ess loca-
tio n, wi thin the XRT86VL32) upon the rising edge of th is input
pin.
Motorol a-Asynchr onous Mode - R/W* - Rea d/Write Oper a-
tion Identific ati on Input Pin:
This pin is functionally equivalent to the “R/W *” input pin. In the
Motorola Mo de, a “READ” operation occurs if this pin is held at
a logi c “1”, coinc ident to a falli ng edge of the RD/DS* (Dat a
S t robe) i nput pin. Similarl y a WRITE operati on oc curs if thi s pin
is a t a l ogic “ 0”, c oin cident to a f all ing edge of the RD/ DS* (Dat a
Strobe) in put pin.
Power PC 403 Mode - R/W* - Read/Write Operation Identifi-
cation Input:
This input pin will function as the “Read/Write Operation Identi-
fication Input” pin.
Anytime the Mic roproc essor Interface s am ples this input signal
at a lo gic low ( while als o sampli ng the CS* i nput pin “l ow”) upon
the risin g edge of PCLK, then the Microprocessor Interface wi ll
(upon the very same rising edge of PCLK) latch the contents of
the Address Bus (A[14:0] ) into the M icr oproce ssor Interface cir-
cuit ry, in preparati on for this fort hcoming READ operati on. At
some point (later in this READ operation) the Microprocessor
wil l also assert t he DBEN*/OE* in put pin, and the Mi croproces -
sor Interf ace will then place the co ntents of the “target” r egister
(or address location within the XRT86VL 32 device) upon the
Bi-Directional Data Bus pins (D[7:0]), where it can be read by
the Microprocessor.
Anytime the Mic roproc essor Interface s am ples this input signal
at a logic high (while also sampling the CS* input pin a logic
“low”) upon the rising edge of PCLK, then the Microprocessor
Interface will (upon the very same ri sing edg e of PCLK) latch
the contents of the Address Bus (A[14:0]) int o the Microproces-
sor Inter face c ircui try, in p rep arati on f or the f orthco ming WRI TE
operation. At some point (later in this WRITE operation) th e
Micro process or will a ls o asser t th e RD* /DS*/WE* input pin, a nd
the Microprocessor Interface will then lat ch the contents of the
Bi-Di rectional Data Bus ( D[7:0]) into the contents of the “target”
register or buffer lo cation (wit hin the XRT86VL32).
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
38
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ACK0
ACK1
T2
U2
I - DMA Cycle Acknowledge Input—DMA Controller 0 (Write):
The exter nal DMA Controller will assert this input pin “Low”
when the following two conditi ons are met:
1. After the DMA Co ntr oller, within the Fram er has asserted
(toggled “Low” ), the Req_0 output si gnal.
2. When the external DMA Controller is ready to transfer
data from external memory to the selected Transmit
HDLC buff er.
At this point, the DMA transfer between the external memory
and the selected Transm it HDLC buffer may begin.
Aft er com plet ion of the D MA cycle, the ext er nal DMA C ontrol ler
wil l negate this input pin after the DMA Contr oller withi n the
Framer has negated the Req_0 o utput pin. The exter nal DMA
Controller mus t do th is in order to acknowledge the end of the
DMA cycl e.
DMA Cycle Acknowledge Input—DMA Controller 1 (Read):
The exter nal DMA Controller asserts this input pin “Low” when
the fol lowing two conditions are met:
1. After the DMA Co ntr oller, within the Fram er has asserted
(toggled "Low"), the Req_1 output signal.
2. When the external DMA Controller is ready to transfer
data from the selected Receive HDLC buffer to external
memory.
At this point, the DMA transf er between the sel ected Receive
HDLC buffer and the ext ernal memory may begin.
Aft er com plet ion of the D MA cycle, the ext er nal DMA C ontrol ler
wil l negate this input pin after the DMA Contr oller withi n the
Framer has negated the Req_1 o utput pin. The exter nal DMA
Controller wil l do this in order t o acknowledg e the end of the
DMA cycl e.
NOTE: This pin is internally pulled “ High” with a 50k
Ω
resistor.
BLAST U10 I - Last Cycle o f Burst Indi cator Input:
If t he Microprocessor Interface i s operating i n the Intel- I960
Mode , then this input pin is used to indicate (t o the Micropro-
cessor Interface block) that the current dat a transfer is the la st
data transfer within the c urrent burs t operation.
The Microprocessor shoul d assert this input pin (by t oggling it
“Low”) in order to denot e that the current READ or WRIT E
operation (wi thin a BURST o peration) is t he las t operatio n of
this BURST oper ation.
NOTES:
1. If the user has configured the Microprocessor
Interface to operate in the Intel-Asynchronous, the
Motorola-Asynchronous or the Power PC 403 Mode,
then he/ she should tie thi s in put pin to GND .
2. This pin is internally pulled “High” with a 50k
Ω
resistor.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
39
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
RESET P1 I - Hardware Reset Input
Reset i s an active low input. If thi s pin is pulled “Low” for more
than 10μS, the devi ce wil l be reset. When this occurs , all outpu t
will be ‘tri-stated’, and all internal registers will be reset to their
default values.
MICROPROCESSOR INTERFAC E
SIGNAL NAME BALL #TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL32
40
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER SUPPLY PINS (3.3V)
SIGNAL NAME BALL # TYPE DESCRIPTION
VDD D16
P3
R15
T9
PWR Framer Block Power Supply (I/O)
RVDD E3
J3 PWR Receiver Analog Power Supply for LIU Section
TVDD F3
K3 PWR Transmitter Analog Power Supply for LI U Section
POWER SUPPL Y PINS ( 1 .8 V)
SIGNAL NAME BALL # TYPE DESCRIPTION
DVDD18 B8
C4
J16
R13
U7
PWR Digit al Power Supply for LIU Sect ion
AVDD18 A2 PWR Analog Power Supply for LIU Sect ion
VDDPLL18 B1
C2
D2
D3
PWR Analog Power Supply for PLL
XRT86VL32
41
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
GROUND PINS
SIGNAL NAME BALL # TYPE DESCRIPTION
VSS A5
B14
C16
M15
M16
R4
T5
U16
GND Framer Block Gr ound
DGND C5 GND Digital Ground for LIU Sect ion
AGND B3 GND Analog Ground for LIU Sect ion
RGND E2
J2 GND Receiver Analog Ground f or LIU Sect ion
TGND F2
K2 GND Transmitt er Anal og Ground for LIU Sect ion
GNDPLL18 A1
C1
D1
D4
GND Analog Ground for PLL
NO CONNECT PINS
SIGNAL NAME TYPE DESCRIPTION
NC NC No Connect Pins
A15, A16, A17, A18, B15, B16, B17, B18, C13, C15, C17, C18, D13, D14, D17, D18,
E15, E16, E17, E18, F15, F16, F17, G1, G2, G3, G4, G17, G18, H1, H2, H3, H4, H18,
L1, L2, L3, L4, M1, M2, M3, M4, P16, P17, P18, R12, R14, R16, R17, R18, T11, T12,
T13, T14, T1 5, T17, T18, U12, U13, U14, U15, U17, U18, V14, V15, V1 6, V17, V18
XRT86VL32
42
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUMS
Power Supply.....................................................................
VDDIO .. ................................................ -0.5V to +3.465V
VDDCORE...............................................-0.5V to +1.890V
Power Rating PBGA Package..................................1.39W
(at zero air flow)
Storage Temperature ...............................-65°C to 150°C Input Logic Signal Voltage (Any Pin) .........-0. 5V to + 5.5V
Operati ng Temperature Range... ..............-40° C to 85°C ESD Protection (HBM)...........................................>2000V
Supply Volt age ...... ....... .. ....... GND-0.5V to +VDD + 0.5V Input Current (Any Pi n) .. ................. .......... ....... .. + 100mA
DC ELECTRICAL CHARACTERIST ICS
Test Conditions: TA = 25°C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5% unle ss otherwis e specified
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
ILL Data Bus Tri-State Bus Leakage Current -10 +10 µA
VIL Input Low voltage 0.8 V
VIH Input High Voltage 2.0 VDD V
VOL Output Low Voltage 0.0 0.4 V IOL = -1.6mA
VOH Output High Voltage 2.4 VDD V IOH = 40µA
IOC Open Drain Output Leakage Current µA
IIH Input High Voltage Current -10 10 µA VIH = VDD
IIL Input Low Voltage Cur rent -10 10 µA VIL = G N D
TABLE 4: XRT86VL32 POWER CONSUMPTION
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5% , TA=25°C, UNLESS OTHERWISE SPECIFIED
MODE SUPPLY
VOLTAGE IMPEDANCE TERMINATION
RESISTOR
TRANSFORMER RATIO TYP. MAX. UNIT TEST
CONDITIONS
RECEIVER TRANSMITTER
E1 3.3V 75ΩInternal 1:1 1:2 776 mW PRBS Pattern
E1 3.3V 120ΩInternal 1:1 1:2 724 mW PRBS Pattern
T1 3.3V 100ΩInternal 1:1 1:2 829 mW PRBS Pattern
XRT86VL32
43
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
AC ELECTRICAL CHARACTERISTICS TRANSMIT FRAMER (BASE RATE/NON-MUX)
Test Condit ions: TA = 25°C, VDD = 3.3V + 5% unless other w ise specifi ed
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
t1TxSER CLK to TxMSYNC del ay 234 nS
t2TxSERCLK to TxSYNC delay 230 nS
t3TxSERCLK to TxSER data del ay 230 nS
t4Rising Edge of TxSERCLK to Rising Edge of TxCH-
CLK 13 nS
t5Rising Edge of TxCHCLK to Valid TxCHN[ 4:0] Data 6nS
t6TxSERCLK to TxSIG delay 230 nS
t7TxSERCLK to TxFRACT delay 110 nS
FIGURE 2. FRAMER SYSTEM TRANSMIT TIMING DIAGRAM (BASE RATE/NON-MUX)
TxMSYNC
TxSERCLK
TxSER
TxSYNC
TxCHN[4:0]
(Output)
TxCHCLK
(Output)
TxCHN_0
(TxSIG)
TxCHN_1
(TxFRACT)
t1
t3
t5
t2
t4
t6
t7
ABCD
XRT86VL32
44
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (BASE RATE/NON-MUX)
Test Condit ions: TA = 25°C, VDD = 3.3V + 5% unless other w ise specifi ed
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
RxSERCLK as an Output
t8Rising Edge of RxSERCLK to Rising Edge of
RxCASYNC 4nS
t9Rising Edge of RxSERCLK to Rising Edge of
RxCRCSYNC 4nS
t10 Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output) 4nS
t11 Rising Edge of RxSERCLK to Rising Edge of
RxSER 6nS
t12 Rising Edge of RxSERCLK to Rising Edge of Valid
RxCHN[4: 0] dat a 6nS
RxSERCLK as an Input
t13 Rising Edge of RxSERCLK to Rising Edge of
RxCASYNC 8nS
t14 Rising Edge of RxSERCLK to Rising Edge of
RxCRCSYNC 8nS
t15 Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output) 10 nS
t15 Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Input) 230 nS
t16 Rising Edge of RxSERCLK to Rising Edge of
RxSER 10 nS
t17 Rising Edge of RxSERCLK to Rising Edge of Valid
RxCHN[4: 0] dat a 9nS
FIGURE 3. FRAMER SYSTEM RECEIVE TIMING DIAGRAM (RXSERCLK AS AN OUTPUT)
RxCRCSYNC
RxCASYNC
RxSERCLK
(Output)
RxSER
RxSYNC
RxCHN[4:0]
t
8
t9
t10
t11
t12
XRT86VL32
45
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
FIGURE 4. FRAMER SYSTEM RECEIVE TIMING DIAGRAM (RXSERCLK AS AN INPUT)
RxCRCSYNC
RxCASYNC
RxSERCLK
(Input)
RxSER
RxSYNC
RxCHN[4:0]
t13
t14
t15
t16
t17
XRT86VL32
46
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS TRANSMIT FRAMER (HMVIP/H100 MODE)
FIGURE 5. FRAMER SYSTEM TRANSMIT TIMING DIAGRAM (HMVIP AND H100 MODE)
NOTE: Se tup and Hold time is not valid from TxInClk to TxSERCLK as TxInClk i s used as the ti ming source for the back
plane interface and TxSERCLK is used as the timing source on the line side.
Test Condit ions: TA = 25°C, VDD = 3.3V + 5% unless other w ise specifi ed
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
t1TxSYNC Setup Time - HMVIP Mode 7nS
t2TxSYNC Hold Time - HMVIP Mode 4nS
t3TxSYNC Setup Time - H100 Mode 7nS
t4TxSYNC Hold Time - H100 Mode 4nS
t5TxSER Setup Time - HMVIP and H100 Mode 6nS
t6TxSER Hold Time - HMVIP and H100 Mode 3nS
t7TxSIG Set up Ti me - HMVIP and H100 Mode 6nS
t8TxSIG Hold Time - HMVIP and H100 Mode 3nS
TxSYNC
(H100 Mode)
TxCHN_0
(TxSIG)
t4
ABCD
t3
TxSERCLK
TxSER t5t6t7
t8
TxSYNC
(HMVIP Mode) t2
t1
TxInClk
(16MHz)
XRT86VL32
47
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (HMVIP/H100 MODE)
NOTE: Both RxSERCLK and RxSYNC are inputs
FIGURE 6. FRAMER SYSTEM RECEIVE TIMING DIAGRAM (HMVIP/H100 M ODE)
Test Condit ions: TA = 25°C, VDD = 3.3V + 5% unless other w ise specifi ed
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
t1RxSYNC Setup Time - HMVIP Mode 4nS
t2RxSYNC Hold Tim e - HMVIP Mode 3nS
t3RxSYNC Setup Time - H100 Mode 5nS
t4RxSYNC Hold Tim e - H100 Mode 3nS
t5Rising Edge of RxSERCLK to Rising Edge of
RxSER delay 11 nS
RxSYNC
(H100 Mode)
t4
t3
RxSER t5
RxSYNC
(HMVIP Mode) t2
t1
RxSERCLK
(16MHz)
XRT86VL32
48
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS TRANSMIT OVERHEAD FRAMER
Test Condit ions: TA = 25°C, VDD = 3.3V + 5% unless other w ise specifi ed
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
t18 TxSYNC Setup Time (Falling Edge TxSERCLK) 6nS
t19 TxSYNC Hold Time (Falling Edge TxSERCLK) 4nS
t20 Rising Edge of TxSERCLK to TxOHCLK 12 nS
FIGURE 7. FRAMER SYSTEM TRANSMIT OVERHEAD TIMING DIAGRAM
TxSERCLK
TxSYNC
t18 t19
TxOHCLK
t20
XRT86VL32
49
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
AC ELECTRICAL CHARACTERISTICS RECEIVE OVERHEAD FRAMER
Test Condit ions: TA = 25°C, VDD = 3.3V + 5% unless other w ise specifi ed
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
RxSERCLK as an Output
t21 Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output) 4nS
t22 Rising Edge of RxSERCLK to Rising Edge of RxO-
HCLK 6nS
t23 Rising Edge of RxSERCLK to Rising Edge of RxOH 8nS
RxSERCLK as an Input
t24 Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output) 12 nS
t24 Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Input) 230 nS
t25 Rising Edge of RxSERCLK to Rising Edge of RxO-
HCLK 12 nS
t26 Rising Edge of RxSERCLK to Rising Edge of RxOH 15 nS
FIGURE 8. FRAMER SYSTEM RECEIVE OVERHEAD TIMING DIAGRAM (RXSERCLK AS AN OUTPUT)
FIGURE 9. FRAMER SYSTEM RECEIVE OVERHEAD TIMING DIAGRAM (RXSERCLK AS AN INPUT)
RxSERCLK
(Output)
RxOHCLK
RxSYNC
RxOH
t21
t22
t23
RxOH Interface with RxSERCLK as an Input
RxOH
t24
t25
t26
RxSERCLK
(Input)
RxOHCLK
RxSYNC
XRT86VL32
50
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 5: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , V D D CORE = 1.8V + 5%, TA= -40° to 85°C, unless otherwise specified
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zer os before
RLOS is set
Input si gnal level at RLOS
RLOS De-asserted
15
12.5
32
20 dB
% ones
Cable attenuation @1024kHz
ITU-G.775, ETSI 300 233
R ec e iv e r Sen s it iv ity
(Short Haul with cable loss) 11 dB With nomi nal pul se ampl itude o f 3.0V
for 120Ω and 2. 37V for 75 Ω applica-
tion.
Receiver Sensitivi ty
(Long Haul with cable loss) 043 dB With nomi nal pul se ampl itude o f 3.0V
for 120Ω and 2. 37V for 75 Ω applica-
tion.
Input Impedance 15 kΩ
Input Jitter Tolerance:
1 Hz
10kHz-100kHz 37
0.3 UIpp
UIpp ITU G.823
Recove red C lock Jitter
Transfer Corner Frequency
Peaking Amplitude -20 0.5 kHz
dB ITU G.736
Jitter Attenuator Corner Fre-
quency (-3dB curve) (JABW=0)
(JABW=1) -10
1.5 -Hz
Hz ITU G.736
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
12
8
8
- - dB
dB
dB
ITU-G.703
XRT86VL32
51
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
TABLE 6: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless otherwise spe cif ied
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
Rece iver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS Clear
15
12.5
175
20
-
-
-
dB
% ones
Cable attenuation @772kHz
ITU-G.775, ETSI 300 233
Rec eiver S ensit ivity
(Short Haul with cable loss) 12 -dB With nomina l pulse ampli tude of 3.0V
for 1 00 Ω terminati o n
Rec eiver S ensit ivity
(Long Haul with cable loss)
Normal
Extended 0
0
-
36
45 dB
dB
With n omina l pulse amplit ude of 3.0 V
for 1 00 Ω te rmin at io n
Input Impedance 15 -kΩ
Jitter Tolerance:
1Hz
10kHz - 100kHz 138
0.4 -
--
-UIpp AT&T Pub 62411
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude -
-10 -
0.1 KHz
dB TR-TSY-000499
Jitter Attenuator Corner Frequency
(-3dB cur ve) - 3 Hz AT&T Pub 62411
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
-
-
-
14
20
16
-
-
-
dB
dB
dB
XRT86VL32
52
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 7: E1 T RANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless otherwise spe cif ied
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
AMI Output Pulse Am plitude :
75Ω Appli cation
120Ω Application 2.13
2.70 2.37
3.00 2.60
3.30 V
V
1:2 Transformer
Output Pul se W idth 224 244 264 ns
Output Pul se Width Rati o 0.95 -1.05 - ITU-G.7 03
Output Pul se Amplitude Ratio 0.95 -1.05 - ITU -G.7 03
Jitt er Added by the Tran sm it ter Output -0.025 0.05 UIpp Bro ad Band wit h ji tter free TCLK
appli ed to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
15
9
8
-
-
-
-
-
-
dB
dB
dB
ETSI 300 166
TABLE 8: E1 TRANSMIT RETURN LOSS REQUIREMENT
FREQUENCY RETURN LOSS
ETS 300166
51-102kHz 6dB
102-2048kHz 8dB
2048-3072kHz 8dB
XRT86VL32
53
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
TABLE 9: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C , unl ess otherwi se specified
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
AMI Output Pulse Am plitude : 2.4 3.0 3.60 V1:2 Transformer measured at DSX_1.
Output Pul se W idth 338 350 362 ns ANSI T1.102
Output Pul se W idth Imbalance - - 20 -ANSI T1.102
Output Pul se Am plitude Imbalance - - +200 mV ANSI T1.102
Jitt er Added by the Tran sm it ter Output -0.025 0.05 UIpp Bro ad Band wit h ji tter free TCLK
appli ed to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
-
-
-
17
12
10
-
-
-
dB
dB
dB
XRT86VL32
54
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
FIGURE 10. ITU G.703 PULSE T EMPLATE
TABLE 10: TRANSMIT PULSE MASK SPECIFICATION
Test Load I mp edance 75Ω Resistive (Coax) 120Ω R esistive (twist ed Pair)
Nominal Peak Voltage of a Mark 2.37V 3.0V
Peak voltage of a Space (no Mark) 0 + 0.237V 0 + 0.3V
Nominal Pulse width 244ns 244ns
Ratio of Posit ive and Negative Pulses Imbalance 0. 9 5 t o 1.0 5 0.95 to 1.05
10% 10%
10%10%
10% 10%
269 ns
(244 + 25)
194 ns
(244–50)
244 ns
219 ns
(244 – 25)
488 ns
(244 + 244)
0%
50%
20%
V = 100%
Nominal puls
e
Note – V corresponds to the nominal peak value.
20%
20%
XRT86VL32
55
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
FIGURE 11. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
TABLE 11: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE MAXIMUM CURVE
TIME (UI) NORMALIZED AMPLITUDE TIME (UI) NORMALIZED AMPLITUDE
-0.77 -.05V -0.77 .05V
-0.23 -.05V -0.39 .05V
-0.23 0.5V -0.27 .8V
-0.15 0.95V -0.27 1.15V
0.0 0.95V -0.12 1.15V
0.15 0.9V 0.0 1.05V
0.23 0.5V 0.27 1.05V
0.23 -0.45V 0.35 -0.07V
0.46 -0.45V 0.93 0.05V
0.66 -0.2V 1.16 0.05V
0.93 -0.05V
1.16 -0.05V
XRT86VL32
56
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 12: AC ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER SYMBOL MIN. TYP. MAX. UNITS
MCLKIN Clock Duty Cycle 40 -60 %
MCLKI N Clock Toleranc e -±50 -ppm
XRT86VL32
57
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The s ignals used for the Intel microproc essor in terface ar e: Add ress Latch Enable (ALE ), Read E nable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum
external glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The ALE
signal can be tied ’HIGH’ if this signal is not available, and the corresponding timing interface is shown in
Figure 13 and Table 14.
FIGURE 12. INTEL µP INTERFACE TIMING DURING PROGRAMMED I/O R EAD AND WRITE OPERATIONS WHEN ALE IS
NOT TIED ’H IG H ’
TABLE 13: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL PARAMETER MIN MAX UNITS
t0Valid Address to CS Fall ing Edge and ALE Rising
Edge 0 - ns
t1 ALE Falli ng Edge to RD Assert 5 - ns
t2RD Assert to RDY Assert -320 ns
NA RD Pulse Width (t2)320 -ns
t3ALE Falling Edge to WR Assert 5 - ns
t4WR Assert to RDY Assert -320 ns
NA WR Pulse Wid th (t4)320 -ns
t5ALE Pulse Width(t5)10 ns
CS
A
DDR[14:0]
ALE
DATA[7:0]
RD
WR
RDY
Valid Data for Readback Data Available to Write Into the LIU
READ OPERATION WRITE OPERAT ION
t0t0
t1
t4
t2
t3
Valid Address Valid Address
t5t5
XRT86VL32
58
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
FIGURE 13. INTEL µP INTERFACE TIMING DURING PROGRAMMED I/O R EAD AND WRITE OPERATIONS WHEN ALE IS
TIED ’HIGH ’
TABLE 14: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL PARAMETER MIN MAX UNITS
t0Valid Address to CS Falling Edge 0 - ns
t1CS Falli ng Edge to RD Assert 0 - ns
t2RD Assert to RDY Assert -320 ns
NA RD Pulse Width (t2)320 -ns
t3CS Falli ng Edge to WR Asser t 0 - ns
t4WR Assert to RDY Assert -320 ns
NA WR Pulse Wid th (t4)320 -ns
CS
A
DDR[14:0]
ALE
DATA[7:0]
RD
WR
RDY
Valid Data for Readbac k Data Available to Write Into the LIU
READ OPERATION WRITE OPERATION
t0t0
t1
t4
t2
t3
Valid Address Valid Address
XRT86VL32
59
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
MOTOROLA ASYCHRONOUS INTERFACE TIMING
The signals used in the Motorola microprocessor interface mode are: Address S t robe (AS), Data Strobe (DS),
Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing
of a Motorola 68000 mi cro pr oc essor fa mi ly. The interf ac e timing is shown in Figure 14. The I/O specifications
are shown in Table 15.
FIGURE 14. MOTOROLA ASYCHRONOUS MODE INTERFACE SIGNALS DURING PROGRAMMED I/O R EAD AND WRITE
OPERATIONS
TABLE 15: MOTOROLA ASYCHRONOUS MODE MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL PARAMETER MIN MAX UNITS
t0Valid Address to CS Falling Edge 0 - ns
t1CS Falli ng Edge to DS (P in RD_DS) Asse rt 0 - ns
t2DS Assert to DTACK Assert -320 ns
NA DS Pulse Width (t2)320 -ns
t3CS Falling Edge to AS (Pin ALE_AS) Falling Edge 0 - ns
CS
ADDR[6:0]
DATA[7:0]
RD_DS
WR_R/W
RDY_DTACK
V a l id D ata for Rea db ac k Da ta Av a ilable to Write Into the LIU
READ OP E RATION WRITE OPERATION
t0t0
t1
t2
Valid Address Valid Address
t3t3
t1
t2
ALE_AS
XRT86VL32
60
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER PC 403 SYCHRONOUS INTERFACE TIMING
The signals u sed in the P ower PC 403 Synchronus microprocessor interface mode are: Address St robe (AS),
Microprocessor Clock (uPCLK), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), Address and
Data bits. T he interfac e timin g is shown in Figure 15. The I/O s pecifi c ati ons are shown in Table 16.
FIGURE 15. POWER PC 403 INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
TABLE 16: POWER PC 403 MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL PARAMETER MIN MAX UNITS
t0Valid Address to CS Falling Edge 0 - ns
t1CS Falli ng Edge to WE Assert 0 - ns
t2WE Assert to TA Assert -320 ns
NA WE Pulse Width (t2)320 -ns
t3CS Falli ng Edge to TS Falling Edge 0 -
tdc μPCLK Duty Cycle 40 60 %
tcp μPCLK Clock Per iod 20 -ns
CS
ADDR[14:0]
DATA[7:0]
WE
R/W
TA
Valid Data for Readback Data Available to Write Into the LIU
READ OPERATION WRITE OPERATION
t0t0
t2
Valid Address Valid Address
t3t3
t1
t2
TS
uPCLK
tcp
tdc
XRT86VL32
61
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
ORDERING INFORMATION
PACKAGE DIMENSIONS
PRODUCT NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT86VL32IB 225 LEAD PBGA -400C to +8 5 0C
E
225 Ball Plastic Ball Grid Array
(19.0 mm x 19 .0 mm, 1.0mm p itch
PBGA)
Rev.
1.00
SYMBOL MIN MAX MIN MAX
A 0.049 0.096 1.24 2.45
A1 0.016 0.024 0.40 0.60
A2 0.013 0.024 0.32 0.60
A3 0.020 0.048 0.52 1.22
D 0.740 0.756 18.80 19.20
D1 0.669 BSC 17.00 BSC
D2 0.665 0.669 16.90 17.00
b 0.020 0.028 0.50 0.70
e 0.039 BSC 1.00 BSC
INCHES
MILLIMETERS
No t e : T he con tr ol dime nsion i s i n m i llim eter.
1
24 37
86
5
1
7
1
61
4
1
5
1
2
1
31
1
1
09
1
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
D
D1
DD1
A1
Feature /
Mark
D2
AA
1
A
2
A
3
e
b
(A1 corner feature is mfger
option)
Se ati n g P lane
62
NOTICE
EXAR Corporati on res er ves t he right to m ak e c hanges to the pr oduc ts contained in t his publication in order t o
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and m ay vary depen ding upon a user’s spec ific applic ation . While the info rmation in this publi cati on
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected t o cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corp oration r eceives, in writing, assurances to its sat isfaction that: (a) the risk of i njury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 E XAR Corpor at ion
Datasheet January 2007.
Reproduct ion, in part or whole, wit hout the prior written c ons ent of EXAR Corpor at ion is prohibit ed.
XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1. 2.0
REV ISI O N H ISTOR Y
REVISION # DATE DESCRIPTION
V1.2.0 Januar y 29, 2007 Relea sed to production.
