VIPER20ASPTR-E - STMicroelectronics

June 2006 Rev 2 1/34

VIPer20A-E

SMPS primary I.C.

General features

■Adjustable switching frequency up to 200 kHz

■Current mode control

■Soft start and shutdown control

■Automatic burst mode operation in stand-by

condition able to meet “blue angel” norm (<1w

total power consumption)

■Internally trimmed zener reference

■Undervoltage lock-out with hysteresis

■Integrated start-up supply

■Over-temperature protection

■Low stand-by current

■Adjustable current limitation

Description

All the devices are made using VIPower M0

Technology, combines on the same silicon chip a

state-of-the-art PWM circuit together with an

optimized, high voltage, Vertical Power MOSFET

(700V/ 0.5A).

Typical applications cover offline power supplies

with a secondary power capability of 10W in wide

range condition and 20W in single range or with

doubler configuration. It is compatible from both

primary or secondary regulation loop despite

using around 50% less components when

compared with a discrete solution. Burst mode

operation is an additional feature of this device,

offering the ability to operate in stand-by mode

without extra components.

Type VDSS InRDS(on)

VIPer20A-E

VIPer20ASP-E

VIPer20ADIP-E

700V

0.5A

18Ω

PENTAWATT HV

PENTAWATT HV (022Y)

DIP-8

POWERSO-10TM

www.st.com

Block diagram

VDD

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH

PWM

LATCH

FFFF

R/S

R2 R3

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER

0.5 V +

1.7

µs

delay

250 ns

Blanking

CURRENT

AMPLIFIER

ON/OFF

0.5V

6 V/A

4.5 V

FC00491

Contents VIPer20A-E

2/34

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Drain pin (Integrated Power MOSFET drain): . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Source pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 VDD pin (power supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Compensation pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.5 OSC pin (oscillator frequency): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Current mode topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.3 High voltage start-up current suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 External clock synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Primary peak current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7 Over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VIPer20A-E Contents

3/34

6 Electrical over stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Electrical over stress ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electrical data VIPer20A-E

4/34

1 Electrical data

1.1 Maximum rating

Table 1. Absolute maximum rating

Symbol Parameter Value Unit

VDS Continuous Drain-Source Voltage (TJ = 25 to 125°C) –0.3 to 700 V

IDMaximum Current Internally limited A

VDD Supply Voltage 0 to 15 V

VOSC Voltage Range Input 0 to VDD V

VCOMP Voltage Range Input 0 to 5 V

ICOMP Maximum Continuous Current ±2mA

VESD Electrostatic Discharge (R = 1.5kΩ; C = 100pF) 4000 V

ID(AR)

Avalanche Drain-Source Current, Repetitive or Not Repetitive

(TC = 100°C; Pulse width limited by TJ max; δ < 1%) 0.4 A

PTOT Power Dissipation at TC= 25ºC57 W

TJJunction Operating Temperature Internally limited °C

TSTG Storage Temperature -65 to 150 °C

VIPer20A-E Electrical data

5/34

1.2 Electrical characteristics

TJ = 25°C; VDD = 13V, unless otherwise specified

Table 2. Power section

(1) On Inductive Load, Clamped.

Table 3. Supply section

Table 4. Oscillator section

Symbol Parameter Test conditions Min Typ Max Unit

BVDS Drain-Source Voltage ID = 1mA; VCOMP = 0V 700 V

IDSS Off-State Drain

Current

VCOMP = 0V; Tj = 125°C

VDS = 700V 1.0 mA

RDS(on)

Static Drain-Source

On Resistance

ID = 0.4A

ID = 0.4A; TJ= 100°C

15.5 18

Ω

tfFall Time ID = 0.2A; VIN =300V (1) Figure 7 100 ns

tr Rise Time ID = 0.4A; VIN = 300V (1) Figure 7 50 ns

Coss Output Capacitance VDS = 25V 90 pF

Symbol Parameter Test conditions Min Typ Max Unit

IDDch

Start-Up Charging Current VDD = 5V; VDS = 35V

Figure 6, Figure 11 -2 mA

IDD0

Operating Supply Current VDD = 12V; FSW = 0kHz

Figure 6 12 16 mA

IDD1 Operating Supply Current VDD = 12V; Fsw = 100kHz 13 mA

IDD2 Operating Supply Current VDD = 12V; Fsw = 200kHz 14 mA

VDDoff Undervoltage Shutdown Figure 6 7.5 8 9 V

VDDon Undervoltage Reset Figure 6 11 12 V

VDDhyst Hysteresis Start-up Figure 6 2.4 3 V

Symbol Parameter Test conditions Min Typ Max Unit

FSW Oscillator Frequency Total

Variation

RT=8.2KΩ; CT=2.4nF

VDD=9 to 15V;

with RT± 1%; CT± 5%

(see Figure )(see Figure 14)

90 100 110 KHz

VOSCIH Oscillator Peak Voltage 7.1 V

VOSCIL Oscillator Valley Voltage 3.7 V

Electrical data VIPer20A-E

6/34

Table 5. Error amplifier section

Table 6. PWM comparator section

Table 7. Shutdown and overtemperature section

Symbol Parameter Test conditions Min Typ Max Unit

VDDREG VDD Regulation Point ICOMP=0mA (see Figure 5) 12.6 13 13.4 V

∆VDDreg Total Variation TJ = 0 to 100°C 2%

GBW Unity Gain Bandwidth

From Input =VDD to

Output = VCOMP

COMP pin is open

Figure 15

150 KHz

AVOL Open Loop Voltage Gain COMP pin is open

Figure 15 45 52 dB

GmDC Transconductance VCOMP=2.5V(see Figure 5) 1.1 1.5 1.9 mA/V

VCOMPLO Output Low Level ICOMP=-400µA; VDD=14V 0.2 V

VCOMPHI Output High Level ICOMP=400µA; VDD=12V 4.5 V

ICOMPLO Output Low Current Capability VCOMP=2.5V; VDD=14V -600 µA

ICOMPHI Output High Current

Capability VCOMP=2.5V; VDD=12V 600 µA

Symbol Parameter Test conditions Min Typ Max Unit

HID ∆VCOMP / ∆IDPEAK VCOMP = 1 to 3 V 4.267.8V/A

VCOMPoff VCOMP Offset IDPEAK = 10mA 0.5 V

IDpeak Peak Current Limitation VDD = 12V; COMP pin open 0.50.670.9 A

tdCurrent Sense Delay to Turn-

Off ID = 1A 250 ns

tbBlanking Time 250 360 ns

ton(min) Minimum On Time 350 1200 ns

Symbol Parameter Test conditions Min Typ Max Unit

VCOMPth Restart Threshold (see Figure 8) 0.5 V

tDISsu Disable Set Up Time (see Figure 8) 1.7 5 µs

Ttsd Thermal Shutdown

Temperature (see Figure 8) 140 170 190 °C

Thyst Thermal Shutdown Hysteresis (see Figure 8) 40 °C

VIPer20A-E Thermal data

7/34

2 Thermal data

Table 8. Thermal data

Symbol Parameter PENTAWATT PowerSO-10™(1)

1. When mounted using the minimum recommended pad size on FR-4 board.

DIP-8 Unit

RthJA Thermal Resistance Junction-pin Max 20 °C/W

RthJC Thermal Resistance Junction-case Max 2.0 2.0 °C/W

RthJC Thermal Resistance Ambient-case Max 70 60 35 (2)

2. On multylayer PCB.

°C/W

Pin description VIPer20A-E

8/34

3 Pin description

3.1 Drain pin (Integrated Power MOSFET drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an

integrated high voltage current source which is switched off during normal operation. The

device is able to handle an unclamped current during its normal operation, assuring self

protection against voltage surges, PCB stray inductance, and allowing a snubberless operation

for low output power.

3.2 Source pin:

Power MOSFET source pin. Primary side circuit common ground connection.

3.3 VDD pin (power supply):

This pin provides two functions :

●It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below

8V, the start-up current source is activated and the output power MOSFET is switched off

until the VDD voltage reaches 11V. During this phase, the internal current consumption is

reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to

ground. After that, the current source is shut down, and the device tries to start up by

switching again.

●This pin is also connected to the error amplifier, in order to allow primary as well as

secondary regulation configurations. In case of primary regulation, an internal 13V

trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a

voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to

stuck the output of the transconductance amplifier to the high state. The COMP pin

behaves as a constant current source, and can easily be connected to the output of an

optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the

error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage

will be somewhat higher than the nominal one, but still under control.

3.4 Compensation pin

This pin provides two functions :

●It is the output of the error transconductance amplifier, and allows for the connection of a

compensation network to provide the desired transfer function of the regulation loop. Its

bandwidth can be easily adjusted to the needed value with usual components value. As

stated above, secondary regulation configurations are also implemented through the

COMP pin.

●When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a

zero duty cycle for the power MOSFET. This feature can be used to switch off the

converter, and is automatically activated by the regulation loop (no matter what the

configuration is) to provide a burst mode operation in case of negligible output power or

open load condition.

VIPer20A-E Pin description

9/34

3.5 OSC pin (oscillator frequency):

An Rt-Ct network must be connected on that to define the switching frequency. Note that

despite the connection of Rt to VDD, no significant frequency change occurs for VDD varying

from 8V to 15V. It provides also a synchronisation capability, when connected to an external

frequency source.

Figure 1. Connection diagrams (top view)

Figure 2. Current and voltage convention

PENTAWATT HV PENTAWATT HV (022Y) DIP-8 PowerSO-10TM

13V

OSC

COMP SOURCE

DRAINVDD

VCOMP

VOSC

VDD VDS

ICOMP

IOSC

IDD ID

FC00020

Typical circuit VIPer20A-E

10/34

4 Typical circuit

Figure 3. Offline power supply with auxiliary supply feedback

Figure 4. Offline power supply with optocoupler feedback

AC IN

+Vcc

GND

BR1

TR2

C10

TR1

VIPer20

13V

OSC

COMP SOURCE

DRAINVDD

FC00401

C11

AC IN

BR1

TR2

C10

TR1

+Vcc

GND

VIPer20

ISO1

13V

OSC

COMP SOURCE

DRAINVDD

FC00411

C11

VIPer20A-E Operation description

11/34

5 Operation description

5.1 Current mode topology:

The current mode control method, like the one integrated in the devices, uses two control loops

- an inner current control loop and an outer loop for voltage control. When the Power MOSFET

output transistor is on, the inductor current (primary side of the transformer) is monitored with a

SenseFET technique and converted into a voltage VS proportional to this current. When VS

reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the

outer voltage control loop defines the level at which the inner loop regulates peak current

through the power switch and the primary winding of the transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input

voltage feedforward characteristic of the current mode control. This results in improved line

regulation, instantaneous correction to line changes, and better stability for the voltage

regulation loop.

Current mode topology also ensures good limitation in case there is a short circuit. During the

first phase the output current increases slowly following the dynamic of the regulation loop.

Then it reaches the maximum limitation current internally set and finally stops because the

power supply on VDD is no longer correct. For specific applications the maximum peak current

internally set can be overridden by externally limiting the voltage excursion on the COMP pin.

An integrated blanking filter inhibits the PWM comparator output for a short time after the

integrated Power MOSFET is switched on. This function prevents anomalous or premature

termination of the switching pulse in case there are current spikes caused by primary side

capacitance or secondary side rectifier reverse recovery time.

5.2 Stand-by mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode

operation allowing voltage regulation on the secondary side. The transition from normal

operation to burst mode operation happens for a power PSTBY given by :

Where:

LP is the primary inductance of the transformer. FSW is the normal switching frequency.

ISTBY is the minimum controllable current, corresponding to the minimum on time that the

device is able to provide in normal operation. This current can be computed as :

tb + td is the sum of the blanking time and of the propagation time of the internal current sense

and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY

may be affected by the efficiency of the converter at low load, and must include the power

drawn on the primary auxiliary voltage.

PSTBY

---LPI2STBYFSW=

ISTBY

tbtd

+()VIN

-----------------------------=

Operation description VIPer20A-E

12/34

As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase

above the 13V regulation level, forcing the output voltage of the transconductance amplifier to

low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power

switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as

VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates

again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty

cycle is much lower than the minimum one when in normal operation. The equivalent switching

frequency is also lower than the normal one, leading to a reduced consumption on the input

main supply lines. This mode of operation allows the VIPer20A-E to meet the new German

"Blue Angel" Norm with less than 1W total power consumption for the system when working in

stand-by mode. The output voltage remains regulated around the normal level, with a low

frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because

of the output capacitors and low output current drawn in such conditions.The normal operation

resumes automatically when the power gets back to higher levels than PSTBY

5.3 High voltage start-up current suorce

An integrated high voltage current source provides a bias current from the DRAIN pin during

the start-up phase. This current is partially absorbed by internal control circuits which are

placed into a standby mode with reduced consumption and also provided to the external

capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage

threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The

start-up current generator is switched off, and the converter should normally provide the

needed current on the VDD pin through the auxiliary winding of the transformer, as shown on

(see Figure 11).

In case there are abnormal conditions where the auxiliary winding is unable to provide the low

voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the

external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the

device goes back to the inactive state where the internal circuits are in standby mode and the

start-up current source is activated. The converter enters a endless start-up cycle, with a start-

up duty cycle defined by the ratio of charging current towards discharging when the VIPer20-E

tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle

while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.

This low value start-up duty cycle prevents the application of stress to the output rectifiers as

well as the transformer when a short circuit occurs.

The external capacitor CVDD on the VDD pin must be sized according to the time needed by the

converter to start up, when the device starts switching. This time tSS depends on many

parameters, among which transformer design, output capacitors, soft start feature, and

compensation network implemented on the COMP pin. The following formula can be used for

defining the minimum capacitor needed:

where:

IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2

values.

tSS is the start up time of the converter when the device begins to switch. Worst case is

generally at full load.

VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).

CVDD

IDDtSS

VDDhyst

--------------------

VIPer20A-E Operation description

13/34

The soft start feature can be implemented on the COMP pin through a simple capacitor which

will be also used as the compensation network. In this case, the regulation loop bandwidth is

rather low, because of the large value of this capacitor. In case a large regulation loop

bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high

performance compensation network together with a separate high value soft start capacitor.

Both soft start time and regulation loop bandwidth can be adjusted separately.

If the device is intentionally shut down by tying the COMP pin to ground, the device is also

performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.

This voltage can be used for supplying external functions, provided that their consumption does

not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched

shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state

until the input voltage is removed.

5.4 Transconductance error amplifier

The VIPer20A-E includes a transconductance error amplifier. Transconductance Gm is the

change in output current (ICOMP) versus change in input voltage (VDD). Thus:

The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:

This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP:

AVOL = Gm x ZCOMP

where Gm value for VIPer20A-E is 1.5 mA/V typically.

Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances.

An impedance Z can be connected between the COMP pin and ground in order to define the

transfer function F of the error amplifier more accurately, according to the following equation

(very similar to the one above):

F(S) = Gm x Z(S)

The error amplifier frequency response is reported in for different values of a simple resistance

connected on the COMP pin. The unloaded transconductance error amplifier shows an internal

ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP pin to

achieve different compensation level. A capacitor will provide an integrator function, thus

eliminating the DC static error, and a resistance in series leads to a flat gain at higher

frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20

As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to

avoid any high frequency interference.

Is also possible to implement a slope compensation when working in continuous mode with

duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the

classical compensation network, and Q1 is injecting the slope compensation with the correct

polarity from the oscillator sawtooth.

∂lCOMP

∂VDD

-------------------=

ZCOMP

∂VCOMP

∂ICOMP

-------------------- 1

--------∂VCOMP

∂VDD

------------------------

×==

Operation description VIPer20A-E

14/34

5.5 External clock synchronization:

The OSC pin provides a synchronisation capability when connected to an external frequency

source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.

If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is

sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through

the optotransistor.

5.6 Primary peak current limitation

The primary IDPEAK current and, consequently, the output power can be limited using the

simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on

the COMP pin in order to limit the primary peak current of the device to a value:

where:

The suggested value for R1+R2 is in the range of 220KΩ.

5.7 Over-temperature protection

Over-temperature protection is based on chip temperature sensing. The minimum junction

temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is

170ºC. The device is automatically restarted when the junction temperature decreases to the

restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)

IDPEAK

VCOMP 0.5–

HID

--------------------------------=

VCOMP 0.6 R1R2

-------------------

×=

VIPer20A-E Operation description

15/34

5.8 Operation pictures

Figure 5. VDD Regulation point Figure 6. Undervoltage lockout

Figure 7. Transition time Figure 8. Shutdown action

Figure 9. Breakdown voltage vs temperature Figure 10. Typical frequency variation

ICOMP

ICOMPHI

ICOMPLO

DDreg

Slope =

Gm i n mA/ V

FC00150

VDDon

IDDch

IDD0

VDD

VDDoff

VDS= 35 V

Fsw = 0

IDD

VDDhyst

FC00170

VDS

tf tr

10% Ipeak

10% VD

90% VD

FC00160

VCOMP

VOSC

tDISsu

ENABLE

DISABLE

ENABLE

VCOMPth

FC00060

Temperature (°C)

FC00180

0 20406080100120

0.95

1.05

1.1

1.15

BVDSS

(Normalized)

Temperature (°C)

0 20 40 60 80 100 120 140

-5

-4

-3

-2

-1

FC00190

(%)

Operation description VIPer20A-E

16/34

Figure 11. Behaviour of the high voltage current source at start-up

Figure 12. Start-up waveforms

Ref.

UNDERVOLTAGE

LOCK OUT LOGIC

15 mA1 mA

3 mA

2 mA

15 mA

VDD DRAIN

SOURCE

VIPer20

Auxiliary primary

winding

VDD

VDDoff

VDDon

Start up duty cycle ~ 12%

CVDD

FC00101A

VIPer20A-E Operation description

17/34

Figure 13. Over-temperature protection

SC 101 91

tsd

-T

h yst

ts c

dd on

dd off

co m p

Operation description VIPer20A-E

18/34

Figure 14. Oscillator

OSC

VDD

~360Ω

CLK

FC00050

Fsw

40kHz

15nF

22nF

Forbidden area

Ct(nF) = Fsw(kHz)

880

1 2 3 5 10 20 30 50

100

200

300

500

1,000

Rt (kΩ)

Frequency (kHz)

Oscillator frequency vs Rt and Ct

Ct = 1.5 nF

Ct = 2.7 nF

Ct = 4.7 nF

Ct = 10 nF

FC00030FC00030

For Rt > 1.2kΩ and Ct ≤ 40KHz

VIPer20A-E Operation description

19/34

Figure 15. Error amplifier frequency response

Figure 16. Error amplifier phase response

0.001 0.01 0.1 1 10 100 1,000

(20)

Frequency (kHz)

Voltage Gain (dB)

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00200

0.001 0.01 0.1 1 10 100 1,000

(50)

100

150

200

Frequency (kHz)

Phase (°)

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00210

Operation description VIPer20A-E

20/34

Figure 17. Mixed soft start and compensation Figure 18. Latched shut down

Figure 19. Typical compensation network Figure 20. Slope compensation

Figure 21. External clock sinchronisation Figure 22. Current limitation circuit example

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

C1 +C2

+C3

AUXILIARY

WINDING

FC00431

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

Shutdown Q1

R2R3

FC00440

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

FC00451

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

R1R2

C1 R3

FC00461

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

10 kΩ

FC00470

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

FC00480

VIPer20A-E Electrical over stress

21/34

6 Electrical over stress

6.1 Electrical over stress ruggedness

The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or

lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages

most of the time. However in some cases, the voltage surges coupled through the transformer

auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events

may trigger the VDD internal protection circuitry which could be damaged by the strong

discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be

implemented to improve the application immunity to such surges.

Figure 23. Input voltage surges protection

Bulk capacitor

(Optional)

22nF

Auxilliary winding

13V

OSC

COMP SOURCE

DRAIN

VDD

VIPerXX0

39R

Layout VIPer20A-E

22/34

7 Layout

7.1 Layout considerations

Some simple rules insure a correct running of switching power supplies. They may be

classified into two categories:

– Minimizing power loops: The switched power current must be carefully analysed and

the corresponding paths must be as small an inner loop area as possible. This avoids

radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a

better efficiency by eliminating parasitic inductances, especially on secondary side.

– Using different tracks for low level and power signals: Interference due to mixing of

signal and power may result in instabilities and/or anomalous behaviour of the device

in case of violent power surge (Input overvoltages, output short circuits...).

In case of VIPer, these rules apply as shown on (see Figure 24).

– Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized.

– C6 must be as close as possible to T1.

– Signal components C2, ISO1, C3, and C4 are using a dedicated track connected

directly to the power source of the device.

Figure 24. Recommended layout

VIPerXX0

13V

OSC

COMP SOURCE

DRAINVDD

ISO1

Fr om input

diodes bridge

To secondary

f i l t er i n g and l o ad

FC00500

VIPer20A-E Package mechanical data

23/34

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.

These packages have a Lead-free second level interconnect . The category of second Level

Interconnect is marked on the package and on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:

www.st.com.

Package mechanical data VIPer20A-E

24/34

Table 9. Pentawatt HV Mechanical data

Figure 25. Package dimension

Dim

mm. inch

Min Typ Max Min Typ Max

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.11

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 15.60 17.30 6.14 0.681

L1 14.60 15.22 0.575 0.599

L2 21.20 21.85 0.835 0.860

L3 22.20 22.82 0.874 0.898

L5 2.60 3 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 4.50 5.60 0.177 0.220

R 0.50 0.02

V4 90°

Diam 3.65 3.85 0.144 0.152

P023H3

VIPer20A-E Package mechanical data

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Table 10. Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical data

Figure 26. Package dimension

Dim

mm. inch

Min Typ Max Min Typ Max

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.110

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 16.42 17.42 0.646 0.686

L1 14.60 15.22 0.575 0.599

L3 20.52 21.52 0.808 0.847

L5 2.60 3.00 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 5.00 5.70 0.197 0.224

R 0.50 0.02 0.020

V4 90°90°

Diam 3.65 3.85 0.144 0.154

DIA

LL1

EResin between

leads

Package mechanical data VIPer20A-E

26/34

Figure 27. Package dimensions

Table 11. DIP-8 Mechanical data

Dim.

mm Inch

Min Typ Max Min Typ Max

A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150

Z 1.52 0.060

VIPer20A-E Package mechanical data

27/34

Figure 28. Package dimension

Table 12. PowerSO-10 mechanical data

Dim.

mm Inch

Min Typ Max Min Typ Max

A 3.35 3.65 0.132 0.144

A1 0.00 0.10 0.000 0.004

B 0.40 0.60 0.016 0.024

C 0.35 0.55 0.013 0.022

D 9.40 9.60 0.370 0.378

D1 7.40 7.60 0.291 0.300

e 1.27 0.050

E 9.30 9.50 0.366 0.374

E1 7.20 7.40 0.283 0.291

E2 7.20 7.60 0.283 0.300

E3 6.10 6.35 0.240 0.250

E4 5.90 6.10 0.232 0.240

F 1.25 1.35 0.049 0.053

h 0.50 0.002

H 13.80 14.40 0.543 0.567

L 1.20 1.80 0.047 0.071

q 1.70 0.067

α0o 8

Package mechanical data VIPer20A-E

28/34

Figure 29. Power Pad layout

Figure 30. Tube shipment

Table 13. Tube shipment

Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)

Casablanca 50 1000 532 10.4 16.4 0.8

Muar 50 1000 532 4.9 17.2 0.8

VIPer20A-E Package mechanical data

29/34

Figure 31. Reel shipment

Note: All dimensoin are in mm.

Table 14. Reel dimension

Base Q.ty 600

Bulk Q.ty 600

A (max) 330

B (min) 1.5

C (± 0.2) 13

F 20.2

G (± 0.2) 24.4

N (min) 60

T (max) 30.4

Package mechanical data VIPer20A-E

30/34

Figure 32. Tape shipment

Note: All dimensions are in mm.

Table 15. Tape dimension

Tape width W 24

Tape Hole Spacing P0 (± 0.1) 4

Component Spacing P 24

Hole Diameter D (± 0.1/-0) 1.5

Hole Diameter D1 (min) 1.5

Hole Position F (± 0.05) 11.5

Compartment Depth K (max) 6.5

Hole Spacing P1 (± 0.1) 2

VIPer20A-E Package mechanical data

31/34

Figure 33. Pentawatt HV tube shipment ( no suffix )

Note: All dimensions are in mm.

Figure 34. Dip-8 Tube shipment (no suffix)

Note: All dimensions are in mm.

Table 16. Tube dimension

Base Q.ty 50

Bulk Q.ty 1000

Tube length (± 0.5 ) 532

A 18

B 33.1

C (± 0.1) 1

Table 17. Tube dimension

Base Q.ty 20

Bulk Q.ty 1000

Tube length (± 0.5 ) 532

A 8.4

B 11.2

C (± 0.1) 0.8

Order code VIPer20A-E

32/34

9 Order code

Table 18. Order code

Part number Package

VIPer20A-E PENTAWATT HV

VIPer20A-22-E PENTAWATT HV (022Y)

VIPer20ADIP-E DIP-8

VIPer20ASP-E PowerSO-10

VIPer20A-E Revision history

33/34

10 Revision history

Table 19. Revision history

Date Revision Changes

28-Sep-2005 1 Initial release.

21-Jun-2006 2 New template, few updates

VIPer20A-E

34/34

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