NB4N121KMNGEVB NB4N121KMNGEVB Evaluation Board User's Manual Board Name: NB4N121KMNGEVB Device Name: NB4N121KMN http://onsemi.com EVAL BOARD USER'S MANUAL Description Board Features * Fully assembled evaluation board with Device-Under- The NB4N121K Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of the device under test NB4N121K. The NB4N121K is a Clock differential input fanout distribution device with 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply. Clock input pins incorporate an internal 50 W on die termination resistors. Output drive current at IREF (Pin 1) for 1X load is selected by connecting a 0 kW to 1 kW external resistor to GND. To drive a 2X load, connect the IREF Pin 1 through 20 kW to 50 kW external resistors. The NB4N121K specifically guarantees low output-to-output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N121K's performance to distribute low skew clocks across the backplane or the motherboard. The device is packaged in a low profile 8 x 8 mm 52-pin QFN package. This user's manual provides detailed information on the board's contents, layout and use. The manual should be used in conjunction with the NB4N121K data sheet which contains full technical details on device specifications and operation. (c) Semiconductor Components Industries, LLC, 2012 February, 2012 - Rev. 2 * * * * Test (DUT) soldered mounted. The device may be demounted and replaced by a test fixture socket (ANTARES Test Technology, P/N FP0052QN0805C, 3350 Scott Blvd., Bldg 58, Santa Clara, CA 95054, Phone: (408) 988-6800, www.antares-att.com,) for manual insertion of different sample device units. Accommodates the electrical characterization of the NB4N121K in the QFN52 package Equal length input and output data lines to minimize skew measurement calibration. Default 1X output drive (50 W load) with optional 2X load capability (25 W load) selectable by installing pulldown resistors and adjusting board RREF setting on IREF (pin1). Adjustable RREF resistor potentiometer for fine tuning output drive current (amplitude) levels. Single + 3.3 V Operation for direct LOW Impedance probe connection (50 W to GND). Appendix 1: Device Information Appendix 2: Schematics Appendix 3: IREF Pin Load Plot Appendix 4: Bill of Materials, Board Stackup 1 Publication Order Number: EVBUM2072/D NB4N121KMNGEVB Board Map VCC and GND Supply Connections C2 and C3 Power Supply Caps Not Used RREF Trimpot 0 to 50 kW Figure 1. Front Figure 2. Back Front Notes: 3. Back D.U.T. area detail: (See Figure 3) Odd numbered resistors R17 to R81 are populated for 1X load. Even numbered resistors are not populated. The even numbered resistors may be repopulated with 50 W (to GND) components to convert the board to 2X load use with 50 W scope input impedance loading (presents a 25 W parallel load to the device outputs). Even numbered "series shorting" resistors R17 to R81 are populated zero ohm value. These may be repopulated with a series resistor value to improve signal integrity. Components C1, C4, C5, C6, and C7 are 0.01 mF bypass caps. 1. VCCO and VCC contacts must be ganged and connected together to the positive 3.3 V supply. 2. CLKSEL is not used (no SMA). Back Notes: 1. C2 and C3 are power supply caps 2. RREF trimpot is connected from IREF to GND to select output drive for 1X (0 to 1 kW; Short to GND) or 2X loading (20 K to 50 kW; Open or Short to VCC). See Appendix 3: Device IREF pin 1 load plot of RREF vs. IREF current http://onsemi.com 2 NB4N121KMNGEVB Figure 3. Back D.U.T. Area Detail Test and Measurements Setup Details: Step 1: Basic Equipment * Signal Generator * Oscilloscope * Power Supply * Voltmeter * Matched High-Speed Coax Cables with SMA Connectors Step 2: Board Test Connections Setup: (1X Load configuration, IREF pin shorted to GND) VCC, VCCO (Note 1) Signal Generator OUT OUT NB4L121K Oscilloscope VTCLK 50 W Coax 50 W Coax CLK Qx CLK Qx VTCLK Trigger 50 W Coax 50 W Coax IN IN IREF GND Figure 4. NB4N121KMNGEVB Evaluation Board Connector Configuration Table 1. Power Supply Connections Positive and GND supplies must be connected to anvil clips for proper operation. Bridge VCC and VCCO board connection together. Board Connector Pin Supply Value Device Pin VCC, VCCO (Note 1) VCC 3.0 to 3.6 V 7, 26, 39, 52 GND GND 0V 2 IREF (Note 2) RREF to GND For 1x loading: 0 to 50 kW For 2x loading: 20 K to 50 kW 1 EXPOSED PAD Vias GND Thermal Conduit Exposed Pad 1. Short together and connect to VCC supply. See Appendix 4: Board Lamination Stackup 2. See Appendix 3: Device IREF pin 1 Load Plot of RREF vs. IREF Current http://onsemi.com 3 NB4N121KMNGEVB Input Pins and Signals Table 1. Input/Output Board to Device Pin Connections Board Connector Device Pin Name Device Pin VTCLK VTCLK 3 CLK CLK 4 CLK and CLK pins require differential LVPECL levels swinging around an acceptable common mode voltage per datasheet. Internal impedance matching resistor of 50 W is provided for driver termination from input pin to the respective VTx pin. Typically the VTx pins are connected to a VTT of VCC-2.0 V. The differential inputs can be driven single ended per the datasheet. CLK CLK 5 VTCLK VTCLK 6 Q20 Q20 8 Q20 Q20 9 Q19 Q19 10 Q19 Q19 11 Q18 Q18 12 Q19 Q19 13 Q17 Q17 14 Q17 Q17 15 Q16 Q16 16 Q16 Q16 17 Q15 Q15 18 Q15 Q15 19 Q14 Q14 20 Q14 Q14 21 Q13 Q13 22 Q13 Q13 23 Q12 Q12 24 Q12 Q12 25 Q11 Q11 27 Q11 Q11 28 Q10 Q10 29 Q10 Q10 30 Q9 Q9 31 Q9 Q9 32 Q8 Q8 33 Q8 Q8 34 Q7 Q7 35 Q7 Q7 36 Q6 Q6 37 Q6 Q6 38 Q5 Q5 40 Q5 Q5 41 Q4 Q4 42 Q4 Q4 43 Q3 Q3 44 Q3 Q3 45 Q2 Q2 46 Q2 Q2 47 Output pairs in use must always be balance in each pins loading and termination even if only one side of an output pair is delivered to receiver or scope. Do not unbalance an output pair by loading or probing only one line. Unused outputs should be left floating open. The Rs resistors values are zero W, but may be changed to value such as 6 to 12W to improve signal integrity. For 1X loading, set RREF potentiometer between 0 and 1 kW to GND for 1X loading (see Appendix 1: Device IREF pin 1 load plot of RREF vs. IREF current). For 50 W (Low Impedance) probes with High Bandwidth (>1 GHz): The odd numbered Serial Resistors R17 to R81 positions are populated with zero W resistors. The even numbered Parallel Loading resistors R18 to R82 should not be populated (open). Scope module inputs will provide proper termination 50 W to GND. Un-probed outputs will need to be externally loaded with 50 W to GND for proper balanced operation. For High Impedance Probes, low input capacitance probe with High Bandwidth (>1 GHz), odd numbered Series Resistors positions R17 to R81 are populated with 0 W value components. The even numbered Parallel Loading resistors R18 to R82 should also all be populated with 50 W (to GND) components for proper termination. For 2X loading, set the RREF between 20 K and 50 kW to GND or tie IREF directly to VCC. For 50 W (Low Impedance) probes with High Bandwidth (>1 GHz), the odd numbered Serial Resistors R17 to R81 positions should be populated with zero W value components. All even numbered Parallel Loading resistors R18 to R82 should have 50 W value components installed. A typical scope (probe) 50 W impedance in parallel with the installed even numbered Parallel Loading 50 W resistors R18 to R82 will present a 25 W (2X) load to the device. Un-probed outputs will need to be externally loaded with 50W to GND to present the proper 25 W load to the device. For High Impedance Probes, low input capacitance probe with High Bandwidth (>1 GHz), odd numbered Series Resistors positions R17 to R81 are populated with 0 W value components. The even numbered Parallel Loading resistors R18 to R82 should also all be populated with 25 W (to GND) components for proper termination. Q1 Q1 48 Low Impedance Probes: Q1 Q1 49 Q0 Q0 50 Q0 Q0 51 Use 50 W (Low Impedance) probes with High Bandwidth (>1 GHz). The odd numbered Resistors R18 to R82 positions should be populated with 50 W value components. Output Pins and Signals http://onsemi.com 4 NB4N121KMNGEVB Step 3: Electrical Measurements A typical scope (probe) 50 W impedance in parallel with the installed odd numbered 50 W Resistor value will present a 25W load to the device. Un-probed outputs will need to be externally loaded with 25 W to GND for proper operation. Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. High Impedance Probes: Use a high impedance, low input capacitance probe with High Bandwidth (>1 GHz) and repopulate odd numbered Resistors R18 to R82 (25 W value). APPENDIXES Appendix 1: Device Information MARKING DIAGRAM Device Under Test: NB4N121K Package Case Identification, Device Marking Diagram, Device Function Diagram, Output Loading Diagram, Pinout Diagram, Pin Description 1 52 1 xxxxxxxxx xxxxxxxxx AWLYYWWG XXXXXXXXX A WL YY WW G 52 QFN-52 CASE 485M MN SUFFIX Figure 5. Package Case Identification = Device Code = Assembly Site = Wafer Lot = Year = Work Week = Pb-Free Package Figure 6. Device Marking Diagram Q0 1X Load Qx Q0 RS1C Z0 = 50 W RS2C Z0 = 50 W Q1 HCSL Driver Q1 CLK CLK Q19 Qx Q19 RL1B 50 RREFA RL2B 50 CL1D 2 pF Q20 VCC GND RREF IREF Q20 Figure 7. Device Function Diagram Figure 8. Output Loading Diagram RS1C = 0 W, RREFA = 0-1 kW for 1X Load, 20 K-50 K for 2X Load RLxB may be open for 1X load (supplied by scope input module, may be 50 W for 2X load to present a 25 W load with scope 50 W input module impedance. http://onsemi.com 5 Exposed Pad (EP) Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VCC NB4N121KMNGEVB 52 40 IREF 1 GND 51 50 49 48 47 46 45 44 43 42 41 39 VCC 2 38 Q6 VTCLK 3 37 Q6 CLK 4 36 Q7 CLK 5 35 Q7 VTCLK 6 34 Q8 33 Q8 NB4N121K VCC 7 Q20 8 32 Q9 Q20 9 31 Q9 Q19 10 30 Q10 Q19 11 29 Q10 Q18 12 28 Q11 Q18 13 27 Q11 15 16 17 18 19 20 21 22 23 24 25 VCC Q12 Q12 Q13 Q13 Q14 Q14 Q15 Q15 Q16 Q16 Q17 26 Q17 14 Figure 9. Pinout Diagram Table 2. PIN DESCRIPTION Pin Name I/O Description 1 IREF Output Output current programming pin to select 1X or 2X load. Connect a selected resistor from IREF pin to GND (See Appendix 3: Device IREF pin 1 load plot of RREF vs. IREF current. 2 GND - Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 3, 6 VTCLK, VTCLK - Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to self-oscillation. 4 CLK LVPECL Input CLOCK Input (TRUE) 5 CLK LVPECL Input CLOCK Input (INVERT) 7, 26, 39, 52 VCC - 8, 10, 12, 14, 16, 18, 20, 22, 24, 27, 29, 31, 33, 35, 37, 40, 42, 44, 46, 48, 50 Q[20-0] HCSL Output Output (INVERT) 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 30, 32, 34, 36, 38, 41, 43, 45, 47, 49, 51 Q[20-0] HCSL Output Output (TRUE) Exposed Pad EP GND Positive Supply pins. VCC pins must be externally connected to a power supply to guarantee proper operation. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat-sinking conduit for proper thermal operation. (Note 1) http://onsemi.com 6 NB4N121KMNGEVB Appendix 2: Schematics J3 2 3 4 J4 5 1 2 2 1 R51 0 2 DNI R50 2 1 R49 0 DNI R44 1 2 3 4 DNI R48 5 5 CON_SMA_ST 1 1 2 2 2 5 CON_SMA_ST 1 2 3 4 J42 DNI R52 5 CON_SMA_ST 1 2 3 4 J41 5 CON_SMA_ST 1 2 3 4 J11 VCC VCCO 5 CON_SMA_ST 1 2 3 4 J10 0.1 mF 5 CON_SMA_ST 1 2 3 4 J38 C5 CON_SMA_ST 1 2 3 4 J37 3 5 2 CON_SMA_ST 1 2 3 4 J8 POTBOU3269W0-50 K CON_SMA_ST 1 2 3 4 J7 1 CON_SMA_ST 1 1 DNI R42 2 2 1 2 DNI R46 2 0 0 1 2 1 0 1 0 1 R47 R45 1 5 Figure 10. Pins 1 to 13 http://onsemi.com 7 R43 R41 1 2 3 4 5 6 7 8 9 10 11 12 13 IREF GND VTCLK CLK CLK VTCLK VCC Q20 Q20 Q19 Q19 Q18 Q18 Figure 11. Pins 14 to 26 http://onsemi.com 8 J21 J20 J19 J16 J29 J30 J15 J14 J13 J12 J35 J36 5 5 5 5 5 1 2 2 1 DNI R70 DNI R74 DNI R76 1 R83 2 2 2 2 2 1 5 5 5 5 5 CON_SMA_ST 1 2 3 4 2 3 4 5 CON_SMA_ST 1 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 DNI R78 DNI R80 DNI R68 1 2 2 2 2 1 2 1 1 0 0 1 1 R77 R79 DNI R66 DNI R62 2 0 0 1 2 1 2 1 R73 DNI R64 DNI R72 0 0 1 R75 1 0 0 1 R81 CON_SMA_ST 1 1 2 2 2 2 1 2 DNI R84 DNI R82 5 2 3 4 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 2 3 4 2 2 0 0 R61 2 R63 2 1 R69 1 R71 1 1 1 R65 1 R67 0 0 14 15 16 17 18 19 20 21 22 23 24 25 26 Q17 Q17 Q16 Q16 Q15 Q15 Q14 Q14 Q13 Q13 Q12 Q12 VCCO NB4N121KMNGEVB NB4N121KMNGEVB CON_SMA_ST 1 5 1 1 R17 2 1 0 1 R5 2 1 0 39 38 37 36 35 34 33 32 31 30 29 28 27 0 2 1 DNI R2 2 1 5 DNI R4 1 1 R9 2 0 2 5 1 DNI R10 2 5 2 0 R11 1 R13 2 1 DNI R12 1 2 5 1 2 R15 0 2 1 R55 R53 5 DNI R16 2 2 1 1 1 0 DNI R56 2 0 2 1 DNI R54 Figure 12. Pins 27 to 39 http://onsemi.com 9 J28 4 3 2 CON_SMA_ST 1 5 J27 4 3 2 CON_SMA_ST 1 5 J26 4 3 2 CON_SMA_ST 1 5 J25 4 3 2 CON_SMA_ST 1 0 J22 4 3 2 CON_SMA_ST 1 DNI R14 J6 4 3 2 CON_SMA_ST 1 2 J5 4 3 2 CON_SMA_ST 1 2 J33 4 3 2 CON_SMA_ST 1 DNI R8 J32 4 3 2 CON_SMA_ST 1 5 0 R3 1 5 DNI R20 1 2 1 R1 2 VCC Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11 DNI R6 J2 4 3 2 CON_SMA_ST 1 2 1 2 0 R7 1 5 2 0 R19 4 3 2 CON_SMA_ST 1 DNI R18 2 J1 4 3 2 J31 NB4N121KMNGEVB J24 5 2 3 4 5 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 DNI R58 1 2 2 2 2 1 0 0 2 1 1 R57 1 R59 DNI R36 2 1 2 2 0 0 1 R35 0 0 1 2 1 2 1 R33 1 2 2 2 1 2 R39 R37 1 R31 1 R29 R23 2 0 0 R21 2 2 2 0 0 1 1 1 R27 1 R25 40 41 42 43 44 45 46 47 48 49 50 51 52 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VCC Figure 14. Schematic Bypass and Supply Connector Details 5 DNI R60 DNI R34 DNI R32 1 1 DNI R26 DNI R22 DNI R24 0 0 TP3 KEYSTONE 5016 2 3 4 CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 5 2 1 1 2 1 2 2 2 2 1 1 J23 J48 J40 2 3 4 5 DNI R30 DNI R28 DNI R40 DNI R38 http://onsemi.com CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 2 3 4 5 CON_SMA_ST 1 2 3 4 CON_SMA_ST 1 10 J39 J34 J18 J17 J49 J50 J51 J52 GND J43 1 6 2 7 3 8 4 9 5 + C3 C4 + C2 C1 C6 VCCO VCC TP2 KEYSTONE 5016 VCC VCCO 1 TP1 KEYSTONE 5016 C7 VCCO VCC Figure 13. Pins 40 to 52 CON DSUB09-RAMP-788796 NB4N121KMNGEVB Appendix 3: Device IREF Pin 1 Load Plot of RREF vs. IREF Current 32 30 Ityp @ 50 kW: 29.3 mA 28 26 IREF 24 22 20 3.0 V 3.3 V 3.6 V +20C 14.54 mA/27.15 mA 15.06 mA/28.66 mA 15.65 mA/29.97 mA +85C 14.92 mA/27.42 mA 15.42 mA/29.33 mA 15.86 mA/30.60 mA +130C 15.05 mA/26.93 mA 14.60 mA/29.25 mA 16.03 mA/30.80 mA 18 Ityp @ 1 kW: 15.4 mA 16 14 0 10 20 30 RREF (K) Figure 15. Device IREF pin 1 Load Plot of RREF vs. IREF Current http://onsemi.com 11 40 50 NB4N121KMNGEVB Appendix 4: Bill of Materials, Board Lamination Stackup, and Fabrication Notes Bill of Materials Table Top Bot Description Value 0 5 Cap, Chip, 0.1 mF, 0603, 50 V, 10% X7R 0.1 mF C1, C4, C5, C6, C7 0 2 Cap, Chip, 10 mF, Tant "C", 25 V, 10% 10 mF C2, C3 1 0 ANTARES 52 QFN Socket 4 2-56 Pem Nuts DUT1 TP1, TP2, TP3 KEYSTONE 5016 (or similar) 3 46 0 1 Source Source P/N FP0052QN0805C Connector, SMA, Straight Johnson J43 0 42 Res, Chip, 0 W, 0603, 1/16 W, 5% 0 0 1 0-50 K POTENTIOMETER, TOP ADJUST 0-50 kW Reference Designators Alternative construction option: ANTARES Test Technology 3350 Scott Blvd., Bldg 58, Santa Clara, CA 95054, Phone: (408) 988-6800, www.antares-att.com 142-0701-201 J1, J2, J3, J4, J5, J6, J7, J8, J10, J11, J12, J13, J14J15, J16, J17, J18, J19, J20, J21, J22, J23, J24, J25, J26, J27, J28, J29, J30, J31, J32, J33, J34, J35, J36, J37, J38, J39, J40, J41, J42, J48, J49, J50, J51, J52 CON DSUB09- RAMP-788796 J43 (Optional - Not Supplied) R1, R3, R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25, R27, R29, R31, R33, R35, R37, R39, R41, R43, R45, R47, R49, R51, R53, R55, R57, R59, R61, R63, R65, R67, R69, R71, R73, R75, R77, R79, R81, R83 BOURNS 3269W-1-503 R85 Board Lamination Stackup: Dielectric is FR4 (interlayer between 1-2, 2-3, 3-4, 4-5, 5-6). Layers #1 (Topside) and #6 (Bottomside) are signal path copper (trace width 0.014). LAMINATION DIAGRAM Layer Number Layer Name Copper Thickness Dielectric Thickness Layer Material Trace Width EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE 1 2 3 4 5 6 TOP GND PWR1 PWR2 GND BTN 1/2 OZ. 0.014 0.008 See Note 1 0.005 See Note 1 Adjust See Note 1 0.005 See Note 1 0.008 See Note 1 1 OZ. N/A 1 OZ. N/A 1 OZ. N/A 1 OZ. N/A 1/2 OZ. 0.014 FINISHED PCB THICKNESS TO BE: 0.100 10% http://onsemi.com 12 NB4N121KMNGEVB Board Fabrication Notes: (Unless otherwise specified) 1. ARTWORK: Fabricate using ADC artwork No. AZ10035 Rev A. Drill locations determined by ADC file AZ10035NC.DRL 2. MATERIAL: High temp FR4 - 170C Tg 3. BOARD THICKNESS: Refer to stacking diagram for finished board thickness. 4. TWIST AND WARP: Board twist shall not exceed 0.5% (0.005 in.) per linear inch. 5. PLATING: Copper thickness for internal and external layers is specified in the stacking diagram. Finished PCB to be electrodeposited hard gold plate, type 1 (99.7% min gold), grade C (knoop hardness 130-200), class X, 3-10 micro inches thick, over entire board surface. Selective plating is not required. 7. SOLDERMASK: Apply soldermask, color: green, type: LP1, per artwork provided. If VIA plugs are required, plug pattern will be supplied with artwork. 8. SILKSCREEN: To be white, non-conductive ink per artwork. No ink is to be on plated thru hole or surface mount pads. Silkscreen lines and text width are to be 0.006 minimum. 9. SOLDERABILITY: Plated holes shall not be rough or irregular so as to prevent proper solder wicking. 10. DRILL CHART: Hole sizes specified are finished hole sizes, unless otherwise specified: Standard plated hole tolerance is 0.003 Standard non-plated hole tolerance is 0.002 11. IMPEDANCE: Impedance controlled layers: 1, 6. 12. APPROVAL: 100% continuity and isolation test required for each fabricated PCB. Final test data must be cross referenced to the IPC-D-356 file provided. A verification stamp is required on each PCB. A TDR report shall be provided for each impedance controlled layer at the time of shipment. Final acceptance shall be determined by these layers having a characteristic impedance of 50 ohms 10%. Vendor can make line width adjustments on impedance controlled conductor widths of 0.0005. All other artwork deviations must have prior approval from R&D ADC. Hole Plating: 0.011 minimum barrel avg. / 0.009 absolute minimum. Absolute maximum to be determined by PCB vendor based on the required finished hole diameter. Hole diameters are after plating unless otherwise specified. 5.1 - Surface pads in this area to be free from any irregularities or defects that might hinder proper performance of the pad. 6. ANNULAR RING: Annular ring to be 0.005 minimum with top to bottom registration to be within 0.003. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative EVBUM2072/D