MC14506UBD - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATA 1

MC14506UB

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The MC14506UB is an expandable AND–OR–INVERT gate with inhibit

and 3–state output. The expand option allows cascading with any other gate,

which may be carried as far as desired as long as the propagation delay

added with each gate is considered. For example, the second AOI gate in

this device may be used to expand the first gate, giving an expanded 4–wide,

2–input AOI gate. This device is useful in data control and digital multiplexing

applications.

•3–State Output

•Separate Inhibit Line

•Diode Protection on All Inputs

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage – 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current (DC or Transient),

per Pin ± 10 mA

PDPower Dissipation, per Package† 500 mW

Tstg Storage Temperature – 65 to + 150

_

C

TLLead Temperature (8–Second Soldering) 260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_

C From 65

_

C To 125

_

C

Ceramic “L” Packages: – 12 mW/

_

C From 100

_

C To 125

_

C

LOGIC DIAGRAM

AA1

BA2

CA3

DA4

EA5

INH 6

DIS 14

EB13

DB12

CB11

BB10

AB9

3–STATE

OUTPUT DISABLE

15 ZA

7 ZB

VDD = PIN 16

VSS = PIN 8

Z = (AB + CD + E + I)



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXUBCP Plastic

MC14XXXUBCL Ceramic

MC14XXXUBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

v

(Vin or Vout)

v

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

TRUTH TABLE

A B C D E Inhibit Disable Z

0 0 0 0 1 0 0 1

0 X 0 X 1 0 0 1

0 X X 0 1 0 0 1

X 0 0 X 1 0 0 1

X 0 X 0 1 0 0 1

1 1 X X X X 0 0

X X 1 1 X X 0 0

X X X X 0 X 0 0

X X X X X 1 0 0

X X X X X X 1 High

Impedance

X = Don’t Care

MOTOROLA CMOS LOGIC DATAMC14506UB

2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

– 55

_

C 25

_

C 125

_

C

Unit

Characteristic

Symbol

VDD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

VOL 5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

Input Voltage

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIL 5.0

10

15

—

1.0

2.0

2.5

—

2.25

4.50

6.75

1.0

2.0

2.5

—

1.0

2.0

2.5

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

4.0

8.0

12.5

—

4.0

8.0

12.5

2.75

5.50

8.25

—

4.0

8.0

12.5

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH 5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0) Cin — — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package) IDD 5.0

10

15

—

1.0

2.0

4.0

—

0.002

0.004

0.006

1.0

2.0

4.0

—

30

60

120

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

IT5.0

10

15

IT = (0.6 µA/kHz) f + IDD

IT = (1.1 µA/kHz) f + IDD

IT = (1.7 µA/kHz) f + IDD

µAdc

Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

**The formulas given are for the typical characteristics only at 25

_

C.

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

DB

EB

DISABLE

ZA

VDD

AB

BB

CB

DA

CA

BA

AA

VSS

ZB

INH

EA

MOTOROLA CMOS LOGIC DATA 3

MC14506UB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25

_

C)

Characteristic Symbol VDD Min Typ # Max Unit

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH, tTHL 5.0

10

15

—

100

50

40

200

100

80

ns

Data Propagation Delay Time

tPLH = (1.7 ns/pF) CL + 210 ns

tPLH = (0.66 ns/pF) CL + 77 ns

tPLH = (0.5 ns/pF) CL + 50 ns

tPLH 5.0

10

15

—

295

110

75

580

225

180

ns

tPHL = (1.7 ns/pF) CL + 185 ns

tPHL = (0.66 ns/pF) CL + 62 ns

tPHL = (0.5 ns/pF) CL + 40 ns

tPHL 5.0

10

15

—

270

95

65

480

175

140

ns

Expand Propagation Delay Time

tPLH = (1.7 ns/pF) CL + 95 ns

tPLH = (0.66 ns/pF) CL + 42 ns

tPLH = (0.5 ns/pF) CL + 25 ns

tPLH 5.0

10

15

—

180

75

50

430

160

125

ns

tPHL = (1.7 ns/pF) CL + 115 ns

tPHL = (0.66 ns/pF) CL + 47 ns

tPHL = (0.5 ns/pF) CL + 30 ns

tPHL 5.0

10

15

—

200

80

55

330

110

90

ns

Inhibit Propagation Delay Time

tPLH = (1.7 ns/pF) CL + 135 ns

tPLH = (0.66 ns/pF) CL + 67 ns

tPLH = (0.5 ns/pF) CL + 40 ns

tPLH 5.0

10

15

—

220

100

65

500

225

160

ns

tPHL = (1.7 ns/pF) CL + 145 ns

tPHL = (0.66 ns/pF) CL + 62 ns

tPHL = (0.5 ns/pF) CL + 35 ns

tPHL 5.0

10

15

—

230

95

60

400

175

150

ns

3–State Propagation Delay Time

“1” to High Impedance tPHZ 5.0

10

15

—

60

45

35

150

110

90

ns

“0” to High Impedance tPLZ 5.0

10

15

—

90

55

40

225

140

100

ns

High Impedance to “1” tPZH 5.0

10

15

—

110

50

40

300

125

100

ns

High Impedance to “0” tPZL 5.0

10

15

—

170

70

50

425

175

125

ns

*The formulas given are for the typical characteristics only at 25

_

C.

#Data labelled “Typ” Is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

Figure 1. Typical Voltage Transfer Characteristics

(a) Expand Inputs (b) Data Inputs

161412108.06.04.02.00

16

14

12

10

8.0

6.0

4.0

2.0

0

Vin, INPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

abc

c

ab

a

bc

VDD = 15 Vdc

10 Vdc

5.0 Vdc

a

b

c

TA = + 125

°

C

TA = + 25

°

C

TA = – 55

°

C

UNUSED INPUTS

CONNECTED TO

VSS

161412108.06.04.02.00

16

14

12

10

8.0

6.0

4.0

2.0

0

Vin, INPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

a

b

c

TA = + 125

°

C

TA = + 25

°

C

TA = – 55

°

C

A AND B CONNECTED TO Vin

ENABLE INPUT CONNECTED TO

VDD. OTHER INPUTS CONNECTED

TO VSS.

VDD = 15 Vdc

10 Vdc

5.0 Vdc

bc

a

b

ac

bc

a

MOTOROLA CMOS LOGIC DATAMC14506UB

4

Figure 2. Typical Output Source

Characteristics Test Circuit Figure 3. Typical Output Sink

Characteristics Test Circuit

EXTERNAL

POWER

SUPPLY

IOH

VOH

VDD

16

VSS

8

ZA

ZB

INH

AA

BA

CA

DA

EA

AB

BB

CB

DB

EB

DIS

VDD

16

VOL

IOL

EXTERNAL

POWER

SUPPLY

ZA

ZB

INH

AA

BA

CA

DA

EA

AB

BB

CB

DB

EB

DIS

VSS

8

Figure 4. 3–State Leakage Current

Test Circuit Figure 5. Typical Power Dissipation

Test Circuit

VDD

ITL

16

VSS

8

ZA

ZB

INH

AA

BA

CA

DA

EA

AB

BB

CB

DB

EB

DIS

PULSE

GENERATOR

50% DUTY CYCLE

0.01

µ

F

CERAMIC

VDD 16

ZA

ZB

INH

AA

BA

CA

DA

EA

AB

BB

CB

DB

EB

DIS

VSS

8CLCL

IDD

500

µ

F

B

A

MOTOROLA CMOS LOGIC DATA 5

MC14506UB

Figure 6. Switching Time Test Circuit and Waveforms

(Data Inputs)

16

VSS

8

ZA

ZB

INH

AA

BA

CA

DA

EA

AB

BB

CB

DB

EB

DIS

PULSE

GENERATOR

CL

VDD

CL

20 ns 20 ns

VDD

VSS

VOH

VOL

OUTPUT

INPUT 90%

50%

10%

tPHL tPLH

50%

90%

10%

tTHL tTLH

VDD Vout VDD

16

ZA

ZB

INH

AA

BA

CA

DA

EA

AB

BB

CB

DB

EB

DIS

VSS

8

PULSE

GENERATOR

B

A

CL1 k

A

B

S2

20 ns 20 ns

DISABLE

INPUT 90%

50%

10%

tPLZ tPZL VOH

VOL

10%

tPZH

tPHZ

90%

10% 90%

OUTPUT

≈

2.5 V @ VDD = 5 V,

10 V AND 15 V

≈

2 V @ VDD = 5 V

≈

6 V @ VDD = 10 V

≈

10 V @ VDD = 15 V

S1

*To test other side of circuit connect to this output and

change switch (S1) to other expand input (E).

SWITCH POSITIONS

TEST S1 S2

tPLZ A A

tPHZ B B

tPZL A A

tPZH B B

Figure 7. Switching Time Test Circuit and Waveforms

(For 3–State Output)

MOTOROLA CMOS LOGIC DATAMC14506UB

6

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

FC

S

HGD

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

–T–

FE

G

NK

C

SEATING

PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.93

B0.240 0.295 6.10 7.49

C––– 0.200 ––– 5.08

D0.015 0.020 0.39 0.50

E0.050 BSC 1.27 BSC

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

H0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA 7

MC14506UB

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

RX 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided

in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,

including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent

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MC14506UB/D

*MC14506UB/D*

◊