SEMICONDUCTOR
13-101
Features
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . ±15V
• Low “ON” Resistance (Typ) . . . . . . . . . . . . . . . . . . 25Ω
• High Current Capability (Typ) . . . . . . . . . . . . . . . . 80mA
• Break-Before-Make Switching
- Turn-On Time (Typ) . . . . . . . . . . . . . . . . . . . . . .370ns
- Turn-Off Time (Typ) . . . . . . . . . . . . . . . . . . . . . 280ns
• No Latch-Up
• Input MOS Gates are Protected from Electrostatic
Discharge
• DTL, TTL, CMOS, PMOS Compatible
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Description
This family of CMOS analog switches offers low resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
operating signal voltage and current. rON remains
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
0oC and 75oC. rON is nominally 25Ω for HI-5048 through
HI-5051 and HI-5046A and HI-5047A and 50Ω for HI-5040
through HI-5047.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at 25oC).
This family of switches also features very low power
operation (1.5mW at 25oC).
There are 14 devices in this switch series which are
differentiated by type of switch action and value of RON (see
Functional Description). All devices are available in 16 lead
DIP packages. The HI-5040 and HI-5050 switches can
directly replace IH-5040 series devices except IH5048, and
are functionally compatible with the DG180 and DG190
family. Each switch type is available in the -55oC to 125oC
and 0oC to 75oC performance grades.
Functional Description Functional Block Diagram
TYPICAL DIAGRAM
PART NUMBER TYPE rON
HI-5040 SPST 50Ω
HI-5041 Dual SPST 50Ω
HI-5042 SPDT 50Ω
HI-5043 Dual SPDT 50Ω
HI-5044 DPST 50Ω
HI-5045 Dual DPST 50Ω
HI-5046 DPDT 50Ω
HI-5046A DPDT 25Ω
HI-5047 4PST 50Ω
HI-5047A 4PST 25Ω
HI-5048 Dual SPST 25Ω
HI-5049 Dual DPST 25Ω
HI-5050 SPDT 25Ω
HI-5051 Dual SPDT 25Ω
S
N
AP
D
August 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
HI-5040 thru HI-5051,
HI-5046A and HI-5047A
CMOS Analog Switches
File Number 3127.1
13-102
Ordering Information
PART
NUMBER TEMP. RANGE
(oC) PACKAGE PKG.
NO.
HI3-5040-5 0 to 75 16 Ld PDIP E16.3
HI1-5040-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5040-5 0 to 75 16 Ld CERDIP F16.3
HI3-5041-5 0 to 75 16 Ld PDIP E16.3
HI1-5041-5 0 to 75 16 Ld CERDIP F16.3
HI1-5041-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5042-5 0 to 75 16 Ld PDIP E16.3
HI1-5042-5 0 to 75 16 Ld CERDIP F16.3
HI1-5042-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5043-7 0 to 75
+ 96 Hr. Burn-In 16 Ld CERDIP F16.3
HI1-5043-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5043-5 0 to 75 16 Ld PDIP E16.3
HI1-5043-5 0 to 75 16 Ld CERDIP F16.3
HI1-5044-5 0 to 75 16 Ld CERDIP F16.3
HI3-5044-5 0 to 75 16 Ld PDIP E16.3
HI1-5045-5 0 to 75 16 Ld CERDIP F16.3
HI1-5045-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5045-5 0 to 75 16 Ld PDIP E16.3
HI1-5046-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5046-5 0 to 75 16 Ld CERDIP F16.3
HI3-5046-5 0 to 75 16 Ld PDIP E16.3
HI3-5046A-5 0 to 75 16 Ld PDIP E16.3
HI1-5046A-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5046A-5 0 to 75 16 Ld CERDIP F16.3
HI1-5047-5 0 to 75 16 Ld CERDIP F16.3
HI1-5047-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5047-5 0 to 75 16 Ld PDIP E16.3
HI1-5047A-5 0 to 75 16 Ld CERDIP F16.3
HI1-5047A-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5047A-5 0 to 75 16 Ld PDIP E16.3
HI1-5048-5 0 to 75 16 Ld CERDIP F16.3
HI3-5048-5 0 to 75 16 Ld PDIP E16.3
HI1-5048-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5049-5 0 to 75 16 Ld CERDIP F16.3
HI1-5049-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5049-5 0 to 75 16 Ld PDIP E16.3
HI1-5050-5 0 to 75 16 Ld CERDIP F16.3
HI1-5050-2 -55 to 125 16 Ld CERDIP F16.3
HI3-5050-5 0 to 75 16 Ld PDIP E16.3
HI1-5051-5 0 to 75 16 Ld CERDIP F16.3
HI1-5051-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5051-7 0 to 75
+ 96 Hr. Burn-In 16 Ld CERDIP F16.3
HI4P5051-5 0 to 75 20 Ld PLCC N20.35
HI3-5051-5 0 to 75 16 Ld PDIP E16.3
HI1-5040/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5041/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5042/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5043/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5044/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5045/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5046/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5046A/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5047/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5047A/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5048/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5049/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5050/883 -55 to 125 16 Ld CERDIP F16.3
HI1-5051/883 -55 to 125 16 Ld CERDIP F16.3
HI4-5043/883 -55 to 125 20 Lead CLCC J20.A
HI4-5045/883 -55 to 125 20 Lead CLCC J20.A
HI4-5051/883 -55 to 125 20 Lead CLCC J20.A
HI9P5043-5 0 to 75 16 Ld SOIC M16.15
HI9P5045-5 0 to 75 16 Ld SOIC M16.15
HI9P5051-5 0 to 75 16 Ld SOIC M16.15
HI9P5043-9 -40 to 85 16 Ld SOIC M16.15
HI9P5051-9 -40 to 85 16 Ld SOIC M16.15
PART
NUMBER TEMP. RANGE
(oC) PACKAGE PKG.
NO.
HI-5040 Series
13-103
Pin Configurations
Switch States are Logic “0” Input
SINGLE CONTROL
SPST
HI-5040 (50Ω)SPDT
HI-5042 (50Ω), HI-5050 (25Ω)DPST
HI-5044 (50Ω)
DPDT
HI-5046 (50Ω), HI-5046A (25Ω)4PST
HI-5047 (50Ω), HI-5047A (25Ω)
DUAL CONTROL
DUAL SPST
HI-5041 (50Ω)DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)DUAL DPST
HI-5045 (50Ω), HI-5049 (25Ω)
DUAL SPST
HI-5048 (25Ω)DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)
NOTE: Unused pins may be internally connected. Ground all unused pins.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DS
V-
VR
VL
V+
A
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D1
D2
S2
S1
A
VL
VR
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D1
D2
S2
S1
A
VL
VR
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D2
D1
S1
S2
S4
D4
D3
VL
VR
A
S3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D2
D1
S1
S2
S4
D4
D3
VL
VR
A
S3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
D1S1
D2S2
A2
VL
VR
A114
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D3
S3
S4
D4
V-
V+
S1
S2
A2
VL
VR
A1
D1
D2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
S1
S2
A2
VL
VR
A1
D3
S3
S4
D4
D1
D2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V-
V+
A2
VL
VR
A1
D1
S1
S2
D2
14
15
16
17
18
4
5
6
7
8
32120 19
910 11 12 13
NC NC
V+
D3V-
NC
D1
NC
A1
S1
S3
S4
D4
VR
VL
NC
D2
NC
A2
S2
HI-5040 Series
13-104
Switch Functions
Switch States are Logic “1” Input
SPST
HI-5040 (50Ω)DUAL SPST
HI-5041 (50Ω)SPDT
HI-5042 (50Ω)
DUAL SPDT
HI-5043 (50Ω)DPST
HI-5044 (50Ω)DUAL DPST
HI-5045 (50Ω)
DPDT
HI-5046 (50Ω), HI-5046A (25Ω)4PST
HI-5047 (50Ω), HI-5047A (25Ω)DUAL SPST
HI-5048 (25Ω)
DUAL DPST
HI-5049 (25Ω)SPDT
HI-5050 (25Ω)DUAL SPDT
HI-5051 (25Ω)
1
12
16 11
13 14
D
V+
V-
VL
VR
15
S
A
1
8
9
10
12
15
16 11
13 14
S1
A1
A2
S2
D1
D2
V-VR
V+VL
12 11
13 14
15
A
1
16
3
4
V+VL
S1
S2
V-VR
D1
D2
1
3
8
6
5
9
10
12
15
4
16 11
13 14
V+VL
S1
A1
A2
S4
S3
S2
V-VR
D1
D2
D4
D3
12 11
13 14
15
1
16
3
4
A
S1
S2
V+VL
D1
D2
V-VR
1
3
8
6
5
9
10
12
15
4
16 11
13 14
D1
D2
D4
D3
S1
A1
A2
S4
S3
S2
V-VR
V+VL
12 11
13 14
15
3
4
1
16
8
9
6
5
S1
S3
S4
S2
A
V-VR
V+VL
D1
D2
D4
D3
12 11
13 14
15
3
4
1
16
8
9
6
5
D1
D2
D4
D3
S1
S3
S4
S2
A
V-VR
V+VL
3
6
5
10
12
15
411
13 14
S1
A1
A2
S2
D1
D2
V-VR
V+VL
1
3
8
6
5
9
10
12
15
4
16 11
13 14
V+VL
S1
A1
A2
S4
S3
S2
V-VR
D1
D2
D4
D3
12 11
13 14
15
1
16
3
4
A
S1
S2
V+VL
D1
D2
V-
VR
1
3
8
6
5
9
10
12
15
4
16 11
13 14
D1
D2
D4
D3
S1
A1
A2
S4
S3
S2
V-VR
V+VL
HI-5040 Series
13-105
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
VR to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+, V-
Digital and Analog Input Voltage . . . +VSUPPLY +4V, -VSUPPLY -4V
Analog Current (S to D) Continuous. . . . . . . . . . . . . . . . . . . . .30mA
Analog Current (S to D) Peak. . . . . . . . . . . . . . . . . . . . . . . . . .80mA
Operating Conditions
Temperature Range
HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-50XX-5, -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 85 32
SOIC Package. . . . . . . . . . . . . . . . . . . 120 N/A
PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
PLCC Package . . . . . . . . . . . . . . . . . . 80 N/A
CLCC Package . . . . . . . . . . . . . . . . . . 65 14
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(PLCC, SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = +0.8V,
VL= +5V, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded
PARAMETER TEST
CONDITIONS TEMP
(oC)
-55oC TO 125oC0
o
C TO 75oC
UNITSMIN TYP MAX MIN TYP MAX
SWITCHING CHARACTERISTICS
tON, Switch On Time (Note 5) 25 - 370 500 - 370 500 ns
tOFF, Switch Off Time (Note 5) 25 - 280 500 - 280 500 ns
Charge Injection (Note 3) 25 - 5 20 - 5 - mV
“Off Isolation” (Note 4) 25 75 80 - - 80 - dB
“Crosstalk” (Note 4) 25 80 88 - - 88 - dB
CS(OFF), Input Switch Capacitance 25 - 11 - - 11 - pF
CD(OFF), Output Switch Capacitance 25 - 11 - - 11 - pF
CD(ON), Output Switch Capacitance 25 - 22 - - 22 - pF
CA, Digital Input Capacitance 25 - 5 - - 5 - pF
CDS(OFF), Drain-To-Source Capacitance 25 - 0.5 - - 0.5 - pF
DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold Full - - 0.8 - - 0.8 V
VAH, Input High Threshold Full 2.4 - - 2.4 - - V
IA, Input Leakage Current (High or Low) Full - 0.01 1.0 - 0.01 1.0 µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range Full -15 - +15 -15 - +15 V
rON, On Resistance (Note 2A) 25 - 50 75 - 50 75 Ω
Full - - 150 - - 150 Ω
rON, On Resistance (Note 2B) 25 - 25 45 - 25 45 Ω
Full - - 50 - - 50 Ω
rON, Channel-to-Channel Match (Note 2A) 25 - 2 10 - 2 10 Ω
rON, Channel-to-Channel Match (Note 2B) 25 - 1 5 - 1 5 Ω
HI-5040 Series
13-106
IS(OFF) = ID(OFF), Off Input or
Output Leakage Current 25 - 0.8 2 - 0.8 2 nA
Full - 100 200 - 100 200 nA
ID(ON), On Leakage Current 25 - 0.01 2 - 0.01 2 nA
Full - 2 200 - 2 200 nA
POWER REQUIREMENTS
PD, Quiescent Power Dissipation 25 - 1.5 - - 1.5 - mW
I+, I-, IL, IR25 - - 0.2 - - 0.3 mA
I+, +15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
I-, -15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
IL, +5V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
IR, Ground Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
NOTES:
2. VOUT = ±10V, IOUT = 1mA
A). For HI-5040 thru HI-5047
B). For HI-5048 thru HI-5051, HI-5046A/5047A.
3. VIN = 0V, CL = 10,000pF.
4. RL = 100Ω, f = 100kHz, VIN = 2.0VP-P, CL = 5pF.
5. VAL = 0V, VAH = 5V.
Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = +0.8V,
VL= +5V, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded (Continued)
PARAMETER TEST
CONDITIONS TEMP
(oC)
-55oC TO 125oC0
o
C TO 75oC
UNITSMIN TYP MAX MIN TYP MAX
Switching Waveforms
Top: TTL Input (1V/Div.)
VAH = 5V, VAL = 0V
Bottom: Output (2V/Div.)
Horizontal: 200ns/Div.
FIGURE 1.
Top: CMOS Input (5V/Div.)
VAH = 10V, VAL = 0V
Bottom: Output (5V/Div.)
Horizontal: 200ns/Div.
FIGURE 2.
INPUT
OUTPUT
INPUT
OUTPUT
HI-5040 Series
13-107
Typical P erf ormance Curves and Test Cir cuits
TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH =3V
and VAL = 0.8V, Unless Otherwise Specified
FIGURE 3. “ON” RESISTANCE vs ANALOG SIGNAL LEVEL, SUPPLY VOLTAGE AND TEMPERATURE
FIGURE 4. “ON” RESISTANCE vs ANALOG SIGNAL LEVEL
AND POWER SUPPLY VOLTAGE FIGURE 5. NORMALIZED “ON” RESISTANCE vs TEMPERATURE
FIGURE 6. ON/OFF LEAKAGE CURRENT vs TEMPERATURE
IN OUT
1mA
1/2
rON = 1mA
V2
±VIN
ANALOG SIGNAL LEVEL (V)
“ON” RESISTANCE (Ω)
80
60
40
20
0-15 -10 -5 0 +5 +10 +15
V+ = +10V
V- = -10V
V+ = +12V
V- = -12V
V+ = +15V
V- = -15V
TEMPERATURE (oC)
-50 -25 0 75 100 1255025
0.6
1.2
1.1
1.0
0.9
0.8
0.7
NORMALIZED “ON” RESISTANCE
(REFERRED TO 25oC)
VIN = 0V
IN OUT AA
±10V
±
IN OUT
A
±10V
ID(ON)
ID(OFF)
IS(OFF)
10V
ON LEAKAGE CURRENT vs TEMPERATURE
OFF LEAKAGE CURRENT vs TEMPERATURE
ID(ON)
TEMPERATURE (oC)
75 100 1255025
IS(OFF) = ID(OFF)
100nA
10nA
1nA
100pA
10pA
LEAKAGE CURRENT
HI-5040 Series
13-108
FIGURE 7. NORMALIZED “ON” RESISTANCE vs ANALOG CURRENT
FIGURE 8. “OFF” ISOLATION vs FREQUENCY
FIGURE 9. CROSSTALK vs FREQUENCY
Typical P erf ormance Curves and Test Cir cuits
TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH =3V
and VAL = 0.8V, Unless Otherwise Specified (Continued)
“ON” RESISTANCE vs ANALOG CURRENT
ANALOG CURRENT (mA)
40 60 80200
1.4
NORMALIZED “ON” RESISTANCE
IN OUT
±VIN
1.3
1.2
1.1
1.0
(REFERRED TO 1mA)
I
rON VIN
I
---------=
FREQUENCY (Hz)
10K 100K 1M1001
-200
OFF ISOLATION (dB)
-160
-120
-80
-40
50ΩRL
VOUT
VIN
2VP-P
IN OUT
1K10
RL = 100Ω
RL = 10kΩOFF ISOLATION 20 Log VIN
VOUT
----------------



=
FREQUENCY (Hz)
200
160
120
80
40
50Ω
RL
RL
VOUT
VIN
2VP-P
SWITCHED
CHANNEL
10K 100K 1M10011K10
0
CROSSTALK (dB)
CROSSTALK 20 Log VIN
VOUT
----------------



=
HI-5040 Series
13-109
FIGURE 10. POWER CONSUMPTION vs FREQUENCY
Typical P erf ormance Curves and Test Cir cuits
TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH =3V
and VAL = 0.8V, Unless Otherwise Specified (Continued)
TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz)
200
160
120
80
40
10K 100K 1M01K
0
POWER CONSUMPTION (mW)
VR
VL
IL
V+ V-
A
I-
I+
+5V +15V -15V
+10V
-10V
TOGGLE
AT 50%
DUTY
Switching Characteristics
FIGURE 11. ON/OFF SWITCH TIME vs LOGIC LEVEL
FIGURE 12. SWITCHING TIMES FOR POSITIVE DIGITAL
TRANSITION FIGURE 13. SWITCHING TIMES FOR NEGATIVE DIGITAL
TRANSITION
+10V
IN1
IN2
VA
1K 1K
90% 90%
tOFF tON
tON tOFF
90%
90%
VAL VA
OUT 1
OUT 2
VAH
DIGITAL “HIGH” (V)
2.4 3.0 3.6 4.2 4.8
720
660
600
540
480
420
360
300
240
180
120
60
tON
tOFF
DIGITAL “LOW” (V)
0 0.5 1.0 1.5
720
660
600
540
480
420
360
300
240
180
120
60
tON
tOFF
HI-5040 Series
13-110
NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits.
FIGURE 14. TTL/CMOS REFERENCE CIRCUIT (NOTE)
Switching Characteristics
(Continued)
P14 P15 P16
QN1
QP1
25µA
P13
V+
QN2
N14 N15 N16
QP2
R7
QP3 QP4
QP5 QP6
QP8
R2
QP7
R4
R5
R6 R3
to VR’
to VL’
V-
V+
25µA
25µA
25µA
100µA
16µA
25µA
VL
VR
35µA
N13
HI-5040 Series
13-111
FIGURE 15. SWITCH CELL
NOTES:
1. All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
2. For further information refer to Application Notes AN520, AN521, AN531, AN532 and AN557.
FIGURE 16. DIGITAL INPUT BUFFER AND LEVEL SHIFTER
Switching Characteristics
(Continued)
P2
N2
N1
N3
V-
P1
IN OUT
V+
A1(A2)
A1(A2)
N1
N2
P2
P1
P3
P5
P4
P6 P7 P8 P9 P10 P11 P12
A1
A2
N12N11N10N9N8N7N6
N5
N4
N3
V-
VL'
VR'
V+
V+
D2
D1
V-
AR4
200Ω
A1
A2
HI-5040 Series